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Mon, 25 Nov 2024 03:33:49 -0800 From: Yishai Hadas To: , CC: , , , , , Subject: [PATCH] vfio/mlx5: Align the page tracking max message size with the device capability Date: Mon, 25 Nov 2024 13:32:49 +0200 Message-ID: <20241125113249.155127-1-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|DS0PR12MB9275:EE_ X-MS-Office365-Filtering-Correlation-Id: b72048f4-6c9b-4d1b-1c66-08dd0d450b4a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: IP3MRkV2CJ+xuucPTpLq0kHDLxXicHDWn5jgwnpslfq3fwQdlaGP9JtRVVNlm/L2GR3jc6yjjTT/qitCXL9TCs8/QFT14bTrIa+ZSE3ckqUksgARPl8CQeayhn4lSDnnDi0NRrOQvzqqnWEls7GQaAaEdRNxh5J7EomeSIojJ9ZeQTriQA4kEr2S9WiapGPAWKxqJ8zMuSo/7qkSzztUzz5TRaLZp2eArJuYAFcJ98Bv9uwl6oG0ncY5mskTgd6OExRF5/EMwR+1X5hXUOvytz7O4Dx0iekC5EhyCEWuCczd1RvN96n04giKTGIiSntagMlVQNAk5yw3oszh3WNPmT9yjhHh/ycJf7OLKoSFAVjPxfobYxdUKCz+BrHn5sjzJtbKunBviKm7CJVcQPbeS6e4hHRAxV9yscAYu9f10zGpJCYnSqfwGtEZlma4bLYiRWLl2n5lfRUU9Dnws0wAkYgSDuvtcKDLdd69zKWFcXWwiEFhCvsbqpb0328FQiXcV3sIFKRhqHQd21DsvQO+e+qoSh/trBPskMWK3vc5fBT5AA+ydfyBWj2arr+V9qs1tSLytsqlmfEwV9v/iyxI3eqyCZfHcdnUR/o0h6qTsjj8ov776S9BneG19L4TYjnQpBxv78/mVApeIyakwipYuRRjQ8BLXWRwvM3rowoHHKR8giD5YW1XCOkNxP930XWYMbi2DSGgUYoQkhmV03VOfwPc6F5xXxa2kidCNTchXOi94u729HEx0mJBjT16i4R7HT6htBCHp8O1ClTvFOcGlPzKYAP/LrMKjk89B/r+z+HC3ZdQIApsl9tWIJmrtRBd0bKfRlcgjY5q17ghgFRe0bGmThleLuCV3ygOIPyVMvVbUoft7Hxnjxz/DZX39mu+1T0CQ5bLUxbq8C8EwQvUh1fcQoaBM7Jua6hAzUiPLmdRu7DG7SWuoOZzwUnsmF92CHaPT1wqIlY0heSAJLS/uoCFDa1PAzZ3jnR3NMVlHldSUp/kIS29Jt0GzteXSToja3bSwfmYpXVK+pczjszn64HQhdNr4+K2Dh05yAR95ZxxZSGMOEFnqhi2Ddr5EM4sbWPh5jBBZj7TLUMXzxErWTpYwEVFQEUViqyfCjv4xUyHKDxqtBjlKbM8q4Ax2wA5JS/fOwDz1Wy2cCHdQtganZUPvLpkrtad0C/jRoDzuSQIKR8OxkxqBTqahT+mWaIlfXqLShYjfP63y77VbBvKdjpfgfK5CvwMm8IzVc8LGvz9SrIjMvDGixNpBXCtzWqrA9d0qgiHkmkiUh+ltZ+xabRPFgfD9y8n9+h+UeIVvfS7RBYDOsM135c2B0GI7LnI0+heAdanahQIgVODeMasFDLCwEdIBoogQM/FqTylw0kv8xXALlDOSJ312KLHGvylcXr79GOtOyg6A0bWohPSBfcRG7dPALcMucBlnU20gpNOVGYxxrasv3CBBTmxUX28 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2024 11:33:54.8383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b72048f4-6c9b-4d1b-1c66-08dd0d450b4a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9275 Align the page tracking maximum message size with the device's capability instead of relying on PAGE_SIZE. This adjustment resolves a mismatch on systems where PAGE_SIZE is 64K, but the firmware only supports a maximum message size of 4K. Now that we rely on the device's capability for max_message_size, we must account for potential future increases in its value. Key considerations include: - Supporting message sizes that exceed a single system page (e.g., an 8K message on a 4K system). - Ensuring the RQ size is adjusted to accommodate at least 4 WQEs/messages, in line with the device specification. The above has been addressed as part of the patch. Fixes: 79c3cf279926 ("vfio/mlx5: Init QP based resources for dirty tracking") Signed-off-by: Yishai Hadas --- drivers/vfio/pci/mlx5/cmd.c | 47 +++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/vfio/pci/mlx5/cmd.c b/drivers/vfio/pci/mlx5/cmd.c index 7527e277c898..a61d303d9b6a 100644 --- a/drivers/vfio/pci/mlx5/cmd.c +++ b/drivers/vfio/pci/mlx5/cmd.c @@ -1517,7 +1517,8 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, struct mlx5_vhca_qp *host_qp; struct mlx5_vhca_qp *fw_qp; struct mlx5_core_dev *mdev; - u32 max_msg_size = PAGE_SIZE; + u32 log_max_msg_size; + u32 max_msg_size; u64 rq_size = SZ_2M; u32 max_recv_wr; int err; @@ -1534,6 +1535,12 @@ int mlx5vf_start_page_tracker(struct vfio_device *vdev, } mdev = mvdev->mdev; + log_max_msg_size = MLX5_CAP_ADV_VIRTUALIZATION(mdev, pg_track_log_max_msg_size); + max_msg_size = (1ULL << log_max_msg_size); + /* The RQ must hold at least 4 WQEs/messages for successful QP creation */ + if (rq_size < 4 * max_msg_size) + rq_size = 4 * max_msg_size; + memset(tracker, 0, sizeof(*tracker)); tracker->uar = mlx5_get_uars_page(mdev); if (IS_ERR(tracker->uar)) { @@ -1623,25 +1630,41 @@ set_report_output(u32 size, int index, struct mlx5_vhca_qp *qp, { u32 entry_size = MLX5_ST_SZ_BYTES(page_track_report_entry); u32 nent = size / entry_size; + u32 nent_in_page; + u32 nent_to_set; struct page *page; + void *page_start; + u32 page_offset; + u32 page_index; + u32 buf_offset; u64 addr; u64 *buf; int i; - if (WARN_ON(index >= qp->recv_buf.npages || + buf_offset = index * qp->max_msg_size; + if (WARN_ON(buf_offset + size >= qp->recv_buf.npages * PAGE_SIZE || (nent > qp->max_msg_size / entry_size))) return; - page = qp->recv_buf.page_list[index]; - buf = kmap_local_page(page); - for (i = 0; i < nent; i++) { - addr = MLX5_GET(page_track_report_entry, buf + i, - dirty_address_low); - addr |= (u64)MLX5_GET(page_track_report_entry, buf + i, - dirty_address_high) << 32; - iova_bitmap_set(dirty, addr, qp->tracked_page_size); - } - kunmap_local(buf); + do { + page_index = buf_offset / PAGE_SIZE; + page_offset = buf_offset % PAGE_SIZE; + nent_in_page = (PAGE_SIZE - page_offset) / entry_size; + page = qp->recv_buf.page_list[page_index]; + page_start = kmap_local_page(page); + buf = page_start + page_offset; + nent_to_set = min(nent, nent_in_page); + for (i = 0; i < nent_to_set; i++) { + addr = MLX5_GET(page_track_report_entry, buf + i, + dirty_address_low); + addr |= (u64)MLX5_GET(page_track_report_entry, buf + i, + dirty_address_high) << 32; + iova_bitmap_set(dirty, addr, qp->tracked_page_size); + } + kunmap_local(page_start); + buf_offset += (nent_to_set * entry_size); + nent -= nent_to_set; + } while (nent); } static void