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Mon, 25 Nov 2024 17:45:35 GMT Received: from 4215f72c9660.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 09:45:31 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Mike Tipton , Sibi Sankar , , , , Subject: [PATCH V6 1/4] interconnect: qcom: Add multidev EPSS L3 support Date: Mon, 25 Nov 2024 17:45:08 +0000 Message-ID: <20241125174511.45-2-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241125174511.45-1-quic_rlaggysh@quicinc.com> References: <20241125174511.45-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0l9k3kxCgNpLfPGrN1e3vXhYqCX1OUj- X-Proofpoint-GUID: 0l9k3kxCgNpLfPGrN1e3vXhYqCX1OUj- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250147 EPSS on SA8775P has two instances which requires creation of two device nodes with different compatible and device data because of unique icc node id and name limitation in interconnect framework. Add multidevice support to osm-l3 code to get unique node id from IDA and node name is made unique by appending node address. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 85 ++++++++++++++++++++++-------- 1 file changed, 63 insertions(+), 22 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 6a656ed44d49..a9405b7d251b 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,16 +1,19 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include +#include #include #include #include #include #include +#include #include #include @@ -34,9 +37,14 @@ #define OSM_L3_MAX_LINKS 1 +#define OSM_L3_NODE_ID_START 10000 +#define OSM_NODE_NAME_SUFFIX_SIZE 10 + #define to_osm_l3_provider(_provider) \ container_of(_provider, struct qcom_osm_l3_icc_provider, provider) +static DEFINE_IDA(osm_l3_id); + struct qcom_osm_l3_icc_provider { void __iomem *base; unsigned int max_state; @@ -55,46 +63,40 @@ struct qcom_osm_l3_icc_provider { */ struct qcom_osm_l3_node { const char *name; - u16 links[OSM_L3_MAX_LINKS]; + const char *links[OSM_L3_MAX_LINKS]; u16 id; u16 num_links; u16 buswidth; }; struct qcom_osm_l3_desc { - const struct qcom_osm_l3_node * const *nodes; + struct qcom_osm_l3_node * const *nodes; size_t num_nodes; unsigned int lut_row_size; unsigned int reg_freq_lut; unsigned int reg_perf_state; }; -enum { - OSM_L3_MASTER_NODE = 10000, - OSM_L3_SLAVE_NODE, -}; - -#define DEFINE_QNODE(_name, _id, _buswidth, ...) \ - static const struct qcom_osm_l3_node _name = { \ +#define DEFINE_QNODE(_name, _buswidth, ...) \ + static struct qcom_osm_l3_node _name = { \ .name = #_name, \ - .id = _id, \ .buswidth = _buswidth, \ .num_links = COUNT_ARGS(__VA_ARGS__), \ - .links = { __VA_ARGS__ }, \ + __VA_OPT__(.links = { #__VA_ARGS__ }) \ } -DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16); +DEFINE_QNODE(osm_l3_master, 16, osm_l3_slave); +DEFINE_QNODE(osm_l3_slave, 16); -static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { +static struct qcom_osm_l3_node * const osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &osm_l3_master, [SLAVE_OSM_L3] = &osm_l3_slave, }; -DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32); +DEFINE_QNODE(epss_l3_master, 32, epss_l3_slave); +DEFINE_QNODE(epss_l3_slave, 32); -static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { +static struct qcom_osm_l3_node * const epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &epss_l3_master, [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; @@ -123,6 +125,19 @@ static const struct qcom_osm_l3_desc epss_l3_l3_vote = { .reg_perf_state = EPSS_REG_L3_VOTE, }; +static u16 get_node_id_by_name(const char *node_name, + const struct qcom_osm_l3_desc *desc) +{ + struct qcom_osm_l3_node *const *nodes = desc->nodes; + int i; + + for (i = 0; i < desc->num_nodes; i++) { + if (!strcmp(nodes[i]->name, node_name)) + return nodes[i]->id; + } + return 0; +} + static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) { struct qcom_osm_l3_icc_provider *qp; @@ -164,10 +179,11 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) const struct qcom_osm_l3_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - const struct qcom_osm_l3_node * const *qnodes; + struct qcom_osm_l3_node * const *qnodes; struct icc_node *node; size_t num_nodes; struct clk *clk; + u64 addr; int ret; clk = clk_get(&pdev->dev, "xo"); @@ -188,6 +204,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) if (!qp) return -ENOMEM; + ret = of_property_read_reg(pdev->dev.of_node, 0, &addr, NULL); + if (ret) + return ret; + qp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(qp->base)) return PTR_ERR(qp->base); @@ -242,8 +262,13 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) icc_provider_init(provider); + /* Allocate unique id for qnodes */ + for (i = 0; i < num_nodes; i++) + qnodes[i]->id = ida_alloc_min(&osm_l3_id, OSM_L3_NODE_ID_START, GFP_KERNEL); + for (i = 0; i < num_nodes; i++) { - size_t j; + char *node_name; + size_t j, len; node = icc_node_create(qnodes[i]->id); if (IS_ERR(node)) { @@ -251,13 +276,29 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) goto err; } - node->name = qnodes[i]->name; + /* len = strlen(node->name) + @ + 8 (base-address) + NULL */ + len = strlen(qnodes[i]->name) + OSM_NODE_NAME_SUFFIX_SIZE; + node_name = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!node_name) { + ret = -ENOMEM; + goto err; + } + + snprintf(node_name, len, "%s@%08llx", qnodes[i]->name, addr); + node->name = node_name; + /* Cast away const and add it back in qcom_osm_l3_set() */ node->data = (void *)qnodes[i]; icc_node_add(node, provider); - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); + for (j = 0; j < qnodes[i]->num_links; j++) { + u16 link_node_id = get_node_id_by_name(qnodes[i]->links[j], desc); + + if (link_node_id) + icc_link_create(node, link_node_id); + else + goto err; + } data->nodes[i] = node; } From patchwork Mon Nov 25 17:45:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 13885164 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B39051B87FC; Mon, 25 Nov 2024 17:45:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732556746; cv=none; b=KuGoaQb1BRaFViPiURPNg/FSCiGfiFEM/jGRzjwlPF0fuPnM7BDyrkr9Fs9bGjXdxuT8bykTxgo+iL3Be3OvMRDrLDmymmWGXbe4QTWUpv/VPb20xlhS+F/SiR8f6afLchhF/lWe2I8phr9ZcbItEjD2Rm/W9/QXNVaxN9k9UcA= ARC-Message-Signature: i=1; a=rsa-sha256; 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Add new generic compatible "qcom,epss-l3-perf" for PERF_STATE register based L3 scaling. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index a9405b7d251b..7937e7c16c71 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -318,6 +318,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, + { .compatible = "qcom,epss-l3-perf", .data = &epss_l3_perf_state }, { .compatible = "qcom,osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, From patchwork Mon Nov 25 17:45:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 13885165 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87F521BBBFD; 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Signed-off-by: Raviteja Laggyshetty --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 21dae0b92819..e24399ca110f 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -28,12 +28,15 @@ properties: - const: qcom,osm-l3 - items: - enum: - - qcom,sc7280-epss-l3 - qcom,sc8280xp-epss-l3 - qcom,sm6375-cpucp-l3 - - qcom,sm8250-epss-l3 - qcom,sm8350-epss-l3 - const: qcom,epss-l3 + - items: + - enum: + - qcom,sc7280-epss-l3 + - qcom,sm8250-epss-l3 + - const: qcom,epss-l3-perf reg: maxItems: 1 From patchwork Mon Nov 25 17:45:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raviteja Laggyshetty X-Patchwork-Id: 13885166 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82AE01BD4FD; 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Update the generic compatible for SM8250 and SC7280 SoCs to "qcom,epss-l3-perf" as they use PERF_STATE register for L3 scaling. Signed-off-by: Raviteja Laggyshetty --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9f315a51a7c1..0c2bd15f9ef0 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -4282,6 +4283,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,sm8250-epss-l3", + "qcom,epss-l3-perf"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sa8775p-cpufreq-epss", "qcom,cpufreq-epss"; @@ -4295,6 +4305,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,sm8250-epss-l3", + "qcom,epss-l3-perf"; + reg = <0x0 0x18592000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + remoteproc_gpdsp0: remoteproc@20c00000 { compatible = "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 55db1c83ef55..544c6d725764 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -6125,7 +6125,7 @@ rpmhcc: clock-controller { }; epss_l3: interconnect@18590000 { - compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; + compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3-perf"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 48318ed1ce98..f4a223bfe748 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6230,7 +6230,7 @@ apps_bcm_voter: bcm-voter { }; epss_l3: interconnect@18590000 { - compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; + compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3-perf"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;