From patchwork Tue Nov 26 09:20:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885620 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA1FF19A2B0 for ; Tue, 26 Nov 2024 09:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612871; cv=none; b=VgdJ7PErg02VHgF4lFQy5q65Hzvep5KVlFBprIB7e7bRRYLKn6HHqlNTsK9QfrBXekjFHUaUoqJanFhjvXRylB7A+q7Gr6+qH+Q10P8JS82jfLuOaCDJlcQhmZjnyiysRsHj1gmwz+ayGunFZjRe6X0tJOcziI5X9sDXDYZ/e0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612871; c=relaxed/simple; bh=V/DGxPq334std3OZDw1Q13cvXzTcQ8HKIYrcq1YIJz8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LhDmwVbMuuOnMeocmlb5eSItRbURV2obq0hbMJkZ9/H5pHElbQjPIG8mUzNu4Qb2vxYMMcKjPHJ/WFevE5xf6YTk/qnMwGHWecx+gWzer68umaSWCHpBqnyBJBDIUelV8/W+PUA0gfW5ys129p5fVpxgH2o0IPeVXaZccgmxqjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ecJ7nixf; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ecJ7nixf" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-382588b7a5cso3426332f8f.3 for ; Tue, 26 Nov 2024 01:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612867; x=1733217667; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oQlGMIlStcYoMIShuvfUaEr5YyWxZQ2PUL1/5BTbV6c=; b=ecJ7nixfA9OMlsZb5dKVxfMvfwF7PKkDh5DkWFugpB4EsQvjgWSgc3jhd1U+x21D87 QwdsGbBIMykVGFzXhVasqjUgxA3ZosL+0hTJjJcN58OA/T8vPzjfqlnAmk53/VzAwv/5 Pf3tR29uewY1nGXArtHy2jql+0OdIqRm0G3GtViX/9uBqUvHXnBBPxQ+XCgeZgAkSGoz R47QCkotM647N1hHa4kbpDKmOIxWIS1PuzOx1jio5T5scBDHvo0r905IYD0ITSD6kNo9 gMDWbPA7TePcSu4I1jCra3+zkzq2J/8ugnuQJAOxY1Nc69ZpwQkNcMIosU4NjstiMYlK tc0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612867; x=1733217667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oQlGMIlStcYoMIShuvfUaEr5YyWxZQ2PUL1/5BTbV6c=; b=J8ZnwfXX+M8SaX8ZYZReSOX+EfWpbpDtoarP3A0rYHM1CBFIIqtxDfH3C3sXR7sZwa aB9ne97lCxUl1zRDJKaLNK529baGYNWk4ecjAgw3gwnSSJLjWZLY1DpeqvnbGxcfTkS6 iRTDipqgGZrt/lYIf5jiCAebMNaWmSM4HPKw3AOlip3/jOpsDs//Qc46e/bD9/zlOcSz poAa+5MOKNPFKkRhcFRuLP54rbrRAPgU4z30myRs6Wdzo/89Esgu9bi0X2cWe58cetim oypI9ACauxK/koZtlcEuSnnxtrwR9EthFBpFoTmIacmYp2RHMe08h082mG8FZpG6RLRU toAw== X-Forwarded-Encrypted: i=1; AJvYcCUC7cXnasv2aXULnKK61jH+iHkunzNmyaqUJmHtiMm1CPZKkcIwF10RiWxglQUzXwXGVBvJrlJLlLd14t+GQIUflw==@vger.kernel.org X-Gm-Message-State: AOJu0Yy2qIVi9dS+/7glsBOzpv42JmCB7S5ZkoBDEM6wE0xsHg1aPSR5 UiaYeeiX4oI7naIp65fIW9/zM44mPqKZLKqIP+inSCUdZPHdgtIc2/I9YH1fDhg= X-Gm-Gg: ASbGnct24ZHOrcGbzM42RrqqW90jZe6KykiilEECVMvUEBVRDRqCBBW1xA9//r7yaFs j8Cj388f9/EmmAedzQ4kmTskASqDaQF57YGkw83eZIsyNiylthgYMeZNcVtKSVSNd3C7PwKWMNk ZD3llihB48v0s3BmD4LHQclinsXWUoVDytrCw/D7IEMCevIH4VpTSFQngZ8wJGxEReT4F9xwgIy VthwvTjlspYVgNBgwIU5VFN7LQd74kQjwo3vdAP2Xj18ylFbafAoqgJs4DE1uKZmNYKxkMGL9Xv 1fo= X-Google-Smtp-Source: AGHT+IGG2IQ+U6IJTaeTyTNQI6LGmc4AjJAHShu01o6855LNNPFEdIbHv35w4G1l6XXNHmNrrqLTjw== X-Received: by 2002:a5d:5984:0:b0:382:415e:a144 with SMTP id ffacd0b85a97d-382608a4b7bmr12377286f8f.0.1732612867211; Tue, 26 Nov 2024 01:21:07 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:06 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 01/15] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Add #renesas,sysc-signal-cells Date: Tue, 26 Nov 2024 11:20:36 +0200 Message-Id: <20241126092050.1825607-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S system controller (SYSC) has registers to control signals that are routed to various IPs. These signals must be controlled during configuration of the respective IPs. One such signal is the USB PWRRDY, which connects the SYSC and the USB PHY. This signal must to be controlled before and after the power to the USB PHY is turned off/on. Other similar signals include the following (according to the RZ/G3S hardware manual): * PCIe: - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B register - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register * SPI: - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA register * I2C/I3C: - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers (x=0..3) - af_bypass I3C signal controlled through SYS_I3C_CFG register * Ethernet: - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG registers (x=0..1) Add #renesas,sysc-signal-cells DT property to allow different SYSC signals consumers to manage these signals. The goal is to enable consumers to specify the required access data for these signals (through device tree) and let their respective drivers control these signals via the syscon regmap provided by the system controller driver. For example, the USB PHY will describe this relation using the following DT property: usb2_phy1: usb-phy@11e30200 { // ... renesas,sysc-signal = <&sysc 0xd70 0x1>; // ... }; Along with it, add the syscon to the compatible list as it will be requested by the consumer drivers. The syscon was added to the rest of system controller variants as these are similar with RZ/G3S and can benefit from the implementation proposed in this series. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new .../soc/renesas/renesas,rzg2l-sysc.yaml | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml index 4386b2c3fa4d..90f827e8de3e 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -19,11 +19,13 @@ description: properties: compatible: - enum: - - renesas,r9a07g043-sysc # RZ/G2UL and RZ/Five - - renesas,r9a07g044-sysc # RZ/G2{L,LC} - - renesas,r9a07g054-sysc # RZ/V2L - - renesas,r9a08g045-sysc # RZ/G3S + items: + - enum: + - renesas,r9a07g043-sysc # RZ/G2UL and RZ/Five + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L + - renesas,r9a08g045-sysc # RZ/G3S + - const: syscon reg: maxItems: 1 @@ -42,9 +44,17 @@ properties: - const: cm33stbyr_int - const: ca55_deny + "#renesas,sysc-signal-cells": + description: + The number of cells needed to configure a SYSC controlled signal. First + cell specifies the SYSC offset of the configuration register, second cell + specifies the bitmask in register. + const: 2 + required: - compatible - reg + - "#renesas,sysc-signal-cells" additionalProperties: false @@ -53,7 +63,7 @@ examples: #include sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; + compatible = "renesas,r9a07g044-sysc", "syscon"; reg = <0x11020000 0x10000>; interrupts = , , @@ -61,4 +71,5 @@ examples: ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; }; From patchwork Tue Nov 26 09:20:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885621 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCAC31B85C2 for ; Tue, 26 Nov 2024 09:21:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; cv=none; b=E2ppTkCQHOLWO7v14dK3YgS4whWRgUkN+mR8hBChiOjRZ2kTyDFgYdC+MbUzo+0lwjyhjD+yGpT9j6mblzTSd2B973ruHu63cRhLH/a7LRbN/2Qr5QtWIIv1n2kjdq2pq+gVD32BTxc6I3WCH8G9D+7ShWmo5KFD7E4urjK5bb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; c=relaxed/simple; bh=EqyCCrGqEJwg3+iLhcuJrpOwueTe8BY2KShqIIlG8ZY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F8HmXr6mAT1vYhop+IQibB/vgjZK45fzwTB9iAsUxovKzbgjaAfgTdiFEkfwzttBuiH/IwnVq18VYNIIVnC7LJjZJUWO16lpoDYKw9OFiCAWHMEm6daCbP245e8X2QWD2D2dvl8jbN+5xNxIGr9iaWHE8UlO2y/056aBFkXtNzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=WpmWgXyr; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="WpmWgXyr" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43155abaf0bso49707365e9.0 for ; Tue, 26 Nov 2024 01:21:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612869; x=1733217669; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5vCamtieJ1Any0nEDdOYudZWF6ph91xcO8/i+h+/3r0=; b=WpmWgXyrfuIkNdGBirDiL0o9+2F5c/OS9QxGPfWXRN14eKKiLmwatebdp8nz/Nq1hk OyohD5xO9pkHRT7odfi4tx+HukktcrVdtHGQQAdH3HQP3SaeSy2B3ynG/nH/1CXe6IG7 WNgEHOhQzJn/cDHa7kS8zUo+PHqz05tblKrdgTJFguG/Xn4Bf4PfUo7KzLHmDhdQ87Yg 1ckjGVQmD+DniYnpUUUeBd8Rj6DmQaXRmc+MteZ4bKIuM0KWYgCfaPoDikTp75gZIF0/ 6bgHXEZ8WK/3KNo5mVKDpQLD2r8/9UYw1GE6grw07hpOb8pq1cqFIjC0OAAXnWTStyeC HxZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612869; x=1733217669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5vCamtieJ1Any0nEDdOYudZWF6ph91xcO8/i+h+/3r0=; b=V6shCiLEst0j5ma5mjgvVmvPKprenNeQ2KAHAgxtxm+ozSzncbMHTF097Npkc8zHBD E2oMBCpsJ6yJF8UhJgCeBOysa7zogIIj0PQZzE4ImcGle5ieltaJ0OyJe3+oAO/ABmRI ElsEONvT94g+5pTNJvPUbE66IggwxZjhNwrJE21EJiRVoeS94OMWKlbmGY59q/CHvark XakEOg8MgfV02bZ/qYH/czyx60jO50EW0Dh/YWplnMgBjzXNOIHJgk1W4VYE4c8Rvjk4 VTG4ib3JFaB8S10+eymEUuvdfNnjEy2qXwK2fchUE8xWZubJEb0qLV5J8IijPzZTQYdH HgUQ== X-Forwarded-Encrypted: i=1; AJvYcCUHL3VYYH1jhP98xuXjw3FJHlF6cA2EtdYrg8xUbROKxK6+63ZQ877xliuZ+KrK5CdQmKCcazTI8tdIymIB1yJwQw==@vger.kernel.org X-Gm-Message-State: AOJu0YxCqz1egxUiGkaosQ44qx7EKrj+ngV7nwk9JfT6rKReRrSQgr/+ 8hImQmC0hOBea++JduW97oJ6mf5d+57LJddjfGDlihInBQh/MJFJ1sgaI37r5ms= X-Gm-Gg: ASbGncvooApazvFFNtJVprvNsN9WAWPjPO+Hq6vRr0D76ZrTKxbMIZF/JLcA0/+4NRw N/a2Twa7afsQHh1rqNf7aSqzOkWXXonukWhL6XbsYy7QVytRacM6pyaflTiqzzDD9d/PVWzqa5M +f0rNuF6lrjeNpQ89yo3NOD0wpJ30mtVRqp7Fo3MXJNaJM957pEaU15UG1iFo6/PSY0FUzsbAfv VAIJ4xVcopsaGVwMNYxqkHVW7nRt2Yc0ySxiBbN/myE3qGSNPhjObYxizzlwjzy616yv6buNRDs dZ0= X-Google-Smtp-Source: AGHT+IHaYOnIDbCpLmYeLO1a6tWYrQIEozAksJelkAeI7VXpQtyjiqqF3I9/uKkLk0h0PGHL3GFAQQ== X-Received: by 2002:a05:6000:2ad:b0:382:4a4e:25bb with SMTP id ffacd0b85a97d-38260bcc4fdmr15091977f8f.46.1732612868973; Tue, 26 Nov 2024 01:21:08 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:08 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 02/15] soc: renesas: Add SYSC driver for Renesas RZ family Date: Tue, 26 Nov 2024 11:20:37 +0200 Message-Id: <20241126092050.1825607-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S system controller (SYSC) has various registers that control signals specific to individual IPs. IP drivers must control these signals at different configuration phases. Add SYSC driver that allows individual SYSC consumers to control these signals. The SYSC driver exports a syscon regmap enabling IP drivers to use a specific SYSC offset and mask from the device tree, which can then be accessed through regmap_update_bits(). Currently, the SYSC driver provides control to the USB PWRRDY signal, which is routed to the USB PHY. This signal needs to be managed before or after powering the USB PHY off or on. Other SYSC signals candidates (as exposed in the the hardware manual of the RZ/G3S SoC) include: * PCIe: - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B register - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register * SPI: - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA register * I2C/I3C: - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers (x=0..3) - af_bypass I3C signal controlled through SYS_I3C_CFG register * Ethernet: - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG registers (x=0..1) As different Renesas RZ SoC shares most of the SYSC functionalities available on the RZ/G3S SoC, the driver if formed of a SYSC core part and a SoC specific part allowing individual SYSC SoC to provide functionalities to the SYSC core. Signed-off-by: Claudiu Beznea Reviewed-by: Biju Das --- Change in v2: - this was patch 04/16 in v1 - dropped the initial approach proposed in v1 where a with a reset controller driver was proposed to handle the USB PWRRDY signal - implemented it with syscon regmap and the SYSC signal concept (introduced in this patch) drivers/soc/renesas/Kconfig | 7 + drivers/soc/renesas/Makefile | 2 + drivers/soc/renesas/r9a08g045-sysc.c | 31 +++ drivers/soc/renesas/rz-sysc.c | 286 +++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.h | 52 +++++ 5 files changed, 378 insertions(+) create mode 100644 drivers/soc/renesas/r9a08g045-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 9f7fe02310b9..0686c3ad9e27 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -378,4 +378,11 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST +config SYSC_RZ + bool "System controller for RZ SoCs" if COMPILE_TEST + +config SYSC_R9A08G045 + bool "Renesas RZ/G3S System controller support" if COMPILE_TEST + select SYSC_RZ + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 734f8f8cefa4..8cd139b3dd0a 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,7 +6,9 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif +obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o +obj-$(CONFIG_SYSC_RZ) += rz-sysc.o diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c new file mode 100644 index 000000000000..ceea738aee72 --- /dev/null +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include + +#include "rz-sysc.h" + +#define SYS_USB_PWRRDY 0xd70 +#define SYS_USB_PWRRDY_PWRRDY_N BIT(0) +#define SYS_MAX_REG 0xe20 + +static const struct rz_sysc_signal_init_data rzg3s_sysc_signals_init_data[] __initconst = { + { + .name = "usb-pwrrdy", + .offset = SYS_USB_PWRRDY, + .mask = SYS_USB_PWRRDY_PWRRDY_N, + .refcnt_incr_val = 0 + } +}; + +const struct rz_sysc_init_data rzg3s_sysc_init_data = { + .signals_init_data = rzg3s_sysc_signals_init_data, + .num_signals = ARRAY_SIZE(rzg3s_sysc_signals_init_data), + .max_register_offset = SYS_MAX_REG, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c new file mode 100644 index 000000000000..dc0edacd7170 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rz-sysc.h" + +/** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address + * @dev: SYSC device pointer + * @signals: SYSC signals + * @num_signals: number of SYSC signals + */ +struct rz_sysc { + void __iomem *base; + struct device *dev; + struct rz_sysc_signal *signals; + u8 num_signals; +}; + +static int rz_sysc_reg_read(void *context, unsigned int off, unsigned int *val) +{ + struct rz_sysc *sysc = context; + + *val = readl(sysc->base + off); + + return 0; +} + +static struct rz_sysc_signal *rz_sysc_off_to_signal(struct rz_sysc *sysc, unsigned int offset, + unsigned int mask) +{ + struct rz_sysc_signal *signals = sysc->signals; + + for (u32 i = 0; i < sysc->num_signals; i++) { + if (signals[i].init_data->offset != offset) + continue; + + /* + * In case mask == 0 we just return the signal data w/o checking the mask. + * This is useful when calling through rz_sysc_reg_write() to check + * if the requested setting is for a mapped signal or not. + */ + if (mask) { + if (signals[i].init_data->mask == mask) + return &signals[i]; + } else { + return &signals[i]; + } + } + + return NULL; +} + +static int rz_sysc_reg_update_bits(void *context, unsigned int off, + unsigned int mask, unsigned int val) +{ + struct rz_sysc *sysc = context; + struct rz_sysc_signal *signal; + bool update = false; + + signal = rz_sysc_off_to_signal(sysc, off, mask); + if (signal) { + if (signal->init_data->refcnt_incr_val == val) { + if (!refcount_read(&signal->refcnt)) { + refcount_set(&signal->refcnt, 1); + update = true; + } else { + refcount_inc(&signal->refcnt); + } + } else { + update = refcount_dec_and_test(&signal->refcnt); + } + } else { + update = true; + } + + if (update) { + u32 tmp; + + tmp = readl(sysc->base + off); + tmp &= ~mask; + tmp |= val & mask; + writel(tmp, sysc->base + off); + } + + return 0; +} + +static int rz_sysc_reg_write(void *context, unsigned int off, unsigned int val) +{ + struct rz_sysc *sysc = context; + struct rz_sysc_signal *signal; + + /* + * Force using regmap_update_bits() for signals to have reference counter + * per individual signal in case there are multiple signals controlled + * through the same register. + */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) { + dev_err(sysc->dev, + "regmap_write() not allowed on register controlling a signal. Use regmap_update_bits()!"); + return -EOPNOTSUPP; + } + + writel(val, sysc->base + off); + + return 0; +} + +static bool rz_sysc_writeable_reg(struct device *dev, unsigned int off) +{ + struct rz_sysc *sysc = dev_get_drvdata(dev); + struct rz_sysc_signal *signal; + + /* Any register containing a signal is writeable. */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) + return true; + + return false; +} + +static bool rz_sysc_readable_reg(struct device *dev, unsigned int off) +{ + struct rz_sysc *sysc = dev_get_drvdata(dev); + struct rz_sysc_signal *signal; + + /* Any register containing a signal is readable. */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) + return true; + + return false; +} + +static int rz_sysc_signals_show(struct seq_file *s, void *what) +{ + struct rz_sysc *sysc = s->private; + + seq_printf(s, "%-20s Enable count\n", "Signal"); + seq_printf(s, "%-20s ------------\n", "--------------------"); + + for (u8 i = 0; i < sysc->num_signals; i++) { + seq_printf(s, "%-20s %d\n", sysc->signals[i].init_data->name, + refcount_read(&sysc->signals[i].refcnt)); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(rz_sysc_signals); + +static void rz_sysc_debugfs_remove(void *data) +{ + debugfs_remove_recursive(data); +} + +static int rz_sysc_signals_init(struct rz_sysc *sysc, + const struct rz_sysc_signal_init_data *init_data, + u32 num_signals) +{ + struct dentry *root; + int ret; + + sysc->signals = devm_kcalloc(sysc->dev, num_signals, sizeof(*sysc->signals), + GFP_KERNEL); + if (!sysc->signals) + return -ENOMEM; + + for (u32 i = 0; i < num_signals; i++) { + struct rz_sysc_signal_init_data *id; + + id = devm_kzalloc(sysc->dev, sizeof(*id), GFP_KERNEL); + if (!id) + return -ENOMEM; + + id->name = devm_kstrdup(sysc->dev, init_data->name, GFP_KERNEL); + if (!id->name) + return -ENOMEM; + + id->offset = init_data->offset; + id->mask = init_data->mask; + id->refcnt_incr_val = init_data->refcnt_incr_val; + + sysc->signals[i].init_data = id; + refcount_set(&sysc->signals[i].refcnt, 0); + } + + sysc->num_signals = num_signals; + + root = debugfs_create_dir("renesas-rz-sysc", NULL); + ret = devm_add_action_or_reset(sysc->dev, rz_sysc_debugfs_remove, root); + if (ret) + return ret; + debugfs_create_file("signals", 0444, root, sysc, &rz_sysc_signals_fops); + + return 0; +} + +static struct regmap_config rz_sysc_regmap = { + .name = "rz_sysc_regs", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, + .reg_read = rz_sysc_reg_read, + .reg_write = rz_sysc_reg_write, + .reg_update_bits = rz_sysc_reg_update_bits, + .writeable_reg = rz_sysc_writeable_reg, + .readable_reg = rz_sysc_readable_reg, +}; + +static const struct of_device_id rz_sysc_match[] = { +#ifdef CONFIG_SYSC_R9A08G045 + { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif + { } +}; +MODULE_DEVICE_TABLE(of, rz_sysc_match); + +static int rz_sysc_probe(struct platform_device *pdev) +{ + const struct rz_sysc_init_data *data; + struct device *dev = &pdev->dev; + struct rz_sysc *sysc; + struct regmap *regmap; + int ret; + + data = device_get_match_data(dev); + if (!data || !data->max_register_offset) + return -EINVAL; + + sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + if (!sysc) + return -ENOMEM; + + sysc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sysc->base)) + return PTR_ERR(sysc->base); + + sysc->dev = dev; + + ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals); + if (ret) + return ret; + + dev_set_drvdata(dev, sysc); + rz_sysc_regmap.max_register = data->max_register_offset; + regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); +} + +static struct platform_driver rz_sysc_driver = { + .driver = { + .name = "renesas-rz-sysc", + .of_match_table = rz_sysc_match + }, + .probe = rz_sysc_probe +}; + +static int __init rz_sysc_init(void) +{ + return platform_driver_register(&rz_sysc_driver); +} +subsys_initcall(rz_sysc_init); + +MODULE_DESCRIPTION("Renesas RZ System Controller Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h new file mode 100644 index 000000000000..bb850310c931 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ System Controller + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __SOC_RENESAS_RZ_SYSC_H__ +#define __SOC_RENESAS_RZ_SYSC_H__ + +#include +#include + +/** + * struct rz_sysc_signal_init_data - RZ SYSC signals init data + * @name: signal name + * @offset: register offset controling this signal + * @mask: bitmask in register specific to this signal + * @refcnt_incr_val: increment refcnt when setting this value + */ +struct rz_sysc_signal_init_data { + const char *name; + u32 offset; + u32 mask; + u32 refcnt_incr_val; +}; + +/** + * struct rz_sysc_signal - RZ SYSC signals + * @init_data: signals initialization data + * @refcnt: reference counter + */ +struct rz_sysc_signal { + const struct rz_sysc_signal_init_data *init_data; + refcount_t refcnt; +}; + +/** + * struct rz_sysc_init_data - RZ SYSC initialization data + * @signals_init_data: RZ SYSC signals initialization data + * @num_signals: number of SYSC signals + * @max_register_offset: Maximum SYSC register offset to be used by the regmap config + */ +struct rz_sysc_init_data { + const struct rz_sysc_signal_init_data *signals_init_data; + u32 num_signals; + u32 max_register_offset; +}; + +extern const struct rz_sysc_init_data rzg3s_sysc_init_data; + +#endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Tue Nov 26 09:20:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885622 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62AEA1BCA11 for ; Tue, 26 Nov 2024 09:21:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; cv=none; b=L8Gm5WUUPEvohg3RdZFCeRHPY+hK6p3UV7HZQLGIdf6JBSAjcAYftgf71Wu2mPVD47ykb0S6UtEeg8OBepEnaMoSIrqM+tufXlNo1U/cCTPGmc6j8CqbjTLHjw1CuYmd8fWAJkbzmCPyLi/RMeXUcgC83hXF7MKf7fDx/ppgG4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; c=relaxed/simple; bh=L3W0t3Ndk3P8WFZClVN2UXeegBaVgcbm+UbE0rvxIiE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cKhbVRdhC4s4Cwoa7g4iw0yv/KUUWAebVyq1oocqled9ZBbY1hDbXUGRl/xPy4JOHNWHNQeakftvC6i0ADhZyV+4vC3h1SC3TIYFUnPE9dHvvZLzndn0oDSi7BjR9zKiD2ofnRFT+TL7PJbPy0Jz2UUEGCOxNKtEkz7M09LeLdQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=FxVeUVkd; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="FxVeUVkd" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-382378f359dso3876955f8f.1 for ; Tue, 26 Nov 2024 01:21:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612871; x=1733217671; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rHg/UpXu0kAmh5cmR42CQBOhisgGmi+P1vH8bY184Vc=; b=FxVeUVkdWtHtY+sPUI6sqE21pehNBnfcBSO5Fe1XNeyDBtjrbLY3RCNlA9/TolWQID Li6rQ/qS3Qh6mPiK7z9ApvT8z9JjymMMtd+NjW2aisnUHkJu/OsDe2JbsoL+qrGxcDyk CucYUv9Ww06tLU/VIw/gNdOyMI5aYZoAGSBuhu8/SF4RZynySUvU4YTf7CrqB/iyiGdt m2DnCMY/tP4KoUn3LROhr7lKQerMxxcN/EVyGCfBSGZUa1bGP329cqKM9Ijwy9eIK3Fy eP2rPHYrwecpEiSyGDpz6s7hEvgSOjXqhNKs51pqZBZSG+PIxckU5X50yuAjDBkpJuVm ue2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612871; x=1733217671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rHg/UpXu0kAmh5cmR42CQBOhisgGmi+P1vH8bY184Vc=; b=eaAIgA/ngZdzuhPcekv94lf/x2PV2uOmlEUIb7MJEcEZ3eySZAk17wC1If0WGHuZv+ lcnvws96ny4nYg0uBTntFLfyNLh+1rkjrDayD18iOpgttKKM8yOUC1hcaoPvX/YaqAWJ o43jYgiDMI4F040eLnLc8l1qGNAplLPdKNoybGUC4rz6pg3FbXZGIw0F4CkCzYtjV0FL tOZSSQsrJ3/QsTYFs7WOAj71c3CPqLfoIlk5CazyNnpe4zxXUUkEARTIykuQNphsPtl9 JTpabRD1+r09Beo9Hu0hhbancf9Avkr2eEE5vNMM8fX6hO7A9EPQyIZ+yJiJeYFCQTVI rcMA== X-Forwarded-Encrypted: i=1; AJvYcCW4pEzWViB1HYuf8apOafm+NlH9ucU5bKl+cVFQdD06CE7AkrLqnUfd55VFaXgWNnz2FojbRrOp8OLBM1u7P6jiRg==@vger.kernel.org X-Gm-Message-State: AOJu0YwJZULXQLHWUmnCnxNaEey/Ke06HFJOC/CEPYukmp6fBtcEPfKz UGwZjiqgVXjlt9DgYt9D2ZTX2gt0dNkyr4l5QcHsFL4eGal4o+IuL3OnzFZ+a4Q= X-Gm-Gg: ASbGncsfvE+uJSG9Fr535PFKXXo8A85CKGNeRb2Ltig9Qg2ytwFUBCxoqtIHM/mTeuB CjJd25yXU3ybn+T25axgSqkT8rY01YlqmAwF+8dnerWDs/+1oWHdBUiqOnFwKzKZ+ycHTph9EQn IpRkAjWR9EsXkHRuv/ZOqmwNfXXoFJKzIawKdGQq5ECCG9whPAQB2TtWaL+vPGvdppdSzdH7/fD NwsOhJ9lrGev10DTTPpgGeuqUMDy8B2gRlaOV6czwZp2eqbxJIaDj7ZTOAHAhXxWe1obag3hpBB sB0= X-Google-Smtp-Source: AGHT+IHWio7klIaUm9lWwgg66sT0uRqFvChifk0YrFUVIwja8OlGoGemJIscbif1ZB71H5mZ9kHl7w== X-Received: by 2002:a5d:5849:0:b0:382:4ce5:f8a4 with SMTP id ffacd0b85a97d-38260be54f9mr11141729f8f.53.1732612870798; Tue, 26 Nov 2024 01:21:10 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:10 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 03/15] soc: renesas: rz-sysc: Enable SYSC driver for RZ/G3S Date: Tue, 26 Nov 2024 11:20:38 +0200 Message-Id: <20241126092050.1825607-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable SYSC driver for RZ/G3S. This is necessary for USB support. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new drivers/soc/renesas/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 0686c3ad9e27..c8065f25ee53 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -334,6 +334,7 @@ config ARCH_R9A07G054 config ARCH_R9A08G045 bool "ARM64 Platform support for RZ/G3S" select ARCH_RZG2L + select SYSC_R9A08G045 help This enables support for the Renesas RZ/G3S SoC variants. From patchwork Tue Nov 26 09:20:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885623 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3EE61C3050 for ; Tue, 26 Nov 2024 09:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612875; cv=none; b=K9SStU0AsyVfcgzFHHuDLSb9OqTzDzEU2NDMhXDJH/0t8KVgHQ08XiIBcJrwjST0tcGX3JxspA9xrBF+cn263/6JCPwvJDbTrm6glcGjou6Ss07VTUiKrBxWvfh1pzzkw/RBG2sgNoKbLI2emNvsNZ5a7ePKUpYDf1kv9I5GhUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612875; c=relaxed/simple; bh=okZZML2tc4SYJzj0YGY5NcNIBGhTp8dqg/vTqnmY3SY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T+EN7X/vUCThaVmipDAk8z6SJTwnxtz4NzXFlCiUwaepTbDBP7i3rBSOUcu9mnDGuN6SJEJREs1vyS/O8ptA+B4dGDNcGcy+rN+WG0f6sd3SGZYUxTSdFO4UF86lJAGwL9NuulMqyQY5dHdImgHxdW6unwXPkUE9ZcFPq4bd35w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=bNOjl/S5; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="bNOjl/S5" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-434a752140eso2728165e9.3 for ; Tue, 26 Nov 2024 01:21:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612872; x=1733217672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VDINqiI7eZIxSdpV6EMx/C3NNutYl7b6+j2YZ5M4Qvg=; b=bNOjl/S5uwPrg6QR9r4uvpJWWI/onLN+H2g5+ab6xGa7jvGAwqhfeW4LzMiewJbo15 boAuzeEnL353Hth/rk2rk3Hu7A5Jaz3I9yPDzy0d+Gj8wZSpNQ+1qo+++ZnJMPQ6R/J+ j3FcQnBaPbyd4/OD1QzY7DzDaWM5wa47YZUOtc+mnqYxAZhPdLrTm05A56/Wu6gG9Lxu HPGHABZJmxVeB96ztwfaPEfVKqkXedrvb77nFrAt+bcaZYzOUsx1SoW8rsxRwSwFNUrJ jx1+La3RJ3+eIzKd6dCEZCvX2aXPCT7a7So76dgSyVn9K8kwmCrf92IXtk8LcaQKr/Zk X2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612872; x=1733217672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDINqiI7eZIxSdpV6EMx/C3NNutYl7b6+j2YZ5M4Qvg=; b=Tpb5IryyQBihLTCDOFHv4MxcJZMu5i2BCsEYYXUGGUdv/oXWk6JocAGh9MXgZ6k9JI /xHbe2Clz7Vi6VFGlk2mjqYTlwiDoZl+lKIBSQ7otPoXN1Ar+llHvRgOyQJLAqqXqwIc YIeX/en5ARgYe3djQbuBvmJo+GrMjS8f8JFpLEB1+7eTiYb3HWXqMsn9McjYCgILZUQ7 1H08KoLqhcVU3Ki6kXB8sPN33gVVXPdjZEq4TPR8n/PF2XkkTjwpatex9EYk5ox0QkkE J3C8agCBQlpZL5JmrMPcTTu4Mg8bxIetVMELzqNOyqW2YpkGQABMirERZIVw2aefMrvw yHMA== X-Forwarded-Encrypted: i=1; AJvYcCUJvjWRDMdiv0s/62sM+HQJjw4mRwTmx6mtY8GXQ4gqYIJFKB2qhiL32W32m9id8RJEtRVxly+791dwJGK34q4YdA==@vger.kernel.org X-Gm-Message-State: AOJu0Yx6bmwUZwWrH7lRA3lMKkFnenb7hyTjMaQqPwTySdUXDQEklDpl D3qKcMOzSj3v5dXth6BzFwcEs19lrws7ohYQjaxM5ebhXgPnGJ2RKKgWQw9qr94= X-Gm-Gg: ASbGncsxcvVrvU1kdvNQa79XDBsFraBM5+InNCGHNK+42WjW7kp3Yzmu+0vfYCaJiw1 SRn1ECPFGpgXtck99x1bBIitpHMatQGvnkRL/r1rZxyQrwHwc5vNxq0LQ45uaVu/YXpdBnVojD9 TNnfSajH5o6zqVLsEkLSkMfPtN1V7s2ZTwfC2VeO9zNUDPcXazyYHPVuEV8QcwdaRC1ay3J3KuJ osssnNxV7YBqzQqoUyWjwbfSGq+KpMwkb5l9dUyaVvVQ7DQjo3n0QxLUt467rouwi4nKt1xyRqA /hI= X-Google-Smtp-Source: AGHT+IFiAn9ufP/2lxYbOVs5nw6bxrcqi6yQ6uQejelWxHdSz9crLVthGd227EDJ3fiqmZHYRLomqQ== X-Received: by 2002:a05:600c:1c23:b0:434:9e63:faff with SMTP id 5b1f17b1804b1-4349e63fe62mr73118195e9.2.1732612872339; Tue, 26 Nov 2024 01:21:12 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:11 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 04/15] soc: renesas: rz-sysc: Add SoC detection support Date: Tue, 26 Nov 2024 11:20:39 +0200 Message-Id: <20241126092050.1825607-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ SYSC controller has registers that keep the SoC ID data. Add driver support to retrieve the SoC ID and register a SoC driver. Signed-off-by: Claudiu Beznea Reviewed-by: Biju Das --- Changes in v2: - this was patch 05/16 in v1 - changed patch title and description - added SoC initialization code in its own function - addressed the review comments - introduced struct rz_sysc_soc_id_init_data and adjusted the code accordingly - dropped the RZ/G3S SoC detection code (it will be introduced in a separate patch) drivers/soc/renesas/rz-sysc.c | 72 +++++++++++++++++++++++++++++++++-- drivers/soc/renesas/rz-sysc.h | 18 +++++++++ 2 files changed, 86 insertions(+), 4 deletions(-) diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index dc0edacd7170..d34d295831b8 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -14,9 +14,12 @@ #include #include #include +#include #include "rz-sysc.h" +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + /** * struct rz_sysc - RZ SYSC private data structure * @base: SYSC base address @@ -211,6 +214,59 @@ static int rz_sysc_signals_init(struct rz_sysc *sysc, return 0; } +static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match) +{ + const struct rz_sysc_init_data *sysc_data = match->data; + const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data; + struct soc_device_attribute *soc_dev_attr; + const char *soc_id_start, *soc_id_end; + u32 val, revision, specific_id; + struct soc_device *soc_dev; + char soc_id[32] = {0}; + u8 size; + + if (!soc_data || !soc_data->family || !soc_data->offset || + !soc_data->revision_mask) + return -EINVAL; + + soc_id_start = strchr(match->compatible, ',') + 1; + soc_id_end = strchr(match->compatible, '-'); + size = soc_id_end - soc_id_start; + if (size > 32) + size = 32; + strscpy(soc_id, soc_id_start, size); + + soc_dev_attr = devm_kzalloc(sysc->dev, sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = soc_data->family; + soc_dev_attr->soc_id = devm_kstrdup(sysc->dev, soc_id, GFP_KERNEL); + if (!soc_dev_attr->soc_id) + return -ENOMEM; + + val = readl(sysc->base + soc_data->offset); + revision = field_get(soc_data->revision_mask, val); + specific_id = field_get(soc_data->specific_id_mask, val); + soc_dev_attr->revision = devm_kasprintf(sysc->dev, GFP_KERNEL, "%u", revision); + if (!soc_dev_attr->revision) + return -ENOMEM; + + if (soc_data->id && specific_id != soc_data->id) { + dev_warn(sysc->dev, "SoC mismatch (product = 0x%x)\n", specific_id); + return -ENODEV; + } + + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, soc_dev_attr->revision); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + return 0; +} + static struct regmap_config rz_sysc_regmap = { .name = "rz_sysc_regs", .reg_bits = 32, @@ -235,14 +291,15 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); static int rz_sysc_probe(struct platform_device *pdev) { const struct rz_sysc_init_data *data; + const struct of_device_id *match; struct device *dev = &pdev->dev; - struct rz_sysc *sysc; struct regmap *regmap; + struct rz_sysc *sysc; int ret; - data = device_get_match_data(dev); - if (!data || !data->max_register_offset) - return -EINVAL; + match = of_match_node(rz_sysc_match, dev->of_node); + if (!match || !match->data) + return -ENODEV; sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) @@ -253,6 +310,13 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); sysc->dev = dev; + ret = rz_sysc_soc_init(sysc, match); + if (ret) + return ret; + + data = match->data; + if (!data->max_register_offset) + return -EINVAL; ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals); if (ret) diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index bb850310c931..babca9c743c7 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -35,13 +35,31 @@ struct rz_sysc_signal { refcount_t refcnt; }; +/** + * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initialization data + * @family: RZ SoC family + * @id: RZ SoC expected ID + * @offset: SYSC SoC ID register offset + * @revision_mask: SYSC SoC ID revision mask + * @specific_id_mask: SYSC SoC ID specific ID mask + */ +struct rz_sysc_soc_id_init_data { + const char * const family; + u32 id; + u32 offset; + u32 revision_mask; + u32 specific_id_mask; +}; + /** * struct rz_sysc_init_data - RZ SYSC initialization data + * @soc_id_init_data: RZ SYSC SoC ID initialization data * @signals_init_data: RZ SYSC signals initialization data * @num_signals: number of SYSC signals * @max_register_offset: Maximum SYSC register offset to be used by the regmap config */ struct rz_sysc_init_data { + const struct rz_sysc_soc_id_init_data *soc_id_init_data; const struct rz_sysc_signal_init_data *signals_init_data; u32 num_signals; u32 max_register_offset; From patchwork Tue Nov 26 09:20:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885624 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88D021CBE94 for ; Tue, 26 Nov 2024 09:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612877; cv=none; b=Y+xBAx9ChyqbhVmvUQuo5kfMKnhL8/PbOuehabaMzFTw0Wbp0C9XzO66EA5StwYRKsbnr64gblbNc3unY+Vq/tAz1uD7K8LMBqND2cbjbU+iX1MVrfLwAYmlt/KcAhunuTwOq6kECUlLByPn4gx+PJz3GEyEa+OTQKfr3xeXMeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612877; c=relaxed/simple; bh=4F232ENECAOLomVUSY8tBxTq5zAbQQSu7jUMFMN+Pp4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h9qhs/+XBkQtZMKNvq1hbqFGGLYfnLN1fE06rIFiY90/ncP/uAccDYuP06HIyBQyk2oWqaesAoRJFkGXVufLke27MRZlZ2nboD+naNhe3d6QLJMhtt/GPqDex18Ss9OHkfg8e2Bwn7U9BhTeQmRG2vNvBbb+ztXaiipTL84E0Yo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=IirP2PBv; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="IirP2PBv" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-434a736518eso3698415e9.1 for ; Tue, 26 Nov 2024 01:21:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612874; x=1733217674; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LKW3EfLpg9xj1NAX34ulRBb1/poqN6qEBq3WFAZfenM=; b=IirP2PBvcho0H6iTKUBPqaFzZSLbr1s7FmnuIkmTtgERTsDdFAzdIRHukfAB2WgkpW 3vGQapU8wAhXsndg+PAL+Mt3Y0nI5ePH+lHgwdVr29Lmf12twCqc0vR/ABqtQvET9ICv ZgXCMAPJdtcginb9Hy+pvQf6zGMIhJhbuv9PaNW3sS0SF4luQBW3CIvAN5+sHujMMCbZ DZjj1EBi/vf0xotjebPF8mbkXsZ/5+GtFUXqPEnnQ3XH9SxrlFxc1ceFghiUYRAnZvJR F6U9iXNYMBbXmP1x5wJbzMroauFk030pDfTT2bnCCa9snMx7W6fNONnlSsML246LhHnu wnbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612874; x=1733217674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LKW3EfLpg9xj1NAX34ulRBb1/poqN6qEBq3WFAZfenM=; b=o90Ek5d536sw7iNcVQ0sOY5emd2Q2/GoPyJb5d/Job3xQIhkUL672/BEV7rZiG5Apf 5u+2DzpHoObmP3cR8BAAoekzbcldLWfMbF+qr+lF9gmNR5lxfdBpXAaHQEJQQ5fA+WFv BSN96Fhz5OL5slQbpm/QSOrjtusjvT8GVRb5o4In/zJhEQ2pPWYCPH1ALtA7V4KJxinw kvT8wPHQzP2aB0qi6CoPXydYpk5qG1uW9VHBU+ruUzpqkZkx8s19yqtxvG/g3bFlLALR dED2fH6gdPqAbsIQFIvqe4DTBFTD4gRJA4Mmk1oqXgpvFD/X3vQT544LGOa50ViVLYa6 7tZQ== X-Forwarded-Encrypted: i=1; AJvYcCVKKQcWXeG9RkEmwpZ/X97jMKbMFLiEF9Zk678Lfxpe7tEm1RHshqTy2fvQ6fO2d/SbZDOOjUQ2OGa+W4HFww++dQ==@vger.kernel.org X-Gm-Message-State: AOJu0Yxtuqlx5NJzjC2IvvpO9PGRGx3MGzZyPJhm9FiDgZ0MQjWrWIiQ IUmDtDr8HszNIj3dhGbGSWtdplVKsbwi+rg8ng+UNvCXHbTYF5oo1dWYoGDV4o0= X-Gm-Gg: ASbGnctlCZnGeqeyoW+haRtbPAWZRYqMYhFsELWN2grj7kzLjBL4nQxAoIYpffVZwDo wdu6sUVS3wuzyer5bFfz/CP1jjdca9J4EYtDei6p00UTHd57O0uq84Y6LBcKVAG+RGqkjDPZlyg cQQH6SQoas+gneN1BhohH2MXklP3KToskpvIfH4BY1qrfLHsGTbiqHUM8zWhH0USuM2rw9aqiht RpFFge4c5/GA7eOoVf6AyGajCBc05c++/bf86dfGNTPbI0zbN1flzzqallPtXtim6aqeZIQiWMg 1w0= X-Google-Smtp-Source: AGHT+IE7w+dBoCGCxxbUApCfNcapHwRVn5rVPYIN6Suv5fX7t/i3bspO7Ak4XFCK5NYSFpFy53f9sQ== X-Received: by 2002:a05:600c:5122:b0:428:d31:ef25 with SMTP id 5b1f17b1804b1-433ce41ffc9mr177417025e9.12.1732612874002; Tue, 26 Nov 2024 01:21:14 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:13 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 05/15] soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver Date: Tue, 26 Nov 2024 11:20:40 +0200 Message-Id: <20241126092050.1825607-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Now that we have SoC detection in the RZ SYSC driver, move the RZ/G3S SoC detection to it. The SYSC provides SoC ID in its own registers. Signed-off-by: Claudiu Beznea --- Changes in v2: - this was handled though patch 05/16 in v1 - provide SoC specific init data through the SoC specific driver drivers/soc/renesas/r9a08g045-sysc.c | 12 ++++++++++++ drivers/soc/renesas/renesas-soc.c | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c index ceea738aee72..81970db300b2 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -11,6 +11,9 @@ #include "rz-sysc.h" +#define SYS_LSI_DEVID 0xa04 +#define SYS_LSI_DEVID_REV GENMASK(31, 28) +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) #define SYS_USB_PWRRDY 0xd70 #define SYS_USB_PWRRDY_PWRRDY_N BIT(0) #define SYS_MAX_REG 0xe20 @@ -24,7 +27,16 @@ static const struct rz_sysc_signal_init_data rzg3s_sysc_signals_init_data[] __in } }; +static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = { + .family = "RZ/G3S", + .id = 0x85e0447, + .offset = SYS_LSI_DEVID, + .revision_mask = SYS_LSI_DEVID_REV, + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC +}; + const struct rz_sysc_init_data rzg3s_sysc_init_data = { + .soc_id_init_data = &rzg3s_sysc_soc_id_init_data, .signals_init_data = rzg3s_sysc_signals_init_data, .num_signals = ARRAY_SIZE(rzg3s_sysc_signals_init_data), .max_register_offset = SYS_MAX_REG, diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 172d59e6fbcf..425d9037dcd0 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -71,10 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; -static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { - .name = "RZ/G3S", -}; - static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { .name = "RZ/V2H", }; @@ -176,11 +172,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; -static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { - .family = &fam_rzg3s, - .id = 0x85e0447, -}; - static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { .family = &fam_rzv2h, .id = 0x847a447, @@ -410,9 +401,6 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#ifdef CONFIG_ARCH_R9A08G045 - { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s }, -#endif #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif From patchwork Tue Nov 26 09:20:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885625 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3849319258B for ; Tue, 26 Nov 2024 09:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612879; cv=none; b=Bo81yQy5mHzlu5kCSQ9BBeO2OFo0KanCHYppSPlrtGlAltqgXPQt7BxDnju2WUfcSqZvCn+m6LkCk1BcEWbs1hOtxaYRBTWCw/q7NzNiArvmRX/I++j6ErH5h8dDezYwZxHUBvQx1zBkhZUmjhebj+EwLTA08Rv3Y6RoARZp4FU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612879; c=relaxed/simple; bh=peR4Vif7woHWK7GGXYa577M+2RIwJeK0uX7OsLiQUiU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=THtsa1FM3ORkZ1W6Bk17zQYDy6CLutr0Ds9FLXIDJqMknmYn+966pGCCrrd9VYbK2d/HqDNsyYr3bbkW4/d2wVKtV36DaHUyuLscV1cBfeN6ZApzZqxr68BYkosaw/DnHiuBUysMw9X+WE9iEMketiAWUwEG/MSgOHkpB+L2ndI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=k2w87Jjk; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="k2w87Jjk" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-434a2f3bae4so10527215e9.3 for ; Tue, 26 Nov 2024 01:21:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612876; x=1733217676; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sn4qpT/iGLCOuVRl/HhbV74eVKZi/FzZDWa4nL4zSFw=; b=k2w87JjkHiabvDLC4jaRhmjbfFPncA2OiY4Gaxwqmhc5ne188YaKHCRXNjLeianRqW 1493NnWQGtdSNN7Axs8Q3bg5IWUWBQcQm4koKNyZAfBQK5lP9tnG2IWpSf8ULwHhQK2p x+3wNDSM2BDkbdFDIqnl1mGB2g7zjbqy6FGGotYxIAHz90d/iw9dWV1N4U8w0wm+hvbt PrhPOrvOevVl+8ZO9I6tY6+yZDQ7vippzhKOM1YmjuuqY4X2HfkZ+rGlW2KcMSPbtR0Z q/iPzepPY3vNz1N5Ec4far7nRrhIgx3o5mpIdhRuY2o0EFGRlTT1+oGZwsyN6rN+GIlL aBhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612876; x=1733217676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sn4qpT/iGLCOuVRl/HhbV74eVKZi/FzZDWa4nL4zSFw=; b=YFqjwqtXQCQyMRn7D4lsqrYyEt7QxeL3rR5LYdDZMdfAH6TJmh66k8lWc71GTUza6k Hg//2Ktfndn6ICBRs0Tj8jDT5fafp612XdBTLz0Y6WdIuVi3SIgtUZRd1XaHpWRas4Nf eJGt8EGLAykd8r8X97wlWPj8n8qF2xYwJ0dusJRXQaU/f7tI/Su62tauS7+Jbc3b5M3J x4I4u/pPtwFXwAEYSYO57dqOWVQwemjKdabYtm6IZv5HGtM3v1hag0Xyzv1pqO40Bhsw NhR+G0QAY+Id0ZL1ZpFTi7Nf2jMTm29esGIeJW15lAbIJQDl/x9BIp3bAE/xS3kxMNvW ndCQ== X-Forwarded-Encrypted: i=1; AJvYcCV58PeWTd9ndFnrGYa3AqgP2XwaDW70L+DhmOIQW3WlfhZhj/nt+1ghldaumwMIbhy3wslBh7Ni1pQ039I5VGxsNg==@vger.kernel.org X-Gm-Message-State: AOJu0YwteflyR5ECm+qgISxL7Tc6TAAoFOxiWfJNcU1XJFac7i3s7bCv 0RnouVnQuOELDDu6P4GALEmksSLsj8TD2NlGoSGH6csm1DHtgz5WHNgGGJaVWoo= X-Gm-Gg: ASbGncuJSNLH5aqC2qaRghnBbTHArO9gkghIXRd0NrGmGjNcvtF+6H2fsvBlwSl1wwA JrjhRiJBqfFbWukor+UPDBpSXUoSJLfPmjEnxLs9EbNeKDij2yb9hEqnDQ/7dhwmsCIGCB5Ydin EKWDn75nqJy1qjYKHOtMZ0RHZZbi6l34wytIo4/KK3PvxClUm2A2ZVOZSc4fi1iMg043eKzaoA1 bcPwabXUe/HgiVxM3zGdoLCkmWawVW6MM6+fqOXrwLJA/HooyCSGyYto9cHdDFu5bIJpj/CpQ7X gGQ= X-Google-Smtp-Source: AGHT+IEownUh3zO6s9pCDV0Clvw+JlHntDQwx/j8qHfP92J8/y9dWvLESVOAtn+7QOc0lvgJXmcboQ== X-Received: by 2002:a5d:5f4b:0:b0:382:1831:f7db with SMTP id ffacd0b85a97d-38260b59bc9mr13021685f8f.19.1732612875617; Tue, 26 Nov 2024 01:21:15 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:15 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , Conor Dooley Subject: [PATCH v2 06/15] dt-bindings: usb: renesas,usbhs: Document RZ/G3S SoC Date: Tue, 26 Nov 2024 11:20:41 +0200 Message-Id: <20241126092050.1825607-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The USBHS IP block on RZ/G3S SoC is identitcal to the one found on the RZ/G2L device. Document the RZ/G3S USBHS IP block. Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 09/16 in v1 - collected tags Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index b23ef29bf794..980f325341d4 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -26,6 +26,7 @@ properties: - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} - renesas,usbhs-r9a07g054 # RZ/V2L + - renesas,usbhs-r9a08g045 # RZ/G3S - const: renesas,rzg2l-usbhs - items: @@ -130,6 +131,7 @@ allOf: - renesas,usbhs-r9a07g043 - renesas,usbhs-r9a07g044 - renesas,usbhs-r9a07g054 + - renesas,usbhs-r9a08g045 then: properties: interrupts: From patchwork Tue Nov 26 09:20:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885626 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B29C91D0E26 for ; Tue, 26 Nov 2024 09:21:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612881; cv=none; b=Ph4eswHubxloPATDc9stPh2QmiyBXp0qIVGAoyzSJjo+GYJ977HsrC+xH+Z95b18ulIs8i3bBV0Q9+Yiz8W3Fm3VavJ9itf1CSkYiYvD4kmeDwRGi8KPzjKk2wyb3mv0hX5bPqZABqYoolQoVMuedqHt66DUiylM+JVU3YgKCGg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612881; c=relaxed/simple; bh=lMDTraku/x7/L+HfQFFu+VuQD5cryMGir72e5kDEJHE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DPAPe4FyTNg4chwoOFovspInQIplsAM66MH4yNRWYNBog4UWbY8HiDvGQIsWxXTEcD6U7sJPfptdMbxm9eT/Bs6sAHFT/qQR69BGB4j2oAIr1Z8gwYKopZy0nzPYY7GO+1dMNbezXlA6ucPqwuF3n3AvZ9+eQAzLxanoJH4geB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=pR77m9w4; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="pR77m9w4" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-37ed3bd6114so3181745f8f.2 for ; Tue, 26 Nov 2024 01:21:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612877; x=1733217677; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DWc+F6Re5lYpUThTPl2Jyvuy/tQl0uxdBQ2YGVSL9kM=; b=pR77m9w406KSH80pqt+Rw6/mp3tHCZZNEafG65Xyl92uhWFAujhH0fhEOiyG0O8qBR fT3sNtG/pMXSSjkZ6jgF+4c4CBVtxY+RTCfuK8trH5gSbwEIapgP4HYa41DWoqBNd3Vb BiDdVc/p57SwlGi1JLopl9iZ11ITRfbsPSouF2xqkz4ZvXh/0ei+4SWY78vK/KPdscWZ jqaCYZBmt8X9fUgO3BJvEhILEY2b0ucpVV9iaCvXa0vnIdDZFyzvYU9kEilMvD/cypRl WQQnJl32wXtcJb+pn9far95lOTpZ3LrTNx689T2PDlzchg5d6hnOo1vFDhsjx9IQA4S/ nvAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612877; x=1733217677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DWc+F6Re5lYpUThTPl2Jyvuy/tQl0uxdBQ2YGVSL9kM=; b=aqkFSNkMFCL0iM0K2A6SLTPBBl8rl5OovEN5M22wG7p/DYAiZJ3CysgrTuGwpNEBUd bpju0s2m9kocn0idXdQaT5++OjewxwCluOod4aUyhJYAHd5Fns8wzbgWiigtq2MQWRDl XZ389g/yCoq99Kjoc5Q4FS9Ugw2TTcu1zoRcloZrVFXXgn6WNGGzTouepz4dXNQoQ8Lu ziOK8d9jnUfsYVcEdTnkoIJd9PpW8mIzgt6dmZdCVW1nqI17zuk4CKSmp45MGNQRWocD PoitiUUJ0jMlcdf+6Pc3WvH0JIPmNHY3SYfVOMO4I+QsVKKj+Hk9mNtol87S4Y0xg+0u HF6g== X-Forwarded-Encrypted: i=1; AJvYcCUA0IVIln8zQU+HKRknE5Js7RnrgVK0HJrdPT3PZvHBhVqyyCGDDPQVeXXT7kYfDqB/3cnBOH7Lukn+2UnlAGvFXA==@vger.kernel.org X-Gm-Message-State: AOJu0YzLqagzr5TMeJH9m+7TEsfoKTA3hJ1AE8TJpN45nR9G7Yd7V31U lk2D38SXhUzV3qML60LckgAoIj//uy8TmNsB2jO4h7NJB6Evbx0yF8XTUsUJ774= X-Gm-Gg: ASbGncuZChDfR0R7lfs/dhbEVZ/KwgTx3Ucr0EGRmTKOXwXw62jmZNk4UkztIoXudt8 fYodp0mhIQVWEm6tsik7nSDJZWWC5eoHvnXGT7fwD400++UvpzDQJrdTtOF6XIct3GeoykeNvnh YIisbRW4hNhaic2pLmC9Bgtll1mmklzUiL829wxYK8gVfS0r+hYsept9i5O1fDRM4iuSY6iDbT2 r3XmplcIXDUuu7de2FMw/emX6uFfoDu7eUq/c1cwcH1BzoU9hMff2nLgZgy1V1anlRPbLmVMVcm q8c= X-Google-Smtp-Source: AGHT+IG3dGq/ZJlhJq/NurIWM/G3VWbjsNdFTR8iP7hMyFJIs0S9/bgfBkT4zkY71Su/dQBJNJTAFQ== X-Received: by 2002:a5d:6da4:0:b0:382:4115:1ccb with SMTP id ffacd0b85a97d-38260b45f98mr11753556f8f.7.1732612877138; Tue, 26 Nov 2024 01:21:17 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:16 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 07/15] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Date: Tue, 26 Nov 2024 11:20:42 +0200 Message-Id: <20241126092050.1825607-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The reset lines are mandatory for the Renesas RZ/G3S platform and must be explicitly defined in device tree. Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings") Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley --- Changes in v2: - none; this patch is new Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index af275cea3456..2babd200bd98 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -105,7 +105,9 @@ allOf: properties: compatible: contains: - const: renesas,rzg2l-usb2-phy + enum: + - renesas,rzg2l-usb2-phy + - renesas,usb2-phy-r9a08g045 then: required: - resets From patchwork Tue Nov 26 09:20:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885627 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B93E1D27BB for ; Tue, 26 Nov 2024 09:21:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612882; cv=none; b=Oun0ciXB/FUL/L3zY+YHNZHpZM1M2C5oSlew9HirZ0CR3EoWwQkYj8jvP+dqt3IYolGIjkmAnhIfox0TerJYW08R5YuZRHSHKO1igz8b3F/iaPhUfJLVGY3B5cTHdVmec6FnBCrCkzaEHXcOv8Ek+lAREY9TBPQgQUlUT5WJnNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612882; c=relaxed/simple; bh=oNWXU+YttETsW6YOLdXCM5FnMtFquAK1N6LvtZPkJkY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EGumpawsg2oexr15GmAVIBzWDcYPKF7746HBagwBoEVkoh1xvoUbcj2lkFz3LPOoTnebl+2svypLlKZkWwYE0QOprvq0fMS/JVdPhQKDBqVPc50xgNhPFT3Crn+Jy+ISYtD6wIpqGvqQDy9s87iNbWBPUaA3KmaZLMmBmG82dQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=UdSqcXsp; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="UdSqcXsp" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-38246333e12so5354226f8f.1 for ; Tue, 26 Nov 2024 01:21:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612879; x=1733217679; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/jPyHfXjv1sKCq+VDx+r3KGfTA+9eZQsBfgYv3YFZiw=; b=UdSqcXspX4GlVVQ9ykeNkVCt1X+Jj/LfbN9xD/pmohjLFZrU8SIiOVFdfAqhU6jGu9 JZ+GNbfv3X5aPU8YWnehhC0HTItYCE9ZdHtmzNJ3TASEVVg15zM5UfKc+NaGYpgO75ze 0vEC0f6dcALONwYLOHbUmQl/78LTYeEA6ClBTI8On0/dYUr1gnsrjrj3TNfSc+5Dq5NQ e6TUy+XjsODNZ/0g08nZiCmro+mWP9Y7nhf8YjGuL+pp45FCXcAMypVC1GNG5VKCPbWd m3UEO4KValOWTdgC/HRl1F2BxIVluJhiJSNXFJdhf7VqtWX3QgqxFT9wB40kffi7dQad 5+LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612879; x=1733217679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/jPyHfXjv1sKCq+VDx+r3KGfTA+9eZQsBfgYv3YFZiw=; b=UeMPhCijDpr0rGpcmxKhOVC+GJSkrwuKeXd25qfRXyy6I2YN4ySv/ZPXP/rlM6Co9H YuPjnaj05PsKf78IkwR+g8Zw4maMvE4Z5kWVmzSuyKIHKKsgy2HZ4yNv+2o0m6nenDga c/LIi0M9srs1YsM9dztE2Dfp3KGCkI41gKYhyJUQmxxPShpYkuDW5dv8y7CB1z5dHn2a M7a/Bw6ihVnsntpcB1P35Vw4/YvfCA6pAchdYP67xMx+2nlCJNLWRluF8EZNBFJF/gZj rr39eYwIkWXw5Ikn4KNkDrIKSS1SxCbrcEvWv4/9tW0e6JJpkLGXiBurqe9yn0h4neyw BD5Q== X-Forwarded-Encrypted: i=1; AJvYcCURBeqxlrXixzTEcA3UpiRSNMEQYD6FaeRToFumGhFVHUvAVWp7aB/VZV38AgJYILj2iEA6mxJMPUb7TuLZIV7zlw==@vger.kernel.org X-Gm-Message-State: AOJu0YzFB+287OlpLkTsge2coTiIQ9ZIc2850CGlBnBePihEjVcs/0lz jKMZOOnZXwhFSBtRvfTW7tjaVuYdOFDJxOpfq0bDWy53IlrL4QsKgT1P8N06vRA= X-Gm-Gg: ASbGncu6FCjpBTVfLLk3NrGesOLGyKvMqSt9tKOFUzJMwRzA2HSbt4EP/sH/aH1Jrpm fbAGtgbvxNnnvhd78WIXQx9e9yh5p8Ja2QDsk8XO8i7rJtJufq2vFHeosAmGH6nuawDMNUs4pdT Lff2RADtTosAEwcd5yilLFjXw7ahk45RQKrrOVb8f23uahjg/5/aKhJG1e5LUT8JR2mx824/IuF rDEA0oqGYl7SOqX4WidBJZKtLgQXKBmNI54+Wh5QSQbKEx1R2l9LCyvMZODnoj+hFIl7jA9K2cg WOs= X-Google-Smtp-Source: AGHT+IEp0nHr3rTgVabZUcIb7+yLYE3qyOs/bjCx+FjVzVqxsxe18o0APHGg56PeptK8REX7Zr/0Jw== X-Received: by 2002:a5d:64a9:0:b0:382:4fa4:e544 with SMTP id ffacd0b85a97d-38260b3caf5mr16113423f8f.6.1732612879055; Tue, 26 Nov 2024 01:21:19 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:18 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 08/15] dt-bindings: phy: renesas,usb2-phy: Add renesas,sysc-signal Date: Tue, 26 Nov 2024 11:20:43 +0200 Message-Id: <20241126092050.1825607-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY receives a signal from the system controller that need to be de-asserted/asserted when power is turned on/off. This signal, called PWRRDY, is controlled through a specific register in the system controller memory space. Add the renesas,sysc-signal DT property to describe the relation b/w the system controller and the USB PHY on the Renesas RZ/G3S. This property provides a phandle to the system controller, along with the offset within the system controller memory space that manages the signal and a bitmask that indicates the specific bits required to control the signal. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new .../bindings/phy/renesas,usb2-phy.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 2babd200bd98..3b8dcacc3740 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -85,6 +85,16 @@ properties: dr_mode: true + renesas,sysc-signal: + description: System controller phandle, specifying the register + offset and bitmask associated with a specific system controller signal + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: system controller phandle + - description: register offset associated with a signal + - description: register bitmask associated with a signal + if: properties: compatible: @@ -112,6 +122,18 @@ allOf: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,usb2-phy-r9a08g045 + then: + required: + - renesas,sysc-signal + else: + properties: + renesas,sysc-signal: false + additionalProperties: false examples: From patchwork Tue Nov 26 09:20:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885628 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE9C61D4354 for ; Tue, 26 Nov 2024 09:21:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612884; cv=none; b=YLmH6OuekBYCJF6a8EDcLTjKLCz2RqluUHXmV4xhyORybVZ2LANNPtfdH6VHaQHoq/R3QKBn/KUoH6s9V2DP0coz0Zj/DgOA/6bnNoYuN/p6TiIk/YyktwwhN6468ywQmkYoSgBvvWKwAd7Uwf/kcyNqUBJw1JAQJz8UTz6+xDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612884; c=relaxed/simple; bh=NXJDF4MBu7FpvuqDy7MLLxA2AvI4Q3ZGL1Xa7NwdgKE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QcSImQHO6F0dmUwRCTk84hdGzdpjmm4FIxnlVqRIZLEQ2rpbyQMMu8C9MGNvABWkBE3wvfwqdGvP/mHL8xH0Td2kLz15wUBdW0Us0aX/V/jJdd8exKc+hsyU7LcY1nQBY1YhCMYkjUhMLpn7yLZ6w70fNmsykt8JMa49nTLsMH8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=SjlqGnr3; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="SjlqGnr3" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-434a044dce2so20411185e9.2 for ; Tue, 26 Nov 2024 01:21:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612881; x=1733217681; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5TAeC3TsRl4RzsqjkZc75Uu8T1ZZEFzes6iwcvWtBHs=; b=SjlqGnr3vxTaeYiHtkkkYEthgTSp6H25zo0JMQD+O9Tp/AWV/TQ26hYLGG7neB1jiB IiiRtylHgMFMjsYbJDb61/XIk7+EoAUEmfF+gL1Z4Kiz0uVLCW274MbPm5Yn2p8Ah9tx QW900dl64UXQtfu4Mo8xTP9b4ThMkbXz/uqL94SdXn/qGlpWEKQ7wZsS2QSAh2NpzNfF n9t+0/feM2u1YOpk/g632ZAnIwLOlbSu8i6IZraCIf37b26YzslofdyC7zRCGVGqCOaK BgRyXZRUIlQm+HUanifsJBNpSeP7TLHASNH09gygRzwXXTXBq7yXN6+PqA2Ehxv8PEom WqxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612881; x=1733217681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5TAeC3TsRl4RzsqjkZc75Uu8T1ZZEFzes6iwcvWtBHs=; b=C+IOfJE+e9Pnkfrl9eV+nGxQj9pIWQKm8P4HrE5laS0ktjFrDQQasMYLjpsZ4K/cy1 flojlvuzkVct0m8tzui6VsvzTV9hHEjaV3IfacpFnGDGWgHb7LMttDg7jwMwKFlWMRsV ryOaptx0g+0V/109NMFDtqVK595ffKpWM4LXTxTpJoOHxlclQuBpRb01vSzjUBG3pPl8 IeLRiUcPv/6dknSpwjUmhpMY7x7/O0E2kYBLR+7RxJMw0X8d7ObwWRgLb0DB0G8WPOiR TwQCo0TvysFPmR972uZlhlS5YxeyxjEjjvyarxNEc7saPGHZIkM3hpPdvh0tuxR1z3pN qzsA== X-Forwarded-Encrypted: i=1; AJvYcCVFxei9CR7wN1RGZWva3FP3Kl73W+uiEpJbcxN8EuF/B2qwQX8qDQOXQcPO2XFOND6wtVGdxekOlaya3ZEzjcFKKQ==@vger.kernel.org X-Gm-Message-State: AOJu0YziB/t04KpzJ3di3sDIZrA7Uh+p+Qpo/UQXIm9VhR3I8NDPqr5K leMqJqCnk/5PygzTjfD+mpLTLGBUWCmJj0JcILrNnzGA6hTG5El9vkVqUqSUgj4= X-Gm-Gg: ASbGncv9bhgBzupt4VE+jfVi+imK09vs8CyyIJv7fd7dN1y/Se+efYr4ZBbgxrpuGAe rZCE4ozXlVNf6KKa3hAvACfHHBoY6EqY5JJBshoWrz+AbJq96W+znyqu/GtFUt0SDq7WFSvu3em 4JaHsSGHmocq0HgxBCVM27T6KMuDCY63hOYjNMNcL/gid8A32+9HUda5EPgvq6rd7JIU1ZQql6r 2hCTkx9KhjBLd1gxpTz7VpWnWoR0Uj2yl+T9JTklO+PBysXOSKlBa9lRtnXMLHmLnwUKFLsdBrU TeY= X-Google-Smtp-Source: AGHT+IFQeadsuQ2/OEFHNB2hCpcL0kFnKhATIbhwU87IinDBEjK+aOIArcqyehdnhZrcXQg6gOKtyA== X-Received: by 2002:a05:600c:1c25:b0:434:a5c2:53c1 with SMTP id 5b1f17b1804b1-434a5c2564dmr15857425e9.23.1732612881055; Tue, 26 Nov 2024 01:21:21 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:20 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Biju Das , Claudiu Beznea Subject: [PATCH v2 09/15] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Date: Tue, 26 Nov 2024 11:20:44 +0200 Message-Id: <20241126092050.1825607-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Christophe JAILLET If an error occurs after the reset_control_deassert(), reset_control_assert() must be called, as already done in the remove function. Use devm_add_action_or_reset() to add the missing call and simplify the .remove() function accordingly. Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initialize the bus") Signed-off-by: Christophe JAILLET Reviewed-by: Biju Das [claudiu.beznea: removed "struct reset_control *rstc = data;" from rcar_gen3_reset_assert()] Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new; re-spinned the Christophe's work at https://lore.kernel.org/all/TYCPR01MB113329930BA5E2149C9BE2A1986672@TYCPR01MB11332.jpnprd01.prod.outlook.com/ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 775f4f973a6c..59f74aa993ac 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -668,6 +668,11 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np) return candidate; } +static void rcar_gen3_reset_assert(void *data) +{ + reset_control_assert(data); +} + static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) { struct device *dev = channel->dev; @@ -686,6 +691,11 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) if (ret) goto rpm_put; + ret = devm_add_action_or_reset(dev, rcar_gen3_reset_assert, + channel->rstc); + if (ret) + goto rpm_put; + val = readl(channel->base + USB2_AHB_BUS_CTR); val &= ~USB2_AHB_BUS_CTR_MBL_MASK; val |= USB2_AHB_BUS_CTR_MBL_INCR4; @@ -815,7 +825,6 @@ static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev) if (channel->is_otg_channel) device_remove_file(&pdev->dev, &dev_attr_role); - reset_control_assert(channel->rstc); pm_runtime_disable(&pdev->dev); }; From patchwork Tue Nov 26 09:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885629 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 620D31D47CB for ; Tue, 26 Nov 2024 09:21:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612886; cv=none; b=AM7GktfnNFnQ+aXff7hi/ask0nbU+UuoBjSzfq3yB7oDKILLTbKIBvFz83br3C4YsCOIb8wF5QT/eLMFoesoljDiCjsUVHILM2wfKuPT4dgtWlqVKDuqbYOlDHSQlvNpJ3ExN3Mws1M3UWAAimX8OOTRejEKd1jszOo6Hg+vVjo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612886; c=relaxed/simple; bh=M5ukcPKgKAfKHyOFRejl++X5XYltOB0VkZUniY5CCHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YAYCI++SHjfIiG3TfrlmUa335Jo7Y5aTTf/shv6vq0kvagoVUMPaLOJizb6GJ+YbYB5DbMYNLkFm+cNe6ZlDEWWhloFzONsQlZgIDXZrgHJg2mZsi0MD8EXcEkqCBgrK9Cq0TpJGRZ17XxAbSzYPdu1OsqXkB7c4FRzb1uGFOyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=m4pWcI94; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="m4pWcI94" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3823cae4be1so3307819f8f.3 for ; Tue, 26 Nov 2024 01:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612883; x=1733217683; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GaBexvzYFyRAvmFf5CNX0T/OFU5Y8NOKhiyYn5h/HqM=; b=m4pWcI94uKuc0Xmc6HVPbZp8l38puM95OFw0TWlvjptLypGHVqNdKvSaiOnw5ofqqv DyMF3h31akudE2xSvjUhDCb92Fj2+CtEXLITUhSXzmjmngxnBp0lFFfZIOT+P09U5MLc /Zm5NjMO+kDT8ORny/HxNQ/nZI99yTa8jAqqc165ey2XMHJvcSkOCwr6u9P+wMAOBpHD XJKuFcMjLUr3JN1x8YkXT6rORWr9dCqpfQ8XFB7wPhEilDBEKrHHnN9zKN51SCYDVac5 +cdnTMa+lmnY341dpeo69+vRvDbYIrEyd+lOoBqU95pJO9lTNjOXf1kMbz3tojCdefi4 LrGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612883; x=1733217683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GaBexvzYFyRAvmFf5CNX0T/OFU5Y8NOKhiyYn5h/HqM=; b=TLhM501E/08kc7kJSjU6fZB9QoRMz+x+sjoEekkXLAAYMAu7vjdRYVaZmzXRAl7eHL rabjxDGJk75720wtTh5tTg3MfKeTiK8DgOFKETZJ4xVk19dRYG7mTtE8xF8KXC/S23HU XB7CAmcIe78O9NSTrcOHRZbqB/d+40hwgQfhOMj9XNRedotRodR+kSqvYASyDIPTN69d pdI8TUH5hiTBpsvcp6rp6cLJuECqNPlh7mvQtRZcg81UbPZjUX68IYneh+OxsOSL+P0P AjLQuhd4nvE6b4eTaJYuPZcYEcV5efhSu3wKQ9CW/JENjrrdl59RSM60URywAKIVTCk+ 6NSQ== X-Forwarded-Encrypted: i=1; AJvYcCXu3/KaioBMZumko+uBbN2fqIpu4FROncu14ovmzge9kIOhSbEBM8QnpbP6esuDhh3Ie01tu4MWCdcO0CIEk2Ed7w==@vger.kernel.org X-Gm-Message-State: AOJu0Ywrh/kH1OdosMcS+F/vT/58W4IQ29VeNcwdMdGFGDtYMbDPmO84 xCifumPaHYRudorQtNtuyM3Nzd1t+NbefM3Pf1nbxOrzX64mqBjF41CgJafOBJo= X-Gm-Gg: ASbGncsqAhuN9DLz9sx8XV6wBbc2ngLCCrXt382/cXT5VlujANsLRJdYF5Q9UodSI+G GLekR+SOSGlw1WuGAumQ9VuQXrov9tY/+G+jVw/rzpbj+N7KZ5bCIUMahzq+QD3fjSVbrhoYa3d W1s7WgCqlbXCkEuFNUgBCo96/0nuU3K5a7mmbM7BuzFPPOIrec6rMhqXZdRlPk/g2AsSZYy8zho S4jWGkWS1FH3ez7qKAzM5FX2/6aHVaCd9IgJK4BceUxuAG3ba5XjHu/mPDylAtD04zDuCphED9C ABU= X-Google-Smtp-Source: AGHT+IGx29P8JteJsbR7aMf1tNqIx4rHFyFlQRbqnmSPeJkN3FtdMhddq6elNPOMjEa7BoKccqaeCw== X-Received: by 2002:a05:6000:1f8c:b0:382:4378:462a with SMTP id ffacd0b85a97d-38260b759c0mr13201703f8f.24.1732612882831; Tue, 26 Nov 2024 01:21:22 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:22 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 10/15] phy: renesas: rcar-gen3-usb2: Add support for PWRRDY Date: Tue, 26 Nov 2024 11:20:45 +0200 Message-Id: <20241126092050.1825607-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. The connection b/w the system controller and the USB PHY is implemented through the renesas,sysc-signal device tree property. This property specifies the register offset and the bitmask required to control the signal. The system controller exports the syscon regmap, and the read/write access to the memory area of the PWRRDY signal is reference-counted, as the same system controller signal is connected to both RZ/G3S USB PHYs. Add support for the PWRRDY signal control. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new drivers/phy/renesas/phy-rcar-gen3-usb2.c | 66 ++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 59f74aa993ac..84459755adf5 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -12,12 +12,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -111,6 +113,12 @@ struct rcar_gen3_phy { bool powered; }; +struct rcar_gen3_pwrrdy { + struct regmap *regmap; + u32 offset; + u32 mask; +}; + struct rcar_gen3_chan { void __iomem *base; struct device *dev; /* platform_device's device */ @@ -118,6 +126,7 @@ struct rcar_gen3_chan { struct rcar_gen3_phy rphys[NUM_OF_PHYS]; struct regulator *vbus; struct reset_control *rstc; + struct rcar_gen3_pwrrdy *pwrrdy; struct work_struct work; struct mutex lock; /* protects rphys[...].powered */ enum usb_dr_mode dr_mode; @@ -133,6 +142,7 @@ struct rcar_gen3_phy_drv_data { const struct phy_ops *phy_usb2_ops; bool no_adp_ctrl; bool init_bus; + bool pwrrdy; }; /* @@ -587,6 +597,7 @@ static const struct rcar_gen3_phy_drv_data rz_g3s_phy_usb2_data = { .phy_usb2_ops = &rcar_gen3_phy_usb2_ops, .no_adp_ctrl = true, .init_bus = true, + .pwrrdy = true, }; static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { @@ -707,6 +718,55 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) return ret; } +static void rcar_gen3_phy_usb2_set_pwrrdy(struct rcar_gen3_chan *channel, bool power_on) +{ + struct rcar_gen3_pwrrdy *pwrrdy = channel->pwrrdy; + + /* N/A on this platform. */ + if (!pwrrdy) + return; + + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, !power_on); +} + +static void rcar_gen3_phy_usb2_pwrrdy_off(void *data) +{ + rcar_gen3_phy_usb2_set_pwrrdy(data, false); +} + +static int rcar_gen3_phy_usb2_init_pwrrdy(struct rcar_gen3_chan *channel) +{ + struct device *dev = channel->dev; + struct rcar_gen3_pwrrdy *pwrrdy; + struct of_phandle_args args; + int ret; + + pwrrdy = devm_kzalloc(dev, sizeof(*pwrrdy), GFP_KERNEL); + if (!pwrrdy) + return -ENOMEM; + + ret = of_parse_phandle_with_args(dev->of_node, "renesas,sysc-signal", + "#renesas,sysc-signal-cells", 0, &args); + if (ret) + return ret; + + pwrrdy->regmap = syscon_node_to_regmap(args.np); + pwrrdy->offset = args.args[0]; + pwrrdy->mask = args.args[1]; + + of_node_put(args.np); + + if (IS_ERR(pwrrdy->regmap)) + return PTR_ERR(pwrrdy->regmap); + + channel->pwrrdy = pwrrdy; + + /* Power it ON. */ + rcar_gen3_phy_usb2_set_pwrrdy(channel, true); + + return devm_add_action_or_reset(dev, rcar_gen3_phy_usb2_pwrrdy_off, channel); +} + static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) { const struct rcar_gen3_phy_drv_data *phy_data; @@ -763,6 +823,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) platform_set_drvdata(pdev, channel); channel->dev = dev; + if (phy_data->pwrrdy) { + ret = rcar_gen3_phy_usb2_init_pwrrdy(channel); + if (ret) + goto error; + } + if (phy_data->init_bus) { ret = rcar_gen3_phy_usb2_init_bus(channel); if (ret) From patchwork Tue Nov 26 09:20:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885630 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F04C71BA86C for ; Tue, 26 Nov 2024 09:21:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612887; cv=none; b=jSaT/lRB8axnDobOMrM3q031IeidpZpdPNtIHX+3n5+jDmR3wnVbxFkUrj6gQwCPgbHSayFGuPCB9l4xdk7HmA2mOFwqp9/9onYP8fUiep63vVtaKYz1N8XWZxTs415bZvYwFeuPf5PQalNCFDfkndgd1BX6xoJaH565Stv5r74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612887; c=relaxed/simple; bh=65f39XdX+JOlbTHLjNv6Nr2gl6HREhiCkJ3xGoC26cY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aSKw5/XUh71e7IECoikwQqBoE7NyrBuBjA7+dlzNiDR5QHx8dGfCTKVsQb0ADNx1yYkderC/wQYkqtyIUzeZJgEZB8x3BVUeS3tVMtf5/5B3ZE5TsLDhioqqwanNmAYU1UA8/UuJgvdY1VBxen4xqml6XNMFeDf+DD9+2IvOvrk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=m8nlkNVh; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="m8nlkNVh" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-3824446d2bcso4767578f8f.2 for ; Tue, 26 Nov 2024 01:21:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612884; x=1733217684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z4yY5kKHWBOgnydB5P9+GaDat1sMgmo5I0rPUXNWFHQ=; b=m8nlkNVhsaB3jK7XongGdX628G4LHMoP0RQb+Fy2eThGVVjEpYrIwzavXgidYzXjpU Akrc2K7sKR/89kelyfMJHdrFuLjNXnRe7qLuRhmkQL25PTdqWdrLdqfV4KJ7lKxB/Zpe AsBPGroAlW3ebNVbLZ96mDTSxMaeIFRj85CXXA4R0Bu6HfPNCyXQtgrk2t6HhhutSHHk Y4szJqEUgY19SJU1s1cXtwhWV2FIolcF7Op8oeYeKnpetH7MZTiTsWXHmQtIS9K2+2L1 gyHrEC26t/ks/8oydQHYVQ7AmO/LpIoRpakONOsedYvRhYPxKsBRh5E0O5kgtRD89RGD HxMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612884; x=1733217684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z4yY5kKHWBOgnydB5P9+GaDat1sMgmo5I0rPUXNWFHQ=; b=jc7RQp/DhNvhkotrq0QKcEWe0GP5ZoZnw9bIIqGme+cTFFF2kGjyUuPgysebzn24Ay AIhRyNlTXZMpxXX+6f3OOH7Teaiu6KkG0GNi02gyTLyPSrh05sFkjsgTmyPOAFmYkuM5 OZJR2ebnv843se60NroG8N4rw01KRrMpt7iHIi8wNGD416EFjxf11wkbaWBRNRHl6Bc6 k14tj2q/m1sYlrW+r6T/x+NzdHEXj9q+Nb3CKZ2TgQUXnFDXkHMnDyPxAkJSeLq925up fT9GlO3/LyD7+KP5SmTFn3pDxAim40GlOH7rzhQ8VBSdlQSb7/w9ggpUwXIrfAm4eeGX lHbQ== X-Forwarded-Encrypted: i=1; AJvYcCVR5FIBWxkBPixugPrG9ToAfxjlcBum2rv6vF4qYKxgeL6OYGHDAvnEqHox1pMq0MhnHOejEPff9MsU4rWRzvdYmQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwVyX8mBu+8qaZ1BtkahWQisazNdpi+lsouZv6CLiN6rIu/2fvi h/k4+xOn0hdZIabJciMMhIRA13h7cnMAHJLU39FjLwB2gHLxh7X6u+bZjrCoz7Q= X-Gm-Gg: ASbGnct2JJ3MungdGj2dKYuWsAqaoUm0hA6vktrJ8K7DtcV82cLvDWjtToNMQ4gos7x RN1AE/sdYXCjvba+Qte8JEIu9n73+HRuKSri0zC3w0wGZKVw/0Nylj1v1xiKt3YptPzylvGmrOC 7UDzCBTGckR1pGaRndhxXdPwqfTp0oqqNpa72AzCzbseOxBtdfKCvj1mF6pXlNYhe23dTZpo9FV DLGWHbKj4YpgwfeOlxsYE1sigahRA5/vlRKkuFBQEbGWRhYIgYCpTRXBJLqEpaT+idWyodlEiMY JeQ= X-Google-Smtp-Source: AGHT+IECNxqnMdsMr8sIEyPl41XrbsF2Eglii8m3iIb2siIoiQVCnnx0E2A0rJ4JNGhhSHg/JoNpCw== X-Received: by 2002:a5d:59ab:0:b0:382:450c:25e9 with SMTP id ffacd0b85a97d-38260b8ce0bmr16781285f8f.35.1732612884408; Tue, 26 Nov 2024 01:21:24 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:24 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 11/15] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Date: Tue, 26 Nov 2024 11:20:46 +0200 Message-Id: <20241126092050.1825607-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S USB PHY control block is similar with the one found on the Renesas RZ/G2L. Add documentation for it. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley --- Changes in v2: - none; this patch is new .../devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index b0b20af15313..ae59c2dcadbf 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -20,6 +20,7 @@ properties: - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - renesas,r9a08g045-usbphy-ctrl # RZ/G3S - const: renesas,rzg2l-usbphy-ctrl reg: From patchwork Tue Nov 26 09:20:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885631 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AEB11D54D1 for ; Tue, 26 Nov 2024 09:21:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612890; cv=none; b=SN8PW51wFRun3JIlIR5u0HxtTKHkS4YKhvJz99xuVKsvtsutbs1rvQWHpJT5NJiJRLeQXZ7YMKPr8vAhkRrnQpTSGstduk5BLoJ5wh2cue11BRi3HgvRNbBGgTVqwdXAWF6kaq/PwHpK9bkmExBmPF6qF7gn3cHySM5BE9nCxyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612890; c=relaxed/simple; bh=pvmXne3/GLaL56C23pmxfpzVcVguFUnVL4SSDyD6KWQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MGrJywkerPSgOqDoSzQRdPwe9HWvsT3ShohChqg/m2O1OwoyH262bprYNzRXSs11xnJDvsG4aP/55EA3PFP28Egj3pD3mTLSGOzn8NmxMER/v2DuxYsUJtVxrjxN/JpRYEkWQxNa1wV+Csn18UGw9cx/QeJT958vGyprUB/JxJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ghPR0LO2; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ghPR0LO2" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3823cae4be1so3307849f8f.3 for ; Tue, 26 Nov 2024 01:21:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612886; x=1733217686; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E4M5g4cOSJdZAIQtrKw1Bn/YMzw7ikJ/cpvkoOSwCx8=; b=ghPR0LO2pC6YkkfzaTqUNsLDZUcp9bERyEyb9YOZEMdOiWVbT9ZUFiF4YmBxMB+D0h Oub/hGH9PTI18stx8oUicM9Zv//kTIHFTaJtBABe/I3aRfGmPoLTemuM3YvtiS+7KenF 4etSN6/T1d+xHmpNRl2gQ2wJflLDShKIhTM8DEsq3IEBl+VW2rNNIJ6/mP5pXZ7lH5k3 lWbWjKdZZaU3XAhS2/3vObsoLDHHN/fZ+64m0/8cHOgfGUhrCaE+r/ZFB9lpkc6CP6c0 OGv6geeuXZTSrY93GlZvKwdyTt3Hn4StKrUnGsFGMOsPjmoCujOlRkDXis81DAb8yqy0 s1TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612886; x=1733217686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E4M5g4cOSJdZAIQtrKw1Bn/YMzw7ikJ/cpvkoOSwCx8=; b=WTGWsN9nspIHvSAbnkNk4xCGdz0eQs/S8vhv7kWP6CRul+LPsTz8Lq+yQ9PbsK+mQd DvaozThADQpZqEk0kQ5owR9xp2NeY3gsfz13x4L0hzWHik0uIu82HKBbsNzVGF+RVYPa ehxkYs5VKNbprVE6Hzx/S10e4fTgi7dD7Qu8VfuYAJvvFOOsa9h0ZptkQIDin9PXj6Fz NktA2OXo6Cn5keQ0V6eXWbHlPk+lEKKDjqRwtPRkbJEqpD5X1ZuYWy5a617x7XBBmYms 0Xg6V1w6cSI1VK5THOc8TTzI1hl8X1CuGUTJkdv6H2jPJIQEa9Jx8uYTKfTZMh2uVO8w G4lQ== X-Forwarded-Encrypted: i=1; AJvYcCVEE4qU1Bv1zVk943U6YAmBX9OPzysWEp6ssNlBce90vYzDXtitY0MHskbI0haejSW7n5ovH75s15U74kfFk4o57g==@vger.kernel.org X-Gm-Message-State: AOJu0YyRMFqvBoDxFeaKjcEQlq3IYHn/OysEs3Hwf3zcxSOMJ7EZ6vzn w+uPUmu6/Gl6vX9sDWBXQSNy87wvE9oyDMEQMbu0sjlG4z/XKXxql7Tvrd/EFBA= X-Gm-Gg: ASbGncvfCzcu99Ei/KUj1vqgUTUp8WeMwCMe/qnh6RnXXOFy90/J0ePiSRLIp+G5oDW myQR9uHymqc5qH1vtvIg0akmKh0lPFI/6BdN6a5ASz/aabzOqgbCs4crhRf6YLt9s5EvzevHg1r S+zZaSodb+MdMVy47+krsGNdDP8ttgsGEs9CIlK/AejnwZxYzo51KjwIkBpoJKKfCt0FdAwPIQt ihyrsjUtoW6+HS1/2fm367ig0pZ+TRlYhpvVn0FXpiNasPplcRlovdvRKzA+S9nU8Qa+F4H5NeC Sic= X-Google-Smtp-Source: AGHT+IFFCuS7xBS3otNkuGr2IzoMyH/CTvsuJMT+O34OiuKVD91ks7D0BrVopsaLaBF4QZUasDuXXQ== X-Received: by 2002:a05:6000:18ac:b0:37c:d1bc:2666 with SMTP id ffacd0b85a97d-38260b502dcmr12951812f8f.4.1732612885919; Tue, 26 Nov 2024 01:21:25 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:25 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 12/15] arm64: dts: renesas: Add #renesas,sysc-signal-cells to system controller node Date: Tue, 26 Nov 2024 11:20:47 +0200 Message-Id: <20241126092050.1825607-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The system controller on RZ/G3S can provide control access to its signals. To enable this, add the #renesas,sysc-signal-cells DT property. Consumers can use the renesas,sysc-signal DT property to reference the specific SYSC signal that needs to be controlled. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 593c66b27ad1..2ebb951e6a39 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -585,8 +585,9 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g043-sysc"; + compatible = "renesas,r9a07g043-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6b1c77cd8261..9dd229cbf288 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -877,7 +877,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; + compatible = "renesas,r9a07g044-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -885,6 +885,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 01f59914dd09..31550b8c3143 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -884,7 +884,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g054-sysc"; + compatible = "renesas,r9a07g054-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -892,6 +892,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index be8a0a768c65..169561386f35 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -198,7 +198,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a08g045-sysc"; + compatible = "renesas,r9a08g045-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -206,6 +206,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; From patchwork Tue Nov 26 09:20:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885632 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EE861D5AB8 for ; Tue, 26 Nov 2024 09:21:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612890; cv=none; b=JJFGVCGwx3nVBiCV3obussFLY+YhI29mKZSiZVVTDhTq6hPIBysoPlSLM5bJnsHPqHyLoGTBzsMUU9AsDfrD+dz+EmoJkjbTWRzQi2LBDpU1a+KNj3Xzl4O6kYCyLJuXezhHgc2Ub3wyyz/3XMJGwxHIPNq3J6gmIFMcOgZQROg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612890; c=relaxed/simple; bh=yx8G5kN1dPvXv5haopV3811q4NYnuaEFQqxgpb3NT9U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LtcAxJm6h6yV67V/fAYb0SHqUUte/r2wG/kHJmB7z2x4bkVXxI3kfZ0Xl2IIDuyARBJxQ1pELbLIYLRgX0X9pRcJqUiYVKhVRpqdLF4rD3N0qm1kPfKbCePfcxv81p5AQXHmK87d1afebl44LJkO5FP6wcxiL2sz020q1ucFkSU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=NrfxCNhi; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="NrfxCNhi" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-53de8ecafeeso697671e87.1 for ; Tue, 26 Nov 2024 01:21:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612887; x=1733217687; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YL9Ut0Si+rVh2q7F4JB/asIqIrf6jT+s8Jqs0j7Utvw=; b=NrfxCNhilBiejXHT9F52bpfhlKI8cP9bJGB16MQHlKRZvZwLiRszjJ90dAXJHV2zue VnJV35XznayLZuWj+EUz+sY9/XHmgGqjziXqcjSTzs+zUZ4Oh2HGpGWJicTe/jv9aw5i zKXCZHUQAO7SN2TmaGYUx5K8ioS4bH/T40pMN+WVMo3A9NAOu6iL4jSjycvU5FIOgKyu glDKSLCbYapA1ZzM5HtN+VR7zqxtLgVt1xDTlSPaXJpUMEmF0+rJQif9qTNO4xyMgb5E eGrF3e71XVu8bB5N/ms7UHFyUjoP9NdCjY2HrQ2vUoeBoE20kBz8lpr0gSW69LHIiEa9 Su4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612887; x=1733217687; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YL9Ut0Si+rVh2q7F4JB/asIqIrf6jT+s8Jqs0j7Utvw=; b=C7urxnt5hBOuMVkFYHZnfFHiH9FIOf/5WjwCLBxxJFnTyAIupbJwp/BVLOzs9nobvC YvrxPrD1gG4jyn6Ppmka75sS0wgVANmfT2YxTyhYsAUnIpR/D5eL9wHPAtt/AlWJaUzo W7UhSDl9j6xhAMPchwps0mduT1dgMX9rkt+WNl0pm5Mc7h3E+zQ8soVAgn2p5MmwolW7 dwZpNTo3RnrBjN3Il/m77BMSlNTrf5ulzD3qZIKRB/XqRpAyEQNGL8eBDkralKje6tTt 8SQGVyOKWMm7UctzBgwEsTiyYZ65uExuLmWT3NVumF5UHCptq/lNbDylTS+gKkmP//eA D6jA== X-Forwarded-Encrypted: i=1; AJvYcCVBZxq2xmMPmgEPO41or6qdJyLtRn1ubnagwcs7/7/2BTYNOoci/03mVdxHLzkd4C1wXYkeVi6mJZ9v9vexGx9gYQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwrE9Hatfn5HJoWAXyPmR+hqCfE3u87E3fvRHUAsTx0+U2nNDXG sqvPnK+JuzdtWYQ8hUd9F9OuMtVF14FIoQGXwFZQouHod8YKBoLq9nyiQqnd+v4= X-Gm-Gg: ASbGncuyeWAZFGLPdc0rGQw/lMzwGlNcaPKWbUR5l3629pqtwA0gfqwsvPs7fmPnb83 PpXafSa4aHxJoDyiPa3WazPPsdvnWsnyytCfpmf3rL8AFvkl3oOHEehZ7PE5zyiklEmHMIvypg7 4WdaWZnjpdDVV1xOFLRodeAf0dD9qqH7CWvy1VJyFdRQHbDDIdSRZoS7TOE45y+3qFRqdYlMC34 WPToYensAG1pDFSG3PFetW3jQoSzXFdpG6/ETz0Ek7gv8/2Xgyi+QbGcak0A4RU1XMSeDcUv9nH bUI= X-Google-Smtp-Source: AGHT+IEqjpoyWsGOaOphc9gwJtzIyZu0gka779JBN5g8gKK1cf1hZ2MPQM9ajRauQ6fRNW3ZJEX2Wg== X-Received: by 2002:a05:6512:e86:b0:53d:de36:7069 with SMTP id 2adb3069b0e04-53dde36707cmr4605894e87.6.1732612887547; Tue, 26 Nov 2024 01:21:27 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:27 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 13/15] arm64: dts: renesas: r9a08g045: Enable the system controller Date: Tue, 26 Nov 2024 11:20:48 +0200 Message-Id: <20241126092050.1825607-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable the system controller. It is needed for USB and SoC identification. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 169561386f35..89cf57eb8389 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -207,7 +207,6 @@ sysc: system-controller@11020000 { interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; #renesas,sysc-signal-cells = <2>; - status = "disabled"; }; pinctrl: pinctrl@11030000 { From patchwork Tue Nov 26 09:20:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885633 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1197F1D5CF2 for ; Tue, 26 Nov 2024 09:21:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612893; cv=none; b=r5Uu+VlopLk8pr/VpbbVbQh0i6/haoPmXYlb1NBpewOBWSCeV9cybgi6FKZmzKj7zNogfWESzeO0iNgtbt3AJJltyl95B3rcRrlaL/jMZdyjmkqTqGQDE4wAg/0PUl8GVfrJzjWPbBXYo4U/xtqFJx+q03SIoHrBkH8uqE9rm4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612893; c=relaxed/simple; bh=2DMTJUAMbvgwMO6a642uq7ua8fsNBEbd1Oxy7nZyQa8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hQcta+ZPYlvOMWuTohqx6AVJYEhdTNypXNR5EYhaXNF4jJstrAJuQq4lOdLGOc2/DlyzPHRbjRFmaYiYDVAlOOn/FHCR1lZ8BaEfuKiOXjZMyTIg1Zob3CBBA3Y/D9ikhZVuFo0QYGdelDEbPgWimvSPpTf6je2T7mO7lspHhXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=GHKxhmxe; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="GHKxhmxe" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-434a10588f3so13280355e9.1 for ; Tue, 26 Nov 2024 01:21:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612889; x=1733217689; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qLdnHZoveqIvO5Hl0Ml7DeyDrz+2Vaoq4NvOVCNrZ/A=; b=GHKxhmxesIrI/tdCGHSbmOfQHu6ELwNJAb70ipA17qFwm1GMQH19ccoVbHToRt9Csd 8ZMaa8o9HGLQMySu7g+3G35vE56oMEIkRSZwp/gwiUQTNyOb6Zv0y+J85OrZfkT4K9KD On+9M8MDYDVrBBmofSaeo+X6YOUyTX4PIKCxqhKrNeQPoKffc+oATZ1anrOorshIcM00 d9icarOpmzQNPzRMOOC/h+Ae6rtjfLsOlzBvmmm6QiJ+8cZroT13MoZiWwIytjRS26kY TTZgblhCkoouhIJmS3cglEKtKdQbv38tWxcK9L/teWhzlrUDatIygv/HU1BWOQpP/TnV ZPTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612889; x=1733217689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qLdnHZoveqIvO5Hl0Ml7DeyDrz+2Vaoq4NvOVCNrZ/A=; b=h7YTlnTys+4x6zFpPb92zD5YyZjR2U9+W/5km2YxVtWzI5H6YMq8x6MSpyKfAKYfTS QTbbEQCydtDDBbSsNUqH/HSZcKjRJJ65I8B17rCgcto/qij1AI3g/9SIFjw3IwDHQYcv 2ET10BMUyvyMROs1IbISOwsG/LfB/GwCLIgyWGucfSpPhui4izNl2v+rBVUy4HVAYiwE wArXV5ihNgC3/OIDSYJCTWlfhnKGyC8G5SGMisOcg+QhXll5Y+rpgZ+jaS7aGOFsp6aG beHNg5/qgcijf7TPkPrrdBh031xL4E/LR2OyQHAnCWXvtrY+Nv+wyAVp4DUEhmnpwJuN 2kEQ== X-Forwarded-Encrypted: i=1; AJvYcCXVxDz0vzQeSW0X/HUlxw/dMj1IeTJUvvbI35qt53dJBSp+MCP16fMuVdJkLFmLbfpKXdiiO4eV35exA62wC5oFKw==@vger.kernel.org X-Gm-Message-State: AOJu0YyUd55iVLOAriQlJx3ELMK4PERuf4e/Kx3mItt6N6oBf7+muFCx xxM08d6rOtOU0palS2TajcGIupHgAX4YAbZGJfoP2KrmnQiqvHv68Cu0iaLfnx0= X-Gm-Gg: ASbGncsbQAZiVsnKAU8jnu5+1HzZACpf3+BYtSVT5pQSWFLyYiTvgl/0CX/e27lJN9/ zqnBVy+ZZelS1PAXQBqBU3zecikhfM0X2j+YkTsg7Ak9FGzr6hiHc+B5ItaFcMDM8e0MSMKBxeP 0BQ/V1M71FPEmfSnD5dfGnpS9WgO7YorQYIGqwILXXiGSPBAVHiYtYFX4Tlb25HD5eQR4TjN0+4 gyR+pPowppuagkkLaBIh2d6B8U+g7KhJ07jXBrPxZUnoEv74sCSSFmZGXvtQJGvip/20fWj0g/P A3A= X-Google-Smtp-Source: AGHT+IFJiTv231Q0pA7mNGDg8+ehro7YZHPIBfZNFr1G9xSWhy4hE646eb2huz0yqoJ24h09vlKStA== X-Received: by 2002:a05:6000:1acc:b0:382:450c:2601 with SMTP id ffacd0b85a97d-38260b6b632mr11281224f8f.24.1732612889501; Tue, 26 Nov 2024 01:21:29 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 14/15] arm64: dts: renesas: r9a08g045: Add USB support Date: Tue, 26 Nov 2024 11:20:49 +0200 Message-Id: <20241126092050.1825607-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 14/16 in v1 - added renesas,sysc-signal properties to USB PHYs - collected tags - Geert: I kept your tag; please let me know if you consider otherwise arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 89cf57eb8389..6ce94bbecfa6 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -417,6 +417,125 @@ eth1: ethernet@11c40000 { status = "disabled"; }; + phyrst: usbphy-ctrl@11e00000 { + compatible = "renesas,r9a08g045-usbphy-ctrl", "renesas,rzg2l-usbphy-ctrl"; + reg = <0 0x11e00000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets = <&cpg R9A08G045_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible = "generic-ohci"; + reg = <0 0x11e10000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11e10100 { + compatible = "generic-ehci"; + reg = <0 0x11e10100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e10200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + renesas,sysc-signal = <&sysc 0xd70 0x1>; + status = "disabled"; + }; + + hsusb: usb@11e20000 { + compatible = "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg = <0 0x11e20000 0 0x10000>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11e30000 { + compatible = "generic-ohci"; + reg = <0 0x11e30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11e30100 { + compatible = "generic-ehci"; + reg = <0 0x11e30100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e30200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + renesas,sysc-signal = <&sysc 0xd70 0x1>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Tue Nov 26 09:20:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13885634 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8D011D63C6 for ; Tue, 26 Nov 2024 09:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612894; cv=none; b=SbpHSJyJsNmoatAf5Dl3TlM7RKif5Civ4y2Owd/0+N9SVE0pdfp2Z/zZnV0jggqByalN49LbX0Eb903CVPB2PC6ZKX8S/pqDsObr7jtsF/fRtr2jYbosXc8B7RhmKwPbVWtq2A6K/UK/UcQwi1Hco9ZBlHT4kVSG05xu5hWX4w8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612894; c=relaxed/simple; bh=sCMOLfdCfDxxCZrfpD7yC3KBNfJKGT4d6K4oqUP2q/o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tT0YoEjFm9fvNiSTDDveUJA535smc8Ay5JoRra6fK2YRMsWO4mkWoiyRQCJPPtMFyxVglQpR+so1acfC+/D83m9EdLHqfFzs30P1r8Y0tSba/eACNzo2QXf90r4uwbkU4py6uo/RL6P+I/bBD6nSaf7Ak0cygCcQWWJg8CWj/no= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=DReuwvzV; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="DReuwvzV" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-3825a721ae5so2977756f8f.1 for ; Tue, 26 Nov 2024 01:21:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612891; x=1733217691; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WCzqc2TaOMYXuzsxltqgd9yUEqr7UmmqRYfJJbdxixs=; b=DReuwvzV3wTK2sEWOAoVa626fObujUr0SEDjx5SVhvI01JdJoR71zoMkZrScwH7t4t BtaO9y+QIoZyTmjaUTZYBbVgEHNivldhvKowYOP183h7pIBVR+XqdsisQZN+LqGR5Cjj lOWBebEijVtZpL1CFpu3fbnOZnsazafyGJF246MiolVXc2l609QJJ/5bQCBNcj/Rg0L5 49Yf2TcYBI2eZsPykwMyJHytA+zyDa4PKFRcmdVJnFXZZDC/pfneJx8UUlO9DjzoPm8x 8nTh1G8XCQKoSds5PRUoX2Fp6iaDBsvRgGohLfLV9JFurlqhE0v0t27xowkzpWdEQouo BYLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612891; x=1733217691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WCzqc2TaOMYXuzsxltqgd9yUEqr7UmmqRYfJJbdxixs=; b=VR2wyvIi2m+a5tLpYdqGUTaLph1QFanmSuMyrw3x+9a/1xI5xgcFT1W6Dj4eyssqNa niA4jtt07b45dE0RvnbWmFmu/W/5CiGmDPK+KqXnSFtMkAsNGNP1y+ezECqhSmxkxRNf Q/VGr4bHG8QBxsmwvzlTTmEJgAu4svW8dS+j7VUEhflEKQ4kFK3gLcJ7UblteeH8gB/s k1HhGZ2PM6T9JFHDCu1XTuwcVDmOjP9pPZbx2OeAB7+lzuTE5s5mSfYFWLOx4nqJLNCa aqrvl5H7JIrQjlUIn0uM3O6C0xY+GR+4tDPdD3e/Pisnx01QW5+4ASPzyrUCfFbx9w47 G39g== X-Forwarded-Encrypted: i=1; AJvYcCVSVpxaLtvsQ1FhHBWYNzDC7xcz+xeVY4OFW3rtDzCK86h8fC8zIbJYqO5rIGEEraHX48pnPzU1HM+AvynMzRjwiw==@vger.kernel.org X-Gm-Message-State: AOJu0YwvuHqTEjPKwJJwQuCx/7D3RyClKjIAbmNHEgLRHgiY2zRKJWLe B0EVAcORoSOdgY7WxWpHWNzwFUfaYti4RV5yqprqwpZUWZPNvCYZOWd61IEKQyg= X-Gm-Gg: ASbGncsBeMLZQgqGVDwiW10c86miEsU7fHjKvJ+UI37mh40k+gw2TMR6cG3/Nm/GnBI WwuuEwssNzySDZxQ+gQN9SQKkkQ4XzuHQVlwz2nvJSlvONG4oUN3+pqhYpAYili7os/iMwnxkck UJZaKI2iJmNOKO4uiioLO45sNbC6tQQ0O/dONfM9s6QlWpiIqrQxq9Xmkwwm/U8UBTIiOk/gyQv kmWGG6g0nWYLZUlPgivnzmcL27k4Gw3ZiU8fF3Sl+poG4q9N3Q1HhFabuWWq3DqtuPrtcwj89K/ C9g= X-Google-Smtp-Source: AGHT+IGt16Gf28ygqBUeg7Z1sI/QNXodT7+mOuBvkflJeOYMzIEcDxZQSC743PyULKBWHu6xn+lhzw== X-Received: by 2002:a5d:47c5:0:b0:382:3cb8:bd4c with SMTP id ffacd0b85a97d-385bfaea942mr2316685f8f.12.1732612891193; Tue, 26 Nov 2024 01:21:31 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:30 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 15/15] arm64: dts: renesas: rzg3s-smarc: Enable USB support Date: Tue, 26 Nov 2024 11:20:50 +0200 Message-Id: <20241126092050.1825607-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable USB support (host, device, USB PHYs). Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 15/16 in v1: - dropped sysc enablement as it is now done in SoC dtsi file arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..84523e771ebf 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -64,12 +64,35 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <1000000>; }; +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; @@ -128,6 +151,27 @@ cd { pinmux = ; /* SD1_CD */ }; }; + + usb0_pins: usb0 { + peri { + pinmux = , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux = ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux = , /* OVC */ + ; /* VBUS */ + }; +}; + +&phyrst { + status = "okay"; }; &scif0 { @@ -148,3 +192,16 @@ &sdhi1 { max-frequency = <125000000>; status = "okay"; }; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +};