From patchwork Tue Nov 26 10:22:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13885760 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 570061C4A1E for ; Tue, 26 Nov 2024 10:22:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732616581; cv=none; b=FqeXByKE3VHr3qI8OUhrAxPbB2YbX7w31etqBM4C3I5lFO25m0ZYQVI2bpmRHuB0XcIDaGmD0cvz4Spc68yk4ATLp4zsCA7VnNJKTra7PPZ8KSQ5DiwEb2FFM1xshjHuThbwGaPYzj2lFv8S0YCfSc5wqmNnlvXy6c7UCZ3Jhew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732616581; c=relaxed/simple; bh=3y33KwWV3X6ptS7V9W6/9HJibX4ha/yfLJjiTJa0VgA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NlY9rMYgJrnOa7PpvS/rxpFLb5ocEGNwIwIlLOZUt3Rbyym/J83g3DIy4tnTcPZ3aS/eDORpJoXEFajxWQM2NljDNBJ9iB/K+Y7iAOtob+yLT0iHnJ7ExAJTB9oYh6iPh/DAbGjF2FO+zjHdZ9/Aob2b79ValHhoc8hZ2xC6Bms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=l15ybey3; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="l15ybey3" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-434a83c6b01so1444055e9.0 for ; Tue, 26 Nov 2024 02:22:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732616576; x=1733221376; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8o3l6m5vwxoJdK2INVmuuDNErcbA+zded2JvEzJ8vLA=; b=l15ybey3Wds6Mdw9+HRTeyivx1Gxq9fLWS9k5R4bn733MTPr38c2DIScteg6gtbio6 b/PmtddDWaFHCRt1V0O4U8MRyFJTSMFjvZqTV24tojB6NxapBOwrEYovzGMvOpIrlljv 16ziclFEfwn9i+pqTxFbnC5qIbsnEvWebih7F/TTGnwdY4I2zGzuwSVygf81JWeB+faG eyW0HcQ2oHaKybjMvc9am2cRKOBJWohO1N/bAobu8VeF+0ilGOiXmIt4HwRFAUbuaDr0 C8tyvOpTOwTtbzI6WcaIZseoP4c8qXNX40oZaja0YmjEk3/GKS1s2NeW8E35cx9WAtcK 1DVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732616576; x=1733221376; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8o3l6m5vwxoJdK2INVmuuDNErcbA+zded2JvEzJ8vLA=; b=ILAreGSb8rnb5X3fgfILROX1c9Dz3Hss1e0Bh+lsi3Dck2ogQSEJf2DofxObxgdoiG bhnS8i2R57dlZFHyuKH34/rmKXe2qVilJop0oTwmyGt6QCyyRkCL1QjTKnemNrLBoVdw 1hS1mta+0Z2lYFwUW+yk4ezNH54e55O7yUGBcg1QvQmEaBbsgFwb1RNza+nf1A0JdFbQ XqNTelj7QuG7DvdHi+90eM9KHW3yG28nEminhQv5wKLkZ+cxpBFT49mWTh97vTC3Jufp Q9fq4/fjZ2GcxwhRu5DEEhT1wOaveK/K0RUh4vSRh3NObnewz5l8mESF/Zh1fEwwruBd p8dA== X-Gm-Message-State: AOJu0YztZK+1ar2Es4wOVlgGgro6Jo4SJCJRW+UaLKTKuR+rE+IPEisN TqMBxLD0U4K/dwPqYfkDifF5Bbw8Swv3m/gLqCYV/OP0nDy8IoqSFtTwGrD6Ybs= X-Gm-Gg: ASbGnctfoPIJQiyTKCJy7ggN1OUAf5H3KZwNkw759ALNPeU/0JaW1opAsUOpIwiX8ot Qmd0PkRkdKDLNin/LX3/4cZaGAqIJ+Y6YbRnxUEn3xjfYr0s78Tn8OtJ7tk9Um9w9OqPsfcRs64 D41W/4A6efohNnealhirXC4HTMJSuyyEMnzRLBVDCbxtoXGiHHISviKuZv3zp6QXkw5U9Z2X2Gi TerG8USormdcwhaifLENFU8J4Ibg5fml8bg54vxHxzcxYExbLFyKl6YfZA9gT2yTwelrRw= X-Google-Smtp-Source: AGHT+IFD1SUZK/wzIE5wrG+sA6a7sit0Bs1O5qLASWCEnOzhJbRnej/agfqThpwvYDHI00Fmt8odsA== X-Received: by 2002:a05:600c:34cd:b0:434:9cf0:d23d with SMTP id 5b1f17b1804b1-4349cf0d3c9mr68830285e9.25.1732616576639; Tue, 26 Nov 2024 02:22:56 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433b01e1046sm228378075e9.4.2024.11.26.02.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 02:22:56 -0800 (PST) From: Neil Armstrong Date: Tue, 26 Nov 2024 11:22:49 +0100 Subject: [PATCH 1/3] dt-bindings: PCI: qcom,pcie-sm8550: document 'global' interrupt Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241126-topic-sm8x50-pcie-global-irq-v1-1-4049cfccd073@linaro.org> References: <20241126-topic-sm8x50-pcie-global-irq-v1-0-4049cfccd073@linaro.org> In-Reply-To: <20241126-topic-sm8x50-pcie-global-irq-v1-0-4049cfccd073@linaro.org> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2273; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=3y33KwWV3X6ptS7V9W6/9HJibX4ha/yfLJjiTJa0VgA=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRaF9wevUPdMUYIutNZvInUfAq/oBR5ApvS691s2M lhUxmR2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0WhfQAKCRB33NvayMhJ0cclEA C1iAj0zWzZ9YFUQdMHFxz1FrUJQLrlgSJw27jNJt3k8mgVXcJUZbRbdqqwtiIa1D5aZcldv2+v2KVB A1yG6l2UsGgLV2ciLU/cVdV1O2B30t9qvsNQ8Qtj7piyKchR+ekb1PJrDDmWXrPGoPd2/ek8JfLMAr HixKHM3zOQ0TRiimKFnfhEzZvf6kjd7CIB3zbJv3IniINoDP8xeuWSqm6ct2mB4LDkuU8QBvdiIYpW 6AUnrZZYidpu9d/2XPHIiu12S5XLJRUuDUv+POeDEFhhw2rv7LD1yolHog6qq6b2a967zUvupRLyDc 7iv51wUH5MuS9HvwvLhRz8o76ZwdFXAWDuqgbmMZ2s8H4K+y9h7b/KnJOD6jfDyRm7mYlNOTtCqdef Gb+NvobOoIVOpDgTiTSeBTybAytZPRnEntaMRpLtJC93ufg5CuAeTrhqOzle8+us3nfrr2dNurSWbg PrRRF6J/Y2+hv7U5BIO1UyKzkCeMCs0SItNbzzc84UbaVZLkzje+STMKlVz9LNmtJ9KuWiBjKf9t57 6TDSOJav9SnhElCnN84XBG4VS3fkvHcmUUOwGwUgYrM+F4j1k5Ujig1TjZl+aJYEDH72AHnGPrp29u wngL4wOoKH748Y9301DM3/SySc3+VOU/umwG61CnYU+BGggB9Q7vVpAz9Z8w== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to handle PCIe link specific events such as Link up and Link down, which give the driver a chance to start bus enumeration on its own when link is up and initiate link training if link goes to a bad state. The PCIe driver can still work without this interrupt but it will provide a nice user experience when device gets plugged and removed. Document the interrupt as optional for SM8550 and SM8650 platforms. Signed-off-by: Neil Armstrong Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 24cb38673581d7391f877d3af5fadd6096c8d5be..19a614c74fa2aae94556ae3dfc24dcfcd520af11 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -55,9 +55,10 @@ properties: interrupts: minItems: 8 - maxItems: 8 + maxItems: 9 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -67,6 +68,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global resets: minItems: 1 @@ -137,9 +139,10 @@ examples: , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Tue Nov 26 10:22:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13885759 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3527A1C5799 for ; Tue, 26 Nov 2024 10:22:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732616581; cv=none; b=YfHnsoZ4K2AdBpjxVjFjIv2qF4u/5Bb6REZNwiGcZtYffjH5CcrifM2R68M48HH2qZ9evvJ99acqieCbCfqZl6tssyoW7gLX2+0kXWU8jpKnV395NkoBRjCsTxJ4VlsdjBTlBlEJGdJgaFreyTX+dFMx2n5VvWkUQxIXlDlrCRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732616581; c=relaxed/simple; bh=DSfkUxtAoj5mu81yWWFvAAd0RzmXItr4kWCdyj1bISk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BtZIDvvxQ77/DcDcvIOK4P39C4I7qXamffZ2HZR9oxH/CQ9sQqbGv/cQY+JuEx0ivFgj7uFpPktVBZ7SUpXPAmQs6kI5zvDZlmKxJmEm5oaMyKdDoh19/HasmkB9fgl5NAgCVbZI/lq+1WwaFaIGn8dWMQ+H8Yb0idhAoxHMwk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=S3bJ1CGm; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="S3bJ1CGm" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-434a8b94fb5so749785e9.0 for ; Tue, 26 Nov 2024 02:22:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732616577; x=1733221377; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yGY7qn3T/vVH05XwetJnmcN100gMBe4kn/nqWGga67s=; b=S3bJ1CGml+rVJGVxl4jTciWrCEhbfod+SdDcZiH5zPZbRcQ+og0nmEeMZcEtFuAkof tm6KGVXO4YkmOIb1I+BZZiE8YfafcgbqDJyvJxXNkiFcHjeN/SzAqS+iX6hzsyeBGhkM TelUbSVscGXMiVtvPqlcz+mFsUOUoiHS162M6EgKYGXOFTcM1zcwFYyjg/x8Y4y5kc8l WgAmcLbSf52PqzsBqqlE9VQGVOVh0n8fbHEhLn34kNv5mYkMdvKq9cXzLjbeRWedOKry JC96+Ku/tTc/ArZVq6qGwtm+RfQzruY6DYP7IVEwiRg7dSydcIKn3Xvp9/l61FUWd+sO UqEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732616577; x=1733221377; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yGY7qn3T/vVH05XwetJnmcN100gMBe4kn/nqWGga67s=; b=ChlifOvx+WMpOmXEjX4hDlbv1gPJNvIDLdAVqAM1GEjKWfs/54Sm11SVqB/cIOiGGp BiyaZ0ctj/mfz6PyF7obojYKzOM9mWFFBxiAOvZaVMe19hQ1Amhn3uVNoMt0kkT7K2At VNU7sWjJwbnLV3/3gdUpcBFj09hbUfBK4GnKwTu/GJj2lgDuE7SkMWhu+xEMuAFolIDb k/f/6dV/uWFDTexl3HAtb0Q3P5KA0MncHUbG4V8cg8G5bdTyV6t8xMAs7US/6cgK+SLf xsGJNlncu1R5lH+A+soagzybpYNP7eznUf2Iav5azbMigjZ043KJo5R01ERrOcY2IiA/ E5kA== X-Gm-Message-State: AOJu0Yx1qEL+cyOg/kL/Xk1rw5zbY3joruTsmHdqaxUjDBOkdlmMX5as xSIpuOiPlaXVS3zzOFYRoCnyyidwOeWYi4mRU/fNkPgM5rTTsJGsuTKOxPxCQ90= X-Gm-Gg: ASbGnctnnjsZAjDtc0unUHyVnybKXqRnEmtePZFvhL29yBnfzqIt6T98wzRoeSs3p5B F4+r1FVnstaotqEGN3O3e0yfEdHKiKCQlKP23J9uw7eS/lDqmgeq+zhMaLghA4PzIRpgWbm1xxO kpbJNjLh2lI/2WiKw4PWyWfaQdAytSnkjZfLyjc/WzxEepPZKQZWQQk7WrMsnz8ewHjmSnyGa9d 7DuufRueajhBEs7bl2JBnqCRbC0qsPIHGZjXZ9Ye3ed/fS1bwiVfU3Wa1KjegGPLyddl64= X-Google-Smtp-Source: AGHT+IGPAdKF60KJgbdHpQ0rkkHhQT35BoPjigPNj6uM+GadsiYB0acZNjOjuCklQM7MHaWYJOgR3g== X-Received: by 2002:a05:600c:3552:b0:431:55f3:d34e with SMTP id 5b1f17b1804b1-434a4e97451mr21967545e9.15.1732616577530; Tue, 26 Nov 2024 02:22:57 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433b01e1046sm228378075e9.4.2024.11.26.02.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 02:22:57 -0800 (PST) From: Neil Armstrong Date: Tue, 26 Nov 2024 11:22:50 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: sm8550: Add 'global' interrupt to the PCIe RC nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241126-topic-sm8x50-pcie-global-irq-v1-2-4049cfccd073@linaro.org> References: <20241126-topic-sm8x50-pcie-global-irq-v1-0-4049cfccd073@linaro.org> In-Reply-To: <20241126-topic-sm8x50-pcie-global-irq-v1-0-4049cfccd073@linaro.org> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2127; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=DSfkUxtAoj5mu81yWWFvAAd0RzmXItr4kWCdyj1bISk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRaF9prwC2FE/20VAFkxL2ILMYJ+aAmceOxTvbWRS z4ZM7MOJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0WhfQAKCRB33NvayMhJ0bHOEA CG5c18zN7eCFM7GX/zPfQuFA7GTJzLR2x/AC88IfhPfsmqMToQCucnNGm8OhNoq92kLLMMv7P/6qR3 uhlj9VIvuZCbODoAKm+9fDgi6A0qGikNYp5X5y/39351trqDgEQfsEVOqXlHAW8PUvL574nffugOjP 3brwvr89SeGqpVci8pCM/MNwukm8MTPax0eTl/k6gEJGbZIKtl4TYRTlBIsMi0K76pwI11qXuYNHB9 X4T3KzeeueNn7XvKlB8ZFarJfNd6n8WQAVHZ8Sh76nHPMLi/aPsC+J0NCpI/Pt/Oc6pr2PQ/dB3xWK YJNrcqQSEXQGjLEnGACG5LLBkRkvAsYRokxV/cSrMVBCL2wMPJCM4Ciesk1kkLEiJqgMV4jJh5CdHB cZdfTfRlmx5SbM1KIwQNRYg3lEcvJt0Bnd5D6XBbBxQ9hQGd4bhmUTaBBEeJpquDLPqHuIli7+xooF 0cLHpXR9IPykR7iA8QlDAAKqW+YRgu/HEg51nt7c+X0IbuZjBBlJFmVVeb6Noyc6kwCeEHrquVIydJ nvx8YrkpTgqVJqDI5rK5Q+DY/W8K6sVCbWlTTuh1G7FdKPmNrKH5Mf8c4MYue7D5iGk5VJBBBIgdDW +sqPlG/LpvsT/V8qkgbh6FVHgdIwC4Ado8JpIZXGqJRsU0G5b4Kkfy7hK0xA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f8711e01934e47331b99e3bb73682..44613fbe0c7f352ea0499782ca825cbe2a257aab 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1734,7 +1734,8 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1742,7 +1743,8 @@ pcie0: pcie@1c00000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1850,7 +1852,8 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1858,7 +1861,8 @@ pcie1: pcie@1c08000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Tue Nov 26 10:22:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13885761 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B27E1CD214 for ; Tue, 26 Nov 2024 10:23:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732616582; cv=none; b=RrDG9mBjH5eBOCGHVz6F/AUK6zdzQQNqZGnqzGdr2KPIfD2xiZm4KliTwuXA9V49uLvkMpeyhuRbbOetbgPq4J+czKJhTuSTd444rFombcMHmPlRHXzm1aYPMIcr3ntQnt9HEH00uxH/McMbE3zwdLDGywkMckwFL5WXRS76tS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732616582; c=relaxed/simple; bh=WD2Ififyc67QT7itZr9mWxPZ1InWr4O/7CEhRE0kxnc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BMsxL4Q8Ru43DUpCDtYLUBqaPhJFcupktW7r0CjfoGb0r4q3/tsUW1usla5EO5u+svJ/VL4Jsxjtasj9wDrXRBh0O3U3h0FIrjxZKpg0UAyAiEcjeGiVUbq9y/L84UByzEMw6dzJwYTAXp96Bs4hpWbglolubxQsD31KgLKBofo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PkhxSiNM; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PkhxSiNM" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-53deeb6d986so43688e87.0 for ; Tue, 26 Nov 2024 02:23:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732616578; x=1733221378; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0U6DI9UiS7mCrw7uF6OaC1EisPMexi0/iLw96bOdlu0=; b=PkhxSiNMgp/MVtG/H+dKZMfu8VKIgEEuHFh4Z8tcu3/jO36KLLLg0/VNTq4ua0gvce Sb3iOHQ9thuf+xVsDGRxmc9+kgo+e7Hq6vgS+rCQxHwX3qnza7d2/TYjl/AgLX2VgYCY LGtCz1kI434/SEU5BzN0hu0F/AvQPUoBmMPcRL4haQMQhrDkmj592Z3UxHBXsDs2G/na 7QtCWneDn8gAE4K4P/LldmTmBJx7YMBogSbqWxWObByb6wJuiTvBEM43Hx+nDvrQTvPO JTCRf+r11n/93EgERgjH8oZWG+cLwLLooWWGV8GpUxrMJIa3YMIEcOEjQhBc9yo0v07J Rr/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732616578; x=1733221378; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0U6DI9UiS7mCrw7uF6OaC1EisPMexi0/iLw96bOdlu0=; b=vkjATBFC/20Z3LX6kmAX1Yeep4auXOM1jOx+W6qr7Ahya2Qua2upQaQMpcTOJLo1h+ vI67n6AQ5FTKKU59w5TAjp2//sL1VFZzb+JMAOFd2v0UHkRpiSL80sTum4AaSvQJ3UVP U6y/wa1DkYqAlA05eT4rsX9VObn7AjTdi6/XoSQTTxGcHAJWUJOxN7Fvwsyk+1r4Pg2y tmE/sgFm0KOulusaET4Bgb/d46VGjkAm/1LTOXDzUTU/RNp9eC8yTsK44G1LyZ0y1b3J LXa1PbCJOeR8Itso/W2UxNDzG4NZ1qZ9oP6lBvyuvqCG4JjpBVxhDiTRP3gqghODoFPP 0/Hg== X-Gm-Message-State: AOJu0Yzi7hX8EKWan490l4cTGC2zAALLsrcvht8Chb6SI6qaNF3vIlhE gwio3ibcwJsnvqFLbr+JC6gjJTmb1eOVeEcATFUAu4CYfM+sg5QODWEOLUn9Apo= X-Gm-Gg: ASbGncsVpUS1O9eiaH+lwo4ilmVhaP+Tb3QPsI/+sA+wT2kngfmPVb4HxZulSZ8FCct lnvotkrl2z34xQIWS4VqY1R5uqX10GAG/UOjGdUPfwnbeFxNB30CtpoX2XIcyxEawti+VRS5sDR sg3xgbqy9s9ojF4Xf4VlENvZ4MIHlyGP+26P47LQaDJs376yK05ed87m1YQ9zGetRYgrITeCG35 xCnrFCxcSmM6rxvBDP87/5dFEGouh8pXUCqfePqGKmPr6w9efLWj52z/fsmrIhLLLB+sVw= X-Google-Smtp-Source: AGHT+IFaLK9Pd5Um5Yaikuh0FrdV/CYyyTM3uVzHgbDOgQuibopiqUgJ00t+FAWEy2IzhwY/faRjag== X-Received: by 2002:ac2:5de2:0:b0:53d:d434:500a with SMTP id 2adb3069b0e04-53dd4345056mr5681073e87.5.1732616578454; Tue, 26 Nov 2024 02:22:58 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433b01e1046sm228378075e9.4.2024.11.26.02.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 02:22:58 -0800 (PST) From: Neil Armstrong Date: Tue, 26 Nov 2024 11:22:51 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: sm8650: Add 'global' interrupt to the PCIe RC nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241126-topic-sm8x50-pcie-global-irq-v1-3-4049cfccd073@linaro.org> References: <20241126-topic-sm8x50-pcie-global-irq-v1-0-4049cfccd073@linaro.org> In-Reply-To: <20241126-topic-sm8x50-pcie-global-irq-v1-0-4049cfccd073@linaro.org> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1995; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=WD2Ififyc67QT7itZr9mWxPZ1InWr4O/7CEhRE0kxnc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnRaF+2QmFQqhnVY1DSzumR+/6knam238u03MuV636 /zgDejCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ0WhfgAKCRB33NvayMhJ0X24D/ wMmt7rkM44OWagYOI9CEjt33RIgQwB1KHAvRxNWq/m5WeGtPfR8rJDFm/u1QS+yDvJETaZXzoFUVhe eA6PMLxkFR1l/wHU1t+F1O4uzs5k5/Qrq7cOVk+ZeBTL8nrdEmmIgjyUGz8e6IRnahlgR63BN6g1yF unDY/rC6asESMyweqW2OwAYgVqPIfe5Zlv2M8ydNoQat6SR15is5mVWeCmWHb4MljcDyOI+IByP/nu NV8Y34YAu3b1Zox4VF6BQhvo0hQmhz6UVH3/nCVSgfAz7ZHzdpECfVvWUhzoVfo2youChlGSU1mTLA vJRNJy8BS5viN5xmb/IlUG/JhSgx5G+PAMW7DPERUJsmxQuGUYuX8WO4wpTq9cPOZBtQol8A9p/FNr usm/qF4CenijJlcpOK1XdCNQxTP/jf5vwVO3pXqC6qBMpr1XyGDbVatomQj9PcYWUWClNXYvAFfAwK 3juOOxZneew3bjBZd43FX6se8hRRQBa9eOZyX/9rCAjQ7hAdtv+icL1KqqgpHFIYsiTwbU9xvFueDV jq/KqXAOWHymXRcoWbetS2JV3EIGXjeEnY8NarRTubdE27KlVvya/lddZFIW8OD/pZfK9ZLeBzhMrZ vMpRg06HJ67f7FuMOfJYk2KXN/uXHrZRbNxQE9pkJVTen8lFmo7eYqRiMz7Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPUs. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, add it to the PCIe RC node along with the existing MSI interrupts. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 01ac3769ffa62ffb83c5c51878e2823e1982eb67..f394fadf11f9ac1f781d31f514946bd5060fa56f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2233,7 +2233,8 @@ pcie0: pcie@1c00000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -2241,7 +2242,8 @@ pcie0: pcie@1c00000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2365,7 +2367,8 @@ pcie1: pcie@1c08000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -2373,7 +2376,8 @@ pcie1: pcie@1c08000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>,