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[176.184.14.96]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aca7eea8sm6937285e9.34.2024.11.27.04.17.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 Nov 2024 04:17:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Nicholas Piggin Subject: [PATCH-for-10.0 1/6] target/ppc: Indent ppc_tcg_ops[] with 4 spaces Date: Wed, 27 Nov 2024 13:16:53 +0100 Message-ID: <20241127121658.88966-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241127121658.88966-1-philmd@linaro.org> References: <20241127121658.88966-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Acked-by: Nicholas Piggin Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c25..daf7f8a93bd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7416,23 +7416,22 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { - .initialize = ppc_translate_init, - .restore_state_to_opc = ppc_restore_state_to_opc, - + .initialize = ppc_translate_init, + .restore_state_to_opc = ppc_restore_state_to_opc, #ifdef CONFIG_USER_ONLY - .record_sigsegv = ppc_cpu_record_sigsegv, + .record_sigsegv = ppc_cpu_record_sigsegv, #else - .tlb_fill = ppc_cpu_tlb_fill, - .cpu_exec_interrupt = ppc_cpu_exec_interrupt, - .cpu_exec_halt = ppc_cpu_has_work, - .do_interrupt = ppc_cpu_do_interrupt, - .cpu_exec_enter = ppc_cpu_exec_enter, - .cpu_exec_exit = ppc_cpu_exec_exit, - .do_unaligned_access = ppc_cpu_do_unaligned_access, - .do_transaction_failed = ppc_cpu_do_transaction_failed, - .debug_excp_handler = ppc_cpu_debug_excp_handler, - .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, - .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, + .tlb_fill = ppc_cpu_tlb_fill, + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, + .cpu_exec_halt = ppc_cpu_has_work, + .do_interrupt = ppc_cpu_do_interrupt, + .cpu_exec_enter = ppc_cpu_exec_enter, + .cpu_exec_exit = ppc_cpu_exec_exit, + .do_unaligned_access = ppc_cpu_do_unaligned_access, + .do_transaction_failed = ppc_cpu_do_transaction_failed, + .debug_excp_handler = ppc_cpu_debug_excp_handler, + .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, + .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; 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[176.184.14.96]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fad60f0sm16157301f8f.22.2024.11.27.04.17.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 Nov 2024 04:17:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 2/6] accel/tcg: Declare local tcg_ops variable in tcg_exec_realizefn() Date: Wed, 27 Nov 2024 13:16:54 +0100 Message-ID: <20241127121658.88966-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241127121658.88966-1-philmd@linaro.org> References: <20241127121658.88966-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Ease reading code by declaring a local 'tcg_ops' variable. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8163295f34b..18d9cf0ea58 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1070,15 +1070,15 @@ int cpu_exec(CPUState *cpu) bool tcg_exec_realizefn(CPUState *cpu, Error **errp) { - static bool tcg_target_initialized; + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; if (!tcg_target_initialized) { /* Check mandatory TCGCPUOps handlers */ #ifndef CONFIG_USER_ONLY - assert(cpu->cc->tcg_ops->cpu_exec_halt); - assert(cpu->cc->tcg_ops->cpu_exec_interrupt); + assert(tcg_ops->cpu_exec_halt); + assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ - cpu->cc->tcg_ops->initialize(); + tcg_ops->initialize(); tcg_target_initialized = true; } From patchwork Wed Nov 27 12:16:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13886953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3ED21D6ACC6 for ; Wed, 27 Nov 2024 12:18:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGGzF-0004n3-1j; Wed, 27 Nov 2024 07:17:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGGyy-0004dD-Sx for qemu-devel@nongnu.org; Wed, 27 Nov 2024 07:17:31 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGGyu-0008LI-P7 for qemu-devel@nongnu.org; Wed, 27 Nov 2024 07:17:23 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-43497839b80so30875775e9.2 for ; Wed, 27 Nov 2024 04:17:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732709837; x=1733314637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UUGCjRn4dTEY6SyGbCBusbLfPJq+6yezwKl0LVNO1Q0=; b=Kxb06jA2SkCzxurnJxtOY0g89flyX1ulqoP2MkOQDueaKo5dqngtIrGyzaqi9RlDM6 sOFBan9axx5eZAXCIDCIBU6zltJwkavAG/yCoAjxK7BSm9/2frZW375VzMj4H3vWXe5Z 1LfKwRhy8YbkGgUrHfGphHPEetiQ7BmQDbSBSIAXHHbr2+ghLu+P1itLHYjV1qGNbw2g 1g09D8ulsQVbKrjwNgAszOAQAiw9fwYUJSaq6sKwfTYC9RBJVy1EmDnpQRcQ751H5ycD w1XeQzXvhuB1Z8I2VQEjMMYH3BUM82AQ7q/RSCRlxvCL+uR4Ctn7looJu04h5nndB+0L IBkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732709837; x=1733314637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UUGCjRn4dTEY6SyGbCBusbLfPJq+6yezwKl0LVNO1Q0=; b=QFJwcz0KLfLeJxR2Ys+AvqBQ3im4T5L1kvkTzk7Sg9NtZJUpGP/HNxcTlxQckt9Co3 zjg+D4Zxc4FltmtiJKFj7s5L5sap1068JrBIuSTa7tT1bY4oZb9eexOm5141zv2HR348 S+/2PK8IbmDRo1t/+r70bDdMgSKjMCwe6keE+nfyVPXctNsACfai9D8bzD0OHEcqyQ7G 5ni3Cu8GN0+TtAtdg3TH44YeENnKjwsQ4Jn0Jt1zis1uuJA5fe2ZESMiTa2I50vzhtKn unoqVeNJkMNeNfBrrNf42LdOeiZpT+P3itetFVhSOji7pCqR6H0DQwUCLPBFyYAqtr08 m+kQ== X-Gm-Message-State: AOJu0Ywp1AUIbTJUjTgvlYrUD7f6rMUbFgKj4sHWXABQPJulr8x7tczj UXdXLeBp8UxyWMOovlgO9CV9jLlEvvdDk3323SNtphVNcrcuNpGPVEUTRUy8KXRzIv0tSuXaE/V u X-Gm-Gg: ASbGncuDczm/JRqawRGwMr03Xc9jpRTY87Wdcs4k8SPWeXMpdil6QbxJzN+yimBbJWt lwqhPHd0NZQHG6xYM0mq+SmYKcXEtQIWy7fsRDgRlJJHc1HYodyFHw1xr65fH69QdnHKOg7r3aJ ZBkjNDqlPsmaOjqt6ur66l9eBQkI0p/sWBJ8vPIj9ithzEuR7a+wn+rPoavqFVbDhVWQ2Uz2il/ 03bL1N9VnwarWRHqSET/DNgY0GQWkGn8N/ZjJ67w1UFno+xW1rPBb6VzXy3DtlPkRg3b82piMAF iJOvm6oJopBRNzw1TP9FfBc003kXrfm8gldSjfKkrjQ= X-Google-Smtp-Source: AGHT+IG7B23T06pCYe7jfDLgjVtafECDOvLd2y6D2sG9pKYg63yaaZs/ZqyQ0VVz6PQWR0tmYdNWKg== X-Received: by 2002:a05:600c:5101:b0:434:942c:1466 with SMTP id 5b1f17b1804b1-434a9df6d91mr23523965e9.29.1732709836811; Wed, 27 Nov 2024 04:17:16 -0800 (PST) Received: from localhost.localdomain (plb95-h02-176-184-14-96.dsl.sta.abo.bbox.fr. [176.184.14.96]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fafe158sm16170000f8f.27.2024.11.27.04.17.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 Nov 2024 04:17:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 3/6] accel/tcg: Rename TCGCPUOps::initialize() as initialize_once() Date: Wed, 27 Nov 2024 13:16:55 +0100 Message-ID: <20241127121658.88966-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241127121658.88966-1-philmd@linaro.org> References: <20241127121658.88966-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While this handler can be called multiple times, it will only be run once. Clarify by renaming the handler name. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- We could "optimize" TGC frontends memory use by passing a CPUClass argument, and each initialize() call would initialize TCG registers required for a particular CPUClass which are not yet initialized by previous calls. Not a priority / worth it. --- include/hw/core/tcg-cpu-ops.h | 6 +++--- accel/tcg/cpu-exec.c | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu-v7m.c | 2 +- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 22 files changed, 24 insertions(+), 24 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 663efb9133c..9a01eb87bfb 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -19,11 +19,11 @@ struct TCGCPUOps { /** - * @initialize: Initialize TCG state + * @initialize_once: Initialize TCG state * - * Called when the first CPU is realized. + * Called once when the first CPU is realized. */ - void (*initialize)(void); + void (*initialize_once)(void); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 18d9cf0ea58..ab77740c954 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1078,7 +1078,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ - tcg_ops->initialize(); + tcg_ops->initialize_once(); tcg_target_initialized = true; } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7a..4a20b0c5d16 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -220,7 +220,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { - .initialize = alpha_translate_init, + .initialize_once = alpha_translate_init, .synchronize_from_tb = alpha_cpu_synchronize_from_tb, .restore_state_to_opc = alpha_restore_state_to_opc, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..f5b0c33a6dc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,7 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops = { - .initialize = arm_translate_init, + .initialize_once = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 58e54578d67..7a887a29b75 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -233,7 +233,7 @@ static void cortex_m55_initfn(Object *obj) } static const TCGCPUOps arm_v7m_tcg_ops = { - .initialize = arm_translate_init, + .initialize_once = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, .restore_state_to_opc = arm_restore_state_to_opc, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3132842d565..e69b5a6af9b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -206,7 +206,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { - .initialize = avr_cpu_tcg_init, + .initialize_once = avr_cpu_tcg_init, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .restore_state_to_opc = avr_restore_state_to_opc, .cpu_exec_interrupt = avr_cpu_exec_interrupt, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc490..6f7777c607e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -322,7 +322,7 @@ static void hexagon_cpu_init(Object *obj) #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { - .initialize = hexagon_translate_init, + .initialize_once = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c38439c1800..e654f133636 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -221,7 +221,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { - .initialize = hppa_translate_init, + .initialize_once = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cca19cd40e8..b44d2f370d1 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -107,7 +107,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps x86_tcg_ops = { - .initialize = tcg_x86_init, + .initialize_once = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, .cpu_exec_enter = x86_cpu_exec_enter, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 57cc4f314bf..32aa5468ceb 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -793,7 +793,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { - .initialize = loongarch_translate_init, + .initialize_once = loongarch_translate_init, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558aa..230057b7375 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -546,7 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { - .initialize = m68k_tcg_init, + .initialize_once = m68k_tcg_init, .restore_state_to_opc = m68k_restore_state_to_opc, #ifndef CONFIG_USER_ONLY diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c1..f75e1cf5ab1 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -420,7 +420,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { - .initialize = mb_tcg_init, + .initialize_once = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a43b6d5c7..4f7d9c03599 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -551,7 +551,7 @@ static Property mips_cpu_properties[] = { * mips hardware (see hw/mips/jazz.c). */ static const TCGCPUOps mips_tcg_ops = { - .initialize = mips_tcg_init, + .initialize_once = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..24125eea1e7 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -232,7 +232,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { - .initialize = openrisc_translate_init, + .initialize_once = openrisc_translate_init, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index daf7f8a93bd..9f90de7f6bd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7416,7 +7416,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { - .initialize = ppc_translate_init, + .initialize_once = ppc_translate_init, .restore_state_to_opc = ppc_restore_state_to_opc, #ifdef CONFIG_USER_ONLY .record_sigsegv = ppc_cpu_record_sigsegv, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c2216961..2be43b90908 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -133,7 +133,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } static const TCGCPUOps riscv_tcg_ops = { - .initialize = riscv_translate_init, + .initialize_once = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f..7c338b584e8 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { - .initialize = rx_translate_init, + .initialize_once = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, .tlb_fill = rx_cpu_tlb_fill, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..a5ab2a083b5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -357,7 +357,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } static const TCGCPUOps s390_tcg_ops = { - .initialize = s390x_translate_init, + .initialize_once = s390x_translate_init, .restore_state_to_opc = s390x_restore_state_to_opc, #ifdef CONFIG_USER_ONLY diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd..75d6504293f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -247,7 +247,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { - .initialize = sh4_translate_init, + .initialize_once = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..d803c329650 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -927,7 +927,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { - .initialize = sparc_tcg_init, + .initialize_once = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1a261715907..19c583ed326 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -170,7 +170,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { - .initialize = tricore_tcg_init, + .initialize_once = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, .tlb_fill = tricore_cpu_tlb_fill, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abaee..71c0a10ef0c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -227,7 +227,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps xtensa_tcg_ops = { - .initialize = xtensa_translate_init, + .initialize_once = xtensa_translate_init, .debug_excp_handler = xtensa_breakpoint_handler, .restore_state_to_opc = xtensa_restore_state_to_opc, From patchwork Wed Nov 27 12:16:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13886952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F626D6ACC4 for ; Wed, 27 Nov 2024 12:18:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGGzE-0004lg-NZ; Wed, 27 Nov 2024 07:17:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGGz0-0004dQ-Uj for qemu-devel@nongnu.org; Wed, 27 Nov 2024 07:17:33 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGGyy-0008NI-FK for qemu-devel@nongnu.org; Wed, 27 Nov 2024 07:17:26 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-38242abf421so4453221f8f.2 for ; Wed, 27 Nov 2024 04:17:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732709842; x=1733314642; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xBB0CLhlW2tPrLDje8K+xxZrR9BoLbGaTyc8yxD5eis=; b=ekfz73OnZ1zAv5WMLVJRgf7I15usIUT9am531a3vipJSljnu9ZSd4UNxUsakibxI/W bB67nWeYLGJKTWUVV5Ez9+F+bSNcx4b9JNcQApw8caVrT/VNnT5T+l/sUIIFnk5qHeEO TeuyrW/LiePScfty6QpjYnMl5hOA/Pb823dmnxxps4W/ns++IIPdI2vveoC5H++LQ9j3 0twXXzX/OZAQs7oCCvClOSkKMI4CQbCe+CQyOHatVAkkefgyWgsPaFgwaHUE4KLIa748 BGCvuidXsTKo1h9f+j3Wu4YggWMG/BOUcL1B0phXpHGkIrOB4xzL6Wvgu3uowR3Rpshw DHqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732709842; x=1733314642; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xBB0CLhlW2tPrLDje8K+xxZrR9BoLbGaTyc8yxD5eis=; b=ok5mevwBXgTQvaD28Y5Q3rqUzX7IP0Cqa7/vy3X7FG5xRy07n6tLv9yhsRI2hr23w9 g2dB4T2QEvKVnHoRmZUxgTqxRw0Y3AhIKuBC008yBvB4Yi70dgbB+5mEDHlktd8F8HAL rALbdFbjXqzWtV7QR5/HzbhRvoF5e7OZXG7xuqDiAROrA5gM4Kq6crKODYF9Rjq2TK+e rRgXpNftnNDy7CBLqbr8ZtVcvJ3dbblXP8r7lZM4iA85RMUUgpQnlFqvR21BkWo17XxL wanz9iDf9ugB1dKZF3FTZlnf/KHfIH6VcvUhP3eK1TRpMwC/zUgPs8KcvrfmNVgUfvkx Td4A== X-Gm-Message-State: AOJu0Yx8XoJV9Y/muE3snDl5SnXa2uqt6eNlA5CI0meo+ki+fXcBGmuV 0tcvwCMaDAKjwq6doWkcygOodC8Yqd2+6PVXg+SY3ZCYc+/ghLfHTiNu96zHTwBdd8MH+6oM7A2 t X-Gm-Gg: ASbGncuosQubcIP8C36dW0MlqNG0P1jKgvHSRprYA/+0pUCjhxPfC5zigdiUVD6aSHS FPppQjXArfFxR4v3rqGCHDGqdlL6/WvfwjiJ1cZjzFIchLrhm/j8xG7g+iU+z3Bp1RfA553iaDH jvWi/EUG1yHaf5LgAMbc57tTgHUeB852uGLSHwZexLmyktLpKmbd/+pmhvBK16rlrYGBGeGTP2M n+41XeZFruPORCO9cZpvXkJTEDusbg3RetkXG2VFiASdDyQqst7GgGNt6EYNnSYxzT22f05woCL Ax5pvpCaXWD9Z/4TTf+SIuNtzRzplpfwyUm5+bTOWNY= X-Google-Smtp-Source: AGHT+IGlJcyJloS/k80XIS4nRahMikb9xI88w5GQVp7kXTMsTD2lTuLnuM8CvjznA+RnkFudC4O3Aw== X-Received: by 2002:a05:6000:4188:b0:382:49f3:4f8e with SMTP id ffacd0b85a97d-385c6ebcdd1mr1351182f8f.18.1732709842163; Wed, 27 Nov 2024 04:17:22 -0800 (PST) Received: from localhost.localdomain (plb95-h02-176-184-14-96.dsl.sta.abo.bbox.fr. [176.184.14.96]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434aa7e33afsm19165815e9.36.2024.11.27.04.17.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 Nov 2024 04:17:21 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 4/6] include: Expose QemuArch in 'qemu/arch_id.h' Date: Wed, 27 Nov 2024 13:16:56 +0100 Message-ID: <20241127121658.88966-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241127121658.88966-1-philmd@linaro.org> References: <20241127121658.88966-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While QEMU architecture bitmask values are only used by system emulation code, they can be used in generic code like TCG accelerator. Move the declarations to "qemu/arch_id.h" and add the QemuArch type definition. Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/arch_id.h | 28 ++++++++++++++++++++++++++++ include/sysemu/arch_init.h | 28 +++------------------------- 2 files changed, 31 insertions(+), 25 deletions(-) create mode 100644 include/qemu/arch_id.h diff --git a/include/qemu/arch_id.h b/include/qemu/arch_id.h new file mode 100644 index 00000000000..e3e8cf5e724 --- /dev/null +++ b/include/qemu/arch_id.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef QEMU_ARCH_ID_H +#define QEMU_ARCH_ID_H + +typedef enum QemuArch { /* FIXME this is not an enum */ + QEMU_ARCH_ALL = -1, + QEMU_ARCH_ALPHA = (1 << 0), + QEMU_ARCH_ARM = (1 << 1), + QEMU_ARCH_I386 = (1 << 3), + QEMU_ARCH_M68K = (1 << 4), + QEMU_ARCH_MICROBLAZE = (1 << 6), + QEMU_ARCH_MIPS = (1 << 7), + QEMU_ARCH_PPC = (1 << 8), + QEMU_ARCH_S390X = (1 << 9), + QEMU_ARCH_SH4 = (1 << 10), + QEMU_ARCH_SPARC = (1 << 11), + QEMU_ARCH_XTENSA = (1 << 12), + QEMU_ARCH_OPENRISC = (1 << 13), + QEMU_ARCH_TRICORE = (1 << 16), + QEMU_ARCH_HPPA = (1 << 18), + QEMU_ARCH_RISCV = (1 << 19), + QEMU_ARCH_RX = (1 << 20), + QEMU_ARCH_AVR = (1 << 21), + QEMU_ARCH_HEXAGON = (1 << 22), + QEMU_ARCH_LOONGARCH = (1 << 23), +} QemuArch; + +#endif diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 5b1c1026f3a..01106de5bcb 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -1,29 +1,7 @@ -#ifndef QEMU_ARCH_INIT_H -#define QEMU_ARCH_INIT_H +#ifndef SYSEMU_ARCH_INIT_H +#define SYSEMU_ARCH_INIT_H - -enum { - QEMU_ARCH_ALL = -1, - QEMU_ARCH_ALPHA = (1 << 0), - QEMU_ARCH_ARM = (1 << 1), - QEMU_ARCH_I386 = (1 << 3), - QEMU_ARCH_M68K = (1 << 4), - QEMU_ARCH_MICROBLAZE = (1 << 6), - QEMU_ARCH_MIPS = (1 << 7), - QEMU_ARCH_PPC = (1 << 8), - QEMU_ARCH_S390X = (1 << 9), - QEMU_ARCH_SH4 = (1 << 10), - QEMU_ARCH_SPARC = (1 << 11), - QEMU_ARCH_XTENSA = (1 << 12), - QEMU_ARCH_OPENRISC = (1 << 13), - QEMU_ARCH_TRICORE = (1 << 16), - QEMU_ARCH_HPPA = (1 << 18), - QEMU_ARCH_RISCV = (1 << 19), - QEMU_ARCH_RX = (1 << 20), - QEMU_ARCH_AVR = (1 << 21), - QEMU_ARCH_HEXAGON = (1 << 22), - QEMU_ARCH_LOONGARCH = (1 << 23), -}; +#include "qemu/arch_id.h" extern const uint32_t arch_type; From patchwork Wed Nov 27 12:16:57 2024 Content-Type: text/plain; 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[176.184.14.96]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbedfccsm16080714f8f.101.2024.11.27.04.17.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 Nov 2024 04:17:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 5/6] accel/tcg: Add TCGCPUOps::arch_id field Date: Wed, 27 Nov 2024 13:16:57 +0100 Message-ID: <20241127121658.88966-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241127121658.88966-1-philmd@linaro.org> References: <20241127121658.88966-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When using multiple TCG frontends concurrently, we need to be able to discriminate by target architecture. While we can infer that from the CPUClass, it can be quicker to get it from a direct field in TCGCPUOps. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 3 +++ target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 21 files changed, 23 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 9a01eb87bfb..ec3d2b50a9e 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -10,6 +10,7 @@ #ifndef TCG_CPU_OPS_H #define TCG_CPU_OPS_H +#include "qemu/arch_id.h" #include "exec/breakpoint.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" @@ -18,6 +19,8 @@ #include "exec/vaddr.h" struct TCGCPUOps { + QemuArch arch_id; + /** * @initialize_once: Initialize TCG state * diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4a20b0c5d16..e020b4ce173 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -220,6 +220,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps alpha_tcg_ops = { + .arch_id = QEMU_ARCH_ALPHA, .initialize_once = alpha_translate_init, .synchronize_from_tb = alpha_cpu_synchronize_from_tb, .restore_state_to_opc = alpha_restore_state_to_opc, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f5b0c33a6dc..9b088c893bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops = { + .arch_id = QEMU_ARCH_ARM, .initialize_once = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 7a887a29b75..7a316561acc 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -233,6 +233,7 @@ static void cortex_m55_initfn(Object *obj) } static const TCGCPUOps arm_v7m_tcg_ops = { + .arch_id = QEMU_ARCH_ARM, .initialize_once = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index e69b5a6af9b..a9cce351755 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -206,6 +206,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps avr_tcg_ops = { + .arch_id = QEMU_ARCH_AVR, .initialize_once = avr_cpu_tcg_init, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .restore_state_to_opc = avr_restore_state_to_opc, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 6f7777c607e..2a3b2e5fb4f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -322,6 +322,7 @@ static void hexagon_cpu_init(Object *obj) #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps hexagon_tcg_ops = { + .arch_id = QEMU_ARCH_HEXAGON, .initialize_once = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e654f133636..9bee8ef24f6 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -221,6 +221,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps hppa_tcg_ops = { + .arch_id = QEMU_ARCH_HPPA, .initialize_once = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index b44d2f370d1..0577d6237a9 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -107,6 +107,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps x86_tcg_ops = { + .arch_id = QEMU_ARCH_I386, .initialize_once = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 32aa5468ceb..96ae8c4ef05 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -793,6 +793,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps loongarch_tcg_ops = { + .arch_id = QEMU_ARCH_LOONGARCH, .initialize_once = loongarch_translate_init, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 230057b7375..8a45fbe9d2f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -546,6 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps m68k_tcg_ops = { + .arch_id = QEMU_ARCH_M68K, .initialize_once = m68k_tcg_init, .restore_state_to_opc = m68k_restore_state_to_opc, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f75e1cf5ab1..e2cfbbbbefd 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -420,6 +420,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps mb_tcg_ops = { + .arch_id = QEMU_ARCH_MICROBLAZE, .initialize_once = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4f7d9c03599..769f25551c7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -551,6 +551,7 @@ static Property mips_cpu_properties[] = { * mips hardware (see hw/mips/jazz.c). */ static const TCGCPUOps mips_tcg_ops = { + .arch_id = QEMU_ARCH_MIPS, .initialize_once = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 24125eea1e7..ac041b4427b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -232,6 +232,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps openrisc_tcg_ops = { + .arch_id = QEMU_ARCH_OPENRISC, .initialize_once = openrisc_translate_init, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9f90de7f6bd..13295b9dfcb 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7416,6 +7416,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps ppc_tcg_ops = { + .arch_id = QEMU_ARCH_PPC, .initialize_once = ppc_translate_init, .restore_state_to_opc = ppc_restore_state_to_opc, #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2be43b90908..ad00183a830 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -133,6 +133,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } static const TCGCPUOps riscv_tcg_ops = { + .arch_id = QEMU_ARCH_RISCV, .initialize_once = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7c338b584e8..12ed4a4101f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,6 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps rx_tcg_ops = { + .arch_id = QEMU_ARCH_RX, .initialize_once = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index a5ab2a083b5..984cacce2d4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -357,6 +357,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } static const TCGCPUOps s390_tcg_ops = { + .arch_id = QEMU_ARCH_S390X, .initialize_once = s390x_translate_init, .restore_state_to_opc = s390x_restore_state_to_opc, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 75d6504293f..cd7336bd7f2 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -247,6 +247,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps superh_tcg_ops = { + .arch_id = QEMU_ARCH_SH4, .initialize_once = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index d803c329650..7e89c4033b2 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -927,6 +927,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps sparc_tcg_ops = { + .arch_id = QEMU_ARCH_SPARC, .initialize_once = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 19c583ed326..a8864955201 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -170,6 +170,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps tricore_tcg_ops = { + .arch_id = QEMU_ARCH_TRICORE, .initialize_once = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 71c0a10ef0c..5d115328ffb 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -227,6 +227,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" static const TCGCPUOps xtensa_tcg_ops = { + .arch_id = QEMU_ARCH_XTENSA, .initialize_once = xtensa_translate_init, .debug_excp_handler = xtensa_breakpoint_handler, .restore_state_to_opc = xtensa_restore_state_to_opc, From patchwork Wed Nov 27 12:16:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13886962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E12B3D6ACC0 for ; Wed, 27 Nov 2024 12:19:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by 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[176.184.14.96]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fad6270sm16075120f8f.14.2024.11.27.04.17.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 Nov 2024 04:17:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Anton Johansson , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.0 6/6] accel/tcg: Allow tcg_exec_realizefn() initialize multiple frontends Date: Wed, 27 Nov 2024 13:16:58 +0100 Message-ID: <20241127121658.88966-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241127121658.88966-1-philmd@linaro.org> References: <20241127121658.88966-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rather than initializing the first random target architecture and ignore the following ones when a global boolean is set, use a bitmask allowing different frontend targets to be initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ab77740c954..b37995f7d0c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1070,16 +1070,17 @@ int cpu_exec(CPUState *cpu) bool tcg_exec_realizefn(CPUState *cpu, Error **errp) { + static unsigned initialized_targets; const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - if (!tcg_target_initialized) { + if (!(initialized_targets & tcg_ops->arch_id)) { /* Check mandatory TCGCPUOps handlers */ #ifndef CONFIG_USER_ONLY assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ tcg_ops->initialize_once(); - tcg_target_initialized = true; + initialized_targets |= tcg_ops->arch_id; } cpu->tb_jmp_cache = g_new0(CPUJumpCache, 1);