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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v2 1/2] xen/mpu: Map early uart when earlyprintk on Date: Wed, 27 Nov 2024 18:39:05 +0000 Message-ID: <20241127183906.485824-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241127183906.485824-1-ayan.kumar.halder@amd.com> References: <20241127183906.485824-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F3:EE_|SN7PR12MB8601:EE_ X-MS-Office365-Filtering-Correlation-Id: ac3b41ab-d065-4906-1b9d-08dd0f12cc17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: jx0rjZZVodD4/tJ1I6ZRurYos7O3lwBx8RufauL/h2r9nImnRoxkzl3W8jiGLoDeSBcxcmlL3dSBU1jr2uoTJZ699wRqLZxpFi69spZuuRXlOLvO7Uaou7YtZx4DNDVhCIMR1/uuLsQQecq59d4EYazsgDCRoNR+Ht9c5lTL1GytXuWwmBlz4rOR4qrDYe4j981g5xmfd8MiYQIVciK+pWA7nVMiR2eyawbh2EPkZgx+wJ2KQMuReypAGVvDXfPL431dsBbs44yK5pK5b0OxPpvehH+L/ChVgCipkFFAQMMwDnB1P3r2bVrPNTM7M6x0VC7f+wQ7HIrpaaxV5EauXAxY6RT80SeQOJ1zh084Bn4G/sH0fS2+sOOCweTC1rjtwlAuDl837j6dUED2ioS3WRsvWzvs6zKkUlaxvrUFWZmAE6FVooDh5QJUJ2DioVLIAnA6Cqej0To87MYryoVkJWXwuopQdkHLwo7sRmS+RmOJ7MqLXH2xQrIdoh09g3o/tGcUCzWE58NXkrPZDuIIaxw7f2zLnY8AqG6MrU6fgnv0rvGL7qGrkBGNrSe8j7NgEmRKKkqzjIXWkiGAhAuvYIiSx9E2fhfOL2VycxwFXjfQE9aZWX/InullpM2Lg2DI4OYXX7hFahLpBKnBGrq3u3nDGsxZWK3Vkb842hlxFdk5T/+H/LCr9WFThn21ikvF01vAYGKqI6w0Co8kUoQIQmmZTjvJeY812SBkYGd8eJrV7HQADatFhZEcKM3y+zW1xDDKUgRRg1MIPPlonsvb/Z28qOJoyztR5L8Zk73F2WJmjLYcKpX+8jp7olKLnCRzbgj4LMoImAhhvUGaAsxdHIFpuXZYnWn0mRnrYAFrIEQrlMqdMfHxnNSBVkWfeZ7G6aqElTK46xMJzs7sMgjeVXFs6Y0hHAtbL/2dx3GUzjA9jMKpuDPjH3xnMzxBROGpdt46yw0DQyJcepc0WGJ2N6i6g3be4UCiHev3taKVDEWQZQq5AXviUXOJW1YNXz7/QYGb1QxZWUvXpmEQI/aUInMSI4n8Qg0VnTRE10vANmyTuqBMvxY8FrqgORwOgiPANy3es+DMLLiMo0DKcaB1w4wRO8OzPxpzmX7WjLXrnmm0BrtehOF64nQdKqAJan/5Sqi1+SAkReU+RqsuDhXIVJY0YBWRbJPkGNebWo+IXt82NdcT38TqZaJmgzJRPk9wk4rN1MO1dY9S0WWNOqrdlY4EScQFBIprEQJ8/6BQDnbb1aFgOfgJWSPy4QQUgAZGveATwE+/++6F3i2axj6dH+ISCJgzEemmPTOItM3Y7xaT351PzKRN2t8BHJLOJnQ8TPIhXR/5XJHX+WOCTYVmqfPLgINaX6rhOJOKz0ePd4eM7X5lpa6LItupkK6ogPMF+ZN7NOg65CAQULRbuO1zjfT8NRaRLhS5y6KtOYzYP4g2Y/yIiB7Kums3x/TLqZyz X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2024 18:39:16.2654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac3b41ab-d065-4906-1b9d-08dd0f12cc17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8601 CONFIG_EARLY_UART_SIZE is introduced to let user provide physical size of early UART. Unlike MMU where we map a page in the virtual address space, here we need to know the exact physical size to be mapped. As VA == PA in case of MPU, the memory layout follows exactly the hardware configuration. As a consequence, we set EARLY_UART_VIRTUAL_ADDRESS as physical address. EARLY_UART_BASE_ADDRESS and EARLY_UART_SIZE should be aligned to the minimum size of MPU region (ie 64 bits) as per the hardware restrictions. Refer ARM DDI 0600A.d ID120821 A1.3 "A minimum protection region size of 64 bytes.". UART is mapped as nGnRE region (as specified by ATTR=100 , refer G1.3.13, MAIR_EL2, "---0100 Device memory nGnRE") and Doc ID - 102670_0101_02_en Table 4-3, Armv8 architecture memory types (nGnRE - Corresponds to Device in Armv7 architecture). Also, it is mapped as outer shareable, RW at EL2 only and execution of instructions from the region is not permitted. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. UART base address and size should be aligned to the minimum size of MPU region (and not PAGE_SIZE). xen/arch/arm/Kconfig.debug | 7 +++++++ xen/arch/arm/arm64/mpu/head.S | 9 ++++++++ xen/arch/arm/include/asm/early_printk.h | 28 ++++++++++++++++++++++++- 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index 7660e599c0..84a0616102 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -121,6 +121,13 @@ config EARLY_UART_BASE_ADDRESS hex "Early printk, physical base address of debug UART" range 0x0 0xffffffff if ARM_32 +config EARLY_UART_SIZE + depends on EARLY_PRINTK + depends on MPU + hex "Early printk, physical size of debug UART" + range 0x0 0xffffffff if ARM_32 + default 0x1000 + config EARLY_UART_PL011_BAUD_RATE depends on EARLY_UART_PL011 int "Early printk UART baud rate for pl011" diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index f692fc7443..86e4019a0c 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -11,8 +11,10 @@ #define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ #define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ #define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ #define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ /* * Macro to prepare and set a EL2 MPU memory region. @@ -138,6 +140,13 @@ FUNC(enable_boot_cpu_mm) ldr x2, =__bss_end prepare_xen_region x0, x1, x2, x3, x4, x5 +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + ldr x1, =CONFIG_EARLY_UART_BASE_ADDRESS + ldr x2, =(CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region x0, x1, x2, x3, x4, x5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR +#endif + b enable_mpu ret END(enable_boot_cpu_mm) diff --git a/xen/arch/arm/include/asm/early_printk.h b/xen/arch/arm/include/asm/early_printk.h index 46a5e562dd..606aaedd6e 100644 --- a/xen/arch/arm/include/asm/early_printk.h +++ b/xen/arch/arm/include/asm/early_printk.h @@ -15,6 +15,29 @@ #ifdef CONFIG_EARLY_PRINTK +#if defined(CONFIG_MPU) + +/* + * For MPU systems, there is no VMSA support in EL2, so we use VA == PA + * for EARLY_UART_VIRTUAL_ADDRESS. + */ +#define EARLY_UART_VIRTUAL_ADDRESS CONFIG_EARLY_UART_BASE_ADDRESS + +/* + * User-defined EARLY_UART_BASE_ADDRESS and EARLY_UART_SIZE must be aligned to + * minimum size of MPU region. + */ + +#if (EARLY_UART_BASE_ADDRESS % MPU_REGION_ALIGN) != 0 +#error "EARLY_UART_BASE_ADDRESS must be aligned to minimum MPU region size" +#endif + +#if (EARLY_UART_SIZE % MPU_REGION_ALIGN) != 0 +#error "EARLY_UART_SIZE must be aligned to minimum MPU region size" +#endif + +#elif defined(CONFIG_MMU) + /* need to add the uart address offset in page to the fixmap address */ #define EARLY_UART_VIRTUAL_ADDRESS \ (FIXMAP_ADDR(FIX_CONSOLE) + (CONFIG_EARLY_UART_BASE_ADDRESS & ~PAGE_MASK)) @@ -22,6 +45,9 @@ #define TEMPORARY_EARLY_UART_VIRTUAL_ADDRESS \ (TEMPORARY_FIXMAP_ADDR(FIX_CONSOLE) + (CONFIG_EARLY_UART_BASE_ADDRESS & ~PAGE_MASK)) -#endif /* !CONFIG_EARLY_PRINTK */ +#else +#error "Unknown Memory management system" +#endif +#endif /* !CONFIG_EARLY_PRINTK */ #endif From patchwork Wed Nov 27 18:39:06 2024 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Ayan Kumar Halder Subject: [PATCH v2 2/2] xen/mmu: enable SMMU subsystem only in MMU Date: Wed, 27 Nov 2024 18:39:06 +0000 Message-ID: <20241127183906.485824-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241127183906.485824-1-ayan.kumar.halder@amd.com> References: <20241127183906.485824-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F3:EE_|SJ0PR12MB8115:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c96b7be-6899-4369-f778-08dd0f12cd96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: fjMW/dXVnGdjTj6+wFY4rx4ME8wdk7IyA0QC5NInbW4/YO2ezYwlaY7NFunCsUGuwtWyufai0OFVWO7qUF502WbTkpRAU9g8/viqk16HfsaAa/BSr4kzHTMVNlsL9hiRxf/S/pPZ+SJXQhxY031Om71lm3UroFLj8rK55kt+99ZXvlws5j23cwgu2Yyr0ySCVE+0+TzPAn9kThdxb8Ay8Y3WQJnZwe+rissdrETK1B4MclvMfXjyK9Z0GqqiYmPbTzxmEOAjVaSARkSwhampqRNuIMCUg/EOMNBESWyb1tGsgPHx0kZQAKCazrbyEewLOabXHE0rEVhKyOTjxteANGaiZpSZRr8cXsSZZgLZ3ZeU9NI2LleyF1mT7zSu8KJ1+vZ5dp25tu64cSmxdxWo8w+R5QkuoevMgm64dQubXIb3IKRYITppJowavG6qztmpd5LaSGN2swlxvXIzam8XhSo1zTGfZwalT+VPExPk8C4G4zVoNTMXOEN6mpnJqHx9G6jj4vgyR4OHxiUFQZ2LFPNZGCpnc/EHWv6xP6hIkHLgk3jpDOeCcMATKgBec+HKB9kZrBYq1nJu7UCzfRHzXAFGUS63A6sJE1TezWdiJxa1mrB4QAdAbVYC9b1aszuf0wxw5+rJ0yCbuF3UKjfcqip9CJZonMCHw26GqzszXktb0D9WC2FOWslFF73u1pIAvtRaAipeVFPP4aURc7jAy2epaDbDe6RH/GolDD+qjfndgpxJVDjoqkxhAWuOzuucwt+AaCgvcP3YiNaYcmEhSLPodd9LK7lTqifCNUep6xL1RtCxIqGAYasc1n5PGgH2qh+k5WLrrnS1lCQ6FEEv7WvcaK7zy8nqvFn1iHu323PZE7Ft5hZSzKlToU6B5xskQya9874DXHpGzUwdfCUlM333cKIqmxm4a3lRgyMvosBGRBMOTNRzCtiz6WcHSSYuogwNvj/Hk/WhDVwc/nKz47JK6aKUHpBV5CucX1HPfdlBzQfE6MvGisWYgBEINMI1mtDYglj2ma0akve3G6hMTaJnbqDU9YyTdn2AwTayC7QCM2gyM2DRVF+UrTngZ7rqwuLRD4ytiGeS6VQhujvEchAaB7hrDl5uKH8X57C2fcIzIxvoNmMVBcPNxwV4lXKnK+lQHD6PWHbv6GpEiKM90wkOIcbSvO8JHiV2a2M9e2cmEif77FNOc3tO4P4Xe1FFLDJF2IvB7jNKfxFXiYl98TiOFrk+lPwQa6rolb/eiLSqn9K+DNLfjiPpa9ESEPVWMozbUhEpe9FKm6kYk3R7mK14/RwpxOXf47MB+RlYSDXL1ZFt5xrEzQEgqh6jckW5Qat0sFvY/oPosYzV9HT/KdzgDmweQR7ICA/OAYkJKuHGCOhygnU6fqAeZ7ENGRaQ55vN/SJbhzXlNDAF+ZfazRVxn7LcBp7yblf3untmMNWVdedPNZYYxw4zIZie3v91 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2024 18:39:18.7810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c96b7be-6899-4369-f778-08dd0f12cd96 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8115 From: Penny Zheng In Xen, SMMU subsystem is supported for MMU system only. The reason being SMMU driver uses the same page tables as MMU. Thus, we make it dependent on CONFIG_MMU. Signed-off-by: Penny Zheng Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. HAS_PASSTHROUGH is now enclosed within "config MMU". There was a pending response on "[PATCH v1 2/2] xen/mmu: enable SMMU subsystem only in MMU" that it might introduce a bunch of #if-defs in arm specific common code. However, there are alternative implementations possible to reduce #if-defs. So, that can be decided at a later point in time and should not block the current patch. xen/arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 15b2e4a227..adebf8d5ca 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -14,9 +14,7 @@ config ARM select FUNCTION_ALIGNMENT_4B select HAS_ALTERNATIVE if HAS_VMAP select HAS_DEVICE_TREE - select HAS_PASSTHROUGH select HAS_UBSAN - select IOMMU_FORCE_PT_SHARE config ARCH_DEFCONFIG string @@ -78,6 +76,8 @@ config MMU bool "MMU" select HAS_PMAP select HAS_VMAP + select HAS_PASSTHROUGH + select IOMMU_FORCE_PT_SHARE help Select it if you plan to run Xen on A-profile Armv7+