From patchwork Fri Nov 29 15:43:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13888823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 392CDD729E9 for ; Fri, 29 Nov 2024 15:44:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tH39P-0005ud-Rb; Fri, 29 Nov 2024 10:43:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tH39K-0005qh-HG for qemu-devel@nongnu.org; Fri, 29 Nov 2024 10:43:18 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tH39J-0001SZ-2J for qemu-devel@nongnu.org; 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Fri, 29 Nov 2024 07:43:15 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5996df797sm188427366b.68.2024.11.29.07.43.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 1/3] MAINTAINERS: Cover RISC-V HTIF interface Date: Fri, 29 Nov 2024 16:43:02 +0100 Message-ID: <20241129154304.34946-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The HTIF interface is RISC-V specific, add it within the MAINTAINERS section covering hw/riscv/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- IMHO 'RISC-V TCG CPUs' should cover target/riscv/ which are the accelerator-facing implementations, and each machine or device in hw/riscv/ should have its own section. Not going to clean that in this patch. --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2b1c4abed65..046e05dd28d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,8 +324,10 @@ S: Supported F: configs/targets/riscv* F: docs/system/target-riscv.rst F: target/riscv/ +F: hw/char/riscv_htif.c F: hw/riscv/ F: hw/intc/riscv* +F: include/hw/char/riscv_htif.h F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ From patchwork Fri Nov 29 15:43:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13888811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2D84D729E9 for ; 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Fri, 29 Nov 2024 07:43:21 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa599973565sm183685666b.202.2024.11.29.07.43.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 2/3] hw/char/riscv_htif: Explicit little-endian implementation Date: Fri, 29 Nov 2024 16:43:03 +0100 Message-ID: <20241129154304.34946-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since our RISC-V system emulation is only built for little endian, the HTIF device aims to interface with little endian memory accesses, thus we can explicit htif_mm_ops:endianness being DEVICE_LITTLE_ENDIAN. In that case tswap64() is equivalent to le64_to_cpu(), as in "convert this 64-bit little-endian value into host cpu order". Replace to simplify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- hw/char/riscv_htif.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 0345088e8b3..3f84d8d6738 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -29,7 +29,7 @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" -#include "exec/tswap.h" +#include "qemu/bswap.h" #include "sysemu/dma.h" #include "sysemu/runstate.h" @@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) } else { uint64_t syscall[8]; cpu_physical_memory_read(payload, syscall, sizeof(syscall)); - if (tswap64(syscall[0]) == PK_SYS_WRITE && - tswap64(syscall[1]) == HTIF_DEV_CONSOLE && - tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { + if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE && + le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE && + le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { uint8_t ch; - cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); + cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1); /* * XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks @@ -324,6 +324,7 @@ static void htif_mm_write(void *opaque, hwaddr addr, static const MemoryRegionOps htif_mm_ops = { .read = htif_mm_read, .write = htif_mm_write, + .endianness = DEVICE_LITTLE_ENDIAN, }; HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, From patchwork Fri Nov 29 15:43:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13888810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CE0BD729E7 for ; Fri, 29 Nov 2024 15:43:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tH39Y-0005xD-Tk; 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Fri, 29 Nov 2024 07:43:27 -0800 (PST) Received: from m1x-phil.lan ([176.176.147.124]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d097e8dcefsm2003596a12.55.2024.11.29.07.43.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 29 Nov 2024 07:43:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Weiwei Li , Alistair Francis , =?utf-8?q?Marc-Andr=C3=A9_Lure?= =?utf-8?q?au?= , Bin Meng , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Palmer Dabbelt , Paolo Bonzini , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-10.0 3/3] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses Date: Fri, 29 Nov 2024 16:43:04 +0100 Message-ID: <20241129154304.34946-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129154304.34946-1-philmd@linaro.org> References: <20241129154304.34946-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Looking at htif_mm_ops[] read/write handlers, we notice they expect 32-bit values to accumulate into to the 'fromhost' and 'tohost' 64-bit variables. Explicit by setting the .impl min/max fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- Notes 1/ these variables belong to HTIFState but are declared statically! static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr; 2/ I believe a 64-bit implementation would simplify the logic. 3/ This is a non-QOM device model! Signed-off-by: Philippe Mathieu-Daudé --- hw/char/riscv_htif.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 3f84d8d6738..db69b5e3ca7 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -325,6 +325,10 @@ static const MemoryRegionOps htif_mm_ops = { .read = htif_mm_read, .write = htif_mm_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,