From patchwork Mon Dec 2 14:14:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70257D78321 for ; Mon, 2 Dec 2024 14:14:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 11E3410E750; Mon, 2 Dec 2024 14:14:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="a1rH53fq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFAAE10E750 for ; Mon, 2 Dec 2024 14:14:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148870; x=1764684870; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NtRXeVJtg1UD35MWccQ1Vp8PEWUhh+sJmVr6a/SAoTM=; b=a1rH53fqMO6kzIAI7KNOfJEAc7bDa5Wf1T1NXTSVw++cplwZV46PfHVb HlSSJXy2Vt2KhOD+sVC2x9PLiCQpEtqjl87s26BZlby75CRk0UBcPZM7A EoU1CuiVZwOxiVDxcTNOaUfiChIPLIy5oZSuxFZHLSr756idOhilbWm4M evT7zYV8rrjyNQD+gmomd6UmQi45lWsZfEi8T4UPmSDvy8Qh/bzkDXBUC XKYae/nFq+Ro8Fbl5dAlTNtHteV55Ry8dslyrI9rEjmnvh4ckl4VLIzqO kPjAx5usY7HSpJx0RsHjuXDYo/Rl6MRL2pIR1WN7ONsb4XXljGJxBqnsP w==; X-CSE-ConnectionGUID: P63dexb8T5iKl005F0XVCw== X-CSE-MsgGUID: bs/2YVBjRcWhB3f1dtNTJg== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807235" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807235" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:30 -0800 X-CSE-ConnectionGUID: RV4Z2OrdSz2+/Kk8VqJiSw== X-CSE-MsgGUID: gqCf2JeSTkCX2+Wdrl9EZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287720" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:28 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:26 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 1/9] drm/i915: Allow async flips with render compression on TGL+ Date: Mon, 2 Dec 2024 16:14:16 +0200 Message-ID: <20241202141424.21446-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Looks like CCS + async flips has been a thing for a while now. Enable this for TGL+ render compression modifiers. Note that we can't update AUX_DIST during async flips we must check to make sure it remains unchanged. We also can't do clear color. Supposedly there was some attempt to make it work, but apparently the issues only got ironed out in MTL. For now we'll not worry about it and refuse async flips with clear color modifiers. Bspec claims that media compression doesn't support async flips. Based on a quick test it does seem to work to some degree, but perhaps it has issues as well. Let's trust the spec here and continue to refuse async flips + media compression. Bspec: 49250,49251,49252,49253 Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++++++++- .../gpu/drm/i915/display/skl_universal_plane.c | 17 ++++++++++------- .../gpu/drm/i915/display/skl_universal_plane.h | 3 +++ 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4805bf682d43..77405a7c706b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6541,6 +6541,9 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: break; @@ -6552,7 +6555,8 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return -EINVAL; } - if (new_plane_state->hw.fb->format->num_planes > 1) { + if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format, + new_plane_state->hw.fb->modifier)) { drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Planar formats do not support async flips\n", plane->base.base.id, plane->base.name); @@ -6598,6 +6602,14 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return -EINVAL; } + if (skl_plane_aux_dist(old_plane_state, 0) != + skl_plane_aux_dist(new_plane_state, 0)) { + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n", + plane->base.base.id, plane->base.name); + return -EINVAL; + } + if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { drm_dbg_kms(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 4c7bcf6806ff..8621c539c110 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -541,15 +541,18 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) return mult * 16 * 1024; return mult * 4 * 1024; - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) + return mult * 16 * 1024; + fallthrough; + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: /* @@ -1203,8 +1206,8 @@ static u32 skl_plane_surf(const struct intel_plane_state *plane_state, return plane_surf; } -static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, - int color_plane) +u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, + int color_plane) { struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_framebuffer *fb = plane_state->hw.fb; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h index 541489479135..18b41d13f0bd 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h @@ -37,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, u8 icl_hdr_plane_mask(void); bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id); +u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, + int color_plane); + #endif From patchwork Mon Dec 2 14:14:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A41ED78326 for ; Mon, 2 Dec 2024 14:14:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 104F210E754; Mon, 2 Dec 2024 14:14:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U4gov9SL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id AEF1F10E754 for ; Mon, 2 Dec 2024 14:14:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148873; x=1764684873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0jaAPrMg+IFj33xyzBuBecQikpjcacHRb8w7ISkJauc=; b=U4gov9SLOlluO5QMjN9ZGsKqHzPCsoUdR+6kS667yHf/JiWEeTULOhvF NjCuEM9J9JnfMmJZ0S2ZSABVmDzbtVBWupMdgVsYR0Iy8DhzJVqyLATM1 P4muix8ugvcovwl71UpcAMe0Y5hiy95sTyjL82BfCaYMIMPDPx0SUEJya DPv2uDaxW3rfdWoux770QQ1afjCNFP4ZV3nWDHPWkIMqQ1XdFoY7kcy5r 56cfLGYuTBrEryYw9WhsZNPA62Axhu+9CMuJgwXhJFJXEY2dFUhvYJxU4 LQZsdcKHv3OzvswrUNNAZpMcLldmHx+sQG8wTQeCCHDR2tc8prRSQurE6 Q==; X-CSE-ConnectionGUID: oQRKGN3SSgSUW3XOBLU+XQ== X-CSE-MsgGUID: twlXGH/dQImBpIx8YHHZ9Q== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807242" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807242" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:33 -0800 X-CSE-ConnectionGUID: FrRNuKF5TDOb+veJx1DopQ== X-CSE-MsgGUID: 5i/DbQh+RwGBN0HfZB3Yow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287723" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:31 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:29 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 2/9] drm/i915: Allow async flips with compression on ICL Date: Mon, 2 Dec 2024 16:14:17 +0200 Message-ID: <20241202141424.21446-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Apparently ICL can do async flips with CCS. In fact it already seems to work on GLK, but apparently can lead to underruns there so we'll only enable it for ICL. Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 21 +++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 77405a7c706b..8b19008202e5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6536,7 +6536,26 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return -EINVAL; } break; - + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* + * Display WA #0731: skl + * WaDisableRCWithAsyncFlip: skl + * "When render decompression is enabled, hardware + * internally converts the Async flips to Sync flips." + * + * Display WA #1159: glk + * "Async flip with render compression may result in + * intermittent underrun corruption." + */ + if (DISPLAY_VER(i915) < 11) { + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", + plane->base.base.id, plane->base.name, + new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); + return -EINVAL; + } + break; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: From patchwork Mon Dec 2 14:14:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A561BD78326 for ; Mon, 2 Dec 2024 14:14:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C60410E758; Mon, 2 Dec 2024 14:14:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="I3HHeJzX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 954F210E757 for ; Mon, 2 Dec 2024 14:14:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148876; x=1764684876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/gHoN0RhmU/Pnw43d8fgkgveyIw9GyEyey2V2/TlP0A=; b=I3HHeJzXneLnY/1GU4oOTdB8OjBC0klyfE4N1MCveaAhKXj3hfk2yvzN TkI6anTG82dEmYholor51bAvukDoZF1XBfIzv5jXWDxUP6BGtrnxn0ltO pP4U5kCSgM8WnzS+P6Ko6EtCK6H+LC3Bbf2IAdQnQcnzlf/6ChqQ2bi5H cnVIITIN4ofSDXvfEGMli9R78pee4yaIeDVa/WfOjQc6KAUfr56SdFOL1 H7h4FWehvupo6Nkj8/Et950JGpQJ3ksGtm8BKs6qbL/gSFc5u5N71yl9m GikasMASH8QMlGWNILiAI+R9sB3uLBswQkgcyUH6MXfmrfRUR6+DlUMKY w==; X-CSE-ConnectionGUID: UGZuY5yJQFaQY0JGLDbVMQ== X-CSE-MsgGUID: By4cueKtS5qRLPrJFzVQpw== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807250" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807250" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:36 -0800 X-CSE-ConnectionGUID: E4xCg1EISUuh6c03weLUAA== X-CSE-MsgGUID: Bmu+5afOTICcI9WU8zaUpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287730" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:34 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:32 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 3/9] drm/i915: Introduce plane->can_async_flip() Date: Mon, 2 Dec 2024 16:14:18 +0200 Message-ID: <20241202141424.21446-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move the "does this modifier support async flips?" check to be handled by the platform specific plane code instead of having a big mess in common code. Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 9 +++ .../gpu/drm/i915/display/intel_atomic_plane.c | 5 ++ .../gpu/drm/i915/display/intel_atomic_plane.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 53 +----------- .../drm/i915/display/intel_display_types.h | 1 + .../drm/i915/display/skl_universal_plane.c | 80 +++++++++++++++++++ 6 files changed, 97 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 17a1e3801a85..7455da863a26 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -672,6 +672,11 @@ vlv_primary_disable_flip_done(struct intel_plane *plane) spin_unlock_irq(&i915->irq_lock); } +static bool i9xx_plane_can_async_flip(u64 modifier) +{ + return modifier == I915_FORMAT_MOD_X_TILED; +} + static bool i9xx_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { @@ -958,19 +963,23 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->async_flip = vlv_primary_async_flip; plane->enable_flip_done = vlv_primary_enable_flip_done; plane->disable_flip_done = vlv_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; } else if (IS_BROADWELL(dev_priv)) { plane->need_async_flip_toggle_wa = true; plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = bdw_primary_enable_flip_done; plane->disable_flip_done = bdw_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; } else if (DISPLAY_VER(dev_priv) >= 7) { plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = ivb_primary_enable_flip_done; plane->disable_flip_done = ivb_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; } else if (DISPLAY_VER(dev_priv) >= 5) { plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = ilk_primary_enable_flip_done; plane->disable_flip_done = ilk_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; } modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index d89630b2d5c1..c9e8e604d40c 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -155,6 +155,11 @@ bool intel_plane_needs_physical(struct intel_plane *plane) DISPLAY_INFO(i915)->cursor_needs_physical; } +bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier) +{ + return plane->can_async_flip && plane->can_async_flip(modifier); +} + unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 0f982f452ff3..fb87b3353ab0 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -19,6 +19,7 @@ struct intel_plane; struct intel_plane_state; enum plane_id; +bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8b19008202e5..ead37c5e51f8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6515,58 +6515,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (!plane->async_flip) continue; - /* - * FIXME: This check is kept generic for all platforms. - * Need to verify this for all gen9 platforms to enable - * this selectively if required. - */ - switch (new_plane_state->hw.fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - /* - * FIXME: Async on Linear buffer is supported on ICL as - * but with additional alignment and fbc restrictions - * need to be taken care of. These aren't applicable for - * gen12+. - */ - if (DISPLAY_VER(i915) < 12) { - drm_dbg_kms(&i915->drm, - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", - plane->base.base.id, plane->base.name, - new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); - return -EINVAL; - } - break; - case I915_FORMAT_MOD_Y_TILED_CCS: - case I915_FORMAT_MOD_Yf_TILED_CCS: - /* - * Display WA #0731: skl - * WaDisableRCWithAsyncFlip: skl - * "When render decompression is enabled, hardware - * internally converts the Async flips to Sync flips." - * - * Display WA #1159: glk - * "Async flip with render compression may result in - * intermittent underrun corruption." - */ - if (DISPLAY_VER(i915) < 11) { - drm_dbg_kms(&i915->drm, - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", - plane->base.base.id, plane->base.name, - new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); - return -EINVAL; - } - break; - case I915_FORMAT_MOD_X_TILED: - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_Yf_TILED: - case I915_FORMAT_MOD_4_TILED: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_BMG_CCS: - case I915_FORMAT_MOD_4_TILED_LNL_CCS: - break; - default: + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) { drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", plane->base.base.id, plane->base.name, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ec68bbfed442..d1c9eab5b7c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1467,6 +1467,7 @@ struct intel_plane { unsigned int (*max_stride)(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); + bool (*can_async_flip)(u64 modifier); /* Write all non-self arming plane registers */ void (*update_noarm)(struct intel_dsb *dsb, struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 8621c539c110..c373b1c6babd 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -516,6 +516,79 @@ skl_plane_max_stride(struct intel_plane *plane, max_pixels, max_bytes); } +static bool tgl_plane_can_async_flip(u64 modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_LINEAR: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return true; + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + return false; + default: + return false; + } +} + +static bool icl_plane_can_async_flip(u64 modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_LINEAR: + /* + * FIXME: Async on Linear buffer is supported on ICL + * but with additional alignment and fbc restrictions + * need to be taken care of. + */ + return false; + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + return true; + default: + return false; + } +} + +static bool skl_plane_can_async_flip(u64 modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_LINEAR: + return false; + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Yf_TILED: + return true; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* + * Display WA #0731: skl + * WaDisableRCWithAsyncFlip: skl + * "When render decompression is enabled, hardware + * internally converts the Async flips to Sync flips." + * + * Display WA #1159: glk + * "Async flip with render compression may result in + * intermittent underrun corruption." + */ + return false; + default: + return false; + } +} + static u32 tgl_plane_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) @@ -2653,6 +2726,13 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->async_flip = skl_plane_async_flip; plane->enable_flip_done = skl_plane_enable_flip_done; plane->disable_flip_done = skl_plane_disable_flip_done; + + if (DISPLAY_VER(dev_priv) >= 12) + plane->can_async_flip = tgl_plane_can_async_flip; + else if (DISPLAY_VER(dev_priv) == 11) + plane->can_async_flip = icl_plane_can_async_flip; + else + plane->can_async_flip = skl_plane_can_async_flip; } if (DISPLAY_VER(dev_priv) >= 11) From patchwork Mon Dec 2 14:14:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6FA3D78327 for ; Mon, 2 Dec 2024 14:14:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F19210E75A; Mon, 2 Dec 2024 14:14:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="D+fYoZFu"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94FE010E75A for ; Mon, 2 Dec 2024 14:14:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148879; x=1764684879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L4R4mZJaf12u3/NmB7wsQJDxZdpL5mtA0CI1IKQsK4Y=; b=D+fYoZFu+WT16eifogk/2xa+WUuzR9tU/4nqG5URjecQdPM6BiwZU1EC QW2QXkFrdlZMNGc2/noTzcyhxVcrCWQjcDQ/bEa/k2/1zBjBd1UkLYPTb q3hBhGFjW15l+LQlYZwtlLaebLKAuFcRv7+fLTTB7gYLQqnZIIzSWZMgu aE8WAcfXqjCRAKoZ97IumrapBHfkTO2W57bybMij1HlT/znU+WrF5CADL Cjm8n3eMLiUHFtEooFPwLHApeVwh2UkOrU6RDFcN36At98e3Vo5ygtYFx evroogKb8/HUUC680iInj5XA6hC0kKLV/K/aFPsMDA0BB1YOecydx8z9q g==; X-CSE-ConnectionGUID: EDDebZLNTxCWW9T3RUKXnQ== X-CSE-MsgGUID: dAw7e9l/RwCWTj+FWpeFJg== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807255" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807255" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:39 -0800 X-CSE-ConnectionGUID: dt9BOlrbRz+rKB+QEOlAKg== X-CSE-MsgGUID: 1NKNB3IuRCqFzkPz2CM9Kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287736" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:37 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:35 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 4/9] drm/i915: Use plane->can_async_flip() for alignment exceptions Date: Mon, 2 Dec 2024 16:14:19 +0200 Message-ID: <20241202141424.21446-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Async flips often require bigger alignment that sync flips. Currently we have HAS_ASYNC_FLIPS() checks strewn about to inidcate that async flips are generally supported and thus we want more alignment. Switch that over to using intel_plane_can_async_flip() so that we can handle these in a slightly less messy way. Currently we don't have cases where async flips would require different alignment for different modifiers on the same plane. We'll also move the HAS_ASYNC_FLIPS() check to the plane init code so that we can still use that as a quick way to disable the async flips workarounds for testing purposes. Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 55 +++++++++---------- .../drm/i915/display/skl_universal_plane.c | 21 ++++--- 2 files changed, 37 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 7455da863a26..8d3346199645 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -779,12 +779,11 @@ static unsigned int vlv_primary_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + if (intel_plane_can_async_flip(plane, fb->modifier)) + return 256 * 1024; switch (fb->modifier) { case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(i915)) - return 256 * 1024; return 4 * 1024; case DRM_FORMAT_MOD_LINEAR: return 128 * 1024; @@ -798,13 +797,11 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + if (intel_plane_can_async_flip(plane, fb->modifier)) + return 256 * 1024; switch (fb->modifier) { case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(i915)) - return 256 * 1024; - return 4 * 1024; case DRM_FORMAT_MOD_LINEAR: return 4 * 1024; default: @@ -959,27 +956,29 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->get_hw_state = i9xx_plane_get_hw_state; plane->check_plane = i9xx_plane_check; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - plane->async_flip = vlv_primary_async_flip; - plane->enable_flip_done = vlv_primary_enable_flip_done; - plane->disable_flip_done = vlv_primary_disable_flip_done; - plane->can_async_flip = i9xx_plane_can_async_flip; - } else if (IS_BROADWELL(dev_priv)) { - plane->need_async_flip_toggle_wa = true; - plane->async_flip = g4x_primary_async_flip; - plane->enable_flip_done = bdw_primary_enable_flip_done; - plane->disable_flip_done = bdw_primary_disable_flip_done; - plane->can_async_flip = i9xx_plane_can_async_flip; - } else if (DISPLAY_VER(dev_priv) >= 7) { - plane->async_flip = g4x_primary_async_flip; - plane->enable_flip_done = ivb_primary_enable_flip_done; - plane->disable_flip_done = ivb_primary_disable_flip_done; - plane->can_async_flip = i9xx_plane_can_async_flip; - } else if (DISPLAY_VER(dev_priv) >= 5) { - plane->async_flip = g4x_primary_async_flip; - plane->enable_flip_done = ilk_primary_enable_flip_done; - plane->disable_flip_done = ilk_primary_disable_flip_done; - plane->can_async_flip = i9xx_plane_can_async_flip; + if (HAS_ASYNC_FLIPS(dev_priv)) { + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + plane->async_flip = vlv_primary_async_flip; + plane->enable_flip_done = vlv_primary_enable_flip_done; + plane->disable_flip_done = vlv_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } else if (IS_BROADWELL(dev_priv)) { + plane->need_async_flip_toggle_wa = true; + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = bdw_primary_enable_flip_done; + plane->disable_flip_done = bdw_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } else if (DISPLAY_VER(dev_priv) >= 7) { + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = ivb_primary_enable_flip_done; + plane->disable_flip_done = ivb_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } else if (DISPLAY_VER(dev_priv) >= 5) { + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = ilk_primary_enable_flip_done; + plane->disable_flip_done = ilk_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } } modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index c373b1c6babd..7eae5fe8c3a5 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -601,25 +601,24 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return mult * 4 * 1024; + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (IS_ALDERLAKE_P(i915) && + intel_plane_can_async_flip(plane, fb->modifier)) + return mult * 16 * 1024; + switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_4_TILED: - /* - * FIXME ADL sees GGTT/DMAR faults with async - * flips unless we align to 16k at least. - * Figure out what's going on here... - */ - if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) - return mult * 16 * 1024; return mult * 4 * 1024; case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) - return mult * 16 * 1024; - fallthrough; case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: @@ -2721,7 +2720,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; - if (plane_id == PLANE_1) { + if (HAS_ASYNC_FLIPS(dev_priv) && plane_id == PLANE_1) { plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); plane->async_flip = skl_plane_async_flip; plane->enable_flip_done = skl_plane_enable_flip_done; From patchwork Mon Dec 2 14:14:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 800D7D78326 for ; Mon, 2 Dec 2024 14:14:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 25B6610E766; Mon, 2 Dec 2024 14:14:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DSYQazhg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85CE910E75E for ; Mon, 2 Dec 2024 14:14:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148882; x=1764684882; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dPDVWd5cFZ0h+z3IpfCq5qzIH45MgS9lrNojiFR2mCE=; b=DSYQazhgJFF+18F+dVpSIMYNZbU/fkOeZHOjCEr0Zvjtx+GfGjYWeVgR 44MMk3hUvSir5A8UhaGTuaMTjpxW6hILRYuX4sp7AFXTPTlQv+mHZ+h2h MQqxZE5/1BRTi/xOMBWm2v7f+FegTh34GkWh6EJQOU1D05rGh59HdCwIc 1Zmtqt2ORfDf3AZjj1kYDCnrVtCeRRyCdgPCJY+YNgdIvtUn/MWgAmuoW fbQ+x+utjBQCPQZZiZgIdxlFW5jji7M3PBR4BUIAQo6/lyVxGrzJY+BhO DSt/H2tFe4Ii6SJWcDZIh56vXX2/JUDcRoUEjlME7YAEeTADvOf/iVJk0 A==; X-CSE-ConnectionGUID: eUP8SlZZQymhv4ASvrfh/w== X-CSE-MsgGUID: WSr4Cm8PTFu53ZmFjWfeSQ== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807258" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807258" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:42 -0800 X-CSE-ConnectionGUID: W0GoIw/0QtumXwilENaeaQ== X-CSE-MsgGUID: mM3UfNFnS1O+NN8QZGhbpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287741" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:40 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:38 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 5/9] drm/i915: Reuse vlv_primary_min_alignment() for sprites as well Date: Mon, 2 Dec 2024 16:14:20 +0200 Message-ID: <20241202141424.21446-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Rename vlv_primary_min_alignment() to vlv_plane_min_alignment() and use it to replace vlv_sprite_min_alignment() since the behaviour is now identical when the plane init doesn't set up any async flips stuff. Technically VLV/CHV sprites do support async flips, so this also makes us a bit more future proof if/when we extend async flip support to more than one plane. Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 8 ++++---- drivers/gpu/drm/i915/display/i9xx_plane.h | 4 ++++ drivers/gpu/drm/i915/display/intel_sprite.c | 17 +---------------- 3 files changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 8d3346199645..943dcd3b7a0e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -775,9 +775,9 @@ i8xx_plane_max_stride(struct intel_plane *plane, return 8 * 1024; } -static unsigned int vlv_primary_min_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) +unsigned int vlv_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) { if (intel_plane_can_async_flip(plane, fb->modifier)) return 256 * 1024; @@ -938,7 +938,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) } if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - plane->min_alignment = vlv_primary_min_alignment; + plane->min_alignment = vlv_plane_min_alignment; else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) plane->min_alignment = g4x_primary_min_alignment; else if (DISPLAY_VER(dev_priv) == 4) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h index 0ca12d1e6839..457f4bccf106 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h @@ -9,6 +9,7 @@ #include enum pipe; +struct drm_framebuffer; struct drm_i915_private; struct intel_crtc; struct intel_initial_plane_config; @@ -19,6 +20,9 @@ struct intel_plane_state; unsigned int i965_plane_max_stride(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); +unsigned int vlv_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int colot_plane); int i9xx_check_plane_surface(struct intel_plane_state *plane_state); struct intel_plane * diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e6fadcef58e0..13996d7059ad 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -253,21 +253,6 @@ int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, return DIV_ROUND_UP(pixel_rate * num, den); } -static unsigned int vlv_sprite_min_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) -{ - switch (fb->modifier) { - case I915_FORMAT_MOD_X_TILED: - return 4 * 1024; - case DRM_FORMAT_MOD_LINEAR: - return 128 * 1024; - default: - MISSING_CASE(fb->modifier); - return 0; - } -} - static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 sprctl = 0; @@ -1616,7 +1601,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = vlv_sprite_get_hw_state; plane->check_plane = vlv_sprite_check; plane->max_stride = i965_plane_max_stride; - plane->min_alignment = vlv_sprite_min_alignment; + plane->min_alignment = vlv_plane_min_alignment; plane->min_cdclk = vlv_plane_min_cdclk; if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { From patchwork Mon Dec 2 14:14:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4210D78321 for ; Mon, 2 Dec 2024 14:14:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B0D410E75B; Mon, 2 Dec 2024 14:14:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kuxcozsv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 683E010E75B for ; Mon, 2 Dec 2024 14:14:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148885; x=1764684885; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I12DxTKveVvnwPOvtSgCj1H/MwMZ2vrlFf/havmMyN4=; b=kuxcozsvkcFdAnqrqpcRy/UTx4orHT8Z+eYRGJtpTO5b9i98q1YPEj+A e6S1YLMQZMmUxvq+v57p6GuyDtYwNUhdi1n3DywaurtB3C+NZ5LcelG98 qFrk1RB0pUI41tIha9Nla53NfH5yroJCLESvc7neAyTQCv6XcUSKytVfq nXpBu+MyrtjLojkYfKxZBjbQdn9vL8XMc2odps9O4cLl8inqrTOD/PlBT vpAHZgC48aymneKvvFguuDlISkpDu24HExHJQvrhcIal8Zk5buMVbj8W5 aYR8F1sWWBi9r7iwSIKMEcz2L/LxLVHfdc3G9oIbhuNUT7xFYHS1wfkoG g==; X-CSE-ConnectionGUID: 41vgrHZ4RWKdzXZ2lbtLiQ== X-CSE-MsgGUID: 2SZPpOm+Qnqni2UgVDsVWQ== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807261" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807261" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:45 -0800 X-CSE-ConnectionGUID: fyTI/WIPRHGJ9pmx64rfmw== X-CSE-MsgGUID: iMWDGH6/SnOoBfLwDoLemQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287744" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:43 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:41 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 6/9] drm/i915: Disable scanout VT-d workaround for TGL+ Date: Mon, 2 Dec 2024 16:14:21 +0200 Message-ID: <20241202141424.21446-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä TGL+ should no longer need any VT-d scanout workarounds. Don't apply any. Not 100% sure whether pre-SNB might also suffer from this. The workaround did originate on SNB but who knows if it was just never caught before that. Not that I ever managed to enable VT-d any older hardware. Last time I tried on my ILK it ate the disk! Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ead37c5e51f8..8ff6d1ae44fd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8727,5 +8727,5 @@ void intel_hpd_poll_fini(struct drm_i915_private *i915) bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) { - return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); + return IS_DISPLAY_VER(i915, 6, 11) && i915_vtd_active(i915); } From patchwork Mon Dec 2 14:14:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED28CD78327 for ; Mon, 2 Dec 2024 14:14:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7794810E763; Mon, 2 Dec 2024 14:14:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="g4nMUr/j"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 79AA910E75E for ; Mon, 2 Dec 2024 14:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148888; x=1764684888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lewTZBgh1+9yfkRb859mL9yGruawPh6t1hUo/+7tOd0=; b=g4nMUr/j1k4y8AofMegG5TjJu5W40Y+oTjjWBpu94+TwOIGLoI9ZnfBB sIX6sY0JgFSQpDJ3NAF2pmlibCV/SVZspj84/6FHsu+ErJkTRsbjylqp/ F0qY7RgsleC47101u/KeE8abF39Dk23Wzrwl5cE/82zwKaQmU9LCaoGtn x66BAKVIM/6AVN3+sHxrM4+dNruUvSiXsoxZeqL8uaC7AXVQl+b54rzBT L2GMiDDBD/6FaYlWLubCwgLxxmPsHOza5GFRmrIXgEh/UUPd1ao+T6fCG N160/HGlqaSKDmMO2UcKEJzlBRiNPEspuToj4gIL2ecRdOYnSqUE9zQ7d g==; X-CSE-ConnectionGUID: YCOx/gedRl6JmfmA5YTOhA== X-CSE-MsgGUID: sqqWAy+4TxKq7WqT946YsQ== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807265" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807265" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:48 -0800 X-CSE-ConnectionGUID: utdtXNwSStCEVOjEPhV5/w== X-CSE-MsgGUID: vlwR9ucjR0SBLe1tcMpkZw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287754" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:45 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:44 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 7/9] drm/i915: Nuke ADL pre-production Wa_22011186057 Date: Mon, 2 Dec 2024 16:14:22 +0200 Message-ID: <20241202141424.21446-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Wa_22011186057 (some CCS problem) only affected ADL A-stepping, which I presume is pre-production hw. Drop the dead code. Bspec: 54369 Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7eae5fe8c3a5..57e8e536ee1f 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2589,10 +2589,6 @@ skl_plane_disable_flip_done(struct intel_plane *plane) static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, enum pipe pipe, enum plane_id plane_id) { - /* Wa_22011186057 */ - if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) - return false; - if (DISPLAY_VER(i915) >= 11) return true; @@ -2614,10 +2610,6 @@ static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915, (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) return false; - /* Wa_22011186057 */ - if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) - return false; - return plane_id < PLANE_6; } From patchwork Mon Dec 2 14:14:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17906D78327 for ; Mon, 2 Dec 2024 14:14:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7DA210E757; Mon, 2 Dec 2024 14:14:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lopivi/i"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59E6C10E757 for ; Mon, 2 Dec 2024 14:14:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148891; x=1764684891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WbgPIQBSDJRVBDLWBf/0NmYolnvvU8KXMRph46GdcUg=; b=lopivi/iX2bQSPZ0gruVLSvJyerDDGGgqxlKMsUvMqLstwAtN9Zd4Efm +bm4FCwNX/wGcX2+y84tU3xc1lpb1AQVmC0WsUL8gFdGmyyFuojlQmfl1 xKQ4BsroGCnFSdijkFjm4YLqIaImaE6ojXoDJIl/FD9C9yLFvMyaW0n4U XetNkM7+op2LqkSKfEd2RgK2ry+Nqz1asMke7Wdnd+ZuQPlP4CIx1A2lX a8M6A6lcpTErC0fgtzaAVT4pxamyM5AZZy/k/eG61D/iu3CHhLjbhtDPB fdD2YwKHfdRbgpAf39hkOwGyDXG8M+esqfXn6aesxOblU937ATL1lFK5K g==; X-CSE-ConnectionGUID: 8NYrLrOxREKZdnJdNnGa2A== X-CSE-MsgGUID: XujHR3tPTbWd9H/l6RRmiw== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807271" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807271" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:51 -0800 X-CSE-ConnectionGUID: iOD+wBzNTH6vhRICNw4+pA== X-CSE-MsgGUID: 8ca5vCqmQKGuvx0Ltl7F9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287764" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:48 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:47 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 8/9] drm/i915: Relocate xe AUX hack Date: Mon, 2 Dec 2024 16:14:23 +0200 Message-ID: <20241202141424.21446-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Move the xe AUX neutering out from skl_get_plane_caps() into the caller so that it'll be easier to refactor skl_get_plane_caps() into a more readable shape. This isn't really hardware specific anyway, and just some kind of bug/misfeature of xe. Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/skl_universal_plane.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 57e8e536ee1f..b06dc106305e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2626,9 +2626,6 @@ static u8 skl_get_plane_caps(struct drm_i915_private *i915, if (HAS_4TILE(display)) caps |= INTEL_PLANE_CAP_TILING_4; - if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915)) - return caps; - if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { caps |= INTEL_PLANE_CAP_CCS_RC; if (DISPLAY_VER(display) >= 12) @@ -2657,6 +2654,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, const u32 *formats; int num_formats; int ret; + u8 caps; plane = intel_plane_alloc(); if (IS_ERR(plane)) @@ -2748,8 +2746,15 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_type = DRM_PLANE_TYPE_OVERLAY; - modifiers = intel_fb_plane_get_modifiers(dev_priv, - skl_get_plane_caps(dev_priv, pipe, plane_id)); + caps = skl_get_plane_caps(dev_priv, pipe, plane_id); + + /* FIXME: xe has problems with AUX */ + if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(dev_priv)) + caps &= ~(INTEL_PLANE_CAP_CCS_RC | + INTEL_PLANE_CAP_CCS_RC_CC | + INTEL_PLANE_CAP_CCS_MC); + + modifiers = intel_fb_plane_get_modifiers(dev_priv, caps); ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, From patchwork Mon Dec 2 14:14:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13890770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97748D78328 for ; Mon, 2 Dec 2024 14:14:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B07C10E75E; Mon, 2 Dec 2024 14:14:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Oq5DA4eD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 39A3310E75E for ; Mon, 2 Dec 2024 14:14:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733148894; x=1764684894; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CFYr3jjhVaoHw7QEPZUQpCbwNjqQ/5WgXVYVOtRzKTc=; b=Oq5DA4eDb29MPD3WEZH2m/X6F3TOadbhJXuZOecSoG9fvolIpFD7TXxj RWopSIkLTiMmt84+d8FQK91pjIM26O14dudtEPgBDsGkKBIRTRIzCTDJp oVZJ+kPwu8FyDU/N8yAgaVIrf/z2EUZVkrCEQEnBV8+l5zoJ5uWgCHxn3 z8P3QUheGqh4Qyezc/Qet5Ne3LnPyG7oTiVzMeKNF6ENa3xo8X2ULASjf E1t6OIJpT+Q0bNN+va6T+PkiM7Co22XYsTevX+2jOJFkObq2x2MsPD4/d BkY10LOmMNlioJFW0jFmFScVazHA9hRnf+K4l9SVer/3GiIlPRb8sXX6Y g==; X-CSE-ConnectionGUID: oT3pnjzRQxWdajZsxz64rA== X-CSE-MsgGUID: mVMOLaaVSQyfxuZqnz8GeA== X-IronPort-AV: E=McAfee;i="6700,10204,11274"; a="55807273" X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="55807273" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Dec 2024 06:14:53 -0800 X-CSE-ConnectionGUID: HizgTLT9Q+GPS+LOHtEJJg== X-CSE-MsgGUID: MYdSz/ffTQK24ZWTJMOeHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,202,1728975600"; d="scan'208";a="93287773" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 02 Dec 2024 06:14:51 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 02 Dec 2024 16:14:50 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 9/9] drm/i915: Carve up skl_get_plane_caps() Date: Mon, 2 Dec 2024 16:14:24 +0200 Message-ID: <20241202141424.21446-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241202141424.21446-1-ville.syrjala@linux.intel.com> References: <20241202141424.21446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Split skl_get_plane_caps() into four variants: skl_plane_caps(), glk_plane_caps(), icl_plane_caps(), tgl_plane_caps(). Makes it easier to figure out what is actually going on there. v2: skl_plane_caps() should return u8 not bool v3: Rebase due to intel_display changes Reviewed-by: Jouni Högander Signed-off-by: Ville Syrjälä --- .../drm/i915/display/skl_universal_plane.c | 81 +++++++++++++------ 1 file changed, 57 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index b06dc106305e..26a44da63352 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2589,48 +2589,74 @@ skl_plane_disable_flip_done(struct intel_plane *plane) static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, enum pipe pipe, enum plane_id plane_id) { - if (DISPLAY_VER(i915) >= 11) - return true; - - if (IS_GEMINILAKE(i915)) - return pipe != PIPE_C; - return pipe != PIPE_C && (plane_id == PLANE_1 || plane_id == PLANE_2); } +static u8 skl_plane_caps(struct drm_i915_private *i915, + enum pipe pipe, enum plane_id plane_id) +{ + u8 caps = INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_TILING_Y | + INTEL_PLANE_CAP_TILING_Yf; + + if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) + caps |= INTEL_PLANE_CAP_CCS_RC; + + return caps; +} + +static bool glk_plane_has_rc_ccs(struct drm_i915_private *i915, + enum pipe pipe) +{ + return pipe != PIPE_C; +} + +static u8 glk_plane_caps(struct drm_i915_private *i915, + enum pipe pipe, enum plane_id plane_id) +{ + u8 caps = INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_TILING_Y | + INTEL_PLANE_CAP_TILING_Yf; + + if (glk_plane_has_rc_ccs(i915, pipe)) + caps |= INTEL_PLANE_CAP_CCS_RC; + + return caps; +} + +static u8 icl_plane_caps(struct drm_i915_private *i915, + enum pipe pipe, enum plane_id plane_id) +{ + return INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_TILING_Y | + INTEL_PLANE_CAP_TILING_Yf | + INTEL_PLANE_CAP_CCS_RC; +} + static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915, enum plane_id plane_id) { - if (DISPLAY_VER(i915) < 12) - return false; - /* Wa_14010477008 */ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || - (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) + (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) return false; return plane_id < PLANE_6; } -static u8 skl_get_plane_caps(struct drm_i915_private *i915, - enum pipe pipe, enum plane_id plane_id) +static u8 tgl_plane_caps(struct drm_i915_private *i915, + enum pipe pipe, enum plane_id plane_id) { struct intel_display *display = &i915->display; - u8 caps = INTEL_PLANE_CAP_TILING_X; + u8 caps = INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_CCS_RC | + INTEL_PLANE_CAP_CCS_RC_CC; - if (DISPLAY_VER(display) < 13 || display->platform.alderlake_p) - caps |= INTEL_PLANE_CAP_TILING_Y; - if (DISPLAY_VER(display) < 12) - caps |= INTEL_PLANE_CAP_TILING_Yf; if (HAS_4TILE(display)) caps |= INTEL_PLANE_CAP_TILING_4; - - if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { - caps |= INTEL_PLANE_CAP_CCS_RC; - if (DISPLAY_VER(display) >= 12) - caps |= INTEL_PLANE_CAP_CCS_RC_CC; - } + else + caps |= INTEL_PLANE_CAP_TILING_Y; if (tgl_plane_has_mc_ccs(i915, plane_id)) caps |= INTEL_PLANE_CAP_CCS_MC; @@ -2746,7 +2772,14 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_type = DRM_PLANE_TYPE_OVERLAY; - caps = skl_get_plane_caps(dev_priv, pipe, plane_id); + if (DISPLAY_VER(dev_priv) >= 12) + caps = tgl_plane_caps(dev_priv, pipe, plane_id); + else if (DISPLAY_VER(dev_priv) == 11) + caps = icl_plane_caps(dev_priv, pipe, plane_id); + else if (DISPLAY_VER(dev_priv) == 10) + caps = glk_plane_caps(dev_priv, pipe, plane_id); + else + caps = skl_plane_caps(dev_priv, pipe, plane_id); /* FIXME: xe has problems with AUX */ if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(dev_priv))