From patchwork Tue Dec 3 03:31:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7646DE6C5F7 for ; Tue, 3 Dec 2024 03:32:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 759A610E8CE; Tue, 3 Dec 2024 03:32:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.b="QjSEQAOY"; dkim-atps=neutral Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 36CA410E1BA; Tue, 3 Dec 2024 03:32:21 +0000 (UTC) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2J7huQ000834; Tue, 3 Dec 2024 03:32:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= q+/VEcu7485AIiWnGGkcoGwamNFxW5YujbP2wZ4RsSs=; b=QjSEQAOYJklNjhNE VPT4y9AKgBl7XbnBBCSxCzuzGnTDW4viJd01mey2LEkJo/7mmbr3acg+fLiC3hrt //Wv/4rtJBJ/VxSZe+bXTReeM3ZOqKG7PKGI+lY3Hsh2kiJXj2+vueOeRwBWbdgG i0WdOUoqiHXguUKpvR91ZESs6Mg9EiOW2PDSczn8vYP5mluUdyb6oPeWbJpFjuFN nKRIFsuRz+0yu4tC17+ms5VhX678nQQGbercnJ4hjG4mDk8A1i9UWO2GuSmUlcMp ABqOCd2tPu+WJpDeM8Ed6dgyBOXXG3dSvvhm1a8PknXUSrG93kalTgKb6aReHx42 oAGl1Q== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437t1gerv5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Dec 2024 03:32:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WDtk003564 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:13 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:12 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:39 -0800 Subject: [PATCH 1/4] dt-bindings: display: msm: dp-controller: document pixel clock stream MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-1-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733196732; l=1325; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=Wc3cnVwQNfQLJ9bbuGhzSSJFTzHRGdE5UAbMwFKKjjo=; b=Bb1l1WQLAjnOWYsL6BUXGEq5O+rUIc6lr8E+cGxLucHIdLXONyE1NpTDF0Y+3VdlwcBg8BKYN XObLkYinHcSD2qMxmdTl4tRe71t8IJEmwqG8gTRQDiZYgLpgGHgkE+z X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kurS0t8mD_469EJxwOUNwkGKY6ecwK4y X-Proofpoint-ORIG-GUID: kurS0t8mD_469EJxwOUNwkGKY6ecwK4y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=936 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030028 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display port controller on some MSM chipsets are capable of supporting multiple streams. In order to distinguish the streams better, describe the current pixel clock better to emphasize that it drives the stream 0. Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index a212f335d5ff..35ae2630c2b3 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -55,7 +55,7 @@ properties: - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock clock-names: items: @@ -68,7 +68,7 @@ properties: assigned-clocks: items: - description: link clock source - - description: pixel clock source + - description: stream 0 pixel clock source assigned-clock-parents: items: From patchwork Tue Dec 3 03:31:40 2024 Content-Type: text/plain; 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Tue, 03 Dec 2024 03:32:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WEpe028939 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:14 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:13 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:40 -0800 Subject: [PATCH 2/4] dt-bindings: display: msm: dp-controller: document clock parents better MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-2-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 35ae2630c2b3..9fe2bf0484d8 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -72,8 +72,8 @@ properties: assigned-clock-parents: items: - - description: phy 0 parent - - description: phy 1 parent + - description: Link clock PLL output provided by PHY block + - description: Stream 0 pixel clock PLL output provided by PHY block phys: maxItems: 1 From patchwork Tue Dec 3 03:31:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1409E6C5F8 for ; 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Tue, 03 Dec 2024 03:32:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WEeY003570 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:14 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:14 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:41 -0800 Subject: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock binding MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-3-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733196732; l=4326; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=WOGgVxaSyvealCotRclm+4BylMOthHPB34gcr+z71s8=; b=/HH69Y2AK4ZWZz3GL7UWlJlCQCqMWMFIsmXhLWyPJp+a6LSKM2T3qLbk25ZR1zVKOL6iuSd/I 2LiI614tW5TAAyCJLJEgG6bmFyHTPzQkQT+1urSoZliQEGUSM2GzlqE X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8BVxJ41RklhKrqVG9iUk9MLrvvPyWkpb X-Proofpoint-GUID: 8BVxJ41RklhKrqVG9iUk9MLrvvPyWkpb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030028 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On some chipsets the display port controller can support more than one pixel stream (multi-stream transport). To support MST on such chipsets, add the binding for stream 1 pixel clock for display port controller. Since this mode is not supported on all chipsets, add exception rules and min/max items to clearly mark which chipsets support only SST mode (single stream) and which ones support MST. Signed-off-by: Abhinav Kumar --- .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++ .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9fe2bf0484d8..650d19e58277 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -50,30 +50,38 @@ properties: maxItems: 1 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel assigned-clocks: + minItems: 2 items: - description: link clock source - description: stream 0 pixel clock source + - description: stream 1 pixel clock source assigned-clock-parents: + minItems: 2 items: - description: Link clock PLL output provided by PHY block - description: Stream 0 pixel clock PLL output provided by PHY block + - description: Stream 1 pixel clock PLL output provided by PHY block phys: maxItems: 1 @@ -175,6 +183,30 @@ allOf: required: - "#sound-dai-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + - const: stream_1_pixel + assigned-clocks: + maxItems: 3 + assigned-clock-parents: + maxItems: 3 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index 58f8a01f29c7..7f10e6ad8f63 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -177,16 +177,19 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>, <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; + assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>, <&mdss0_edp_phy 1>; phys = <&mdss0_edp_phy>; phy-names = "dp"; From patchwork Tue Dec 3 03:31:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46054E6C5F6 for ; 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Tue, 03 Dec 2024 03:32:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WFhX003573 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:15 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:14 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:42 -0800 Subject: [PATCH 4/4] dt-bindings: display: msm: dp: update maintainer entry MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-4-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Signed-off-by: Abhinav Kumar Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 650d19e58277..9867eb5133ab 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -8,6 +8,7 @@ title: MSM Display Port Controller maintainers: - Kuogee Hsieh + - Abhinav Kumar description: | Device tree bindings for DisplayPort host controller for MSM targets