From patchwork Tue Dec 3 10:49:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892145 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C98EC1E284A; Tue, 3 Dec 2024 10:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223351; cv=none; b=Iog8UDY9bCor3ePaWBoRA86bjgAKBz0G/jem4ci5SyA2XA1emlTDPpIpSbafc5i/dtz2Db/ULu4GnowLvFV1AeEmXCMUB0MG1/2XmmYcHlFoO29OzHlXtPvzJ/WzZ6JfSlLdx9ib+V7ki/NT/lakcp9qHnm8mH6stBjd6wOZpwk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223351; c=relaxed/simple; bh=il5uQxRRwe3m1cW8/aVHsvKrWXrxpCQj0vVq+9VUl88=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=siRdRtgfXIzlXYmKDCYjJr5QKAMQWuvlYV3/gU/zkltX9FnbpgVzNNTE0J4ekE6GV+VUZOR1c54hvb5YYAXaSX8YFUz4jJhA/MZ4V3b/yBRg85bAQ36CVPNLcljNHzxWCW4o4aRyHgc6H7/xWx8CDToBLVSfEUGUcsnZrETt9OA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: r4vTt+CxSIOfAhlqah7OKQ== X-CSE-MsgGUID: YrcfNOrUQZ6zR4nofdf4Ig== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="226779505" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:40 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9A6DA4003FA4; Tue, 3 Dec 2024 19:50:24 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v2 04/13] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG Date: Tue, 3 Dec 2024 10:49:31 +0000 Message-ID: <20241203105005.103927-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Added Ack from Conor Dooley. * Fixed typo "CORE_CLK*"->"CORECLK*" to match with hardware manual. --- .../bindings/clock/renesas,rzv2h-cpg.yaml | 15 +++++++------ .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index 926c503bed1f..c3fe76abd549 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,19 +4,22 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar description: - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation - and control of clock signals for the IP modules, generation and control of resets, - and control over booting, low power consumption and power supply domains. + On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + generation and control of clock signals for the IP modules, generation and + control of resets, and control over booting, low power consumption and power + supply domains. properties: compatible: - const: renesas,r9a09g057-cpg + enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H reg: maxItems: 1 @@ -37,7 +40,7 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - , + , - For module clocks, the two clock specifier cells must be "CPG_MOD" and a module number. The module number is calculated as the CLKON register offset index multiplied by 16, plus the actual bit in the register diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ From patchwork Tue Dec 3 10:49:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892130 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2CD801DDA37; Tue, 3 Dec 2024 10:50:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223045; cv=none; b=GFszVbn+FiZC5Vyy7dVsynmry1u0caymMn5+nrROgcu3BQ1jowc5m16o5aiGmfEJpmhwI1ivwVUptzk5PbWZ5fp2724gpAAWJLHCmNzfa+DiXWcdoZOWKlWN+MUsk1wvTCIOhbmj6/GIRwlny6U0+Nr9RCtyqQR7PkWs5IYt/XU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223045; c=relaxed/simple; bh=FcaYsPwrLK3ZqoRhidvcE0etwCXxgZRYqtlhKQkntBI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oy8yEGWCSSKUPN0J24XfFNO17ZS/KgQIL4dqyuj4NXU2bQpEO6Sdw2/wXsXBpbtewuCGJS2NJHU9W+OkHvrZ8jga3AZy5jFp0MY+iuesSyuGSYP374YoPrfPcmvp9kGpHtE/nW8DsWdblQ12J7VCtuDKjKLj0ExX+ohjKjCwLc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: xo2p3+PHTyuoVpmJzaMLDQ== X-CSE-MsgGUID: Nd9GqulZTteRNK0eBOEcwg== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754411" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:42 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7900F40061AD; Tue, 3 Dec 2024 19:50:31 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 06/13] clk: renesas: Add support for RZ/G3E SoC Date: Tue, 3 Dec 2024 10:49:33 +0000 Message-ID: <20241203105005.103927-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1 are present only on the RZ/G3E SoC. Add minimal clock and reset entries required to boot the Renesas RZ/G3E SMARC EVK and binds it with the RZ/V2H CPG core driver. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/clk/renesas/Kconfig | 7 ++- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g047-cpg.c | 98 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 6 ++ drivers/clk/renesas/rzv2h-cpg.h | 1 + 5 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index ff01f5f0ed20..5a4bc3f94d49 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -40,6 +40,7 @@ config CLK_RENESAS select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 + select CLK_R9A09G047 if ARCH_R9A09G047 select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_SH73A0 if ARCH_SH73A0 @@ -194,6 +195,10 @@ config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A09G047 + bool "RZ/G3E clock support" if COMPILE_TEST + select CLK_RZV2H + config CLK_R9A09G057 bool "RZ/V2H(P) clock support" if COMPILE_TEST select CLK_RZV2H @@ -234,7 +239,7 @@ config CLK_RZG2L select RESET_CONTROLLER config CLK_RZV2H - bool "RZ/V2H(P) family clock support" if COMPILE_TEST + bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST select RESET_CONTROLLER config CLK_RENESAS_VBATTB diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 82efaa835ac7..2d6e746939c4 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o +obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c new file mode 100644 index 000000000000..5d7611cee9bc --- /dev/null +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3E CPG driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzv2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK, + + /* External Input Clocks */ + CLK_AUDIO_EXTAL, + CLK_RTXIN, + CLK_QEXTAL, + + /* PLL Clocks */ + CLK_PLLCM33, + CLK_PLLDTY, + CLK_PLLCA55, + + /* Internal Core Clocks */ + CLK_PLLCM33_DIV16, + CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct clk_div_table dtable_2_64[] = { + {0, 2}, + {1, 4}, + {2, 8}, + {3, 16}, + {4, 64}, + {0, 0}, +}; + +static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), + DEF_INPUT("rtxin", CLK_RTXIN), + DEF_INPUT("qextal", CLK_QEXTAL), + + /* PLL Clocks */ + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), + + /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + + DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), + + /* Core Clocks */ + DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), +}; + +static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), +}; + +static const struct rzv2h_reset r9a09g047_resets[] __initconst = { + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ +}; + +const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { + /* Core Clocks */ + .core_clks = r9a09g047_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r9a09g047_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), + .num_hw_mod_clks = 28 * 16, + + /* Resets */ + .resets = r9a09g047_resets, + .num_resets = ARRAY_SIZE(r9a09g047_resets), +}; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 1154493583a7..ef26e7760a88 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -868,6 +868,12 @@ static const struct of_device_id rzv2h_cpg_match[] = { .compatible = "renesas,r9a09g057-cpg", .data = &r9a09g057_cpg_info, }, +#endif +#ifdef CONFIG_CLK_R9A09G047 + { + .compatible = "renesas,r9a09g047-cpg", + .data = &r9a09g047_cpg_info, + }, #endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index ed8d2cad3260..1e5bf1eb65a4 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -202,6 +202,7 @@ struct rzv2h_cpg_info { unsigned int num_resets; }; +extern const struct rzv2h_cpg_info r9a09g047_cpg_info; extern const struct rzv2h_cpg_info r9a09g057_cpg_info; #endif /* __RENESAS_RZV2H_CPG_H__ */ From patchwork Tue Dec 3 10:49:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892144 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 656D81E284D for ; Tue, 3 Dec 2024 10:55:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223342; cv=none; b=kI9Qct8Ihyq/ysrJ823DVHzjK0s5xD8zE3a82qnvF9Oq8Q+wLFRSVbrogbSFdDBE/PqK5a6VyE5t34p9ejbAiV6eRa2zzCIrvncJIiWnMXfqQRCMoGvre8rs8H2TDKl/QWGD3ikeL92ttR1OgASkV746dLlHWyyvhPMKJinpl9g= ARC-Message-Signature: i=1; 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03 Dec 2024 19:50:37 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 653C040015FF; Tue, 3 Dec 2024 19:50:34 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 07/13] clk: renesas: rzv2h-cpg: Add MSTOP support Date: Tue, 3 Dec 2024 10:49:34 +0000 Message-ID: <20241203105005.103927-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add bus MSTOP support for RZ/{V2H, G3E}. For some module clocks, there are no MSTOP bits and the sequence ordering for mstop and clock on is different compared to the RZ/G2L family. Signed-off-by: Biju Das --- v1->v2: * This patch has dependency on [1] * Added MSTOP data for RZ/V2H CRU IP. * Fixed typo clock->clk in error path of rzv2h_cpg_register_mod_clk() [1] https://lore.kernel.org/all/20241202203916.48668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ --- drivers/clk/renesas/r9a09g047-cpg.c | 6 +- drivers/clk/renesas/r9a09g057-cpg.c | 153 ++++++++++++++++++---------- drivers/clk/renesas/rzv2h-cpg.c | 92 ++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 26 +++-- 4 files changed, 214 insertions(+), 63 deletions(-) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 5d7611cee9bc..ab63a7e7e480 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -69,8 +69,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { - DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19), - DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, + BUS_MSTOP(3, BIT(5))), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, + BUS_MSTOP(3, BIT(14))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 5aa9710aa402..5539fdb13d57 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -115,57 +115,108 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { - DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5), - DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3), - DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4), - DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5), - DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6), - DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7), - DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8), - DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9), - DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10), - DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11), - DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12), - DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13), - DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14), - DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15), - DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16), - DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17), - DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18), - DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), - DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19), - DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20), - DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21), - DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22), - DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23), - DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24), - DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25), - DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26), - DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27), - DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3), - DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4), - DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5), - DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6), - DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7), - DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8), - DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9), - DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10), - DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11), - DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12), - DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13), - DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14), - DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18), - DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19), - DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20), - DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21), - DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22), - DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23), - DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24), - DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25), - DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26), - DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27), - DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28), - DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29), + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NO_DATA), + DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, + BUS_MSTOP(5, BIT(10))), + DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, + BUS_MSTOP(5, BIT(11))), + DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, + BUS_MSTOP(2, BIT(13))), + DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, + BUS_MSTOP(2, BIT(14))), + DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, + BUS_MSTOP(11, BIT(13))), + DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, + BUS_MSTOP(11, BIT(14))), + DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, + BUS_MSTOP(11, BIT(15))), + DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, + BUS_MSTOP(12, BIT(0))), + DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, + BUS_MSTOP(3, BIT(10))), + DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, + BUS_MSTOP(3, BIT(10))), + DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, + BUS_MSTOP(5, BIT(13))), + DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, + BUS_MSTOP(5, BIT(13))), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, + BUS_MSTOP(3, BIT(14))), + DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, + BUS_MSTOP(3, BIT(13))), + DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, + BUS_MSTOP(1, BIT(1))), + DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, + BUS_MSTOP(1, BIT(2))), + DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, + BUS_MSTOP(1, BIT(3))), + DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, + BUS_MSTOP(1, BIT(4))), + DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, + BUS_MSTOP(1, BIT(5))), + DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, + BUS_MSTOP(1, BIT(6))), + DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, + BUS_MSTOP(1, BIT(7))), + DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, + BUS_MSTOP(1, BIT(8))), + DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, + BUS_MSTOP_NO_DATA), + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, + BUS_MSTOP(9, BIT(4))), + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, + BUS_MSTOP(9, BIT(4))), + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, + BUS_MSTOP(9, BIT(4))), + DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, + BUS_MSTOP(9, BIT(5))), + DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, + BUS_MSTOP(9, BIT(5))), + DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, + BUS_MSTOP(9, BIT(5))), + DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, + BUS_MSTOP(9, BIT(6))), + DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, + BUS_MSTOP(9, BIT(6))), + DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, + BUS_MSTOP(9, BIT(6))), + DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, + BUS_MSTOP(9, BIT(7))), + DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, + BUS_MSTOP(9, BIT(7))), + DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, + BUS_MSTOP(9, BIT(7))), }; static const struct rzv2h_reset r9a09g057_resets[] __initconst = { diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index ef26e7760a88..fb5221faabea 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -83,6 +84,11 @@ struct rzv2h_cpg_priv { #define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev) +struct rzv2h_mstop { + u32 data; + refcount_t ref_cnt; +}; + struct pll_clk { struct rzv2h_cpg_priv *priv; void __iomem *base; @@ -97,6 +103,7 @@ struct pll_clk { * struct mod_clock - Module clock * * @priv: CPG private data + * @mstop: handle to cpg bus mstop data * @hw: handle between common and hardware-specific interfaces * @no_pm: flag to indicate PM is not supported * @on_index: register offset @@ -106,6 +113,7 @@ struct pll_clk { */ struct mod_clock { struct rzv2h_cpg_priv *priv; + struct rzv2h_mstop *mstop; struct clk_hw hw; bool no_pm; u8 on_index; @@ -433,6 +441,38 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, core->name, PTR_ERR(clk)); } +static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, + struct mod_clock *clock) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&priv->rmw_lock, flags); + if (!refcount_read(&clock->mstop->ref_cnt)) { + val = BUS_MSTOP_VAL(clock->mstop->data) << 16; + writel(val, priv->base + BUS_MSTOP_OFF(clock->mstop->data)); + refcount_set(&clock->mstop->ref_cnt, 1); + } else { + refcount_inc(&clock->mstop->ref_cnt); + } + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + +static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv, + struct mod_clock *clock) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&priv->rmw_lock, flags); + if (refcount_dec_and_test(&clock->mstop->ref_cnt)) { + val = BUS_MSTOP_VAL(clock->mstop->data) << 16 | + BUS_MSTOP_VAL(clock->mstop->data); + writel(val, priv->base + BUS_MSTOP_OFF(clock->mstop->data)); + } + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) { struct mod_clock *clock = to_mod_clock(hw); @@ -447,10 +487,16 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) enable ? "ON" : "OFF"); value = bitmask << 16; - if (enable) + if (enable) { value |= bitmask; - - writel(value, priv->base + reg); + writel(value, priv->base + reg); + if (clock->mstop) + rzv2h_mod_clock_mstop_enable(priv, clock); + } else { + if (clock->mstop) + rzv2h_mod_clock_mstop_disable(priv, clock); + writel(value, priv->base + reg); + } if (!enable || clock->mon_index < 0) return 0; @@ -500,6 +546,38 @@ static const struct clk_ops rzv2h_mod_clock_ops = { .is_enabled = rzv2h_mod_clock_is_enabled, }; +static struct rzv2h_mstop +*rzv2h_cpg_get_mstop(struct rzv2h_cpg_priv *priv, u32 mstop_data) +{ + struct rzv2h_mstop *mstop; + unsigned int i; + + for (i = 0; i < priv->num_mod_clks; i++) { + struct mod_clock *clk; + struct clk_hw *hw; + + if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT)) + continue; + + hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]); + clk = to_mod_clock(hw); + if (!clk->mstop) + continue; + + if (clk->mstop->data == mstop_data) + return clk->mstop; + } + + mstop = devm_kzalloc(priv->dev, sizeof(*mstop), GFP_KERNEL); + if (!mstop) + return NULL; + + mstop->data = mstop_data; + refcount_set(&mstop->ref_cnt, 0); + + return mstop; +} + static void __init rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, struct rzv2h_cpg_priv *priv) @@ -555,6 +633,14 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, priv->clks[id] = clock->hw.clk; + if (mod->mstop_data != BUS_MSTOP_NO_DATA) { + clock->mstop = rzv2h_cpg_get_mstop(priv, mod->mstop_data); + if (!clock->mstop) { + clk = ERR_PTR(-ENOMEM); + goto fail; + } + } + return; fail: diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 1e5bf1eb65a4..8c94a02d5147 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -35,6 +35,7 @@ struct ddiv { #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CPG_BUS_1_MSTOP (0xd00) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) @@ -46,6 +47,14 @@ struct ddiv { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) +#define CPG_BUS_MSTOP_START (CPG_BUS_1_MSTOP - 4) +#define CPG_BUS_MSTOP(x) (CPG_BUS_MSTOP_START + (x) * 4) + +#define BUS_MSTOP(index, mask) ((CPG_BUS_MSTOP(index) & 0xffff) << 16 | (mask)) +#define BUS_MSTOP_OFF(val) (((val) >> 16) & 0xffff) +#define BUS_MSTOP_VAL(val) ((val) & 0xffff) +#define BUS_MSTOP_NO_DATA GENMASK(31, 0) + /** * Definitions of CPG Core Clocks * @@ -104,6 +113,7 @@ enum clk_types { * struct rzv2h_mod_clk - Module Clocks definitions * * @name: handle between common and hardware-specific interfaces + * @mstop_data: packed data mstop register offset and mask * @parent: id of parent clock * @critical: flag to indicate the clock is critical * @no_pm: flag to indicate PM is not supported @@ -114,6 +124,7 @@ enum clk_types { */ struct rzv2h_mod_clk { const char *name; + u32 mstop_data; u16 parent; bool critical; bool no_pm; @@ -123,9 +134,10 @@ struct rzv2h_mod_clk { u8 mon_bit; }; -#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ +#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ { \ .name = (_name), \ + .mstop_data = (_mstop), \ .parent = (_parent), \ .critical = (_critical), \ .no_pm = (_no_pm), \ @@ -135,14 +147,14 @@ struct rzv2h_mod_clk { .mon_bit = (_monbit), \ } -#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit) +#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) -#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit) +#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit) -#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit) +#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit) /** * struct rzv2h_reset - Reset definitions From patchwork Tue Dec 3 10:49:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892131 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 699611E25F5; Tue, 3 Dec 2024 10:50:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223050; cv=none; b=CeVoUcuJdrHWhS/TUu8nxbGH2i55GI4bh0LRy2umm4GURK45gTOBC10uLle60oYYaGJa4PXvcS9+QnIe8SeuJCIVow51qb8Mm7GAmPqjP2x3k0TJU8DuoYvdknhQCdeWByrzXgewuIXCZfHHvu2jZu4Euz6EkPMhLbNMhnuIJvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223050; c=relaxed/simple; bh=TehA2LY+6jKDZWnvVUQjlP2Gb3TeXPhPIgFJ1iP3ug0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mRaUjArXj3a4GalU5z4S8Xi3E665HRhSqcZora0plKiu8b9I1Csx+bouHxeBlk1FnVIT7tbVhyQl+nIObFFbVLYP6wWINJA5Vj24TYI+iafedSGrYUAT6aWAJRIUlmUkla0VIRRgm7SN6qJJOOHJH4sdLyCgWdFoK8uOvkBD/0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: XPHU79RjTQeSxbVtUjuklw== X-CSE-MsgGUID: WB4eK+ECQ/yyNg7GQb21RQ== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754423" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:47 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 90FF2400753A; Tue, 3 Dec 2024 19:50:37 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 08/13] clk: renesas: r9a09g047: Add CA55 core clocks Date: Tue, 3 Dec 2024 10:49:35 +0000 Message-ID: <20241203105005.103927-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add CA55 core clocks which are derived from PLLCA55. Signed-off-by: Biju Das --- v2: * New patch. --- drivers/clk/renesas/r9a09g047-cpg.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index ab63a7e7e480..d4c119c06d06 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -37,6 +37,14 @@ enum clk_ids { MOD_CLK_BASE, }; +static const struct clk_div_table dtable_1_8[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] = { {0, 2}, {1, 4}, @@ -65,6 +73,14 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, + CDDIV1_DIVCTL0, dtable_1_8), + DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, + CDDIV1_DIVCTL1, dtable_1_8), + DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, + CDDIV1_DIVCTL2, dtable_1_8), + DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, + CDDIV1_DIVCTL3, dtable_1_8), DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), };