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Reviewed-by: Peter Griffin Signed-off-by: André Draszik --- v2: * collect tags --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d13218d0c30f..5080fe2ce776 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1121,6 +1121,7 @@ CONFIG_USB_MASS_STORAGE=m CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_QCOM_PMIC=m CONFIG_TYPEC_UCSI=m From patchwork Tue Dec 3 12:40:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13892339 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C9821E7676 for ; Tue, 3 Dec 2024 12:40:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733229630; cv=none; b=aIIa7qzGvw5/fEPO30+qayBw1+boIK5TLkj/hAv6lKaQgGl2xWs4mmpquJZs1/Z9mZ89eDtreZlcKISI5dF60nIH51tkQ1G7MSkrqdXOQZYBTQtawPdwJjRiggSIZGY2v44ccJezViY8vv/fJgrZw7p6P9XZmLdghJ/SHe8kFw8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733229630; c=relaxed/simple; bh=wuW9dlmQHK3i/Jcfb0eJR/IK57A7oEJMFzUPWXw07Qg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gyw2dvaj5BQ9lSF+N8Mt8Nzz0+JP8aSILPZGBRuRcpwkd4j2NLmf2u/5dfs6AegzClp9vN8BT7mzHofgE18eETExqFQNl7fnl3YaVrMLhMwSXf0AqHairdDexPWFRmLe2lSpWb9oDkyNuWhlVgjmQHIL37Yn0js+FqxW9t9Qz8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=yFaBUlMN; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yFaBUlMN" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-5d0ccd931a3so4404322a12.3 for ; Tue, 03 Dec 2024 04:40:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733229626; x=1733834426; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sFCCGNoly/ihHw+f0V0Z4F6JNgdV9f0RgxXs1v/pmwo=; b=yFaBUlMNnZAAoJ7AVCC17HlfrbiVEJSN4sYdHxbO5CkloLRsoAgm5cD4RrEG5wFuWH LjsNolr7AiFOX01F1+/vyUtKayG4+eYeA9nr78j5xNb94SaNahNWyNi7Hdw5pD1TmTu0 q17eTpcj/Yc2EeK2G5b/QJdsGmjXpND3H3rheMy0YN2bKUHNrbCCRarKmBPr8ltJR0q9 V1za+CemA03lO0wnTvOa/N5awDnvHFhJIdnZshU1GykHbtRLjHT0VtvkLrOYGJaUvY69 e1F8SNtk1tDwrsMW5/hUOpmsuOVlWWOmoZh0PuMQr5ntLvkP2CyMnVp2ZntjD9fSold1 LOTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733229626; x=1733834426; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sFCCGNoly/ihHw+f0V0Z4F6JNgdV9f0RgxXs1v/pmwo=; b=pRly1WqkpPK5PliwazjmWhAAsbfNT19I26ji0miaDcxDLRFcAqr0Uzgj0bCZDsVCDD 9g/0+p4rfOpqG0U24Cjk5pZJEVHoiX5JEpey89EtSWgFhs3OD3lTuRWll81+hbEFQXnJ pVl7dyL95vbhuOfkKkvIHKjY8RciL9WXq7pdPappzBCRLXi40c+Ek3YvjDyNPLchXnEG 5YQ0ghcrsZR7+L29uqthQaki4VY22+IDJCDtSGMOjoXr24tpvT66dxPUhSaAQnZKEUhl 962b7VjL18WzTrH9T2iwnF0EcUjZzsI8KnGU07ZaDJpQaVTSI/yXl7Ics0JmfvWnmVh1 qqsQ== X-Forwarded-Encrypted: i=1; AJvYcCV9PGVyuQ2GpG6VHMsz72/9TGoN3p3e/EBhphTlT+FgZ90sBgfheBwc9VcXRWudJIYB/fu35hi8ptS03y+1m97TCA==@vger.kernel.org X-Gm-Message-State: AOJu0YxBjaqJ9+VBVKawaG+Ovfq8bZqnFIbq5sH0/KCgkWzlr2YZMPlz kIl8CtkMG17om2OxsGY8YKpUmkrfwfQyB+Vq9xakuD7kXxt+waZe9Wh8FIHqXAs= X-Gm-Gg: ASbGncvNYdY7oZ5MFDwZrM7SUnnCDOnIuI8e8dpi299RIt9v8FERTOJlYgifGiyYJec 36hSq6kNXkIyufLfxxtWe0HvdT88Pqe+dNDD1ncco9t8r3I2NUi5K3gINHjyG0KYTlz9RZg0XYY d7/YEXZISm65YLhTSxn3NHZSFAVjeBdkP8Zs8V03i8SUALoAxC+zeKTm36+zUpvIStSgyNaKk4W EURfrV6u4TPWVCRcpE8JlaaVgNR/oNvwMVX2X/hBm8yywYmi7/NI7LiMNamUIUzW9wWz2rYrBRJ NLaeJhFQGTIfxrdzI/fOi7TozoDShbcrsA== X-Google-Smtp-Source: AGHT+IHeM2tS5DyKwmkwrU7i8UC/H8zcEneFmZTgM0O6tCH1VZOWSZmfl7YcO9+J0m0pG/15uh5zHQ== X-Received: by 2002:a17:906:2932:b0:aa5:1ef5:261e with SMTP id a640c23a62f3a-aa5f7d4ed45mr162940566b.17.1733229626589; Tue, 03 Dec 2024 04:40:26 -0800 (PST) Received: from puffmais.c.googlers.com (64.227.90.34.bc.googleusercontent.com. [34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5998e6a4csm616809466b.106.2024.12.03.04.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 04:40:26 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 03 Dec 2024 12:40:25 +0000 Subject: [PATCH v2 2/5] arm64: dts: exynos: gs101: phy region for exynos5-usbdrd is larger Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241203-gs101-phy-lanes-orientation-dts-v2-2-1412783a6b01@linaro.org> References: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> In-Reply-To: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> To: Catalin Marinas , Will Deacon , Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 Turns out there are some additional registers in the phy region, update the DT accordingly. Signed-off-by: André Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 302c5beb224a..18d4e7852a1a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,7 +1267,7 @@ cmu_hsi0: clock-controller@11000000 { usbdrd31_phy: phy@11100000 { compatible = "google,gs101-usb31drd-phy"; - reg = <0x11100000 0x0100>, + reg = <0x11100000 0x0200>, <0x110f0000 0x0800>, <0x110e0000 0x2800>; reg-names = "phy", "pcs", "pma"; From patchwork Tue Dec 3 12:40:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13892341 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C741D1E7653 for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5998e6a4csm616809466b.106.2024.12.03.04.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 04:40:26 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 03 Dec 2024 12:40:26 +0000 Subject: [PATCH v2 3/5] arm64: dts: exynos: gs101: allow stable USB phy Vbus detection Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241203-gs101-phy-lanes-orientation-dts-v2-3-1412783a6b01@linaro.org> References: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> In-Reply-To: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> To: Catalin Marinas , Will Deacon , Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 For the DWC3 core to reliably detect the connected phy's Vbus state, we need to disable phy suspend. Add snps,dis_u2_susphy_quirk snps,dis_u3_susphy_quirk to do that. While at it, also add snps,has-lpm-erratum as this is set downstream which implies that the core was configured with LPM Erratum. We should do the same here. Signed-off-by: André Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin --- v2: - drop snps,dis_rxdet_inp3_quirk and instead use the mentioned properties. The former alone wasn't reliable enough in all situations, e.g. when attached to certain USB hubs. --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 18d4e7852a1a..c5335dd59dfe 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1302,6 +1302,9 @@ usbdrd31_dwc3: usb@0 { interrupts = ; phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; status = "disabled"; }; }; From patchwork Tue Dec 3 12:40:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13892343 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 927F91E8829 for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5998e6a4csm616809466b.106.2024.12.03.04.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 04:40:27 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 03 Dec 2024 12:40:27 +0000 Subject: [PATCH v2 4/5] arm64: dts: exynos: gs101-oriole: enable Maxim max77759 TCPCi Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241203-gs101-phy-lanes-orientation-dts-v2-4-1412783a6b01@linaro.org> References: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> In-Reply-To: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> To: Catalin Marinas , Will Deacon , Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 On Pixel 6 (and Pro), a max77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO) * charger * fuel gauge * TCPCi While in the same package, TCPCi and Fuel Gauge have separate I2C addresses, interrupt lines and interrupt status registers and can be treated independently. The TCPCi is required to detect and handle connector orientation in Pixel's USB PHY driver, and to configure the USB controller's role (host vs device). This change adds the TCPCi part as it can be independent and doesn't need a top-level MFD. Signed-off-by: André Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin --- v2: * compatible has changed to maxim,max77759-tcpci * clarify that GPIO is actually part of 'top' in commit message, not separate --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 99 ++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 387fb779bd29..a5cbf1e10c7b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -10,6 +10,7 @@ #include #include +#include #include "gs101-pinctrl.h" #include "gs101.dtsi" @@ -90,6 +91,84 @@ eeprom: eeprom@50 { &hsi2c_12 { status = "okay"; /* TODO: add the devices once drivers exist */ + + usb-typec@25 { + compatible = "maxim,max77759-tcpci", "maxim,max33359"; + reg = <0x25>; + interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&typec_int>; + pinctrl-names = "default"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + self-powered; + try-power-role = "sink"; + op-sink-microwatt = <2600000>; + new-source-frs-typec-current = ; + slow-charger-loop; + /* + * max77759 operating in reverse boost mode (0xA) can + * source up to 1.5A while extboost can only do ~1A. + * Since extboost is the primary path, advertise 900mA. + */ + source-pdos = ; + sink-pdos = ; + sink-vdos = ; + sink-vdos-v1 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdrd31_phy_orien_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&usbdrd31_dwc3_role_switch>; + }; + }; + }; + }; + }; }; &pinctrl_far_alive { @@ -106,6 +185,13 @@ key_volup: key-volup-pins { samsung,pin-pud = ; samsung,pin-drv = ; }; + + typec_int: typec-int-pins { + samsung,pins = "gpa8-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_gpio_alive { @@ -142,9 +228,16 @@ &usbdrd31_dwc3 { role-switch-default-mode = "peripheral"; maximum-speed = "super-speed-plus"; status = "okay"; + + port { + usbdrd31_dwc3_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; }; &usbdrd31_phy { + orientation-switch; /* TODO: Update these once PMIC is implemented */ pll-supply = <®_placeholder>; dvdd-usb20-supply = <®_placeholder>; @@ -153,6 +246,12 @@ &usbdrd31_phy { vdda-usbdp-supply = <®_placeholder>; vddh-usbdp-supply = <®_placeholder>; status = "okay"; + + port { + usbdrd31_phy_orien_switch: endpoint { + remote-endpoint = <&usbc0_orien_sw>; + }; + }; }; &usi_uart { From patchwork Tue Dec 3 12:40:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 13892344 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D96511E8836 for ; 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[34.90.227.64]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5998e6a4csm616809466b.106.2024.12.03.04.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 04:40:27 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 03 Dec 2024 12:40:28 +0000 Subject: [PATCH v2 5/5] arm64: dts: exynos: gs101-oriole: add pd-disable and typec-power-opmode Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241203-gs101-phy-lanes-orientation-dts-v2-5-1412783a6b01@linaro.org> References: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> In-Reply-To: <20241203-gs101-phy-lanes-orientation-dts-v2-0-1412783a6b01@linaro.org> To: Catalin Marinas , Will Deacon , Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Sam Protsenko , Will McVicker , Roy Luo , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 When the serial console is enabled, we need to disable power delivery since serial uses the SBU1/2 pins and appears to confuse the TCPCI, resulting in endless interrupts. For now, change the DT such that the serial console continues working. Note1: We can not have both typec-power-opmode and new-source-frs-typec-current active at the same time, as otherwise DT binding checks complain. Note2: When using a downstream DT, the Pixel boot-loader will modify the DT accordingly before boot, but for this upstream DT it doesn't know where to find the TCPCI node. The intention is for this commit to be reverted once an updated Pixel boot-loader becomes available. Signed-off-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index a5cbf1e10c7b..e58881c61d53 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -107,7 +107,6 @@ connector { self-powered; try-power-role = "sink"; op-sink-microwatt = <2600000>; - new-source-frs-typec-current = ; slow-charger-loop; /* * max77759 operating in reverse boost mode (0xA) can @@ -146,6 +145,12 @@ VDO_DFP(DFP_VDO_VER1_1, 0, 0, 0x18d1) VDO_CERT(0x0) VDO_PRODUCT(0x4ee1, 0x0)>; + /* + * Until bootloader is updated to set those two when + * console is enabled, we disable PD here. + */ + pd-disable; + typec-power-opmode = "default"; ports { #address-cells = <1>;