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2024 13:41:48 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 01/14] clk: thead: Refactor TH1520 clock driver to share common code Date: Tue, 3 Dec 2024 14:41:24 +0100 Message-Id: <20241203134137.2114847-2-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: 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CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134150eucas1p24ba8d2fbf2af5b8f9abe503b4334127d References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054153_796871_2416557F X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The T-Head TH1520 SoC includes various clocks for different subsystems like Application Processor (AP) and Video Output (VO) [1]. Currently, the clock driver only implements AP clocks. Since the programming interface for these clocks is identical across subsystems, refactor the code to move common functions into clk-th1520.c. This prepares the driver to support VO clocks by reducing code duplication and improving maintainability. No functional changes are introduced with this refactoring. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 2 +- drivers/clk/thead/Makefile | 2 +- drivers/clk/thead/clk-th1520-ap.c | 301 +----------------------------- drivers/clk/thead/clk-th1520.c | 188 +++++++++++++++++++ drivers/clk/thead/clk-th1520.h | 134 +++++++++++++ 5 files changed, 326 insertions(+), 301 deletions(-) create mode 100644 drivers/clk/thead/clk-th1520.c create mode 100644 drivers/clk/thead/clk-th1520.h diff --git a/MAINTAINERS b/MAINTAINERS index 1e930c7a58b1..7c85abf1dd1e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20188,7 +20188,7 @@ F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml F: arch/riscv/boot/dts/thead/ -F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/clk/thead/ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c diff --git a/drivers/clk/thead/Makefile b/drivers/clk/thead/Makefile index 7ee0bec1f251..d7cf88390b69 100644 --- a/drivers/clk/thead/Makefile +++ b/drivers/clk/thead/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_CLK_THEAD_TH1520_AP) += clk-th1520-ap.o +obj-$(CONFIG_CLK_THEAD_TH1520_AP) += clk-th1520.o clk-th1520-ap.o diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index 17e32ae08720..a6015805b859 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -5,297 +5,9 @@ * Authors: Yangtao Li */ -#include -#include -#include -#include -#include -#include -#include - -#define TH1520_PLL_POSTDIV2 GENMASK(26, 24) -#define TH1520_PLL_POSTDIV1 GENMASK(22, 20) -#define TH1520_PLL_FBDIV GENMASK(19, 8) -#define TH1520_PLL_REFDIV GENMASK(5, 0) -#define TH1520_PLL_BYPASS BIT(30) -#define TH1520_PLL_DSMPD BIT(24) -#define TH1520_PLL_FRAC GENMASK(23, 0) -#define TH1520_PLL_FRAC_BITS 24 - -struct ccu_internal { - u8 shift; - u8 width; -}; - -struct ccu_div_internal { - u8 shift; - u8 width; - u32 flags; -}; - -struct ccu_common { - int clkid; - struct regmap *map; - u16 cfg0; - u16 cfg1; - struct clk_hw hw; -}; - -struct ccu_mux { - struct ccu_internal mux; - struct ccu_common common; -}; - -struct ccu_gate { - u32 enable; - struct ccu_common common; -}; - -struct ccu_div { - u32 enable; - struct ccu_div_internal div; - struct ccu_internal mux; - struct ccu_common common; -}; - -struct ccu_pll { - struct ccu_common common; -}; - -#define TH_CCU_ARG(_shift, _width) \ - { \ - .shift = _shift, \ - .width = _width, \ - } - -#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ - { \ - .shift = _shift, \ - .width = _width, \ - .flags = _flags, \ - } - -#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ - struct ccu_gate _struct = { \ - .enable = _gate, \ - .common = { \ - .clkid = _clkid, \ - .cfg0 = _reg, \ - .hw.init = CLK_HW_INIT_PARENTS_DATA( \ - _name, \ - _parent, \ - &clk_gate_ops, \ - _flags), \ - } \ - } - -static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) -{ - return container_of(hw, struct ccu_common, hw); -} - -static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) -{ - struct ccu_common *common = hw_to_ccu_common(hw); - - return container_of(common, struct ccu_mux, common); -} - -static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) -{ - struct ccu_common *common = hw_to_ccu_common(hw); +#include "clk-th1520.h" - return container_of(common, struct ccu_pll, common); -} - -static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) -{ - struct ccu_common *common = hw_to_ccu_common(hw); - - return container_of(common, struct ccu_div, common); -} - -static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) -{ - struct ccu_common *common = hw_to_ccu_common(hw); - - return container_of(common, struct ccu_gate, common); -} - -static u8 ccu_get_parent_helper(struct ccu_common *common, - struct ccu_internal *mux) -{ - unsigned int val; - u8 parent; - - regmap_read(common->map, common->cfg0, &val); - parent = val >> mux->shift; - parent &= GENMASK(mux->width - 1, 0); - - return parent; -} - -static int ccu_set_parent_helper(struct ccu_common *common, - struct ccu_internal *mux, - u8 index) -{ - return regmap_update_bits(common->map, common->cfg0, - GENMASK(mux->width - 1, 0) << mux->shift, - index << mux->shift); -} - -static void ccu_disable_helper(struct ccu_common *common, u32 gate) -{ - if (!gate) - return; - regmap_update_bits(common->map, common->cfg0, - gate, ~gate); -} - -static int ccu_enable_helper(struct ccu_common *common, u32 gate) -{ - unsigned int val; - int ret; - - if (!gate) - return 0; - - ret = regmap_update_bits(common->map, common->cfg0, gate, gate); - regmap_read(common->map, common->cfg0, &val); - return ret; -} - -static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate) -{ - unsigned int val; - - if (!gate) - return true; - - regmap_read(common->map, common->cfg0, &val); - return val & gate; -} - -static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct ccu_div *cd = hw_to_ccu_div(hw); - unsigned long rate; - unsigned int val; - - regmap_read(cd->common.map, cd->common.cfg0, &val); - val = val >> cd->div.shift; - val &= GENMASK(cd->div.width - 1, 0); - rate = divider_recalc_rate(hw, parent_rate, val, NULL, - cd->div.flags, cd->div.width); - - return rate; -} - -static u8 ccu_div_get_parent(struct clk_hw *hw) -{ - struct ccu_div *cd = hw_to_ccu_div(hw); - - return ccu_get_parent_helper(&cd->common, &cd->mux); -} - -static int ccu_div_set_parent(struct clk_hw *hw, u8 index) -{ - struct ccu_div *cd = hw_to_ccu_div(hw); - - return ccu_set_parent_helper(&cd->common, &cd->mux, index); -} - -static void ccu_div_disable(struct clk_hw *hw) -{ - struct ccu_div *cd = hw_to_ccu_div(hw); - - ccu_disable_helper(&cd->common, cd->enable); -} - -static int ccu_div_enable(struct clk_hw *hw) -{ - struct ccu_div *cd = hw_to_ccu_div(hw); - - return ccu_enable_helper(&cd->common, cd->enable); -} - -static int ccu_div_is_enabled(struct clk_hw *hw) -{ - struct ccu_div *cd = hw_to_ccu_div(hw); - - return ccu_is_enabled_helper(&cd->common, cd->enable); -} - -static const struct clk_ops ccu_div_ops = { - .disable = ccu_div_disable, - .enable = ccu_div_enable, - .is_enabled = ccu_div_is_enabled, - .get_parent = ccu_div_get_parent, - .set_parent = ccu_div_set_parent, - .recalc_rate = ccu_div_recalc_rate, - .determine_rate = clk_hw_determine_rate_no_reparent, -}; - -static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct ccu_pll *pll = hw_to_ccu_pll(hw); - unsigned long div, mul, frac; - unsigned int cfg0, cfg1; - u64 rate = parent_rate; - - regmap_read(pll->common.map, pll->common.cfg0, &cfg0); - regmap_read(pll->common.map, pll->common.cfg1, &cfg1); - - mul = FIELD_GET(TH1520_PLL_FBDIV, cfg0); - div = FIELD_GET(TH1520_PLL_REFDIV, cfg0); - if (!(cfg1 & TH1520_PLL_DSMPD)) { - mul <<= TH1520_PLL_FRAC_BITS; - frac = FIELD_GET(TH1520_PLL_FRAC, cfg1); - mul += frac; - div <<= TH1520_PLL_FRAC_BITS; - } - rate = parent_rate * mul; - rate = rate / div; - return rate; -} - -static unsigned long th1520_pll_postdiv_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct ccu_pll *pll = hw_to_ccu_pll(hw); - unsigned long div, rate = parent_rate; - unsigned int cfg0, cfg1; - - regmap_read(pll->common.map, pll->common.cfg0, &cfg0); - regmap_read(pll->common.map, pll->common.cfg1, &cfg1); - - if (cfg1 & TH1520_PLL_BYPASS) - return rate; - - div = FIELD_GET(TH1520_PLL_POSTDIV1, cfg0) * - FIELD_GET(TH1520_PLL_POSTDIV2, cfg0); - - rate = rate / div; - - return rate; -} - -static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - unsigned long rate = parent_rate; - - rate = th1520_pll_vco_recalc_rate(hw, rate); - rate = th1520_pll_postdiv_recalc_rate(hw, rate); - - return rate; -} - -static const struct clk_ops clk_pll_ops = { - .recalc_rate = ccu_pll_recalc_rate, -}; +#define NR_CLKS (CLK_UART_SCLK + 1) static const struct clk_parent_data osc_24m_clk[] = { { .index = 0 } @@ -956,15 +668,6 @@ static struct ccu_common *th1520_gate_clks[] = { &sram3_clk.common, }; -#define NR_CLKS (CLK_UART_SCLK + 1) - -static const struct regmap_config th1520_clk_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .fast_io = true, -}; - static int th1520_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; diff --git a/drivers/clk/thead/clk-th1520.c b/drivers/clk/thead/clk-th1520.c new file mode 100644 index 000000000000..e2bfe56de9af --- /dev/null +++ b/drivers/clk/thead/clk-th1520.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#include "clk-th1520.h" + +static u8 ccu_get_parent_helper(struct ccu_common *common, + struct ccu_internal *mux) +{ + unsigned int val; + u8 parent; + + regmap_read(common->map, common->cfg0, &val); + parent = val >> mux->shift; + parent &= GENMASK(mux->width - 1, 0); + + return parent; +} + +static int ccu_set_parent_helper(struct ccu_common *common, + struct ccu_internal *mux, u8 index) +{ + return regmap_update_bits(common->map, common->cfg0, + GENMASK(mux->width - 1, 0) << mux->shift, + index << mux->shift); +} + +static void ccu_disable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return; + regmap_update_bits(common->map, common->cfg0, gate, ~gate); +} + +static int ccu_enable_helper(struct ccu_common *common, u32 gate) +{ + unsigned int val; + int ret; + + if (!gate) + return 0; + + ret = regmap_update_bits(common->map, common->cfg0, gate, gate); + regmap_read(common->map, common->cfg0, &val); + return ret; +} + +static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate) +{ + unsigned int val; + + if (!gate) + return true; + + regmap_read(common->map, common->cfg0, &val); + return val & gate; +} + +static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_div *cd = hw_to_ccu_div(hw); + unsigned long rate; + unsigned int val; + + regmap_read(cd->common.map, cd->common.cfg0, &val); + val = val >> cd->div.shift; + val &= GENMASK(cd->div.width - 1, 0); + rate = divider_recalc_rate(hw, parent_rate, val, NULL, cd->div.flags, + cd->div.width); + + return rate; +} + +static u8 ccu_div_get_parent(struct clk_hw *hw) +{ + struct ccu_div *cd = hw_to_ccu_div(hw); + + return ccu_get_parent_helper(&cd->common, &cd->mux); +} + +static int ccu_div_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_div *cd = hw_to_ccu_div(hw); + + return ccu_set_parent_helper(&cd->common, &cd->mux, index); +} + +static void ccu_div_disable(struct clk_hw *hw) +{ + struct ccu_div *cd = hw_to_ccu_div(hw); + + ccu_disable_helper(&cd->common, cd->enable); +} + +static int ccu_div_enable(struct clk_hw *hw) +{ + struct ccu_div *cd = hw_to_ccu_div(hw); + + return ccu_enable_helper(&cd->common, cd->enable); +} + +static int ccu_div_is_enabled(struct clk_hw *hw) +{ + struct ccu_div *cd = hw_to_ccu_div(hw); + + return ccu_is_enabled_helper(&cd->common, cd->enable); +} + +const struct clk_ops ccu_div_ops = { + .disable = ccu_div_disable, + .enable = ccu_div_enable, + .is_enabled = ccu_div_is_enabled, + .get_parent = ccu_div_get_parent, + .set_parent = ccu_div_set_parent, + .recalc_rate = ccu_div_recalc_rate, + .determine_rate = clk_hw_determine_rate_no_reparent, +}; + +static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_pll *pll = hw_to_ccu_pll(hw); + unsigned long div, mul, frac; + unsigned int cfg0, cfg1; + u64 rate = parent_rate; + + regmap_read(pll->common.map, pll->common.cfg0, &cfg0); + regmap_read(pll->common.map, pll->common.cfg1, &cfg1); + + mul = FIELD_GET(TH1520_PLL_FBDIV, cfg0); + div = FIELD_GET(TH1520_PLL_REFDIV, cfg0); + if (!(cfg1 & TH1520_PLL_DSMPD)) { + mul <<= TH1520_PLL_FRAC_BITS; + frac = FIELD_GET(TH1520_PLL_FRAC, cfg1); + mul += frac; + div <<= TH1520_PLL_FRAC_BITS; + } + rate = parent_rate * mul; + rate = rate / div; + return rate; +} + +static unsigned long th1520_pll_postdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_pll *pll = hw_to_ccu_pll(hw); + unsigned long div, rate = parent_rate; + unsigned int cfg0, cfg1; + + regmap_read(pll->common.map, pll->common.cfg0, &cfg0); + regmap_read(pll->common.map, pll->common.cfg1, &cfg1); + + if (cfg1 & TH1520_PLL_BYPASS) + return rate; + + div = FIELD_GET(TH1520_PLL_POSTDIV1, cfg0) * + FIELD_GET(TH1520_PLL_POSTDIV2, cfg0); + + rate = rate / div; + + return rate; +} + +static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long rate = parent_rate; + + rate = th1520_pll_vco_recalc_rate(hw, rate); + rate = th1520_pll_postdiv_recalc_rate(hw, rate); + + return rate; +} + +const struct clk_ops clk_pll_ops = { + .recalc_rate = ccu_pll_recalc_rate, +}; + +const struct regmap_config th1520_clk_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; diff --git a/drivers/clk/thead/clk-th1520.h b/drivers/clk/thead/clk-th1520.h new file mode 100644 index 000000000000..285d41e65008 --- /dev/null +++ b/drivers/clk/thead/clk-th1520.h @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + * + * clk-th1520.h - Common definitions for T-HEAD TH1520 Clock Drivers + */ + +#ifndef CLK_TH1520_H +#define CLK_TH1520_H + +#include +#include +#include +#include +#include +#include +#include + +#define TH1520_PLL_POSTDIV2 GENMASK(26, 24) +#define TH1520_PLL_POSTDIV1 GENMASK(22, 20) +#define TH1520_PLL_FBDIV GENMASK(19, 8) +#define TH1520_PLL_REFDIV GENMASK(5, 0) +#define TH1520_PLL_BYPASS BIT(30) +#define TH1520_PLL_DSMPD BIT(24) +#define TH1520_PLL_FRAC GENMASK(23, 0) +#define TH1520_PLL_FRAC_BITS 24 + +struct ccu_internal { + u8 shift; + u8 width; +}; + +struct ccu_div_internal { + u8 shift; + u8 width; + u32 flags; +}; + +struct ccu_common { + int clkid; + struct regmap *map; + u16 cfg0; + u16 cfg1; + struct clk_hw hw; +}; + +struct ccu_mux { + struct ccu_internal mux; + struct ccu_common common; +}; + +struct ccu_gate { + u32 enable; + struct ccu_common common; +}; + +struct ccu_div { + u32 enable; + struct ccu_div_internal div; + struct ccu_internal mux; + struct ccu_common common; +}; + +struct ccu_pll { + struct ccu_common common; +}; + +#define TH_CCU_ARG(_shift, _width) \ + { \ + .shift = _shift, \ + .width = _width, \ + } + +#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ + { \ + .shift = _shift, \ + .width = _width, \ + .flags = _flags, \ + } + +#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ + struct ccu_gate _struct = { \ + .enable = _gate, \ + .common = { \ + .clkid = _clkid, \ + .cfg0 = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parent, \ + &clk_gate_ops, \ + _flags), \ + } \ + } + +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) +{ + return container_of(hw, struct ccu_common, hw); +} + +static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mux, common); +} + +static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_pll, common); +} + +static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_div, common); +} + +static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) +{ + struct ccu_common *common = hw_to_ccu_common(hw); + + return container_of(common, struct ccu_gate, common); +} + +extern const struct clk_ops ccu_div_ops; +extern const struct clk_ops clk_pll_ops; +extern const struct regmap_config th1520_clk_regmap_config; + +#endif /* CLK_TH1520_H */ From patchwork Tue Dec 3 13:41:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07D7CE64A9E for ; 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Tue, 3 Dec 2024 13:41:49 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 02/14] dt-bindings: clock: thead,th1520: Rename header file Date: Tue, 3 Dec 2024 14:41:25 +0100 Message-Id: <20241203134137.2114847-3-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0xTZxzNd+/tvbfNCpfSxE9gYe2ibi7AaAx8RAMuUXITlgBGAllGtJPL IzzTwthwDwwPgZUNF4laqwVEy4odGY9aWDsGIy1S7ZxsUDJB4iSuyCA8xeFg1Fs3/zu/8zvn O7+TfDQu6SSD6JyCYk5VoMyTkyLCbH/qCtOLErPePmuLQMPjLRjq2dBS6LrNhSH9kEuApu52 Y+jX1QUSfTtzh0J/2k4RaKztEoUq7B0k8minSLSomRKg0T4diZbrhwAyL1eSyDQ0SaGOVT2G mhd7CNRq6QOouvaaAP0ychh5RjU4qtb6oy2rhUKbY98R6OJ8P4W6584IkMOUiir7zxIHX2UX 3FUUO+fxEOxPNSsUa1trIthe7STFanpvAbbTWEuy98asJHv5ZjJ7/wsHxna1fs5WmuwYu/DD byT7ZbcRsHcrxim2y3kyKeA90YEMLi/nQ04VEXtclH2mNa3o9msfXa0cFpQDS3AdENKQ2Qf/ abxD1AERLWHaAFw1DWD8sAJgo75PwA/LAI65f6deWDb+mKb4hQFA3dQVn2UOwJahHwmvimQU cNqgf26XMo9x6F6dIL0DzjwC0PxQR3pVgcxRuLZZjnkxweyCW2Yt8GIxEwdPb93H+LxQ2D9w G/diIXMQPm6sE/CaAHjzwsPnafi2pqLnIu4NgIxJBK/XPCF48yG4Puf2PRQIZx3dvhIhcKtX 7+ML4XTPEs7jT2CvxuHD++E919/bh9LbAW/Cjr4Inn4H2hdchJeGjB90/xXAn+AHvzafw3la DGuqJbx6N2zU1P8X6moz+0JZOKubAA1Apn2pjPalMtr/c5sAbgQ7uBJ1fhanVhRwpeFqZb66 pCAr/ERhfifY/tbOTceKBRhmF8MHAUaDQQBpXC4VGzoSsiTiDOXHZZyq8JiqJI9TD4JgmpDv EO/KCOUkTJaymMvluCJO9WKL0cKgcqxkOL5UJrjS6eSM7a+HNPhrEurl+9azkw4rdLGO3qAL VcKGRyRHj0h/thV3xc8kTTmsyZ+l2WeMT/VLwvMt8ht9pW+UXFWe3xMcOW6ZDDiSsjej6oGs O8wQGJ1Q5Oz35AkTYw+1t2QWZF+yeKy6qvdzFpdyrc4PFNkPbqXv/j6yOXq+9S2QJttIefdJ 2WJdWkdqCj3YrrgRfU22VhkzYo+q5Y7teUUjS3XGrZ9sFobuPzW8FJWYLHl2ThHjCTsgXThB jotDJX7T3/SMckMTNjZdMJ4R0rgVFX48s2msTFpU9akprul0ZkxIQvxX/kHzO9OP7MytCOKO 5gueDcy50+WEOlsZuRdXqZX/ApXKKZRFBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsVy+t/xe7rzufzTDU4tFbQ4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZUxcElFwVqFiacsJ1gbGHdJdjJwcEgImEr8fP2DvYuTiEBJYyigx5fJNNoiEjMS1 7pcsELawxJ9rXWwQRa8YJZq73jKBJNgEjCQeLJ/PCpIQEehkkXi7eS0jiMMs8JZR4vrMjWDt wgJBElum/WAHsVkEVCX+b5vFCGLzCthLtP+/zwSxQl5i/8GzzCA2p4CDxOupXawgthBQzY6/ h1kh6gUlTs58AjaTGai+eets5gmMArOQpGYhSS1gZFrFKJJaWpybnltsqFecmFtcmpeul5yf u4kRmFa2Hfu5eQfjvFcf9Q4xMnEwHmKU4GBWEuFdvt47XYg3JbGyKrUoP76oNCe1+BCjKdDd E5mlRJPzgYktryTe0MzA1NDEzNLA1NLMWEmc1+3y+TQhgfTEktTs1NSC1CKYPiYOTqkGJp/J 4g1S7XLrdypwFZ0sOJDXsWntDev/ziIJbx1n/1r8luGhXsmHhZ2rP+SemXpw+2VHh8bJyZsX aR8SsZyilyAaJ/3a4cZNDlGHhXkTvrncFDUN/6K+xv/inQm7y9f3MC4W3mTwsO/4k5lNTeWq RU2b+467q120fiFmc95d8Y1tZ7tit/LhefG/bdZzaT/peaoppsHAcq1/usrFF1EW9ze/z0rS X3vq0Pyfb7UchFNdbv3dFj/jWtCFlRf/HpbLLr1vOuHCgtm/DXI8H0sEd1Seznx22uu9zFrn 6canjeyiV5bOnFj4V3byr76JtwSSVRecnZS4INXiGe/6DV8f/v7uJ8D7h+fSx0NPpWPWzHqn xFKckWioxVxUnAgAGT2kN7QDAAA= X-CMS-MailID: 20241203134151eucas1p18edf7fb37cd8f30983a559d7481f560b X-Msg-Generator: CA X-RootMTR: 20241203134151eucas1p18edf7fb37cd8f30983a559d7481f560b X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134151eucas1p18edf7fb37cd8f30983a559d7481f560b References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054153_990934_EB2D38E6 X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As support for clocks from new subsystems is being added to the T-Head TH1520 SoC, the header file name should reflect this broader scope. The existing header file 'thead,th1520-clk-ap.h' includes the '-ap' suffix, indicating it's specific to the Application Processor (AP) subsystem. Rename the header file to 'thead,th1520-clk.h' to generalize it for all subsystems. Update all references to this header file accordingly. Signed-off-by: Michal Wilczynski --- .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 4 ++-- .../devicetree/bindings/mailbox/thead,th1520-mbox.yaml | 2 +- MAINTAINERS | 2 +- arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- drivers/clk/thead/clk-th1520.h | 2 +- .../clock/{thead,th1520-clk-ap.h => thead,th1520-clk.h} | 0 6 files changed, 6 insertions(+), 6 deletions(-) rename include/dt-bindings/clock/{thead,th1520-clk-ap.h => thead,th1520-clk.h} (100%) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 0129bd0ba4b3..4a0806af2bf9 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -32,7 +32,7 @@ properties: "#clock-cells": const: 1 description: - See for valid indices. + See for valid indices. required: - compatible @@ -44,7 +44,7 @@ additionalProperties: false examples: - | - #include + #include clock-controller@ef010000 { compatible = "thead,th1520-clk-ap"; reg = <0xef010000 0x1000>; diff --git a/Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml b/Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml index 0971fb97896e..0b58b8d0d351 100644 --- a/Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml @@ -68,7 +68,7 @@ additionalProperties: false examples: - | - #include + #include soc { #address-cells = <2>; #size-cells = <2>; diff --git a/MAINTAINERS b/MAINTAINERS index 7c85abf1dd1e..bd4bbf07d588 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20192,7 +20192,7 @@ F: drivers/clk/thead/ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c -F: include/dt-bindings/clock/thead,th1520-clk-ap.h +F: include/dt-bindings/clock/thead,th1520-clk.h RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index acfe030e803a..dc2d554b4a71 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -5,7 +5,7 @@ */ #include -#include +#include / { compatible = "thead,th1520"; diff --git a/drivers/clk/thead/clk-th1520.h b/drivers/clk/thead/clk-th1520.h index 285d41e65008..5d30f55e88a1 100644 --- a/drivers/clk/thead/clk-th1520.h +++ b/drivers/clk/thead/clk-th1520.h @@ -10,7 +10,7 @@ #ifndef CLK_TH1520_H #define CLK_TH1520_H -#include +#include #include #include #include diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk.h similarity index 100% rename from include/dt-bindings/clock/thead,th1520-clk-ap.h rename to include/dt-bindings/clock/thead,th1520-clk.h From patchwork Tue Dec 3 13:41:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FA46E64AA4 for ; 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Tue, 3 Dec 2024 13:41:51 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 03/14] clk: thead: Enable clock gates with regmaps Date: Tue, 3 Dec 2024 14:41:26 +0100 Message-Id: <20241203134137.2114847-4-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SfUxbVRz19r2+9+goe5QBN/vItHGLm5GBQb3TukFEfcwlMBOjMyyzgWcB +djasaFiYHwVunbZwII8mB0LgQ7GiAMaYDAGEkqtNNIhoJYPl46vMZGxjs4hCn1M99/5nd85 95xfcilM0khsphJSTrDKFHmSlBDhpt5HtpcqRVGK4IUKCvUNXxKg5sccia502ATI0GMTojF7 kwANuuYJdPXOTySa7jiNoyHjBRLl9DYQaIYbI9CCdkyIbrVVEGhR1wOQaTGXQPU9oyRqcBkE qHKhGUdVLW0A5RdWC9HAD2+jmVtaDOVzG9E/7S0kWhn6Dkflf3SSqGnuvBCZ6z9EuZ1f42Hb mPmRPJKZm5nBme8LHpBMx8OLONPKjZKMtvVHwFyrLSQYx1A7wXxrOcSMnzELmMaqTCa3vlfA zN/4mWDONtUCxp4zTDKN1i+jfT8WyeLYpISTrHLPvk9E8ct1Y+Sxe/7pRc6zeBb41VcDvChI h8Kp8/OkBogoCW0EsH7iDsEPDwB0j3M4PywC2FHiAE8s5Wo9xi9qALRWmwE/zAG45C7G1lQE /TKcqDEI1xab6LsYHHH94nkYo6cANDkriDWVHx0Jzbc78TWM0ztg9k2Dxy2m98PrY2oBn7cd dnb1e3gvOgze1WuEvMYXWsqcHi+2qslpLvd0gvRlEfx7anLdHAFHr+sJHvvBWXMTyeOt0Fqs xXmcCiea72M8zoCtWvM6fgM6bH+teqnVgF2woW0PT4fD5RWdh4a0Dxy558tX8IFFplKMp8Ww IF/Cq3dCvVb3X6jNaFovxkCjaQWcA89xTx3DPXUM93/uRYDVgkA2TZWsYFUhKeypIJU8WZWW ogiKTU2+Blb/tXXFfL8FXJhdCOoGAgp0A0hh0k3imob3FBJxnPzzL1hl6lFlWhKr6gZbKFwa KN4Rt52V0Ar5CfYzlj3GKp9sBZTX5ixBesCGug3905FH9C57b3/sufqlYPt+H82WjzTp3MBl Q5gutrw048/qaCedod6aFyTJVhmeeStzr4WKnq5YlG2McIZO2s90Hbzttxzjiq/MrDMe97aV uaNlXUfKuq68EuM+8Glf1tW5x3vVrpNGf0thuk7WGnHwcEHA4abEosTTD2XZR8eHh7x/35mQ ePwbqrqmLJJbuETcbGgf9I8wv4qV1Bz6rff5d194c9SRosiS5nUGB/o79O+HlHi7l2ILP/Dh 1AeyvSfzrX2hrHhK/FXmLHWjCs2p9oVXWyrxXe+YTrW8GFW72/bsYPu2kWJTTH54qvO10vFH lihn/ECA3+uhfUYproqXh+zGlCr5vypymldGBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEKsWRmVeSWpSXmKPExsVy+t/xe7oLuPzTDY4cUbE4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZfxZfY+94K1oxaQnfSwNjLcEuxg5OSQETCRmt09l7mLk4hASWMoosXr3JXaIhIzE te6XLBC2sMSfa11sEEWvGCU+7uxnBkmwCRhJPFg+nxUkISLQySLxdvNaRhCHWeAto8T1mRvB 2oUFPCWOP9oPZrMIqEo0HZgP1s0rYC+x+147E8QKeYn9B8+CxTkFHCReT+1iBbGFgGp2/D3M ClEvKHFy5hOwOcxA9c1bZzNPYBSYhSQ1C0lqASPTKkaR1NLi3PTcYiO94sTc4tK8dL3k/NxN jMDEsu3Yzy07GFe++qh3iJGJg/EQowQHs5II7/L13ulCvCmJlVWpRfnxRaU5qcWHGE2B7p7I LCWanA9MbXkl8YZmBqaGJmaWBqaWZsZK4rxsV86nCQmkJ5akZqemFqQWwfQxcXBKNTDVhLqy PnWujjyx5UH0qmP3/z9clHzo2d37klkPy82alIWPK+85Mp9JfY1+zZScSyxm8r5MR2VY5gmX zuyvX/5T5I+Zs9qrDY/cM7W8DvB5WJ3+mfRV6dSiV6Iul48V8D34JmZ48nzczBexGx74Ti/4 vmn1ZEbm30cvb1/DUTrx1Repexml13izD06cPikuK8/+Xlql8UbJlQxrjBnTAk5snrXozjXf qKeRFtcbOfSuKjlpz1f+wGkX18sWL77043P+TNMU+UlNDxZPCHKI3CPBKrDLqPL27CML+FIU jITW/KpJN+tZXccssOG5akkFs1hJUtmfRvctay3zvH/EbpgtqpsRkcRT/tvmY1xLbIkSS3FG oqEWc1FxIgBpGSjwtQMAAA== X-CMS-MailID: 20241203134152eucas1p1ed480afaf4d7de3a4a706477e709b6fd X-Msg-Generator: CA X-RootMTR: 20241203134152eucas1p1ed480afaf4d7de3a4a706477e709b6fd X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134152eucas1p1ed480afaf4d7de3a4a706477e709b6fd References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054155_126352_3F141C7C X-CRM114-Status: GOOD ( 16.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The current implementation of the CCU_GATE macro assumes direct access to memory-mapped registers, which isn't suitable when using regmaps for register access. In the TH1520 SoC, the address space for the VO (Video Output) subsystem clocks is shared with other control registers, such as those used for resetting the GPU. To prevent conflicts and ensure synchronized access, it's important to access these registers via a regmap. This patch updates the CCU_GATE macro to support regmap-based access by reusing the clk_ops from the divider clocks (ccu_div_ops). This change allows the clock gates to be controlled through regmap, enabling proper synchronization when multiple components interact with the shared address space. Signed-off-by: Michal Wilczynski --- drivers/clk/thead/clk-th1520.c | 10 ++++++++-- drivers/clk/thead/clk-th1520.h | 15 +++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/clk/thead/clk-th1520.c b/drivers/clk/thead/clk-th1520.c index e2bfe56de9af..3ada8b98bd8e 100644 --- a/drivers/clk/thead/clk-th1520.c +++ b/drivers/clk/thead/clk-th1520.c @@ -120,8 +120,14 @@ const struct clk_ops ccu_div_ops = { .determine_rate = clk_hw_determine_rate_no_reparent, }; -static unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +const struct clk_ops ccu_gate_ops = { + .disable = ccu_div_disable, + .enable = ccu_div_enable, + .is_enabled = ccu_div_is_enabled, +}; + +unsigned long th1520_pll_vco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { struct ccu_pll *pll = hw_to_ccu_pll(hw); unsigned long div, mul, frac; diff --git a/drivers/clk/thead/clk-th1520.h b/drivers/clk/thead/clk-th1520.h index 5d30f55e88a1..532afbbfea01 100644 --- a/drivers/clk/thead/clk-th1520.h +++ b/drivers/clk/thead/clk-th1520.h @@ -94,6 +94,20 @@ struct ccu_pll { } \ } +#define CCU_GATE_REGMAP(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ + struct ccu_gate _struct = { \ + .enable = _gate, \ + .common = { \ + .clkid = _clkid, \ + .cfg0 = _reg, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parent, \ + &ccu_gate_ops, \ + _flags), \ + } \ + } + static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) { return container_of(hw, struct ccu_common, hw); @@ -130,5 +144,6 @@ static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) extern const struct clk_ops ccu_div_ops; extern const struct clk_ops clk_pll_ops; extern const struct regmap_config th1520_clk_regmap_config; +extern const struct clk_ops ccu_gate_ops; #endif /* CLK_TH1520_H */ From patchwork Tue Dec 3 13:41:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDD55E64AA7 for ; Tue, 3 Dec 2024 13:42:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Tue, 3 Dec 2024 13:41:52 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 04/14] clk: thead: Add clock driver for TH1520 Video Output subsystem Date: Tue, 3 Dec 2024 14:41:27 +0100 Message-Id: <20241203134137.2114847-5-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SbUxTVxjOuff23ktj9VIYPdENFcFMFz7V5EyclsXpFZiImSwuC6wZd9WM D9OCH9sYIIzPYkAhulKEESOMrDSD0gABKsioUKyzYOk2qGxhyJcQiiiwRWe5bPPf8z7v857n fd4cGhc3kBvp00kpnCJJluBDCglDz7LFv1oYJQ8qXZKgO0PVGGr6S02hH9otGKrstgiQw6rH 0ODiHInq//yZQhPtmQSy1VZQKKtHR6JJtYNE8yqHAA20aki0UNQNkGEhm0Ta7hEK6RYrMfTd fBOBbjS3ApSTf1OA7ve9hyYHVDjKUW9AL9qaKfTc9iOBymeNFNLPlAiQSfshyjaWEtI32Dn7 NxQ7MzlJsLfznlBs+9Mqgm1Rj1CsqqUfsA11+SQ7bGsj2eu90ezDQhPGNt5IZ7O1PRg71/GA ZC/p6wBrzRqi2Ebzl8fcPxLui+cSTp/lFIH7PxGeGrNN4Wcyjp7vq7iHZ4DGsALgRkNmNxwb XSILgJAWM7UAOp13ML54AqB+0QH4YgHA8sw+qgDQqyMj1bE8XwOgyVy8JpoBsPniFHC9SzIh cLSmUuBqeDLTOLQv/rJqgjOPADSMaUiXyoOJhbPPslcnCMYP5hvNq7yIOQCzBjQCfsPN0Nh5 F3dhN0YKp8sKBLzGHfZ+O0a4MP5Sk9VUjrsMIKMVwpWrKxQ/fBD+1PA7zmMPOGXSr/GvQ/MV FcHjZDja5FzTfAVbVKY1HAqHLSukKzPO7IC61kCeDoODRtddXKdYD+2P3fkV1sPLhqs4T4tg Xo6YV2+HZaqi/0wttQaMxyycXtITxWCr+pUw6lfCqP/3rQJ4HZBwqcpEOacMTuLOBShlicrU JHnAp8mJDeDltzY/NzmbQcXUfEAXwGjQBSCN+3iKanQRcrEoXnbhC06RHKdITeCUXWATTfhI RH7xmzkxI5elcJ9z3BlO8W8Xo902ZmDnt5tvnzVeuZxSfMxwnUzr3MUMaUfLipnl8It1uu/7 pc6SWuv0rF/k+EPGfit9276SE6HPonLlI12NkUHrqk7MRZwLlh8KuSmKCbzgdVfhHfN0b15p UMeOKjoqIfdB3a0tY74nB9reFYQXWt4fjag3yQKjQ8bVhhe+RzRxEXjygfQ3f/0gRrLSFyyd 6Oy/lH7toKNX0+Ep2VI/GDlODe1qk8PQw8xvJ4/7Xyv8wzbhveGtDoHab79Xpk0Um5GbVr5X 2v7ZOip1T9iylaIO+2L335bHDTu+Pvq3f8hjD432eJAlJmznvSOP3inq8QqXei8d+nh3+tbu XmGaPXp4T5R1k/01H0J5Sha8E1coZf8APWKGtkUEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAKsWRmVeSWpSXmKPExsVy+t/xe7oLufzTDVpvWFqcuL6IyWLr71ns Fmv2nmOymH/kHKvFvUtbmCyufH3PZrHu6QV2ixd7G1ksrq2Yy27RfGw9m8XLWffYLD723GO1 uLxrDpvF594jjBbbPrewWaw9cpfdYv3X+UwWCz9uZbFYsmMXo0Vb5zJWi4unXC1eXu5htmib xW/xf88Odot/1zayWMx+t5/dYsubiawWx9eGW7Tsn8LiIOvx/kYru8ebly9ZPA53fGH32Ptt AYvHzll32T16dp5h9Ni0qpPN4861PWwe804GetzvPs7ksXlJvUfL2mNMHu/3XWXz6NuyitHj UvN1do/Np6sDBKP0bIryS0tSFTLyi0tslaINLYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLL Uov07RL0Mp5ce8Vc0OBXcWrueeYGxs2OXYwcHBICJhJ3F8V1MXJyCAksZZQ4+MIQxJYQkJG4 1v2SBcIWlvhzrYuti5ELqOYVo8T048vBEmwCRhIPls9nBUmICHSySLzdvJYRxGEWeMsocX3m RrAqYYEYiYfndzOB2CwCqhKd+0+zgdi8AvYSzZfnsEKskJfYf/AsM4jNKeAg8XpqFyvESfYS O/4eZoWoF5Q4OfMJ2ExmoPrmrbOZJzAKzEKSmoUktYCRaRWjSGppcW56brGRXnFibnFpXrpe cn7uJkZgUtl27OeWHYwrX33UO8TIxMF4iFGCg1lJhHf5eu90Id6UxMqq1KL8+KLSnNTiQ4ym QHdPZJYSTc4HprW8knhDMwNTQxMzSwNTSzNjJXFetivn04QE0hNLUrNTUwtSi2D6mDg4pRqY YgQ0yhl/bN9U/2dn9Qb2Z5UuRRx72srz/AI5U5zlmOece+/yh0nn5An26C6LN/51c0+urjxT bpXPKfhM+ABX3WPeCMuqAu9Hx20sXSz0F18TPXxoXV/m/4afnYs9z61kV9qzbmG7+AXuyk1t lZn7L/xS27f2Qn7lVCPp17HMD0XXL61euux65YN2p4x9H9SeLWwJnfV4x/8NEarbFsU3ZfRO sJ5vWrJ96bzrfxaEFk1I/uFjsUrH07Vgbeeip7abr9o6ySWfy1IO2cCq4lQhs69abvMZTbUM 9epTRpXdDF/WxPj6NTH8//S0OUYoensMs2HopqLKGTV816L0zX4ErLV7zizwTfGOcLiZM78S S3FGoqEWc1FxIgD4HSclswMAAA== X-CMS-MailID: 20241203134154eucas1p12517024f618800141cd4e7e20e0da72d X-Msg-Generator: CA X-RootMTR: 20241203134154eucas1p12517024f618800141cd4e7e20e0da72d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134154eucas1p12517024f618800141cd4e7e20e0da72d References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054159_502886_3A451459 X-CRM114-Status: GOOD ( 23.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Video Output (VO) module on the T-Head TH1520 SoC has its own set of clocks that need proper management. This commit introduces the clk-th1520-vo driver to support the VO subsystem clocks. Currently, only the clock gates are implemented, as they are the primary relevant clocks for the VO subsystem at this stage. Signed-off-by: Michal Wilczynski --- drivers/clk/thead/Kconfig | 11 ++ drivers/clk/thead/Makefile | 1 + drivers/clk/thead/clk-th1520-vo.c | 168 +++++++++++++++++++ include/dt-bindings/clock/thead,th1520-clk.h | 34 ++++ 4 files changed, 214 insertions(+) create mode 100644 drivers/clk/thead/clk-th1520-vo.c diff --git a/drivers/clk/thead/Kconfig b/drivers/clk/thead/Kconfig index 95e0d9eb965e..937927a1a4b8 100644 --- a/drivers/clk/thead/Kconfig +++ b/drivers/clk/thead/Kconfig @@ -11,3 +11,14 @@ config CLK_THEAD_TH1520_AP on the T-HEAD TH1520 SoC. This includes configuration of both CPU PLLs, both DPU PLLs as well as the GMAC, VIDEO, and TEE PLLs. + +config CLK_THEAD_TH1520_VO + bool "T-HEAD TH1520 VO clock support" + depends on ARCH_THEAD || COMPILE_TEST + depends on 64BIT + default ARCH_THEAD + select REGMAP_MMIO + help + Say yes here to support the VO sub system clock controller + on the T-HEAD TH1520 SoC. This includes clock gates for the + Video Output components like HDMI, MIPI, DPU and GPU. diff --git a/drivers/clk/thead/Makefile b/drivers/clk/thead/Makefile index d7cf88390b69..9afaee27b0b9 100644 --- a/drivers/clk/thead/Makefile +++ b/drivers/clk/thead/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CLK_THEAD_TH1520_AP) += clk-th1520.o clk-th1520-ap.o +obj-$(CONFIG_CLK_THEAD_TH1520_VO) += clk-th1520.o clk-th1520-vo.o diff --git a/drivers/clk/thead/clk-th1520-vo.c b/drivers/clk/thead/clk-th1520-vo.c new file mode 100644 index 000000000000..3c6d246ab53a --- /dev/null +++ b/drivers/clk/thead/clk-th1520-vo.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include "clk-th1520.h" + +#define NR_CLKS (CLK_HDMI_PIXCLK + 1) + +static const struct clk_parent_data video_pll_pd[] = { + /* TODO: provide a proper parent here */ + NULL, +}; + +static CCU_GATE_REGMAP(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk", + video_pll_pd, 0x50, BIT(0), 0); +static CCU_GATE_REGMAP(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_pd, + 0x50, BIT(3), 0); +static CCU_GATE_REGMAP(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", + video_pll_pd, 0x50, BIT(4), 0); +static CCU_GATE_REGMAP(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", + video_pll_pd, 0x50, BIT(5), 0); +static CCU_GATE_REGMAP(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", + video_pll_pd, 0x50, BIT(6), 0); +static CCU_GATE_REGMAP(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_pd, 0x50, + BIT(7), 0); +static CCU_GATE_REGMAP(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_pd, 0x50, + BIT(8), 0); +static CCU_GATE_REGMAP(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_pd, 0x50, + BIT(9), 0); +static CCU_GATE_REGMAP(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_pd, + 0x50, BIT(10), 0); +static CCU_GATE_REGMAP(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_pd, + 0x50, BIT(11), 0); +static CCU_GATE_REGMAP(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_pd, + 0x50, BIT(12), 0); +static CCU_GATE_REGMAP(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk", + video_pll_pd, 0x50, BIT(13), 0); +static CCU_GATE_REGMAP(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk", + video_pll_pd, 0x50, BIT(14), 0); +static CCU_GATE_REGMAP(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, + "mipi-dsi0-cfg-clk", video_pll_pd, 0x50, BIT(15), 0); +static CCU_GATE_REGMAP(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, + "mipi-dsi1-cfg-clk", video_pll_pd, 0x50, BIT(16), 0); +static CCU_GATE_REGMAP(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, + "mipi-dsi0-refclk", video_pll_pd, 0x50, BIT(17), 0); +static CCU_GATE_REGMAP(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, + "mipi-dsi1-refclk", video_pll_pd, 0x50, BIT(18), 0); +static CCU_GATE_REGMAP(CLK_HDMI_I2S, hdmi_i2c_clk, "hdmi-i2c-clk", video_pll_pd, + 0x50, BIT(19), 0); +static CCU_GATE_REGMAP(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk", + video_pll_pd, 0x50, BIT(20), 0); +static CCU_GATE_REGMAP(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk", + video_pll_pd, 0x50, BIT(21), 0); +static CCU_GATE_REGMAP(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk", + video_pll_pd, 0x50, BIT(22), 0); +static CCU_GATE_REGMAP(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk, + "iopmp-vosys-dpu-pclk", video_pll_pd, 0x50, BIT(23), 0); +static CCU_GATE_REGMAP(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk, + "iopmp-vosys-dpu1-pclk", video_pll_pd, 0x50, BIT(24), 0); +static CCU_GATE_REGMAP(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk, + "iopmp-vosys-gpu-pclk", video_pll_pd, 0x50, BIT(25), 0); +static CCU_GATE_REGMAP(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk", + video_pll_pd, 0x50, BIT(27), 0); +static CCU_GATE_REGMAP(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk", + video_pll_pd, 0x50, BIT(28), 0); +static CCU_GATE_REGMAP(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk", + video_pll_pd, 0x50, BIT(29), 0); +static CCU_GATE_REGMAP(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, + "mipi-dsi0-pixclk", video_pll_pd, 0x50, BIT(30), 0); +static CCU_GATE_REGMAP(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, + "mipi-dsi1-pixclk", video_pll_pd, 0x50, BIT(31), 0); +static CCU_GATE_REGMAP(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", + video_pll_pd, 0x54, BIT(0), 0); + +static struct ccu_common *th1520_vo_gate_clks[] = { + &axi4_vo_aclk.common, + &gpu_core_clk.common, + &gpu_cfg_aclk.common, + &dpu0_pixelclk.common, + &dpu1_pixelclk.common, + &dpu_hclk.common, + &dpu_aclk.common, + &dpu_cclk.common, + &hdmi_sfr_clk.common, + &hdmi_pclk.common, + &hdmi_cec_clk.common, + &mipi_dsi0_pclk.common, + &mipi_dsi1_pclk.common, + &mipi_dsi0_cfg_clk.common, + &mipi_dsi1_cfg_clk.common, + &mipi_dsi0_refclk.common, + &mipi_dsi1_refclk.common, + &hdmi_i2c_clk.common, + &x2h_dpu1_aclk.common, + &x2h_dpu_aclk.common, + &axi4_vo_pclk.common, + &iopmp_vosys_dpu_pclk.common, + &iopmp_vosys_dpu1_pclk.common, + &iopmp_vosys_gpu_pclk.common, + &iopmp_dpu1_aclk.common, + &iopmp_dpu_aclk.common, + &iopmp_gpu_aclk.common, + &mipi_dsi0_pixclk.common, + &mipi_dsi1_pixclk.common, + &hdmi_pixclk.common +}; + +static int th1520_clk_vo_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_hw_onecell_data *priv; + struct regmap *map; + struct clk_hw *hw; + int ret, i; + + priv = devm_kzalloc(dev, struct_size(priv, hws, NR_CLKS), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->num = NR_CLKS; + + map = syscon_regmap_lookup_by_phandle(np, "thead,vosys-regmap"); + if (IS_ERR(map)) + return PTR_ERR(map); + + for (i = 0; i < ARRAY_SIZE(th1520_vo_gate_clks); i++) { + struct ccu_gate *cg = hw_to_ccu_gate(&th1520_vo_gate_clks[i]->hw); + + th1520_vo_gate_clks[i]->map = map; + + ret = devm_clk_hw_register(dev, &th1520_vo_gate_clks[i]->hw); + if (ret) + return ret; + + priv->hws[cg->common.clkid] = hw; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id th1520_clk_vo_match[] = { + { + .compatible = "thead,th1520-clk-vo", + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, th1520_clk_vo_match); + +static struct platform_driver th1520_clk_vo_driver = { + .probe = th1520_clk_vo_probe, + .driver = { + .name = "th1520-clk-vo", + .of_match_table = th1520_clk_vo_match, + }, +}; +module_platform_driver(th1520_clk_vo_driver); + +MODULE_DESCRIPTION("T-HEAD TH1520 VO Clock driver"); +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/clock/thead,th1520-clk.h b/include/dt-bindings/clock/thead,th1520-clk.h index a199784b3512..86a7cf2c9acf 100644 --- a/include/dt-bindings/clock/thead,th1520-clk.h +++ b/include/dt-bindings/clock/thead,th1520-clk.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_CLK_TH1520_H_ #define _DT_BINDINGS_CLK_TH1520_H_ +/* AP clocks */ #define CLK_CPU_PLL0 0 #define CLK_CPU_PLL1 1 #define CLK_GMAC_PLL 2 @@ -93,4 +94,37 @@ #define CLK_SRAM3 83 #define CLK_PLL_GMAC_100M 84 #define CLK_UART_SCLK 85 + +/* VO clocks */ +#define CLK_AXI4_VO_ACLK 0 +#define CLK_GPU_CORE 1 +#define CLK_GPU_CFG_ACLK 2 +#define CLK_DPU_PIXELCLK0 3 +#define CLK_DPU_PIXELCLK1 4 +#define CLK_DPU_HCLK 5 +#define CLK_DPU_ACLK 6 +#define CLK_DPU_CCLK 7 +#define CLK_HDMI_SFR 8 +#define CLK_HDMI_PCLK 9 +#define CLK_HDMI_CEC 10 +#define CLK_MIPI_DSI0_PCLK 11 +#define CLK_MIPI_DSI1_PCLK 12 +#define CLK_MIPI_DSI0_CFG 13 +#define CLK_MIPI_DSI1_CFG 14 +#define CLK_MIPI_DSI0_REFCLK 15 +#define CLK_MIPI_DSI1_REFCLK 16 +#define CLK_HDMI_I2S 17 +#define CLK_X2H_DPU1_ACLK 18 +#define CLK_X2H_DPU_ACLK 19 +#define CLK_AXI4_VO_PCLK 20 +#define CLK_IOPMP_VOSYS_DPU_PCLK 21 +#define CLK_IOPMP_VOSYS_DPU1_PCLK 22 +#define CLK_IOPMP_VOSYS_GPU_PCLK 23 +#define CLK_IOPMP_DPU1_ACLK 24 +#define CLK_IOPMP_DPU_ACLK 25 +#define CLK_IOPMP_GPU_ACLK 26 +#define CLK_MIPIDSI0_PIXCLK 27 +#define CLK_MIPIDSI1_PIXCLK 28 +#define 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2024 13:41:53 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: Add support for Video Output subsystem Date: Tue, 3 Dec 2024 14:41:28 +0100 Message-Id: <20241203134137.2114847-6-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: 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CMS-TYPE: 201P X-CMS-RootMailID: 20241203134155eucas1p1e90c71c4f8eb5da41d2cc8a500f54dc7 References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054157_834857_C72CFA86 X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The device tree bindings for the T-Head TH1520 SoC clocks currently support only the Application Processor (AP) subsystem. This commit extends the bindings to include the Video Output (VO) subsystem clocks. Update the YAML schema to define the VO subsystem clocks, allowing the clock driver to configure and manage these clocks appropriately. This addition is necessary to enable the proper operation of the video output features on the TH1520 SoC. Signed-off-by: Michal Wilczynski --- .../bindings/clock/thead,th1520-clk-ap.yaml | 31 +++++++++++++++---- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml index 4a0806af2bf9..5a8f1041f766 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml @@ -4,11 +4,13 @@ $id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: T-HEAD TH1520 AP sub-system clock controller +title: T-HEAD TH1520 sub-systems clock controller description: | - The T-HEAD TH1520 AP sub-system clock controller configures the - CPU, DPU, GMAC and TEE PLLs. + The T-HEAD TH1520 sub-systems clock controller configures the + CPU, DPU, GMAC and TEE PLLs for the AP subsystem. For the VO + subsystem clock gates can be configured for the HDMI, MIPI and + the GPU. SoC reference manual https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf @@ -20,7 +22,9 @@ maintainers: properties: compatible: - const: thead,th1520-clk-ap + enum: + - thead,th1520-clk-ap + - thead,th1520-clk-vo reg: maxItems: 1 @@ -29,6 +33,17 @@ properties: items: - description: main oscillator (24MHz) + thead,vosys-regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to a syscon node representing the shared register + space of the VO (Video Output) subsystem. This register space + includes both clock control registers and other control + registers used for operations like resetting the GPU. Since + these registers reside in the same address space, access to + them is coordinated through a shared syscon regmap provided by + the specified syscon node. + "#clock-cells": const: 1 description: @@ -36,8 +51,6 @@ properties: required: - compatible - - reg - - clocks - "#clock-cells" additionalProperties: false @@ -51,3 +64,9 @@ examples: clocks = <&osc>; #clock-cells = <1>; }; + + clock-controller-vo { + compatible = "thead,th1520-clk-vo"; + thead,vosys-regmap = <&vosys_regmap>; + #clock-cells = <1>; + }; From patchwork Tue Dec 3 13:41:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B18C0E64AA3 for ; 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Tue, 3 Dec 2024 13:41:55 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 06/14] dt-bindings: clock: thead,th1520: Rename YAML schema file Date: Tue, 3 Dec 2024 14:41:29 +0100 Message-Id: <20241203134137.2114847-7-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxbZRTGfe+9vfdSU7iUTd5At4U60GnskBXzOsnAZMabzAQ1i5MNlSpX NuRjaYHNwQRXRD4K2ZYxt1KgLGArGdaND2kD8illsBaBjbXKgBm2UehE6Fh0LiDlMt1/v3PO 8z7POclL4+IfyCD6UFoGp0xTpEhJIdHS97f9pTphbFJ4l16A+m9cwFDzP1oKXWy3Y6i61y5A EyNNGLq2NE+i72//QqGZ9i8JNGaspJC6z0Qil3aCRAuaCQEatehI5CntBajFk0+iht6bFDIt VWOoZqGZQLWtFoAKir4VoOGBN5BrVIOjAq0fWmlrpdDy2CUCVfzRQaEm9ykBsjbsQ/kdZ4iY Tey84yuKdbtcBNtTeJ9i2x/oCdasvUmxGvNVwF6uLyLZ8bE2kq268g47WWLF2MbaXDa/oQ9j 53+6TrJlTfWAHVHfoNjGwey3/fcLoxK5lENZnHL7rgThwaLhrYcLxUd1HhueB371KwY+NGTk sMBxEi8GQlrMGAG81TdH8MV9AKea1OuFB8DhqjLy8ZN+o5rkBwYAf/7Ts164V59Y7AKvimQi 4JShWuAdbGDmcOhYcq6pcOYugC3TujWvACYONvaXrjJNE0wobHyU622LmGg4OFMO+LgtsKPL hnvZh4mBc+XFAl7jD6+cnya8jK9q1M0Va1dA5jshHBgwE15PyOyGt64n8D4BcNbaRPEsgSvm aozndDjVvIjznAPNGus6vwbH7Q/XVsOZbdBk2c63X4ejlmKSd/eFjnv+/Aa+8HTLNzjfFsHC AjGvDoPlmtL/Qu3GlvVQFva4e7GTIET7xC3aJ27R/p+rB3g9COQyValJnGpHGndEplKkqjLT kmSfpKdeBqufenDZutQKjLMLsm6A0aAbQBqXbhAZTHuSxKJExefHOGX6R8rMFE7VDYJpQhoo Ck3cwomZJEUG9xnHHeaUj6cY7ROUh7HZmqyttWfbIsNLyg+AjtyKyuL5nj553FObsuTHlyLu 2nrC74SqK6ej9HXSjt8kVRLRSuV71wjHqaG8t44snE7xnFi2fZER+WLAPZ1kZ4hub4OtzDmq B+Gd88fuhIVN+Fhdw+aC1geN0RFRF3aEbm4dkXWWRJ4Iqskx7fpx+dy2+Nqjzzsl8mTD3kvR UrDTsni85vyjuCwUfO7ieHxwXbb+tmRjHRE/m6Ytiv1QEvr1w/3v25wJbosiZuDq7k+NnQMo +5Vu35BJv+cCZXv+MkwOHXi6x/nBDEu7kmf31X1MWoZ+dxgDn3k2SJr76sZY7WZdd9GbTNcZ /bs5ZxflyeauGimhOqh4+QVcqVL8CyvUVdlDBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAKsWRmVeSWpSXmKPExsVy+t/xe7pLuPzTDU7dVLU4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZXReVCnoEKqY8/kscwPjLf4uRk4OCQETiRMrmtm6GLk4hASWMkpM6tjICpGQkbjW /ZIFwhaW+HOtC6roFaPEpeOtzCAJNgEjiQfL57OCJEQEOlkk3m5eywjiMAu8ZZS4PnMjWLuw QLjEu0fTmboYOThYBFQlNv+pBwnzCthLnH4xlRFig7zE/oNnwYZyCjhIvJ7aBXaFEFDNjr+H WSHqBSVOznwCNpIZqL5562zmCYwCs5CkZiFJLWBkWsUoklpanJueW2yoV5yYW1yal66XnJ+7 iRGYVLYd+7l5B+O8Vx/1DjEycTAeYpTgYFYS4V2+3jtdiDclsbIqtSg/vqg0J7X4EKMp0NkT maVEk/OBaS2vJN7QzMDU0MTM0sDU0sxYSZzX7fL5NCGB9MSS1OzU1ILUIpg+Jg5OqQYmptks DJPNDUP0/zr0fmcKWPTOT9csyPaZ3OPp0zKsDjR/VljNWZ358RDvwtqWvyUN82X2Bj5fwhmz ZlHPF9OYuF0LClfOVc14/8TUJXqXaE3v8ZB70bU/Fv03L05SDwteHjtVsk+pi7XZaYVhhpVL WdTR26Znv1SGLuF/1OT2v4N1W/4PG39tiQmcm6rPZ8ge55stxpHqPMv7uNACf5dN1nLVRlt4 d4qWTWRa59x4RDBTMt8t58Ks3Y2lm/qNNnx/7hf+MJX5zoIfi7wLGGJzWX+98PU+O/eaUPWM U/yPeeYLV35bXad5tYEx32bbDJslgk8XdKTcSy+YPnXHsYVPag3k9CoU/juKfot8Z6LEUpyR aKjFXFScCADRXE+gswMAAA== X-CMS-MailID: 20241203134156eucas1p2326d84fcef2ee0914586122520b18dcc X-Msg-Generator: CA X-RootMTR: 20241203134156eucas1p2326d84fcef2ee0914586122520b18dcc X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134156eucas1p2326d84fcef2ee0914586122520b18dcc References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054200_759744_7A0A6D4E X-CRM114-Status: GOOD ( 11.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As support for clocks from new subsystems is being added to the T-Head TH1520 SoC, the Device Tree binding YAML schema file name should reflect this broader scope. The existing schema file 'thead,th1520-clk-ap.yaml' includes the '-ap' suffix, indicating it's specific to the Application Processor (AP) subsystem. Rename the YAML schema file to 'thead,th1520-clk.yaml' to generalize it for all subsystems. Update all references to this schema file accordingly. Signed-off-by: Michal Wilczynski --- .../clock/{thead,th1520-clk-ap.yaml => thead,th1520-clk.yaml} | 2 +- MAINTAINERS | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/clock/{thead,th1520-clk-ap.yaml => thead,th1520-clk.yaml} (96%) diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk.yaml similarity index 96% rename from Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml rename to Documentation/devicetree/bindings/clock/thead,th1520-clk.yaml index 5a8f1041f766..416c8882942e 100644 --- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml# +$id: http://devicetree.org/schemas/clock/thead,th1520-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: T-HEAD TH1520 sub-systems clock controller diff --git a/MAINTAINERS b/MAINTAINERS index bd4bbf07d588..2f8f529e6a31 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20183,7 +20183,7 @@ M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained T: git https://github.com/pdp7/linux.git -F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/clock/thead,th1520-clk.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml From patchwork Tue Dec 3 13:41:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: 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2024 13:41:58 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eusmtrp1.samsung.com (KnoxPortal) with ESMTP id 20241203134158eusmtrp12c6e026a48b1b32a921993c6bf37ce78~NroULWYK40888908889eusmtrp1G; Tue, 3 Dec 2024 13:41:58 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-8b-674f0aa6ed9a Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 4F.F6.19654.5AA0F476; Tue, 3 Dec 2024 13:41:57 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241203134156eusmtip28456b9c6ad65c0da49bb5bf6132bdc18~NroS3YUQb3010130101eusmtip2Y; Tue, 3 Dec 2024 13:41:56 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 07/14] soc: thead: power-domain: Add skeleton power-domain driver for TH1520 Date: Tue, 3 Dec 2024 14:41:30 +0100 Message-Id: <20241203134137.2114847-8-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01SfVBUdRSd33tv33u7uPZYGfYXYdYSNFECYU0/0UlzMt72YVIzfVlDWzwX R2BtV0QTYw1aAVekwBgWi8URlhgIgWWDBeRzWA3cCBI2gwUVQoRYiI9GCozlYfnfueeec8+9 M5fGJRdIH3pf3EFOHaeIkZEiwtJ+56eNRaLXlSEu5yPoUt85DFX/baBQaYMdQ/ltdgFydpsx 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X-CRM114-Status: GOOD ( 34.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The T-Head TH1520 SoC contains multiple power islands that can be programmatically turned on and off using the AON (Always-On) protocol and a hardware mailbox [1]. The relevant mailbox driver has already been merged into the mainline kernel in commit 5d4d263e1c6b ("mailbox: Introduce support for T-head TH1520 Mailbox driver"); however, the AON implementation is still under development. This commit introduces a skeleton power-domain driver for the TH1520 SoC, designed to be easily extended to work with the AON protocol in the future. Currently, it only supports the GPU. Since there is no mechanism yet to turn the GPU power island on, the driver will only set the relevant registers to bring the GPU out of the reset state. This should be done after the power-up sequence requested through the mailbox is completed. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Signed-off-by: Michal Wilczynski --- MAINTAINERS | 2 + drivers/pmdomain/Kconfig | 1 + drivers/pmdomain/Makefile | 1 + drivers/pmdomain/thead/Kconfig | 12 ++ drivers/pmdomain/thead/Makefile | 2 + drivers/pmdomain/thead/th1520-pm-domains.c | 195 ++++++++++++++++++ .../dt-bindings/power/thead,th1520-power.h | 19 ++ 7 files changed, 232 insertions(+) create mode 100644 drivers/pmdomain/thead/Kconfig create mode 100644 drivers/pmdomain/thead/Makefile create mode 100644 drivers/pmdomain/thead/th1520-pm-domains.c create mode 100644 include/dt-bindings/power/thead,th1520-power.h diff --git a/MAINTAINERS b/MAINTAINERS index 2f8f529e6a31..16fb58aa74b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20192,7 +20192,9 @@ F: drivers/clk/thead/ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c +F: drivers/pmdomain/thead/th1520-pm-domains.c F: include/dt-bindings/clock/thead,th1520-clk.h +F: include/dt-bindings/power/thead,th1520-power.h RNBD BLOCK DRIVERS M: Md. Haris Iqbal diff --git a/drivers/pmdomain/Kconfig b/drivers/pmdomain/Kconfig index 23c64851a5b0..91f04ace35d4 100644 --- a/drivers/pmdomain/Kconfig +++ b/drivers/pmdomain/Kconfig @@ -16,6 +16,7 @@ source "drivers/pmdomain/st/Kconfig" source "drivers/pmdomain/starfive/Kconfig" source "drivers/pmdomain/sunxi/Kconfig" source "drivers/pmdomain/tegra/Kconfig" +source "drivers/pmdomain/thead/Kconfig" source "drivers/pmdomain/ti/Kconfig" source "drivers/pmdomain/xilinx/Kconfig" diff --git a/drivers/pmdomain/Makefile b/drivers/pmdomain/Makefile index a68ece2f4c68..7030f44a49df 100644 --- a/drivers/pmdomain/Makefile +++ b/drivers/pmdomain/Makefile @@ -14,6 +14,7 @@ obj-y += st/ obj-y += starfive/ obj-y += sunxi/ obj-y += tegra/ +obj-y += thead/ obj-y += ti/ obj-y += xilinx/ obj-y += core.o governor.o diff --git a/drivers/pmdomain/thead/Kconfig b/drivers/pmdomain/thead/Kconfig new file mode 100644 index 000000000000..8a063b3b96f3 --- /dev/null +++ b/drivers/pmdomain/thead/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config TH1520_PM_DOMAINS + bool "Support TH1520 Power Domains" + depends on ARCH_THEAD || COMPILE_TEST + select REGMAP_MMIO + help + This driver enables power domain management for the T-HEAD + TH-1520 SoC. On this SoC there are number of power domains, + which can be managed independently. For example GPU, AUDIO, + NPU, DPU reside in their own power domains which can be + turned on/off. diff --git a/drivers/pmdomain/thead/Makefile b/drivers/pmdomain/thead/Makefile new file mode 100644 index 000000000000..adfdf5479c68 --- /dev/null +++ b/drivers/pmdomain/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_TH1520_PM_DOMAINS) += th1520-pm-domains.o diff --git a/drivers/pmdomain/thead/th1520-pm-domains.c b/drivers/pmdomain/thead/th1520-pm-domains.c new file mode 100644 index 000000000000..60bdd011b017 --- /dev/null +++ b/drivers/pmdomain/thead/th1520-pm-domains.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* register offset in VOSYS_REGMAP */ +#define TH1520_GPU_RST_CFG 0x0 +#define TH1520_GPU_RST_CFG_MASK GENMASK(2, 0) + +/* register values */ +#define TH1520_GPU_SW_GPU_RST BIT(0) +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) + +struct th1520_power_domain { + struct regmap *reg; + struct generic_pm_domain genpd; + u32 rsrc; +}; + +struct th1520_power_info { + char *name; + u32 rsrc; +}; + +static const struct th1520_power_info th1520_pd_ranges[] = { + { "gpu", TH1520_AON_GPU_PD } +}; + +static inline struct th1520_power_domain * +to_th1520_power_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct th1520_power_domain, genpd); +} + +static void th1520_rst_gpu_enable(struct regmap *reg) +{ + int val; + + /* if the GPU is not in a reset state it, put it into one */ + regmap_read(reg, TH1520_GPU_RST_CFG, &val); + if (val) { + regmap_update_bits(reg, TH1520_GPU_RST_CFG, + TH1520_GPU_RST_CFG_MASK, 0x0); + } + + /* rst gpu clkgen */ + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_CLKGEN_RST); + /* rst gpu */ + regmap_set_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_SW_GPU_RST); +} + +static void th1520_rst_gpu_disable(struct regmap *reg) +{ + regmap_update_bits(reg, TH1520_GPU_RST_CFG, TH1520_GPU_RST_CFG_MASK, 0x0); +} + +static int th1520_pd_power_on(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + /* The missing component here is the call to E902 core through the + * AON protocol using hardware mailbox. + */ + + /* Initially after the power up the GPU and GPU clocks are + * in the reset state. Get them from that state to normal operation. + */ + th1520_rst_gpu_enable(pd->reg); + + return 0; +} + +static int th1520_pd_power_off(struct generic_pm_domain *domain) +{ + struct th1520_power_domain *pd = to_th1520_power_domain(domain); + + /* The missing component here is the call to E902 core through the + * AON protocol using hardware mailbox. + */ + + /* Put the GPU into reset state after powering it off */ + th1520_rst_gpu_disable(pd->reg); + + return 0; +} + +static struct generic_pm_domain *th1520_pd_xlate(const struct of_phandle_args *spec, + void *data) +{ + struct generic_pm_domain *domain = ERR_PTR(-ENOENT); + struct genpd_onecell_data *pd_data = data; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + pd = to_th1520_power_domain(pd_data->domains[i]); + if (pd->rsrc == spec->args[0]) { + domain = &pd->genpd; + break; + } + } + + return domain; +} + +static struct th1520_power_domain * +th1520_add_pm_domain(struct device *dev, const struct th1520_power_info *pi) +{ + struct th1520_power_domain *pd; + int ret; + + pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return ERR_PTR(-ENOMEM); + + pd->rsrc = pi->rsrc; + pd->genpd.power_on = th1520_pd_power_on; + pd->genpd.power_off = th1520_pd_power_off; + pd->genpd.name = pi->name; + + ret = pm_genpd_init(&pd->genpd, NULL, true); + if (ret) { + devm_kfree(dev, pd); + return ERR_PTR(ret); + } + + return pd; +} + +static int th1520_pd_probe(struct platform_device *pdev) +{ + struct generic_pm_domain **domains; + struct genpd_onecell_data *pd_data; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct regmap *reg; + int i; + + reg = syscon_regmap_lookup_by_phandle(np, "thead,vosys-regmap"); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + domains = devm_kcalloc(dev, ARRAY_SIZE(th1520_pd_ranges), + sizeof(*domains), GFP_KERNEL); + if (!domains) + return -ENOMEM; + + pd_data = devm_kzalloc(dev, sizeof(*pd_data), GFP_KERNEL); + if (!pd_data) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(th1520_pd_ranges); i++) { + struct th1520_power_domain *pd; + + pd = th1520_add_pm_domain(dev, &th1520_pd_ranges[i]); + if (IS_ERR_OR_NULL(pd)) + continue; + + pd->reg = reg; + domains[i] = &pd->genpd; + dev_dbg(dev, "added power domain %s\n", pd->genpd.name); + } + + pd_data->domains = domains; + pd_data->num_domains = ARRAY_SIZE(th1520_pd_ranges); + pd_data->xlate = th1520_pd_xlate; + + return of_genpd_add_provider_onecell(dev->of_node, pd_data); +} + +static const struct of_device_id th1520_pd_match[] = { + { .compatible = "thead,th1520-pd",}, + { /* sentinel */ } +}; + +static struct platform_driver th1520_pd_driver = { + .driver = { + .name = "th1520-pd", + .of_match_table = th1520_pd_match, + }, + .probe = th1520_pd_probe, +}; +builtin_platform_driver(th1520_pd_driver); diff --git a/include/dt-bindings/power/thead,th1520-power.h b/include/dt-bindings/power/thead,th1520-power.h new file mode 100644 index 000000000000..30fb4e9892e7 --- /dev/null +++ b/include/dt-bindings/power/thead,th1520-power.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef __DT_BINDINGS_POWER_TH1520_H +#define __DT_BINDINGS_POWER_TH1520_H + +#define TH1520_AON_AUDIO_PD 0 +#define TH1520_AON_VDEC_PD 1 +#define TH1520_AON_NPU_PD 2 +#define TH1520_AON_VENC_PD 3 +#define TH1520_AON_GPU_PD 4 +#define TH1520_AON_DSP0_PD 5 +#define TH1520_AON_DSP1_PD 6 + +#endif From patchwork Tue Dec 3 13:41:31 2024 Content-Type: text/plain; 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Tue, 3 Dec 2024 13:41:59 +0000 (GMT) X-AuditID: cbfec7f2-b09c370000005155-78-674f0aa7012c Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id B1.07.19654.7AA0F476; Tue, 3 Dec 2024 13:41:59 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241203134157eusmtip2c106e0c8996c77f30060740310e5e13f~NroUGITQL2454624546eusmtip2M; Tue, 3 Dec 2024 13:41:57 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 08/14] dt-bindings: power: thead,th1520: Add support for power domains Date: Tue, 3 Dec 2024 14:41:31 +0100 Message-Id: <20241203134137.2114847-9-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Se0xTZxjG851zes6hpnAobHxjGJFFic6BNSz7jKCyuOVMXNRdMmFLsIGz ygaFtYLbNBsIlMsKkxVYrJbb5CIRmFwqVC4ZFCpjwICBZQNEw60ULVejc5FRDm7+93ve93m/ 532Tj8bF1aQ7HSE/zSnk0kgvUkjoOx73vlYqPCrbPXltN7p1uwhDdU+0FLrW1IOhfGOPAI31 12LojxUbiSonf6fQTFMCgYbKdBRK7KgikUU7RqIF9ZgADRguk2gpwwiQfimJRBXGUQpVreRj qHChjkBX6g0AqdJKBKjv17eQZUCNI5XWCa021lPo6dB1Al160EKh2rksATJVfISSWrKJg5tZ mzmZYucsFoJtS12m2KaHBQTboB2lWHXDb4CtLk8j2ZGhRpLN6zzO3vnOhLE1V75lkyo6MNbW PEiymbXlgO1PvE2xNV1njzmHCP3DuciIOE7hu/+k8NTcXxpBzEX45dXVaUE8eOySDhxoyPjB G20pWDoQ0mKmDECV8QLJi2UA8yaSN8QSgOd1d8lnIzMZowK+UQrgdG87xYu5NfGggbK7SGYP HC/NX3e5MlYcmleG19/CmWkA9ROX1wRNuzChcKQP2QcIZhtMuN+G21nEHICaJ8M4H7cFtvzS vc4OzEFozUkX8B5n2HlxgrAzvuZJrLuE29+HTLEQpsxrCX74EMybslI8u8BZU+0Ge8AujXrD Ew3H6xY3ws7BBrVpg/fBkZ6/1/fEmR2wyuDLlwNh9/cDmL0MGUdovu/Mr+AIf9D/iPNlEUxV iXn3dpijzvgvtKdMj/HMwqo7DeAC2Kp97hjtc8do/88tAHg5cONilVEyTimRc2d8lNIoZaxc 5hMWHVUN1r5111PTYj3QzS74tAKMBq0A0riXq6i0KkgmFoVLv/qaU0SHKmIjOWUreJkmvNxE 28K3cGJGJj3Nfc5xMZziWRejHdzjsa0l9ErzVPBeTzyiaVDmZ/buWz7cUQwkFmfh3ojscIsR Sx4bzCqyxaTqg47uElbuFO9iNscz71+nvjhUzD26keu90viO5qfFb4JD5o980P3q/Op7MCtL /WF83DnLWVl/pSh4v9M/V41Li+M5ryso0myajNyz6e6B5pa3zwe046JPA8Lu6QL+tDk4eX+W e0Iip/0Kgtp9U7Je8bD6F4Ub3I94Fr5ofeT6QljKJl3g1PLsjqnUNDdD93xIEHRUTXr0fvJz YM3NhMXg46Djlj/mf6ZQAl76+N3hsdz5kDdPusY9zHSZGddr9g3dC02nOyeydZ2ZA/Jl7zfA 4RLPm1aVsvCEF6E8JZXsxBVK6b+K2htPRQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEKsWRmVeSWpSXmKPExsVy+t/xe7rLufzTDeZcFLQ4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZby5PZm1YKZExcr/z1kbGH8KdzFyckgImEi86L3L2sXIxSEksJRRom/XTHaIhIzE te6XLBC2sMSfa11sEEWvGCVaWn+zgiTYBIwkHiyfD9YtItDJIvF281pGEIdZ4C2jxPWZG8Ha hQViJRZe38oMYrMIqEo0vj0MZvMK2EtM/n2TGWKFvMT+g2fBbE4BB4nXU7vANggB1ez4e5gV ol5Q4uTMJ2AzmYHqm7fOZp7AKDALSWoWktQCRqZVjCKppcW56bnFRnrFibnFpXnpesn5uZsY gYll27GfW3Ywrnz1Ue8QIxMH4yFGCQ5mJRHe5eu904V4UxIrq1KL8uOLSnNSiw8xmgLdPZFZ SjQ5H5ja8kriDc0MTA1NzCwNTC3NjJXEedmunE8TEkhPLEnNTk0tSC2C6WPi4JRqYLIOVjlb 9v606exyy4MTbvH+X8/zVXKnbXLVvg2p6ur5Qle6mz6VBdR87A86y880i/tdSYlXitKGpj2/ bT0F1myIS/y55muOaU99uV2oPoNtYKv0TYYJ0/eH9f1ld51lvuCU+M9t62SCZzEa5N6+FTXn tFfng683UgUmXLE65nU3jL/lIfM3DZXE8wyS2sfLu3iibuceNbS/M1fvyu7DfgzzZ+epbA2r teW0yPmf9PTnycY8YxHtUJb/0pKiur3fvTbvK7RysDBdp3JhesM9KzuDnT5mSivWdU4pND63 Un/Kyk277mzUPmuk+SdgqVgYe8xC6Uem/l0bdy9xdy2c3Za50UZbdtPmNNUM5SfnlViKMxIN tZiLihMB3TtOWLUDAAA= X-CMS-MailID: 20241203134159eucas1p1eafefef0dfe7f2b6343a639733012bcf X-Msg-Generator: CA X-RootMTR: 20241203134159eucas1p1eafefef0dfe7f2b6343a639733012bcf X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134159eucas1p1eafefef0dfe7f2b6343a639733012bcf References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054202_252976_15B6B84E X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add power domain support to the Thead TH1520 clock controller bindings. This enables devices to specify their power domain dependencies, improving power management for components like the GPU. Signed-off-by: Michal Wilczynski --- .../bindings/power/thead,th1520-power.yaml | 52 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/thead,th1520-power.yaml diff --git a/Documentation/devicetree/bindings/power/thead,th1520-power.yaml b/Documentation/devicetree/bindings/power/thead,th1520-power.yaml new file mode 100644 index 000000000000..528af54f4ca6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/thead,th1520-power.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/thead,th1520-power.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 Power Domain Controller + +maintainers: + - Michal Wilczynski + +description: | + The T-HEAD TH1520 SoC includes a power domain controller responsible for + managing the power states of various hardware domains such as the GPU. + + This binding describes the power domain controller node, which can be used by + devices to manage their power domains. + +properties: + compatible: + const: "thead,th1520-pd" + + thead,vosys-regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to a syscon node representing the shared register space of the VO (Video Output) subsystem. + This register space includes both clock control registers and other control registers used for + operations like resetting the GPU. Since these registers reside in the same address space, + access to them is coordinated through a shared syscon regmap provided by the specified syscon node. + + '#power-domain-cells': + const: 1 + +required: + - compatible + - thead,vosys-regmap + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + vosys_regmap: vosys@ffef528000 { + compatible = "syscon"; + reg = <0xff 0xef528000 0x0 0x1000>; + }; + + power-controller { + compatible = "thead,th1520-pd"; + thead,vosys-regmap = <&vosys_regmap>; + #power-domain-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 16fb58aa74b1..acbe311087ad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20187,6 +20187,7 @@ F: Documentation/devicetree/bindings/clock/thead,th1520-clk.yaml F: Documentation/devicetree/bindings/mailbox/thead,th1520-mbox.yaml F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml F: Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml +F: 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AMDC4942.home (unknown [106.210.136.40]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20241203134159eusmtip220458ce3abcd87999c00db6ae33bca7d~NroVWYeUR3160631606eusmtip2F; Tue, 3 Dec 2024 13:41:59 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 09/14] riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs 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20241203134200eucas1p25a1f81ea1ce3f10d507be381da750b31 X-Msg-Generator: CA X-RootMTR: 20241203134200eucas1p25a1f81ea1ce3f10d507be381da750b31 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134200eucas1p25a1f81ea1ce3f10d507be381da750b31 References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054203_499325_7AE02457 X-CRM114-Status: GOOD ( 10.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T-Head SoCs feature separate power domains (power islands) for major components like the GPU, Audio, and NPU. To manage the power states of these components effectively, the kernel requires generic power domain support. This commit enables `CONFIG_PM_GENERIC_DOMAINS` for T-Head SoCs, allowing the power domain driver for these components to be compiled and integrated. This ensures proper power management and energy efficiency on T-Head platforms. By selecting `PM_GENERIC_DOMAINS`, we provide the necessary framework for the power domain drivers to function correctly on RISC-V architecture with T-Head SoCs. Signed-off-by: Michal Wilczynski --- arch/riscv/Kconfig.socs | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index f51bb24bc84c..c414dc618b66 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -48,6 +48,7 @@ config ARCH_THEAD bool "T-HEAD RISC-V SoCs" depends on MMU && !XIP_KERNEL select ERRATA_THEAD + select PM_GENERIC_DOMAINS if PM help This enables support for the RISC-V based T-HEAD SoCs. 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2024 13:42:00 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 10/14] drm/imagination: Add support for IMG BXM-4-64 GPU Date: Tue, 3 Dec 2024 14:41:33 +0100 Message-Id: <20241203134137.2114847-11-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: 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CMS-TYPE: 201P X-CMS-RootMailID: 20241203134202eucas1p26bdcec486ee42440ded94ff801678ba0 References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054204_579639_B81DBEE8 X-CRM114-Status: GOOD ( 13.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The IMG BXM-4-64 GPU is integrated into the T-Head TH1520 SoC. This commit adds the compatible string "img,img-bxm-4-64" to the device tree match table in the drm/imagination driver, enabling support for this GPU. By including this GPU in the compatible devices list, the driver can initialize and manage the BXM-4-64 GPU on the TH1520 SoC, providing graphics acceleration capabilities upstream. This commit doesn't touch the img,powervr-rogue.yaml on purpose, as the new dt-bindings schema was proposed [1], but not merged yet. Link: https://lore.kernel.org/all/20241118-sets-bxs-4-64-patch-v1-v2-1-3fd45d9fb0cf@imgtec.com/ [1] Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/pvr_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagination/pvr_drv.c index 85ee9abd1811..8633a3a315b7 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1475,6 +1475,7 @@ static void pvr_remove(struct platform_device *plat_dev) static const struct of_device_id dt_match[] = { { .compatible = "img,img-axe", .data = NULL }, + { .compatible = "img,img-bxm-4-64", .data = NULL }, {} }; MODULE_DEVICE_TABLE(of, dt_match); From patchwork Tue Dec 3 13:41:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57894E64AA7 for ; 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Tue, 3 Dec 2024 13:42:01 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 11/14] drm/imagination: Enable PowerVR driver for RISC-V Date: Tue, 3 Dec 2024 14:41:34 +0100 Message-Id: <20241203134137.2114847-12-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf1CTdRzH+T7Ps+d5WDd6GHj7ShAnBld2oiJn38vqMLWezlDpnzrO0p08 zQkM3ByZesmvFtAoSBg5SBYh0BBJxhYsafLjmLBcCIUQ8qOLMGS5kB9XGayNB8v/Xp/35/25 9+dz96FxcRMZQssVxzmlQpoSQQoJS/dfzo31wn2yzSOeLejazSoMme/rKXSxzYmhyi6nAI31 N2PohwU3iS792keh39qyCDRY9xmFcrobSTStHyPRrHZMgAasFSSaK+wCyDKXS6KGrlEKNS5U YujzWTOBqlusAGnyawToRu9uND2gxZFG/yjyXGmh0PLgZQKV37VRqNlVLED2htdRrq2EiAtj 3UPvU6xreppgO/PmKbZt0UCwrfpRitW2fgfYJmM+yd4avEKy53sS2PEP7Rhrqj7D5jZ0Y6z7 2x9J9qNmI2D7c25SrMlxan9govC5JC5FnsEpN71wSHjkqvUelm6lTxRPLuGZ4AOqAPjTkImF dcvZRAEQ0mKmDkBdUSHOF/MAns01UHwxB2Bn+ceCByPnvyheGRcztQC6NQd4kwvA5XOTuK9B MjFworZS4GsEMzM4HFoYJn0FztwG0DJZQfpcQUwCvDw8ssIEEwk7bk9iPhYxcdCu7cH5uHBo a7++wv5efaa0QMB7AmHPuUnCx7jXk2MuX1kcMheEcNzgWD1vF+ztM5M8B8E79uZVPRQ6zmoJ ntPghPneathp2Kq1r/J2eMv5t3eW9gY8BRutm3h5B9S7C4BPhkwAHPo9kF8hAH5iKcN5WQTz NGLeHQVLtYX/hTrrLBjPLPz0n2ZBEVinf+gY/UPH6P/PNQDcCCScWpUq41QxCu6daJU0VaVW yKIPp6U2Ae9bO5bt8y2g9s5sdAfAaNABII1HBItqG/fIxKIk6bsnOWXaQaU6hVN1gMdoIkIi ikwK58SMTHqcS+a4dE75oIvR/iGZmJG2LZX5HTrhr5dkySq+OXbdefirhJKBN2p//j7b9efb r2hNnr2nD7gvnJHJbBtmrnnCl7IPtiX2HS08elenzlfv7fd7fsfwRnHMnl07e967KlkXHxW7 pqqkKObl9mMvRT2TNE7ndAuqwiuSnqZCkk1bDV3y7DJDKPt1EMqzBYneWhtbSf4yrj+5dluv Kb3CdEk+l7Ho2bzwmm27rTPOocmc+oN50xmj/inglCv0xkh7SbDzCWWI9n70kwo59+z6pou7 q2YXE4X1fVNme2LNqyOG+v2YLnGNLsS1/hHdzjbP1qnq+NLSdvOX8ROPJ0vqB4vDIo01WRlh Uy+SgdtGPfv8UG8EoToi3bIBV6qk/wJ0jQjbRQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrEKsWRmVeSWpSXmKPExsVy+t/xe7qrufzTDRqb+S1OXF/EZLH19yx2 izV7zzFZzD9yjtXi3qUtTBZXvr5ns1j39AK7xYu9jSwW11bMZbdoPraezeLlrHtsFh977rFa XN41h83ic+8RRottn1vYLNYeuctusf7rfCaLhR+3slgs2bGL0aKtcxmrxcVTrhYvL/cwW7TN 4rf4v2cHu8W/axtZLGa/289useXNRFaL42vDLVr2T2FxkPV4f6OV3ePNy5csHoc7vrB77P22 gMVj56y77B49O88wemxa1cnmcefaHjaPeScDPe53H2fy2Lyk3qNl7TEmj/f7rrJ59G1Zxehx qfk6u8fm09UBglF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZll qUX6dgl6GQd2fWIq2MVRMfHJX+YGxnb2LkZODgkBE4l5iycC2VwcQgJLGSUa5pyHSshIXOt+ yQJhC0v8udbFBlH0ilGi4/FhNpAEm4CRxIPl81lBEiICnSwSbzevZQRxmAXeMkpcn7kRrF1Y wF9i6sEnYGNZBFQlDj1/wgRi8wo4SBzvOckMsUJeYv/Bs2A2J1D89dQuVhBbSMBeYsffw6wQ 9YISJ2c+AZvJDFTfvHU28wRGgVlIUrOQpBYwMq1iFEktLc5Nzy021CtOzC0uzUvXS87P3cQI TCzbjv3cvINx3quPeocYmTgYDzFKcDArifAuX++dLsSbklhZlVqUH19UmpNafIjRFOjuicxS osn5wNSWVxJvaGZgamhiZmlgamlmrCTO63b5fJqQQHpiSWp2ampBahFMHxMHp1QDkx57bcDm FYkFPZfbZ9zfwdyUfplbcX/XoY0+Ts/nx1dZNe/xWJJw4lhzkgD/VDlZpiVrNtQujmG3iVLZ ++fr5NnfN1wQtDCSt+O+myuW87oxwt571/eFYf5XL3DKVOv5mh6b0KYpNlfFkkNEJnBfpALX jMNSia8zzG+ERizmiJmm9b437MWvJd6vd7ltZC1ROvHl6/t/07kFraJ26+ZfkUhheuFZ7HY7 tTfjt/7vs8vcnrxuXd9j8MFxl4Jz/fTr4tPYPEy6jluL3XttMjN705ZP8x6+i9Ba6Sxfl9u2 97yYEteqRW98cm4vr/11Je1D6tGoQKtv77lXXfav+bU+bpn5tHlOX6YdKzp79DfbXyWW4oxE Qy3mouJEAFZ2wvS1AwAA X-CMS-MailID: 20241203134203eucas1p11a2e36f777af362a333d8865bcb5d34e X-Msg-Generator: CA X-RootMTR: 20241203134203eucas1p11a2e36f777af362a333d8865bcb5d34e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134203eucas1p11a2e36f777af362a333d8865bcb5d34e References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054206_236208_AC98E379 X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Several RISC-V boards feature Imagination GPUs that are compatible with the PowerVR driver. An example is the IMG BXM-4-64 GPU on the Lichee Pi 4A board. This commit adjusts the driver's Kconfig dependencies to allow the PowerVR driver to be compiled on the RISC-V architecture. By enabling compilation on RISC-V, we expand support for these GPUs, providing graphics acceleration capabilities and enhancing hardware compatibility on RISC-V platforms. Signed-off-by: Michal Wilczynski --- drivers/gpu/drm/imagination/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/Kconfig b/drivers/gpu/drm/imagination/Kconfig index 3bfa2ac212dc..5f218896114c 100644 --- a/drivers/gpu/drm/imagination/Kconfig +++ b/drivers/gpu/drm/imagination/Kconfig @@ -3,7 +3,7 @@ config DRM_POWERVR tristate "Imagination Technologies PowerVR (Series 6 and later) & IMG Graphics" - depends on ARM64 + depends on (ARM64 || RISCV) depends on DRM depends on PM select DRM_EXEC From patchwork Tue Dec 3 13:41:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59CAAE64A9E for ; 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Tue, 3 Dec 2024 13:42:03 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 12/14] riscv: dts: Add Video Output clock and syscon regmap nodes Date: Tue, 3 Dec 2024 14:41:35 +0100 Message-Id: <20241203134137.2114847-13-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SfUxTVxjGd+69vfe2Ce7SEjniDJMFdYvCxlx2NhcncdMb/AM/FtyYRptx VxlQWGun4jbEYqWsMN0gmy1IHfIZKhNaQiuMAE0B0c6VTxXQZjipLRK+JGjEUS5u/vc7z/O8 5zlvcmhcXEuG0Inyw5xCLk0OI0VEvWPOucEkipW96WwmUEf/bxiyPNFTqLrJiaFiu1OAhl1m DPXMjJPo0r0bFBptyiRQX0URhdSOGhJ59MMkmtANC1C3rZBEU7l2gOqnskhksg9RqGamGEMX JiwEuthgA0ijLROgv65+jDzdOhxp9C+jZ40NFJrvu0wgw8NmCpl9ZwWo3bQXZTXnE1tWseMD pyjW5/EQbFv2NMU2PTISrFU/RLE66zXA1lZpSXawr5Fkz3fuYu/80I6xdRcz2CyTA2PH/+gl 2TxzFWBd6n6Kres6vjMwXvRBApec+A2niNx8UHTIcHlUkHZLdHTW4KROAA+dA4Q0ZDZCdVkP yAEiWsxUAPh76STlN8TMNIBXb0HemAJwUKsVPJ/QuasEvFEO4NPbVpI/+AB8+MyK+1MkEwXv lhcvpoIYLw4HZm4upnDmPoD1I4WkPyVh4uHpuaHFewkmHHa32YGfA5gtsMN7ZakvFDa3XF+8 VbigewtyBHwmEHaeGyH8jC9k1BYD7i+ATKUI2u/kLg1/BEvb3CTPEvig3Uzx/Ars+llH8JwK 71omcZ6/hVZd+xJvgoPOxwuz9ELB67DGFsnL0bDl75u4X4bMMjgwFsg/YRn8qf6XJTkAZmvE fHoNLNDl/lfqrKjHeGbhmRIXdQas1r+wjP6FZfT/9xoBXgWCOZUyRcYpo+TckQilNEWpkssi vkhNqQUL37prvn26AZQ/mIhoBRgNWgGk8bCggPKaHTJxQIL0WDqnSD2gUCVzylawkibCggPC E0I5MSOTHuaSOC6NUzx3MVoYcgIzzYVKC/allzjN6mhJTPcG+awk7H13wu3T/bHvdrvWjmkU uxu8az+JXr2c3J+5Qrht/1Te8v6iWZtkX6d5249jhd9tOisOOp462qrfMTj7jjFvuqDjRlFS RjW3q3cVRgeHzMRtVk5+3+uJvwZaHLg4/LXPtqY1ZMc8Ss5X5WxfY8HV6dWx8lbpvG/K2HRv T4fV3VV3cvjVFSW/bg8/2vOpsNCp9pa4d3749p9O+dd1X9U9XpnjW1/Z9KXN0OiKOphxpOtK cL8WJnpGikHNSVlc+TmJJvLz8+YLKvfW97Qb508dM5b+E3UgZt36dfOZ9586HMKkvXE9fU/0 +S9Vll2ypIdcDyOUh6RvvYErlNJ/ASKbB4pFBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsVy+t/xe7pruPzTDbbMVbQ4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZcze+IK14BZXxffZ59gbGF9ydDFyckgImEj0PFzF2sXIxSEksJRR4sChbjaIhIzE te6XLBC2sMSfa11gcSGBV4wS8ydpgdhsAkYSD5bPB2sWEehkkXi7eS0jiMMs8JZR4vrMjWDd wgIREod+7mIHsVkEVCUuHz7CCGLzCjhInHi9mxVig7zE/oNnmUFsTqD466ldrBDb7CV2/D3M ClEvKHFy5hOwmcxA9c1bZzNPYBSYhSQ1C0lqASPTKkaR1NLi3PTcYkO94sTc4tK8dL3k/NxN jMC0su3Yz807GOe9+qh3iJGJg/EQowQHs5II7/L13ulCvCmJlVWpRfnxRaU5qcWHGE2B7p7I LCWanA9MbHkl8YZmBqaGJmaWBqaWZsZK4rxul8+nCQmkJ5akZqemFqQWwfQxcXBKNTAZfEsQ kGq9I7b9nqhD9a2LK7qOZzvOEUrdWydetlT8hOis5LX9jA9lZ3jZXuXJ+v5TSlVh7lM3hnn1 59jP653Z9VdQ9NL6UzPNP4g3XnngtKax6PNM3Syxoglbw+Zs3cfIdfbI48iTG1J+K0svT/ZP 7fD2cZI9c+aw+4+WZ/ls1hMUJktMdHvN/7vDwMfs4I+CS8s6wmoW964y/Vq7dEfA/qi1W6VX rO6MZ71xq1Nt36z4pg2bnk5bdHjHj1S1vQqRrMck2s4bMXlNL30ttajrQsLEFb1sFw9yBrKd Nfp6a07k/ZlxRd1nrVqkcr69O/eqavPna7Ipj6Linmyf2bT2wD6JtdeWLy7XPfKqryi/UIml OCPRUIu5qDgRAK6j0Gq0AwAA X-CMS-MailID: 20241203134204eucas1p1d0df90a265637542f0652fd407dc7989 X-Msg-Generator: CA X-RootMTR: 20241203134204eucas1p1d0df90a265637542f0652fd407dc7989 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134204eucas1p1d0df90a265637542f0652fd407dc7989 References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054207_172751_53A39AB2 X-CRM114-Status: GOOD ( 10.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The address space controlling the Video Output (VO) subsystem clocks also contains control registers for GPU resets. To properly synchronize access to this shared address space, create a syscon Device Tree node for the VO registers and reference it in the clock controller node. This change ensures coordinated access to the VO registers between the clock controller and other drivers, preventing conflicts and maintaining system stability. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index dc2d554b4a71..39d39059160d 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -489,6 +489,18 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + vosys_clk: clock-controller { + compatible = "thead,th1520-clk-vo"; + thead,vosys-regmap = <&vosys_reg>; + #clock-cells = <1>; + }; + + vosys_reg: vosys@ffef528000 { + compatible = "thead,th1520-vosys", "syscon"; + reg = <0xff 0xef528000 0x0 0x1000>; + status = "okay"; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; From patchwork Tue Dec 3 13:41:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA05EE64AA3 for ; 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Tue, 3 Dec 2024 13:42:04 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 13/14] riscv: dts: Introduce power domain node with simple-bus compatible Date: Tue, 3 Dec 2024 14:41:36 +0100 Message-Id: <20241203134137.2114847-14-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sa0xTZxjHfc85PefQrHhaEN+BTKzRXeLQFU3ebcIkcclJdBsSLxsfJnUc ixkU1oqDbYk6GANs2bR2aLlZ0nCLeKK9DBiXCQ3lImwoFDCALOJmlUm41GUqsJbDNr/9nuf5 P5f/m5fGZVfJUPqY+jinUStT5KSYcHT8/cvrV8QfqLZ1dwejzqEKDNmfmih0ubkPQ+XOPhEa v2nD0IB3mkRX7v1KofvNpwnkri6lUHYHTyKPaZxEM7pxEbrVWEKiOb0TIMdcDonqnGMU4r3l GDLP2AlkqW8EKDe/UoT6u99Fnls6HOWaVqOlpnoKLbqvEqj4USuFbFNnRchVdwjltJ4ndoWz 08PfUOyUx0Ow7XnzFNv8+BLBNpjGKFbXcAOw12rzSXbU3USyZV372DtnXBhrtZxkc+o6MHa6 ZZBkC221gL2ZPUSx1p4v46QJ4p1JXMqxE5xma0yiONltKsTT51/I/L1Mcgr0iwtAAA2Z7dDx 2CUqAGJaxlQDyLvshBDMA3jasQSEYA7AudJZX4VeblkqDRTyVQB29HZSQjDl62gfwfxzSUYB J6rKl+cGMw9xOOwdIf0BzvwBoGOyhPSrgpgjkNePLjPBbILV1oZlljC74KzLhQkXroet13tx Pwf48g+NBSJBI4VdFycJP+M+Tba9GPcvgEydGJY1nwdC827Y26MnBQ6CD1w2SuB1sMegIwRO gxP2WVzgr2CDzrXCb8PRviek3zPOvAr5xq1COha2DUzgwlMEwuE/pcIJgfCco2glLYF5uTJB vRkadfr/lvZVO1ZcsdCwmA++BxtMz5kxPWfG9P/eSwCvBWu5DG2qitNGqbnPI7XKVG2GWhX5 SVrqNeD71T2LLm89qH4wE9kGMBq0AUjj8mBJFb9HJZMkKbO+4DRphzUZKZy2DYTRhHytZFPS ek7GqJTHuU85Lp3T/FvF6IDQU1hJf3TNYFbYlvu/SV8xh9mjVe/9+FFIaETL2aQbbxkqX6qP +frZ4tO6prE1cRN/lQQNrIt6R3Hi4lDORrJiYUEauhHnupI7DfJZS33XIYVBj4r4ws6yy59Z T/LtHvNuW1pLf82QI5/+0OhWbLmQ/nK47eOaN6vU2Zk2SfZO6cGF/e9HLlDyveqx+ejBFxOK nqTckxUXBfDjIc6fLEZn/Gpx1JrMozsqIwqeHR39uTvaYiAKZFnbW24fTIxI/05hBjQfviq3 PC4h8duQCnJH47693VXxGm/8D7Wxk4qcu7Y7klW51gMb1IfzNhuj8kCS+QweeCF2z/XbRx6d G/Fuc9+N4eWENln5xmu4Rqv8B2fHr1lEBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPKsWRmVeSWpSXmKPExsVy+t/xe7prufzTDZ5fMbM4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZVyb1cdc8IWn4tk83gbGi1xdjBwcEgImEv/n8nUxcnEICSxllPixr4exi5ETKC4j ca37JQuELSzx51oXG0TRK0aJF4v3MIMk2ASMJB4sn88KkhAR6GSReLt5LSOIwyzwllHi+syN LCArhAUSJFom+4A0sAioSqzYvJMNxOYVcJD4dPw4E8QGeYn9B8+CDeUEir+e2sUKYgsJ2Evs +HuYFaJeUOLkzCdgFzED1Tdvnc08gVFgFpLULCSpBYxMqxhFUkuLc9Nzi430ihNzi0vz0vWS 83M3MQJTyrZjP7fsYFz56qPeIUYmDsZDjBIczEoivMvXe6cL8aYkVlalFuXHF5XmpBYfYjQF unsis5Rocj4wqeWVxBuaGZgamphZGphamhkrifOyXTmfJiSQnliSmp2aWpBaBNPHxMEp1cBU vD+7do6LvtfUbxtmzCx57tVYPVdLy+8gz/JiZ0HDtZPLbkfVJV9IeZHRH9AuHRI5Sfe+Z+zC +wucGdI7sv4Et8ve9d3xX25C6qOLUQ++fLvxcqrqpdD9E9ZunB0QO6ma9+GGVxWW/qf9Xkb7 SQq6z/zNYP/ZO9muOOjG8iU/1a6mKrsZ2krYPLMSDKi6vD4nun7Nw3yDwjmnGcq52YW21Xec Dlus/cDIc5a58Sfj9k9CEQy23JGGjmt+Hi1S+yX66Pnj2xKmJ4qnHG4zzGXTdn1uohVybnZq 1a3FrT6ndracu7tue4GLfNLvC3daReLln3NcO9Tx8I3R5zVli7c8e7wxabZIV6Cf7vWFVkxK LMUZiYZazEXFiQCORnAisgMAAA== X-CMS-MailID: 20241203134206eucas1p10ca2d7bb12afbd082d5f8a9ad85f94bd X-Msg-Generator: CA X-RootMTR: 20241203134206eucas1p10ca2d7bb12afbd082d5f8a9ad85f94bd X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134206eucas1p10ca2d7bb12afbd082d5f8a9ad85f94bd References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054208_649469_61475F79 X-CRM114-Status: GOOD ( 14.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The DRM Imagination GPU requires a power-domain driver, but the driver for "thead,th1520-aon" is not yet available. To ensure that the 'aon' node and its child 'pd' node are properly recognized and probed by the kernel, add "simple-bus" to the compatible property of the 'aon' node. This change allows the kernel to treat the 'aon' node as a simple bus, enabling the child nodes to be probed and initialized independently. It ensures that the power domain can be managed appropriately until the specific AON driver is developed. This commit introduces some errors while running dtbs_check, as the aon doesn't have the dt-bindings yet. Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 39d39059160d..58f93ad3eb6e 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { compatible = "thead,th1520"; @@ -229,6 +230,16 @@ stmmac_axi_config: stmmac-axi-config { snps,blen = <0 0 64 32 0 0 0>; }; + aon { + compatible = "thead,th1520-aon", "simple-bus"; + + pd: power-domain { + compatible = "thead,th1520-pd"; + thead,vosys-regmap = <&vosys_reg>; + #power-domain-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; From patchwork Tue Dec 3 13:41:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wilczynski X-Patchwork-Id: 13892499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46C76E64A9E for ; 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Tue, 3 Dec 2024 13:42:05 +0000 (GMT) From: Michal Wilczynski To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, frank.binns@imgtec.com, matt.coster@imgtec.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, ulf.hansson@linaro.org, jszhang@kernel.org, m.szyprowski@samsung.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, Michal Wilczynski Subject: [RFC PATCH v1 14/14] riscv: dts: Add GPU node to TH1520 device tree Date: Tue, 3 Dec 2024 14:41:37 +0100 Message-Id: <20241203134137.2114847-15-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241203134137.2114847-1-m.wilczynski@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf1CTdRzH7/s8z55nWzd6GJjfdMRBJ3cSoQjFlzSlu8qn1My6wyv/sBFP g+KHt4ml0AXxQwdT1MXQgfLzxkLmANnip+C2YyoG6nQCAZFJBix2gOwuMojxWPnf6/t+vz/3 +XFfPi5uJNfwk1IPsvJUaXIwKSTMPX/2v2wU7pZttLrC0NV7VRgy/aWlUH1nH4bKbX08NHq7 GUN35t0kujh+k0K/d2YTyKk/R6GcHiOJJrSjJJpRjfKQo62MRHPHbQCZ53JJZLCNUMg4X46h yhkTgWpa2gDKV+p46Nb1t9CEQ4WjfO2zaKmjhUKLzkYClU53UajZdYqH7Ia9KLfrOyI2gHEP 5FGMa2KCYKzHHlFMp6eCYFq1IxSjar0BmKY6JckMOztI5vy1PczPhXaMuVTzDZNr6MEY9+W7 JHOiuQ4wt3PuUcyl3oz3fT8Wbklgk5MOsfINWz8RJi643MSBxWe+0tU/BllgXlAABHxIR8Gs kiZQAIR8Ma0H8IZRQ3kNMf0IwG9toZwxB+BpXf6ywV+psDiiOb0WwJs9lST3cAHYPraEeatJ ehMcqy3neQ1/egqHA/ODKymcfgig+UEZ6U350TthSdEQ8DJBr4PnbIsrLKJj4W/TwzxuwEDY deVH3MuCZX2quIDHZXzhtbMPCC/jy5kcUynubQDp74Uwz9aAc8VvQtP9LMCxH5y0N1McS2Cv WkVwnAbHTLNP8pmwVWV/wpvhcN8C6d0Zp9dDY9sGTn4DapU5PO4UPnDgD19uBB942lyCc7II HssXc+kQWKw6/l/TPr0Z45iBP3kawEkQpH1qGe1Ty2j/71sB8Dqwmk1XpMhYRWQq+2W4Qpqi SE+VhX+altIEln9176J9vgXoJ2fCLQDjAwuAfDzYX1Rr3CETixKkh4+w8rT98vRkVmEBa/lE 8GrRuoRAVkzLpAfZL1j2ACv/18X4gjVZWAw5npy5R22K9OiqPI4GZcogDxktiWyRRZtR2K0+ HFKl+XBG927IZ5c/Oro9MiT+6rZSkTM2Ptr6nr9j1vP2viPmM1vW9jddeG0pu6Px632FqyL4 1ovZuqXNSUPMc67uU8UT1RF+kib3xvCzC2EvadSBZb/MWarPKKdiVlX7Lr3op38n6EKFtT4v UdJQ5KwRZRCS9hfuB1yJuivatd41XTwlid5bF58XFxfwOTa+/+/z2300/duU7A+e0nrDkDa/ Ky7q+SqX5PXqyhL1bLs6raMxc2T40C3HY81kdOjI1lFBN3N999HkXTHWQcP0naCwE8WvOj/Y 9DA37pXYX7vaRgf9M4IJRaI0IhSXK6T/AGsy6TFEBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsVy+t/xe7rrufzTDeY+57Q4cX0Rk8XW37PY LdbsPcdkMf/IOVaLe5e2MFlc+fqezWLd0wvsFi/2NrJYXFsxl92i+dh6NouXs+6xWXzsucdq cXnXHDaLz71HGC22fW5hs1h75C67xfqv85ksFn7cymKxZMcuRou2zmWsFhdPuVq8vNzDbNE2 i9/i/54d7Bb/rm1ksZj9bj+7xZY3E1ktjq8Nt2jZP4XFQdbj/Y1Wdo83L1+yeBzu+MLusffb AhaPnbPusnv07DzD6LFpVSebx51re9g85p0M9LjffZzJY/OSeo+WtceYPN7vu8rm0bdlFaPH pebr7B6bT1cHCEbp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZfx6856l4B93xbI1fxgbGL9ydjFycEgImEgcumzexcjFISSwlFHix9Jeli5GTqC4 jMS17pdQtrDEn2tdbBBFrxglXp+cA5ZgEzCSeLB8PitIQkSgk0Xi7ea1jCAOs8BbRonrMzeC VQkL+EhM77/FCGKzCKhKzD3yD8zmFXCQePbuDivECnmJ/QfPMoPYnEDx11O7wOJCAvYSO/4e ZoWoF5Q4OfMJ2ExmoPrmrbOZJzAKzEKSmoUktYCRaRWjSGppcW56brGRXnFibnFpXrpecn7u JkZgWtl27OeWHYwrX33UO8TIxMF4iFGCg1lJhHf5eu90Id6UxMqq1KL8+KLSnNTiQ4ymQHdP ZJYSTc4HJra8knhDMwNTQxMzSwNTSzNjJXFetivn04QE0hNLUrNTUwtSi2D6mDg4pRqYNmlv imsyitncuSiw/uS3jUEn5/Wtli65ePHAZrdDclxBhg4Fc68G2Ehnvk7lYTQxnLk4ifn0iuMH bvHn5Zd/sv8XNV1fjFFqn9prPr5ZTDYTPF0W83/TtVNdkjmtQmHe5jkbsz81P87eOcPa3yT6 oM8Ocau+Yvc6G9am75ct5PN1Er4z6qRxnpo6ifv15FyTyA/7ijbqWUzo6TtYoXGQb5maxe4V mY415refeZ3bf10v9aZT0859Uttn7zRi3Ls08dprE+27nL//fPsS039LvS7lk2TiDnW9d9MP H536Sb1MSsvhhcf7GYesXKoV+Yu4DNokFqxIV1ZUapA50bArUfuM1uzD63Mrtl9zl+ZTYinO SDTUYi4qTgQACEKcjLQDAAA= X-CMS-MailID: 20241203134207eucas1p29a2d095c527858729ae706d2a9027a5c X-Msg-Generator: CA X-RootMTR: 20241203134207eucas1p29a2d095c527858729ae706d2a9027a5c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20241203134207eucas1p29a2d095c527858729ae706d2a9027a5c References: <20241203134137.2114847-1-m.wilczynski@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241203_054209_953129_FCC1A0E0 X-CRM114-Status: GOOD ( 12.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. This commit is following convention introduced here [1]. Link: https://lore.kernel.org/all/20241118-sets-bxs-4-64-patch-v1-v2-1-3fd45d9fb0cf@imgtec.com/ [1] Signed-off-by: Michal Wilczynski --- arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 58f93ad3eb6e..5023c0c29168 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -500,6 +500,18 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + gpu: gpu@ffef400000 { + compatible = "img,img-bxm-4-64", "img,img-rogue"; + reg = <0xff 0xef400000 0x0 0x100000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&vosys_clk CLK_GPU_CORE>, + <&vosys_clk CLK_GPU_CFG_ACLK>; + clock-names = "core", "sys"; + power-domains = <&pd TH1520_AON_GPU_PD>; + status = "okay"; + }; + vosys_clk: clock-controller { compatible = "thead,th1520-clk-vo"; thead,vosys-regmap = <&vosys_reg>;