From patchwork Thu Dec 5 14:45:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13895458 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14216E7716D for ; Thu, 5 Dec 2024 14:45:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B466410EEA8; Thu, 5 Dec 2024 14:45:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GetfF4Fj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id D87C410EEA2 for ; Thu, 5 Dec 2024 14:45:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733409948; x=1764945948; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9CRhietudlbjjEZ8syYEmiovY9PyJCbP7FtiaA/3lUY=; b=GetfF4Fj70pa8uoBeUWaFCy0lOPmmzYlf4X3BRwOAwoqgG55wwqAvpg8 TsqnEaY21JvJMlVT0q1s2hwt+NLq8O8MEkKlBz+IrSrjtXhBrN9KPsKT5 CkKUJ0003x6VqS5YHbYf4VyB/XfHr+4lQvHU/rLPwUaV3UPjDG4ghWRCa 0WhDSQKxH5IgtRNGnCfBlJKJcZH7BCLXtDAuMP1QDEFj/fY+Hh05dGdlO AXDHes8erfQ1mjr/zp7/yZDT1jgDFmOYUJ8TFJYTc2Wymh1NvZJM25FHA qFbqvHkJIUELwDB/c3bKT9tr4ucGQUasD+kJz7JLYOzShiFfgKjIk3AOh w==; X-CSE-ConnectionGUID: bgL/FraSRW6ylWKebh8qvw== X-CSE-MsgGUID: k/a1/ZmjTua7rXlNjnIMFg== X-IronPort-AV: E=McAfee;i="6700,10204,11277"; a="33640781" X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="33640781" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:47 -0800 X-CSE-ConnectionGUID: 4WQsVZESSSyABV1+aHm5nw== X-CSE-MsgGUID: VyBdEab5RzKlEDETwXGwfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="94589145" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:47 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 1/5] drm/i915/dsi: fix PIX_FMT_MASK width Date: Thu, 5 Dec 2024 16:45:35 +0200 Message-Id: <0e1a433b3842d38df4334cf8e896c4b2f0a96f35.1733409899.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It's really bits 18:16 not 17:16. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h index d4845ac65acc..0cb9a5f714d2 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -203,7 +203,7 @@ #define VIDEO_MODE_SYNC_PULSE (0x3 << 28) #define TE_SOURCE_GPIO (1 << 27) #define LINK_READY (1 << 20) -#define PIX_FMT_MASK (0x3 << 16) +#define PIX_FMT_MASK (0x7 << 16) #define PIX_FMT_SHIFT 16 #define PIX_FMT_RGB565 (0x0 << 16) #define PIX_FMT_RGB666_PACKED (0x1 << 16) From patchwork Thu Dec 5 14:45:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13895459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BA3BE7716D for ; Thu, 5 Dec 2024 14:45:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0DAA10EEA2; Thu, 5 Dec 2024 14:45:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="V4U7kX1h"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7CDB010EEA2 for ; Thu, 5 Dec 2024 14:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733409951; x=1764945951; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1F7O8STaIOcKK2tVjUXgla8VLecXRq7G+LmEQD+Rz08=; b=V4U7kX1huGnG2tpzi9MkpOmzXMgxAtuMGCJ7tBmlwxFgu3irsmweU3OM 2oFWI5ZQy9slpUFPGopOTcGPTSBwXQzDtiQyjPycnZeD0J3GvJjl8tCSw 4d+HfdBCpH2t9kvLQLAN967NExJmKRE9hQVHaVfoZH9ZySfUm+vC8E+YR 8l7Bj3LnFojIJd2DBnxzApU98Rriwu2MdpCEuNqiQoo9nz0AFnPMrYqoD QJxlBFPEz/KPj+B2vCwWJgGUl3LoKLy4guQx3MKwqgrh2v20GV39PfcnI vExiYwJSbfauEWq4PA7l12zRXRmNCeSUS9YJ6VD9+OMkXwRJpe9ZC5OmZ w==; X-CSE-ConnectionGUID: Q757K7uITs6I6HGuMxslkg== X-CSE-MsgGUID: L1QPjdRRT3eVK/YkAMkOMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11277"; a="51139176" X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="51139176" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:51 -0800 X-CSE-ConnectionGUID: x390VukTSAKUt1a+rsx0pA== X-CSE-MsgGUID: jvQLKxoORRaF5oMLHRPYwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="117357066" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:50 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 2/5] drm/i915/dsi: convert DSI_TRANS_FUNC_CONF to REG_BIT() and friends Date: Thu, 5 Dec 2024 16:45:36 +0200 Message-Id: <7893f23b3e664065262e84565b939fee7d795ac2.1733409899.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The register definition is a nightmare to update. Convert to the modern style. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi_regs.h | 74 ++++++++++----------- 1 file changed, 34 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h index 0cb9a5f714d2..88df1da8ccfd 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -195,46 +195,40 @@ #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ _DSI_TRANS_FUNC_CONF_0,\ _DSI_TRANS_FUNC_CONF_1) -#define OP_MODE_MASK (0x3 << 28) -#define OP_MODE_SHIFT 28 -#define CMD_MODE_NO_GATE (0x0 << 28) -#define CMD_MODE_TE_GATE (0x1 << 28) -#define VIDEO_MODE_SYNC_EVENT (0x2 << 28) -#define VIDEO_MODE_SYNC_PULSE (0x3 << 28) -#define TE_SOURCE_GPIO (1 << 27) -#define LINK_READY (1 << 20) -#define PIX_FMT_MASK (0x7 << 16) -#define PIX_FMT_SHIFT 16 -#define PIX_FMT_RGB565 (0x0 << 16) -#define PIX_FMT_RGB666_PACKED (0x1 << 16) -#define PIX_FMT_RGB666_LOOSE (0x2 << 16) -#define PIX_FMT_RGB888 (0x3 << 16) -#define PIX_FMT_RGB101010 (0x4 << 16) -#define PIX_FMT_RGB121212 (0x5 << 16) -#define PIX_FMT_COMPRESSED (0x6 << 16) -#define BGR_TRANSMISSION (1 << 15) -#define PIX_VIRT_CHAN(x) ((x) << 12) -#define PIX_VIRT_CHAN_MASK (0x3 << 12) -#define PIX_VIRT_CHAN_SHIFT 12 -#define PIX_BUF_THRESHOLD_MASK (0x3 << 10) -#define PIX_BUF_THRESHOLD_SHIFT 10 -#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) -#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) -#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) -#define PIX_BUF_THRESHOLD_FULL (0x3 << 10) -#define CONTINUOUS_CLK_MASK (0x3 << 8) -#define CONTINUOUS_CLK_SHIFT 8 -#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) -#define CLK_HS_OR_LP (0x2 << 8) -#define CLK_HS_CONTINUOUS (0x3 << 8) -#define LINK_CALIBRATION_MASK (0x3 << 4) -#define LINK_CALIBRATION_SHIFT 4 -#define CALIBRATION_DISABLED (0x0 << 4) -#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) -#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) -#define BLANKING_PACKET_ENABLE (1 << 2) -#define S3D_ORIENTATION_LANDSCAPE (1 << 1) -#define EOTP_DISABLED (1 << 0) +#define OP_MODE_MASK REG_GENMASK(29, 28) +#define CMD_MODE_NO_GATE REG_FIELD_PREP(OP_MODE_MASK, 0) +#define CMD_MODE_TE_GATE REG_FIELD_PREP(OP_MODE_MASK, 1) +#define VIDEO_MODE_SYNC_EVENT REG_FIELD_PREP(OP_MODE_MASK, 2) +#define VIDEO_MODE_SYNC_PULSE REG_FIELD_PREP(OP_MODE_MASK, 3) +#define TE_SOURCE_GPIO REG_BIT(27) +#define LINK_READY REG_BIT(20) +#define PIX_FMT_MASK REG_GENMASK(18, 16) +#define PIX_FMT_RGB565 REG_FIELD_PREP(PIX_FMT_MASK, 0) +#define PIX_FMT_RGB666_PACKED REG_FIELD_PREP(PIX_FMT_MASK, 1) +#define PIX_FMT_RGB666_LOOSE REG_FIELD_PREP(PIX_FMT_MASK, 2) +#define PIX_FMT_RGB888 REG_FIELD_PREP(PIX_FMT_MASK, 3) +#define PIX_FMT_RGB101010 REG_FIELD_PREP(PIX_FMT_MASK, 4) +#define PIX_FMT_RGB121212 REG_FIELD_PREP(PIX_FMT_MASK, 5) +#define PIX_FMT_COMPRESSED REG_FIELD_PREP(PIX_FMT_MASK, 6) +#define BGR_TRANSMISSION REG_BIT(15) +#define PIX_VIRT_CHAN_MASK REG_GENMASK(13, 12) +#define PIX_VIRT_CHAN(x) REG_FIELD_PREP(PIX_VIRT_CHAN_MASK, (x)) +#define PIX_BUF_THRESHOLD_MASK REG_GENMASK(11, 10) +#define PIX_BUF_THRESHOLD_1_4 REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 0) +#define PIX_BUF_THRESHOLD_1_2 REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 1) +#define PIX_BUF_THRESHOLD_3_4 REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 2) +#define PIX_BUF_THRESHOLD_FULL REG_FIELD_PREP(PIX_BUF_THRESHOLD_MASK, 3) +#define CONTINUOUS_CLK_MASK REG_GENMASK(9, 8) +#define CLK_ENTER_LP_AFTER_DATA REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 0) +#define CLK_HS_OR_LP REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 2) +#define CLK_HS_CONTINUOUS REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 3) +#define LINK_CALIBRATION_MASK REG_GENMASK(5, 4) +#define CALIBRATION_DISABLED REG_FIELD_PREP(LINK_CALIBRATION_MASK, 0) +#define CALIBRATION_ENABLED_INITIAL_ONLY REG_FIELD_PREP(LINK_CALIBRATION_MASK, 2) +#define CALIBRATION_ENABLED_INITIAL_PERIODIC REG_FIELD_PREP(LINK_CALIBRATION_MASK, 3) +#define BLANKING_PACKET_ENABLE REG_BIT(2) +#define S3D_ORIENTATION_LANDSCAPE REG_BIT(1) +#define EOTP_DISABLED REG_BIT(0) #define _DSI_CMD_RXCTL_0 0x6b0d4 #define _DSI_CMD_RXCTL_1 0x6b8d4 From patchwork Thu Dec 5 14:45:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13895460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE79FE7716D for ; Thu, 5 Dec 2024 14:45:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BCBE10EEA3; Thu, 5 Dec 2024 14:45:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EB/DkhgC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id E84CB10EEA3 for ; Thu, 5 Dec 2024 14:45:54 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="94589170" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:54 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 3/5] drm/i915/dsi: add LP_CLOCK_DURING_LPM bit for DSI_TRANS_FUNC_CONF Date: Thu, 5 Dec 2024 16:45:37 +0200 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We're missing the definition for LP_CLOCK_DURING_LPM. Add it. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h index 88df1da8ccfd..d47a799aad75 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -222,6 +222,7 @@ #define CLK_ENTER_LP_AFTER_DATA REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 0) #define CLK_HS_OR_LP REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 2) #define CLK_HS_CONTINUOUS REG_FIELD_PREP(CONTINUOUS_CLK_MASK, 3) +#define LP_CLOCK_DURING_LPM REG_BIT(7) #define LINK_CALIBRATION_MASK REG_GENMASK(5, 4) #define CALIBRATION_DISABLED REG_FIELD_PREP(LINK_CALIBRATION_MASK, 0) #define CALIBRATION_ENABLED_INITIAL_ONLY REG_FIELD_PREP(LINK_CALIBRATION_MASK, 2) From patchwork Thu Dec 5 14:45:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13895461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19A71E77170 for ; Thu, 5 Dec 2024 14:45:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7F4710EEA5; Thu, 5 Dec 2024 14:45:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LCVzaReU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5435810EEA5 for ; Thu, 5 Dec 2024 14:45:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733409958; x=1764945958; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aOKe7bXuMm8Q40nBvreVtcNPs51v/ZUtUzRxvHat8NM=; b=LCVzaReUD4qHOFGhYr+BvoH2qxWK4bKlKBR4vJP1AiaY0lA9JdORqm0e J8uAT/+1QALaCMYp7xMDTdBMlLuotTeLEB20/veu47wnD4YcZk96SY0Ng ghu0hbWy/saUcII/F7FSidEysMXpme/YjnYmR2ilQOm9nmtUKP2/WP/sm gkA+VWavu6Rzlvhl68D8HLAYQn2WSzXLlkp+5+5f5ryUkUwIlLxeqndo0 k6SkJBIiOZ/eHWKxRH5Fr5pzDRsOy+ca/0OjWqYucYGiDcAnjz7dHD5yq mpuS0l9NX/gvBip1SsmTRyAPatQ9wo6VyHxkfpVgflVf+gVi7Ec5gQEN1 w==; X-CSE-ConnectionGUID: xjaJdtW9QGmIlTK2NkzHNw== X-CSE-MsgGUID: vbPyn8W4TBG8SfHDq422sg== X-IronPort-AV: E=McAfee;i="6700,10204,11277"; a="33640812" X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="33640812" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:58 -0800 X-CSE-ConnectionGUID: wSEQhVzIQMO7O0WOmcKsmg== X-CSE-MsgGUID: Onl38grzS7emVYwQXT/++g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="94589177" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:45:57 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 4/5] drm/i915/vbt: define a few more DSI dphy config bits Date: Thu, 5 Dec 2024 16:45:38 +0200 Message-Id: <758f56bbf5677770a128d3390fbd9cfd526d7e7a.1733409899.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We're missing Blanking Packets During BLLP and LP Clock During LPM. Add them. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index f9841f0498c6..a8ef7f9a5503 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -157,7 +157,9 @@ struct mipi_config { u16 dphy_param_valid:1; u16 eot_pkt_disabled:1; u16 enable_clk_stop:1; - u16 rsvd7:13; + u16 blanking_packets_during_bllp:1; /* 219+ */ + u16 lp_clock_during_lpm:1; /* 219+ */ + u16 rsvd7:11; u32 hs_tx_timeout; u32 lp_rx_timeout; From patchwork Thu Dec 5 14:45:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13895462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A60DE7716D for ; Thu, 5 Dec 2024 14:46:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0216110EEA6; Thu, 5 Dec 2024 14:46:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lAS62QIH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D7E710EEA6 for ; Thu, 5 Dec 2024 14:46:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733409962; x=1764945962; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PBGWuH4xl5O4tGZdFcVYt0IaZhwDYWtjAeUVd4vsXsQ=; b=lAS62QIHCJKHWbiRYY442C1E80Xsdl2amnMb0Mk1T7nEMPzhbsIuXkiS H6Y/yPaLuY+Dc3i27jdb/0kmep6bxMqhTbFkntc8lq4w530aFok77wx1V XdgLcXD/iKcZSsxUK6W8nETa5Th+J3Vg5iupcTRhEBX85GLEp6mVjCSKg qUgShxA4LBU/f0l6Qpniv0kXOBTDKp8AQ/WMh5lYOPefcA0A6gBoTJnay YIADE1LiPtffTXOIpvUfW1xf71GAxXpCbJb6xet1+893AW6rSVSoXhVZv 0Ezn3pFW7QsxKipSC0IlJSEVC5OgXSlIdDgG8JHcHxjdrv/qhPQlsFA1b g==; X-CSE-ConnectionGUID: N3QyDMNHQtay0VFL4OQ0tw== X-CSE-MsgGUID: zY0IXaL9QPmTIhTsnY5hXw== X-IronPort-AV: E=McAfee;i="6700,10204,11277"; a="51139205" X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="51139205" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:46:02 -0800 X-CSE-ConnectionGUID: elWuA6PVSXWJ2I7Fl7F9Uw== X-CSE-MsgGUID: jlgC7resRZarAJZ/HSNKmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,210,1728975600"; d="scan'208";a="117357096" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2024 06:46:01 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 5/5] drm/i915/dsi: set a few DSI_TRANS_FUNC_CONF bits according to VBT Date: Thu, 5 Dec 2024 16:45:39 +0200 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set the relevant DSI_TRANS_FUNC_CONF bits according to VBT DSI DPHY config. The DSI VBT usage is a nightmare, but that's for another time. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_dsi.h | 2 ++ drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 ++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 74ab3d1a1622..bc94bcf5156c 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -704,6 +704,16 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, else tmp |= EOTP_DISABLED; + if (is_vid_mode(intel_dsi) && intel_dsi->blanking_packets_during_bllp) + tmp |= BLANKING_PACKET_ENABLE; + else + tmp &= BLANKING_PACKET_ENABLE; + + if (intel_dsi->lp_clock_during_lpm) + tmp |= LP_CLOCK_DURING_LPM; + else + tmp &= LP_CLOCK_DURING_LPM; + /* enable link calibration if freq > 1.5Gbps */ if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { tmp &= ~LINK_CALIBRATION_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h index e8ba4ccd99d3..58fb0fe48638 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.h +++ b/drivers/gpu/drm/i915/display/intel_dsi.h @@ -82,6 +82,8 @@ struct intel_dsi { /* eot for MIPI_EOT_DISABLE register */ u8 eotp_pkt; u8 clock_stop; + bool blanking_packets_during_bllp; + bool lp_clock_during_lpm; u8 escape_clk_div; u8 dual_link; diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index b2b78f39cfd3..29de72efeed0 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -777,6 +777,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; + intel_dsi->blanking_packets_during_bllp = mipi_config->blanking_packets_during_bllp; + intel_dsi->lp_clock_during_lpm = mipi_config->lp_clock_during_lpm; intel_dsi->lane_count = mipi_config->lane_cnt + 1; intel_dsi->pixel_format = vbt_to_dsi_pixel_format(mipi_config->videomode_color_format);