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Add dw_pcie_stop_link() into dw_pcie_suspend_noirq() to fix this issue and keep symmetric in suspend/resume function since there is dw_pcie_start_link() in dw_pcie_resume_noirq(). Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume functionality") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-host.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f882b11fd7b94..f56cb7b9e6f99 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1001,6 +1001,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) return ret; } + dw_pcie_stop_link(pci); if (pci->pp.ops->deinit) pci->pp.ops->deinit(&pci->pp); From patchwork Tue Dec 10 08:15:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 13901019 Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2052.outbound.protection.outlook.com [40.107.104.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C407F230986 for ; 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Received: from AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) by PA1PR04MB10865.eurprd04.prod.outlook.com (2603:10a6:102:48a::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.18; Tue, 10 Dec 2024 08:16:49 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%5]) with mapi id 15.20.8230.016; Tue, 10 Dec 2024 08:16:49 +0000 From: Richard Zhu To: dlemoal@kernel.org, jingoohan1@gmail.com, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, frank.li@nxp.com, quic_krichai@quicinc.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu , Frank Li Subject: [PATCH v4 2/2] PCI: dwc: Clean up some unnecessary codes in dw_pcie_suspend_noirq() Date: Tue, 10 Dec 2024 16:15:57 +0800 Message-Id: <20241210081557.163555-3-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241210081557.163555-1-hongxing.zhu@nxp.com> References: <20241210081557.163555-1-hongxing.zhu@nxp.com> X-ClientProxiedBy: SI2PR02CA0050.apcprd02.prod.outlook.com (2603:1096:4:196::11) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|PA1PR04MB10865:EE_ X-MS-Office365-Filtering-Correlation-Id: bc8a9ec7-4a1c-4d78-1b54-08dd18f2febe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|376014|7416014|38350700014; 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Since it's safe to send PME_TURN_OFF message regardless of whether the link is up or down. So, there would be no need to test the LTSSM state before sending PME_TURN_OFF message. Only print the message when ltssm_stat is not in DETECT and POLL. In the other words, there isn't an error message when no endpoint is connected at all. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- .../pci/controller/dwc/pcie-designware-host.c | 27 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f56cb7b9e6f99..bdb9c1ad6cdd5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -973,7 +973,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; - int ret = 0; + int ret; /* * If L1SS is supported, then do not put the link into L2 as some @@ -982,25 +982,32 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) return 0; - if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) - return 0; - - if (pci->pp.ops->pme_turn_off) + if (pci->pp.ops->pme_turn_off) { pci->pp.ops->pme_turn_off(&pci->pp); - else + } else { ret = dw_pcie_pme_turn_off(pci); + if (ret) + return ret; + } - if (ret) - return ret; - - ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, + ret = read_poll_timeout(dw_pcie_get_ltssm, val, + val == DW_PCIE_LTSSM_L2_IDLE || + val <= DW_PCIE_LTSSM_DETECT_WAIT, PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US, false, pci); if (ret) { + /* Only dump message when ltssm_stat isn't in DETECT and POLL */ dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); return ret; } + /* + * Refer to r6.0, sec 5.3.3.2.1, software should wait at least + * 100ns after L2/L3 Ready before turning off refclock and + * main power. It's harmless too when no endpoint connected. + */ + udelay(1); + dw_pcie_stop_link(pci); if (pci->pp.ops->deinit) pci->pp.ops->deinit(&pci->pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5c14ed2cb91ed..7efcb4af66da3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -330,6 +330,7 @@ enum dw_pcie_ltssm { /* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */ DW_PCIE_LTSSM_DETECT_QUIET = 0x0, DW_PCIE_LTSSM_DETECT_ACT = 0x1, + DW_PCIE_LTSSM_DETECT_WAIT = 0x6, DW_PCIE_LTSSM_L0 = 0x11, DW_PCIE_LTSSM_L2_IDLE = 0x15,