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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/72] hw/net/lan9118: Extract lan9118_phy Date: Wed, 11 Dec 2024 16:18:53 +0000 Message-Id: <20241211162004.2795499-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow A very similar implementation of the same device exists in imx_fec. Prepare for a common implementation by extracting a device model into its own files. Some migration state has been moved into the new device model which breaks migration compatibility for the following machines: * smdkc210 * realview-* * vexpress-* * kzm * mps2-* While breaking migration ABI, fix the size of the MII registers to be 16 bit, as defined by IEEE 802.3u. Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter Maydell Message-id: 20241102125724.532843-2-shentey@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/lan9118_phy.h | 37 ++++++++ hw/net/lan9118.c | 137 +++++----------------------- hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ hw/net/Kconfig | 4 + hw/net/meson.build | 1 + 5 files changed, 233 insertions(+), 115 deletions(-) create mode 100644 include/hw/net/lan9118_phy.h create mode 100644 hw/net/lan9118_phy.c diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h new file mode 100644 index 00000000000..af12fc33d5f --- /dev/null +++ b/include/hw/net/lan9118_phy.h @@ -0,0 +1,37 @@ +/* + * SMSC LAN9118 PHY emulation + * + * Copyright (c) 2009 CodeSourcery, LLC. + * Written by Paul Brook + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_NET_LAN9118_PHY_H +#define HW_NET_LAN9118_PHY_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +#define TYPE_LAN9118_PHY "lan9118-phy" +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) + +typedef struct Lan9118PhyState { + SysBusDevice parent_obj; + + uint16_t status; + uint16_t control; + uint16_t advertise; + uint16_t ints; + uint16_t int_mask; + qemu_irq irq; + bool link_down; +} Lan9118PhyState; + +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); +void lan9118_phy_reset(Lan9118PhyState *s); +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); + +#endif diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index db28a0ef306..99e87b7178c 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -16,6 +16,7 @@ #include "net/net.h" #include "net/eth.h" #include "hw/irq.h" +#include "hw/net/lan9118_phy.h" #include "hw/net/lan9118.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" @@ -139,14 +140,6 @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) #define MAC_CR_RXEN 0x00000004 #define MAC_CR_RESERVED 0x7f404213 -#define PHY_INT_ENERGYON 0x80 -#define PHY_INT_AUTONEG_COMPLETE 0x40 -#define PHY_INT_FAULT 0x20 -#define PHY_INT_DOWN 0x10 -#define PHY_INT_AUTONEG_LP 0x08 -#define PHY_INT_PARFAULT 0x04 -#define PHY_INT_AUTONEG_PAGE 0x02 - #define GPT_TIMER_EN 0x20000000 /* @@ -228,11 +221,8 @@ struct lan9118_state { uint32_t mac_mii_data; uint32_t mac_flow; - uint32_t phy_status; - uint32_t phy_control; - uint32_t phy_advertise; - uint32_t phy_int; - uint32_t phy_int_mask; + Lan9118PhyState mii; + IRQState mii_irq; int32_t eeprom_writable; uint8_t eeprom[128]; @@ -274,8 +264,8 @@ struct lan9118_state { static const VMStateDescription vmstate_lan9118 = { .name = "lan9118", - .version_id = 2, - .minimum_version_id = 1, + .version_id = 3, + .minimum_version_id = 3, .fields = (const VMStateField[]) { VMSTATE_PTIMER(timer, lan9118_state), VMSTATE_UINT32(irq_cfg, lan9118_state), @@ -301,11 +291,6 @@ static const VMStateDescription vmstate_lan9118 = { VMSTATE_UINT32(mac_mii_acc, lan9118_state), VMSTATE_UINT32(mac_mii_data, lan9118_state), VMSTATE_UINT32(mac_flow, lan9118_state), - VMSTATE_UINT32(phy_status, lan9118_state), - VMSTATE_UINT32(phy_control, lan9118_state), - VMSTATE_UINT32(phy_advertise, lan9118_state), - VMSTATE_UINT32(phy_int, lan9118_state), - VMSTATE_UINT32(phy_int_mask, lan9118_state), VMSTATE_INT32(eeprom_writable, lan9118_state), VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), VMSTATE_INT32(tx_fifo_size, lan9118_state), @@ -385,9 +370,11 @@ static void lan9118_reload_eeprom(lan9118_state *s) lan9118_mac_changed(s); } -static void phy_update_irq(lan9118_state *s) +static void lan9118_update_irq(void *opaque, int n, int level) { - if (s->phy_int & s->phy_int_mask) { + lan9118_state *s = opaque; + + if (level) { s->int_sts |= PHY_INT; } else { s->int_sts &= ~PHY_INT; @@ -395,33 +382,10 @@ static void phy_update_irq(lan9118_state *s) lan9118_update(s); } -static void phy_update_link(lan9118_state *s) -{ - /* Autonegotiation status mirrors link status. */ - if (qemu_get_queue(s->nic)->link_down) { - s->phy_status &= ~0x0024; - s->phy_int |= PHY_INT_DOWN; - } else { - s->phy_status |= 0x0024; - s->phy_int |= PHY_INT_ENERGYON; - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; - } - phy_update_irq(s); -} - static void lan9118_set_link(NetClientState *nc) { - phy_update_link(qemu_get_nic_opaque(nc)); -} - -static void phy_reset(lan9118_state *s) -{ - s->phy_status = 0x7809; - s->phy_control = 0x3000; - s->phy_advertise = 0x01e1; - s->phy_int_mask = 0; - s->phy_int = 0; - phy_update_link(s); + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, + nc->link_down); } static void lan9118_reset(DeviceState *d) @@ -478,8 +442,6 @@ static void lan9118_reset(DeviceState *d) s->read_word_n = 0; s->write_word_n = 0; - phy_reset(s); - s->eeprom_writable = 0; lan9118_reload_eeprom(s); } @@ -678,7 +640,7 @@ static void do_tx_packet(lan9118_state *s) uint32_t status; /* FIXME: Honor TX disable, and allow queueing of packets. */ - if (s->phy_control & 0x4000) { + if (s->mii.control & 0x4000) { /* This assumes the receive routine doesn't touch the VLANClient. */ qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); } else { @@ -834,68 +796,6 @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) } } -static uint32_t do_phy_read(lan9118_state *s, int reg) -{ - uint32_t val; - - switch (reg) { - case 0: /* Basic Control */ - return s->phy_control; - case 1: /* Basic Status */ - return s->phy_status; - case 2: /* ID1 */ - return 0x0007; - case 3: /* ID2 */ - return 0xc0d1; - case 4: /* Auto-neg advertisement */ - return s->phy_advertise; - case 5: /* Auto-neg Link Partner Ability */ - return 0x0f71; - case 6: /* Auto-neg Expansion */ - return 1; - /* TODO 17, 18, 27, 29, 30, 31 */ - case 29: /* Interrupt source. */ - val = s->phy_int; - s->phy_int = 0; - phy_update_irq(s); - return val; - case 30: /* Interrupt mask */ - return s->phy_int_mask; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "do_phy_read: PHY read reg %d\n", reg); - return 0; - } -} - -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) -{ - switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { - phy_reset(s); - break; - } - s->phy_control = val & 0x7980; - /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->phy_status |= 0x0020; - } - break; - case 4: /* Auto-neg advertisement */ - s->phy_advertise = (val & 0x2d7f) | 0x80; - break; - /* TODO 17, 18, 27, 31 */ - case 30: /* Interrupt mask */ - s->phy_int_mask = val & 0xff; - phy_update_irq(s); - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); - } -} - static void do_mac_write(lan9118_state *s, int reg, uint32_t val) { switch (reg) { @@ -929,9 +829,9 @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) if (val & 2) { DPRINTF("PHY write %d = 0x%04x\n", (val >> 6) & 0x1f, s->mac_mii_data); - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); } else { - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); DPRINTF("PHY read %d = 0x%04x\n", (val >> 6) & 0x1f, s->mac_mii_data); } @@ -1126,7 +1026,7 @@ static void lan9118_writel(void *opaque, hwaddr offset, break; case CSR_PMT_CTRL: if (val & 0x400) { - phy_reset(s); + lan9118_phy_reset(&s->mii); } s->pmt_ctrl &= ~0x34e; s->pmt_ctrl |= (val & 0x34e); @@ -1373,6 +1273,13 @@ static void lan9118_realize(DeviceState *dev, Error **errp) const MemoryRegionOps *mem_ops = s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); + memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, "lan9118-mmio", 0x100); sysbus_init_mmio(sbd, &s->mmio); diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c new file mode 100644 index 00000000000..b22c3c28556 --- /dev/null +++ b/hw/net/lan9118_phy.c @@ -0,0 +1,169 @@ +/* + * SMSC LAN9118 PHY emulation + * + * Copyright (c) 2009 CodeSourcery, LLC. + * Written by Paul Brook + * + * This code is licensed under the GNU GPL v2 + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "qemu/osdep.h" +#include "hw/net/lan9118_phy.h" +#include "hw/irq.h" +#include "hw/resettable.h" +#include "migration/vmstate.h" +#include "qemu/log.h" + +#define PHY_INT_ENERGYON (1 << 7) +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) +#define PHY_INT_FAULT (1 << 5) +#define PHY_INT_DOWN (1 << 4) +#define PHY_INT_AUTONEG_LP (1 << 3) +#define PHY_INT_PARFAULT (1 << 2) +#define PHY_INT_AUTONEG_PAGE (1 << 1) + +static void lan9118_phy_update_irq(Lan9118PhyState *s) +{ + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); +} + +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) +{ + uint16_t val; + + switch (reg) { + case 0: /* Basic Control */ + return s->control; + case 1: /* Basic Status */ + return s->status; + case 2: /* ID1 */ + return 0x0007; + case 3: /* ID2 */ + return 0xc0d1; + case 4: /* Auto-neg advertisement */ + return s->advertise; + case 5: /* Auto-neg Link Partner Ability */ + return 0x0f71; + case 6: /* Auto-neg Expansion */ + return 1; + /* TODO 17, 18, 27, 29, 30, 31 */ + case 29: /* Interrupt source. */ + val = s->ints; + s->ints = 0; + lan9118_phy_update_irq(s); + return val; + case 30: /* Interrupt mask */ + return s->int_mask; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "lan9118_phy_read: PHY read reg %d\n", reg); + return 0; + } +} + +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) +{ + switch (reg) { + case 0: /* Basic Control */ + if (val & 0x8000) { + lan9118_phy_reset(s); + break; + } + s->control = val & 0x7980; + /* Complete autonegotiation immediately. */ + if (val & 0x1000) { + s->status |= 0x0020; + } + break; + case 4: /* Auto-neg advertisement */ + s->advertise = (val & 0x2d7f) | 0x80; + break; + /* TODO 17, 18, 27, 31 */ + case 30: /* Interrupt mask */ + s->int_mask = val & 0xff; + lan9118_phy_update_irq(s); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); + } +} + +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) +{ + s->link_down = link_down; + + /* Autonegotiation status mirrors link status. */ + if (link_down) { + s->status &= ~0x0024; + s->ints |= PHY_INT_DOWN; + } else { + s->status |= 0x0024; + s->ints |= PHY_INT_ENERGYON; + s->ints |= PHY_INT_AUTONEG_COMPLETE; + } + lan9118_phy_update_irq(s); +} + +void lan9118_phy_reset(Lan9118PhyState *s) +{ + s->control = 0x3000; + s->status = 0x7809; + s->advertise = 0x01e1; + s->int_mask = 0; + s->ints = 0; + lan9118_phy_update_link(s, s->link_down); +} + +static void lan9118_phy_reset_hold(Object *obj, ResetType type) +{ + Lan9118PhyState *s = LAN9118_PHY(obj); + + lan9118_phy_reset(s); +} + +static void lan9118_phy_init(Object *obj) +{ + Lan9118PhyState *s = LAN9118_PHY(obj); + + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); +} + +static const VMStateDescription vmstate_lan9118_phy = { + .name = "lan9118-phy", + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_UINT16(control, Lan9118PhyState), + VMSTATE_UINT16(status, Lan9118PhyState), + VMSTATE_UINT16(advertise, Lan9118PhyState), + VMSTATE_UINT16(ints, Lan9118PhyState), + VMSTATE_UINT16(int_mask, Lan9118PhyState), + VMSTATE_BOOL(link_down, Lan9118PhyState), + VMSTATE_END_OF_LIST() + } +}; + +static void lan9118_phy_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + rc->phases.hold = lan9118_phy_reset_hold; + dc->vmsd = &vmstate_lan9118_phy; +} + +static const TypeInfo types[] = { + { + .name = TYPE_LAN9118_PHY, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Lan9118PhyState), + .instance_init = lan9118_phy_init, + .class_init = lan9118_phy_class_init, + } +}; + +DEFINE_TYPES(types) diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 7fcc0d7faa2..6b2ff2f937a 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -62,8 +62,12 @@ config VMXNET3_PCI config SMC91C111 bool +config LAN9118_PHY + bool + config LAN9118 bool + select LAN9118_PHY select PTIMER config NE2000_ISA diff --git a/hw/net/meson.build b/hw/net/meson.build index 00a9e9dd515..3bb5d749a83 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -19,6 +19,7 @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) From patchwork Wed Dec 11 16:18:54 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations Date: Wed, 11 Dec 2024 16:18:54 +0000 Message-Id: <20241211162004.2795499-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow imx_fec models the same PHY as lan9118_phy. The code is almost the same with imx_fec having more logging and tracing. Merge these improvements into lan9118_phy and reuse in imx_fec to fix the code duplication. Some migration state how resides in the new device model which breaks migration compatibility for the following machines: * imx25-pdk * sabrelite * mcimx7d-sabre * mcimx6ul-evk Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter Maydell Message-id: 20241102125724.532843-3-shentey@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/imx_fec.h | 9 ++- hw/net/imx_fec.c | 146 ++++----------------------------------- hw/net/lan9118_phy.c | 82 ++++++++++++++++------ hw/net/Kconfig | 1 + hw/net/trace-events | 10 +-- 5 files changed, 85 insertions(+), 163 deletions(-) diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 2d13290c787..83b21637eeb 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -31,6 +31,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) #define TYPE_IMX_ENET "imx.enet" #include "hw/sysbus.h" +#include "hw/net/lan9118_phy.h" +#include "hw/irq.h" #include "net/net.h" #define ENET_EIR 1 @@ -264,11 +266,8 @@ struct IMXFECState { uint32_t tx_descriptor[ENET_TX_RING_NUM]; uint32_t tx_ring_num; - uint32_t phy_status; - uint32_t phy_control; - uint32_t phy_advertise; - uint32_t phy_int; - uint32_t phy_int_mask; + Lan9118PhyState mii; + IRQState mii_irq; uint32_t phy_num; bool phy_connected; struct IMXFECState *phy_consumer; diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 6294d292023..4ee6f742063 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -203,17 +203,12 @@ static const VMStateDescription vmstate_imx_eth_txdescs = { static const VMStateDescription vmstate_imx_eth = { .name = TYPE_IMX_FEC, - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), VMSTATE_UINT32(rx_descriptor, IMXFECState), VMSTATE_UINT32(tx_descriptor[0], IMXFECState), - VMSTATE_UINT32(phy_status, IMXFECState), - VMSTATE_UINT32(phy_control, IMXFECState), - VMSTATE_UINT32(phy_advertise, IMXFECState), - VMSTATE_UINT32(phy_int, IMXFECState), - VMSTATE_UINT32(phy_int_mask, IMXFECState), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription * const []) { @@ -222,14 +217,6 @@ static const VMStateDescription vmstate_imx_eth = { }, }; -#define PHY_INT_ENERGYON (1 << 7) -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) -#define PHY_INT_FAULT (1 << 5) -#define PHY_INT_DOWN (1 << 4) -#define PHY_INT_AUTONEG_LP (1 << 3) -#define PHY_INT_PARFAULT (1 << 2) -#define PHY_INT_AUTONEG_PAGE (1 << 1) - static void imx_eth_update(IMXFECState *s); /* @@ -238,47 +225,19 @@ static void imx_eth_update(IMXFECState *s); * For now we don't handle any GPIO/interrupt line, so the OS will * have to poll for the PHY status. */ -static void imx_phy_update_irq(IMXFECState *s) +static void imx_phy_update_irq(void *opaque, int n, int level) { - imx_eth_update(s); -} - -static void imx_phy_update_link(IMXFECState *s) -{ - /* Autonegotiation status mirrors link status. */ - if (qemu_get_queue(s->nic)->link_down) { - trace_imx_phy_update_link("down"); - s->phy_status &= ~0x0024; - s->phy_int |= PHY_INT_DOWN; - } else { - trace_imx_phy_update_link("up"); - s->phy_status |= 0x0024; - s->phy_int |= PHY_INT_ENERGYON; - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; - } - imx_phy_update_irq(s); + imx_eth_update(opaque); } static void imx_eth_set_link(NetClientState *nc) { - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); -} - -static void imx_phy_reset(IMXFECState *s) -{ - trace_imx_phy_reset(); - - s->phy_status = 0x7809; - s->phy_control = 0x3000; - s->phy_advertise = 0x01e1; - s->phy_int_mask = 0; - s->phy_int = 0; - imx_phy_update_link(s); + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, + nc->link_down); } static uint32_t imx_phy_read(IMXFECState *s, int reg) { - uint32_t val; uint32_t phy = reg / 32; if (!s->phy_connected) { @@ -296,54 +255,7 @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) reg %= 32; - switch (reg) { - case 0: /* Basic Control */ - val = s->phy_control; - break; - case 1: /* Basic Status */ - val = s->phy_status; - break; - case 2: /* ID1 */ - val = 0x0007; - break; - case 3: /* ID2 */ - val = 0xc0d1; - break; - case 4: /* Auto-neg advertisement */ - val = s->phy_advertise; - break; - case 5: /* Auto-neg Link Partner Ability */ - val = 0x0f71; - break; - case 6: /* Auto-neg Expansion */ - val = 1; - break; - case 29: /* Interrupt source. */ - val = s->phy_int; - s->phy_int = 0; - imx_phy_update_irq(s); - break; - case 30: /* Interrupt mask */ - val = s->phy_int_mask; - break; - case 17: - case 18: - case 27: - case 31: - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", - TYPE_IMX_FEC, __func__, reg); - val = 0; - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", - TYPE_IMX_FEC, __func__, reg); - val = 0; - break; - } - - trace_imx_phy_read(val, phy, reg); - - return val; + return lan9118_phy_read(&s->mii, reg); } static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) @@ -365,39 +277,7 @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) reg %= 32; - trace_imx_phy_write(val, phy, reg); - - switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { - imx_phy_reset(s); - } else { - s->phy_control = val & 0x7980; - /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->phy_status |= 0x0020; - } - } - break; - case 4: /* Auto-neg advertisement */ - s->phy_advertise = (val & 0x2d7f) | 0x80; - break; - case 30: /* Interrupt mask */ - s->phy_int_mask = val & 0xff; - imx_phy_update_irq(s); - break; - case 17: - case 18: - case 27: - case 31: - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", - TYPE_IMX_FEC, __func__, reg); - break; - default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", - TYPE_IMX_FEC, __func__, reg); - break; - } + lan9118_phy_write(&s->mii, reg, val); } static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) @@ -682,9 +562,6 @@ static void imx_eth_reset(DeviceState *d) s->rx_descriptor = 0; memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); - - /* We also reset the PHY */ - imx_phy_reset(s); } static uint32_t imx_default_read(IMXFECState *s, uint32_t index) @@ -1329,6 +1206,13 @@ static void imx_eth_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->irq[0]); sysbus_init_irq(sbd, &s->irq[1]); + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { + return; + } + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index b22c3c28556..d2dcd732ac1 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -4,6 +4,8 @@ * Copyright (c) 2009 CodeSourcery, LLC. * Written by Paul Brook * + * Copyright (c) 2013 Jean-Christophe Dubois. + * * This code is licensed under the GNU GPL v2 * * Contributions after 2012-01-13 are licensed under the terms of the @@ -16,6 +18,7 @@ #include "hw/resettable.h" #include "migration/vmstate.h" #include "qemu/log.h" +#include "trace.h" #define PHY_INT_ENERGYON (1 << 7) #define PHY_INT_AUTONEG_COMPLETE (1 << 6) @@ -36,59 +39,88 @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) switch (reg) { case 0: /* Basic Control */ - return s->control; + val = s->control; + break; case 1: /* Basic Status */ - return s->status; + val = s->status; + break; case 2: /* ID1 */ - return 0x0007; + val = 0x0007; + break; case 3: /* ID2 */ - return 0xc0d1; + val = 0xc0d1; + break; case 4: /* Auto-neg advertisement */ - return s->advertise; + val = s->advertise; + break; case 5: /* Auto-neg Link Partner Ability */ - return 0x0f71; + val = 0x0f71; + break; case 6: /* Auto-neg Expansion */ - return 1; - /* TODO 17, 18, 27, 29, 30, 31 */ + val = 1; + break; case 29: /* Interrupt source. */ val = s->ints; s->ints = 0; lan9118_phy_update_irq(s); - return val; + break; case 30: /* Interrupt mask */ - return s->int_mask; + val = s->int_mask; + break; + case 17: + case 18: + case 27: + case 31: + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", + __func__, reg); + val = 0; + break; default: - qemu_log_mask(LOG_GUEST_ERROR, - "lan9118_phy_read: PHY read reg %d\n", reg); - return 0; + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", + __func__, reg); + val = 0; + break; } + + trace_lan9118_phy_read(val, reg); + + return val; } void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) { + trace_lan9118_phy_write(val, reg); + switch (reg) { case 0: /* Basic Control */ if (val & 0x8000) { lan9118_phy_reset(s); - break; - } - s->control = val & 0x7980; - /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->status |= 0x0020; + } else { + s->control = val & 0x7980; + /* Complete autonegotiation immediately. */ + if (val & 0x1000) { + s->status |= 0x0020; + } } break; case 4: /* Auto-neg advertisement */ s->advertise = (val & 0x2d7f) | 0x80; break; - /* TODO 17, 18, 27, 31 */ case 30: /* Interrupt mask */ s->int_mask = val & 0xff; lan9118_phy_update_irq(s); break; + case 17: + case 18: + case 27: + case 31: + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", + __func__, reg); + break; default: - qemu_log_mask(LOG_GUEST_ERROR, - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", + __func__, reg); + break; } } @@ -98,9 +130,11 @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) /* Autonegotiation status mirrors link status. */ if (link_down) { + trace_lan9118_phy_update_link("down"); s->status &= ~0x0024; s->ints |= PHY_INT_DOWN; } else { + trace_lan9118_phy_update_link("up"); s->status |= 0x0024; s->ints |= PHY_INT_ENERGYON; s->ints |= PHY_INT_AUTONEG_COMPLETE; @@ -110,6 +144,8 @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) void lan9118_phy_reset(Lan9118PhyState *s) { + trace_lan9118_phy_reset(); + s->control = 0x3000; s->status = 0x7809; s->advertise = 0x01e1; @@ -137,8 +173,8 @@ static const VMStateDescription vmstate_lan9118_phy = { .version_id = 1, .minimum_version_id = 1, .fields = (const VMStateField[]) { - VMSTATE_UINT16(control, Lan9118PhyState), VMSTATE_UINT16(status, Lan9118PhyState), + VMSTATE_UINT16(control, Lan9118PhyState), VMSTATE_UINT16(advertise, Lan9118PhyState), VMSTATE_UINT16(ints, Lan9118PhyState), VMSTATE_UINT16(int_mask, Lan9118PhyState), diff --git a/hw/net/Kconfig b/hw/net/Kconfig index 6b2ff2f937a..7f80218d10f 100644 --- a/hw/net/Kconfig +++ b/hw/net/Kconfig @@ -93,6 +93,7 @@ config ALLWINNER_SUN8I_EMAC config IMX_FEC bool + select LAN9118_PHY config CADENCE bool diff --git a/hw/net/trace-events b/hw/net/trace-events index d0f1d8c0fbe..6100ec324a7 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -10,6 +10,12 @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 +# lan9118_phy.c +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 +lan9118_phy_update_link(const char *s) "%s" +lan9118_phy_reset(void) "" + # lance.c lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" @@ -428,12 +434,8 @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" # imx_fec.c -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" -imx_phy_update_link(const char *s) "%s" -imx_phy_reset(void) "" imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" From patchwork Wed Dec 11 16:18:55 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register Date: Wed, 11 Dec 2024 16:18:55 +0000 Message-Id: <20241211162004.2795499-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and fixes the MSB of selector field to be zero, as specified in the datasheet. Fixes: 2a424990170b "LAN9118 emulation" Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Reviewed-by: Peter Maydell Message-id: 20241102125724.532843-4-shentey@gmail.com Signed-off-by: Peter Maydell --- hw/net/lan9118_phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index d2dcd732ac1..d8fc9ddd3ac 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -54,7 +54,7 @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) val = s->advertise; break; case 5: /* Auto-neg Link Partner Ability */ - val = 0x0f71; + val = 0x0fe1; break; case 6: /* Auto-neg Expansion */ val = 1; From patchwork Wed Dec 11 16:18:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED5B9E7717D for ; Wed, 11 Dec 2024 16:22:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRi-000068-8H; Wed, 11 Dec 2024 11:20:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRg-0008Vz-Fn for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:16 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRe-0007ad-DS for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:16 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3862b364538so534419f8f.1 for ; Wed, 11 Dec 2024 08:20:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934013; x=1734538813; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0WGriA4LS3QsH5lw3Ak1RT7ziiVmWhZi2ZbsQKrrgFY=; b=xd2sH6bJ8TAa5nj4+/CdNKN7h2wptfxPrUWmngd9i9TN061XYPu333ajdTqcyvOcf7 GgnKMxFk7EbdXVyjz84WG6GfMsEtcQZiKAdIy1p+6PzlnhpRE/sElifSHdMBE9gqPPBE 1lviUcgq4aGkpZUF87T1hAKNp2SBzr78QEAHHPnDWsf0Nn++yLCkxxNPiX2CYVUP6BWX 2JJkshoXkK1iMwsbAYuSZWoFps4hgkJ//9mP/hnoSxOa0NWKQVJHTAqwXQ+yuBNcWyEz ejNfLShMtI0gvDmU5S3AvP/UYF8guGPt3pfkQ069FO26G99VYzvA4NG8qJf6YTFWKAQK sRSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934013; x=1734538813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0WGriA4LS3QsH5lw3Ak1RT7ziiVmWhZi2ZbsQKrrgFY=; b=squyPkNjGHsVN5zT+VgS0GXWJvlJeGPpDhIzqnrtJuN8VKRQcILrSTR4zNuCIEDDNv HAytNzP22prSbcL7OH9sPtXUfOldbLmLjVwaWLZgK8g9xnb4VlR7YSiPV69aQtZzI9gy t6bMNYi1PSRBVsnr87bb61Drg86AHWr5a0WQKvVslnLe0uiRqLcQXaVtMwbo83CWTx83 4whS43tlAlRtbOPG2l9/RgOcbglf4/0wlThyP08QjTUWNdHxT3S3P+do7AdzY1B6cPQJ aAo7Ydys7b7ZRjceVj2SkEpB2TlDb1YGmjy05X0vH2+N7JPSHau2Bh6U8h5HDP/4p0HX szeA== X-Gm-Message-State: AOJu0YwERl96RlhAEV2sOotHLcWlZbbvov4O8BvIULnsjztM14SaDN1Q G0GboK/DtT3/JLCVjk4DhBz8fcVlfOvfk1SY7cw9maoSP5K4vsIh0LHrVGIB8bZNsUuZQBZek8N Q X-Gm-Gg: ASbGncvvjiTlzJPuvYhtx+sh9VARjmwWcZVhb0wjbhXwlC+65gVGY+aAZI1DsWM4wEB zYw1xeXhWKzRsNF4m7Pk1Wdz2FCGrozCn4Q1QNW0aDqLyaUnjFo+bYLvKt+xmxBbuL1qQGs5D8x gOsshacStlgaN5YbDMZ4FO6qgHc0169Y/7Ia0KdKcBi5Goof+kzuzkqItP2D4MXqmKtPTe9VLyn ge0UrtIxrlO05mJAWkR/uAIpt8Eva2GY8nxWUeqAsfoUVqtEYLe9c1LHnIS X-Google-Smtp-Source: AGHT+IExs0Ecp2q/kTobX6qkcX2TSXmu1V2m36Myf0N+kL3eW4OxJ/lknQF8UdQqkwg2z3p7Na8+BA== X-Received: by 2002:a05:6000:1f85:b0:386:3672:73e4 with SMTP id ffacd0b85a97d-3864df05fc5mr2365077f8f.26.1733934012634; Wed, 11 Dec 2024 08:20:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/72] hw/net/lan9118_phy: Reuse MII constants Date: Wed, 11 Dec 2024 16:18:56 +0000 Message-Id: <20241211162004.2795499-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow Prefer named constants over magic values for better readability. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Message-id: 20241102125724.532843-5-shentey@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/mii.h | 6 +++++ hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- 2 files changed, 46 insertions(+), 23 deletions(-) diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h index f7feddac9bd..55bf7c92a1c 100644 --- a/include/hw/net/mii.h +++ b/include/hw/net/mii.h @@ -71,6 +71,7 @@ #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ #define MII_ANAR_TXFD (1 << 8) @@ -78,6 +79,7 @@ #define MII_ANAR_10FD (1 << 6) #define MII_ANAR_10 (1 << 5) #define MII_ANAR_CSMACD (1 << 0) +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ #define MII_ANLPAR_ACK (1 << 14) #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ @@ -112,6 +114,10 @@ #define RTL8201CP_PHYID1 0x0000 #define RTL8201CP_PHYID2 0x8201 +/* SMSC LAN9118 */ +#define SMSCLAN9118_PHYID1 0x0007 +#define SMSCLAN9118_PHYID2 0xc0d1 + /* RealTek 8211E */ #define RTL8211E_PHYID1 0x001c #define RTL8211E_PHYID2 0xc915 diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index d8fc9ddd3ac..874dae4155a 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "hw/net/lan9118_phy.h" +#include "hw/net/mii.h" #include "hw/irq.h" #include "hw/resettable.h" #include "migration/vmstate.h" @@ -38,26 +39,28 @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) uint16_t val; switch (reg) { - case 0: /* Basic Control */ + case MII_BMCR: val = s->control; break; - case 1: /* Basic Status */ + case MII_BMSR: val = s->status; break; - case 2: /* ID1 */ - val = 0x0007; + case MII_PHYID1: + val = SMSCLAN9118_PHYID1; break; - case 3: /* ID2 */ - val = 0xc0d1; + case MII_PHYID2: + val = SMSCLAN9118_PHYID2; break; - case 4: /* Auto-neg advertisement */ + case MII_ANAR: val = s->advertise; break; - case 5: /* Auto-neg Link Partner Ability */ - val = 0x0fe1; + case MII_ANLPAR: + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; break; - case 6: /* Auto-neg Expansion */ - val = 1; + case MII_ANER: + val = MII_ANER_NWAY; break; case 29: /* Interrupt source. */ val = s->ints; @@ -92,19 +95,24 @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) trace_lan9118_phy_write(val, reg); switch (reg) { - case 0: /* Basic Control */ - if (val & 0x8000) { + case MII_BMCR: + if (val & MII_BMCR_RESET) { lan9118_phy_reset(s); } else { - s->control = val & 0x7980; + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | + MII_BMCR_CTST); /* Complete autonegotiation immediately. */ - if (val & 0x1000) { - s->status |= 0x0020; + if (val & MII_BMCR_AUTOEN) { + s->status |= MII_BMSR_AN_COMP; } } break; - case 4: /* Auto-neg advertisement */ - s->advertise = (val & 0x2d7f) | 0x80; + case MII_ANAR: + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | + MII_ANAR_SELECT)) + | MII_ANAR_TX; break; case 30: /* Interrupt mask */ s->int_mask = val & 0xff; @@ -131,11 +139,11 @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) /* Autonegotiation status mirrors link status. */ if (link_down) { trace_lan9118_phy_update_link("down"); - s->status &= ~0x0024; + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); s->ints |= PHY_INT_DOWN; } else { trace_lan9118_phy_update_link("up"); - s->status |= 0x0024; + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; s->ints |= PHY_INT_ENERGYON; s->ints |= PHY_INT_AUTONEG_COMPLETE; } @@ -146,9 +154,18 @@ void lan9118_phy_reset(Lan9118PhyState *s) { trace_lan9118_phy_reset(); - s->control = 0x3000; - s->status = 0x7809; - s->advertise = 0x01e1; + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; + s->status = MII_BMSR_100TX_FD + | MII_BMSR_100TX_HD + | MII_BMSR_10T_FD + | MII_BMSR_10T_HD + | MII_BMSR_AUTONEG + | MII_BMSR_EXTCAP; + s->advertise = MII_ANAR_TXFD + | MII_ANAR_TX + | MII_ANAR_10FD + | MII_ANAR_10 + | MII_ANAR_CSMACD; s->int_mask = 0; s->ints = 0; lan9118_phy_update_link(s, s->link_down); From patchwork Wed Dec 11 16:18:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F1DFE77180 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement Date: Wed, 11 Dec 2024 16:18:57 +0000 Message-Id: <20241211162004.2795499-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Bernhard Beschow The real device advertises this mode and the device model already advertises 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to make the model more realistic. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck Message-id: 20241102125724.532843-6-shentey@gmail.com Signed-off-by: Peter Maydell --- hw/net/lan9118_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c index 874dae4155a..5c53a4a1e3f 100644 --- a/hw/net/lan9118_phy.c +++ b/hw/net/lan9118_phy.c @@ -110,8 +110,8 @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) break; case MII_ANAR: s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | - MII_ANAR_SELECT)) + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | + MII_ANAR_10 | MII_ANAR_SELECT)) | MII_ANAR_TX; break; case 30: /* Interrupt mask */ From patchwork Wed Dec 11 16:18:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0380E7717D for ; Wed, 11 Dec 2024 16:22:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRk-00008V-Va; Wed, 11 Dec 2024 11:20:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRj-00006n-1f for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:19 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRh-0007bx-32 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:18 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-435004228c0so31037455e9.0 for ; Wed, 11 Dec 2024 08:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934015; x=1734538815; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jjHu6tm+33f5za7B2UGWHozRv7iZoKjmmA7yl7uJ0xo=; b=tAMPGuUWzdM8ngPSBx/yyajeIjOUwscAYBPGvLUNhePqoQkkhWTRLKRiUTozpF2jNR w0cA1EqiQGn5V0TZwtGlCTUZa4xdPT1bXx5RyH36ZuQ2tTdWDymNlRr9OjWAe4T4LNDj 1/LmVzGF07YPYAs/IU3AIA7m6TTWCLdoGcLnjp4ETJZHvU0KDYlos33R+td7gBqqFkq7 Ecc9q9xIgBsGQSOHV71EcY8P7449p0CWA95UME4FLLFGArf39hCBiZ7rcGb4UO5VFk+x LqFjkN40kHPWm5+a/7WNSzfLtGufHrYlMz3P3LlmIFO7kDYqyBZA6v4b6N7y2Le9H1pi Zk6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934015; x=1734538815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jjHu6tm+33f5za7B2UGWHozRv7iZoKjmmA7yl7uJ0xo=; b=TWkw1xCUuF8ijk8qpMmqqXAKlshcdmZC6Siokgza4yuYiHCGEgLOep1Ii1B2r6sCaj e3aZkxKBNFP0JINTeHsZB6g+QrQfBWilkFR22UYWm8njNbRw8wHlwwGUQrkqO2tRkVvD 8LVRw4lI+tVAMKhPeVBWTH1zez/8gIObRKH30E6F6NQ3iT1mgt+uUaRni6+dExPQB0+T rZ1YigkDfN4spDdQnlKhLT3UE1o5kdnMdtvKgQWa7fHFFec701q5nWO/GsZpFLu/3Tif mN1sGNKya5DlB02HLNo8bQBTbdzc6yip4+Y7mGMi8X4cGuEXXj0hlopxIAnCQGKSasEo Uw4A== X-Gm-Message-State: AOJu0YxH6OEYfZ/zD19GWCgBdHFj5PuFdgyBlUtLIPf+m/3Me/GgEv8v 82S8jt7bshAvqCOzvQaD7HuZLSeUaCEdi4zEE42xXCZ2+3uXS9nLyFm4O6Qc5P3Qlkz+1cS4QOA S X-Gm-Gg: ASbGncs/C6mIvGp36US406HSbQT0QliY6Y/adiVN30ZS1BWoBSD858vvb32P+fJQGEV 5rrOSNAWQgqukF9JcIwY/l1jTZmVLWAIvHPgaIX2QfntQ83DIN1KTrZzRXKMCkGLWuC9Nl/BsRQ SOoIWE9sXLOyMOcPIfAjrGMJDlKiU9Oi+ZmeJ+9qw6+XfjeJkUsxnvPUKJc5sb652WmGo70pGPn r0qy7DiEUJnNQ883UYMTWgTcadmsSR3eKam/hNdtT23cye7aa7kHJ1hf72F X-Google-Smtp-Source: AGHT+IGpSiIlOwwOGpD9QdeTRVNqSQ35bjP7TfDX2WZAdrluTSM1pP+boDuo9zKhqOuM4yPuWgK2hw== X-Received: by 2002:a05:600c:c18:b0:430:57e8:3c7e with SMTP id 5b1f17b1804b1-4361c43d6camr25181595e9.28.1733934015350; Wed, 11 Dec 2024 08:20:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd Date: Wed, 11 Dec 2024 16:18:58 +0000 Message-Id: <20241211162004.2795499-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For IEEE fused multiply-add, the (0 * inf) + NaN case should raise Invalid for the multiplication of 0 by infinity. Currently we handle this in the per-architecture ifdef ladder in pickNaNMulAdd(). However, since this isn't really architecture specific we can hoist it up to the generic code. For the cases where the infzero test in pickNaNMulAdd was returning 2, we can delete the check entirely and allow the code to fall into the normal pick-a-NaN handling, because this will return 2 anyway (input 'c' being the only NaN in this case). For the cases where infzero was returning 3 to indicate "return the default NaN", we must retain that "return 3". For Arm, this looks like it might be a behaviour change because we used to set float_flag_invalid | float_flag_invalid_imz only if C is a quiet NaN. However, it is not, because Arm target code never looks at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we already raised float_flag_invalid via the "abc_mask & float_cmask_snan" check in pick_nan_muladd. For any target architecture using the "default implementation" at the bottom of the ifdef, this is a behaviour change but will be fixing a bug (where we failed to raise the Invalid exception for (0 * inf + QNaN). The architectures using the default case are: * hppa * i386 * sh4 * tricore The x86, Tricore and SH4 CPU architecture manuals are clear that this should have raised Invalid; HPPA is a bit vaguer but still seems clear enough. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-2-peter.maydell@linaro.org --- fpu/softfloat-parts.c.inc | 13 +++++++------ fpu/softfloat-specialize.c.inc | 29 +---------------------------- 2 files changed, 8 insertions(+), 34 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cc6e06b9761..d63cd957a19 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -66,19 +66,20 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int ab_mask, int abc_mask) { int which; + bool infzero = (ab_mask == float_cmask_infzero); if (unlikely(abc_mask & float_cmask_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, - ab_mask == float_cmask_infzero, s); + if (infzero) { + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ + float_raise(float_flag_invalid | float_flag_invalid_imz, s); + } + + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); if (s->default_nan_mode || which == 3) { - /* - * Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag for infzero. - */ parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9bca03c4aed..c557c41b2af 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -480,7 +480,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -507,7 +506,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -529,10 +527,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -553,10 +547,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } + /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -576,10 +567,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * to return an input NaN if we have one (ie c) rather than generating * a default NaN */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB @@ -592,14 +579,9 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_RISCV) - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - } return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -617,11 +599,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } #elif defined(TARGET_SPARC) - /* For (inf,0,nan) return c. */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer SNaN over QNaN, order C, B, A. */ if (is_snan(c_cls)) { return 2; @@ -641,10 +618,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns * an input NaN if we have one (ie c). */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } if (status->use_first_nan) { if (is_nan(a_cls)) { return 0; From patchwork Wed Dec 11 16:18:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DB60E7717D for ; Wed, 11 Dec 2024 16:25:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRl-000099-Gi; Wed, 11 Dec 2024 11:20:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRk-00008J-C2 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:20 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRi-0007cp-JX for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:20 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3862d161947so3392912f8f.3 for ; Wed, 11 Dec 2024 08:20:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934017; x=1734538817; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JXAkJPzlbPpI9TBbDQ7RCzmNVKijs33Nwl+I0eteC5M=; b=J15HBVqoVcsmeNGpl3DNGBN7kScvO2OULEdtZrIVha9qozyI9NsdsaqlFsD3Te7hBm nZ0qNO3HrwM0j000sP7b1QLBge8SwpFxutQ6SiBe6YSSDZnH/YdgF4HAnEsu/cPb5kBi droMa47gkK1pxGNLtn4MVcn601kKDdJCrybXo8lpAngu/+n5dIe8Kl9/tHMym4kiAeY4 XT+uJMBraOTVjRRNEwCq27l++GhGrrru9EEpQyzPWwSUoFQyC1/Aoyr67VPGm+sEp13X yB/KJ2U4p68373smVnG5OMx7YBjnTADNRJkB1XYiQU7tWGZc9boGFf7KaAVUF15G30vH k7LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934017; x=1734538817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JXAkJPzlbPpI9TBbDQ7RCzmNVKijs33Nwl+I0eteC5M=; b=gBd6GBZ1ynJ9ZZhbJvMhWyyNOO+sWjvsvrqT7cleBzCvMw1xZWesZs6s0FINFLtMV+ I+nObUbDKL0laKMJLMsA71rLLHJ4yrgqSDRYdcYDuNmOg/jQ9LpJXbpILEbI2k99yasw shE2l0QNCLA1iE+a4t2zNN0BKfW158ot4F8oNkLVIZoosCgsJRcIzbDmT7q4vs8Agm8x TwEt8yPn2Jy8rPnjPQhnuq+p3PVcPPyh5EBb9Sl3LotgGMbkgOrECBtd52Ao5s6TmbFN 8q2O6nxHiDcjtsA5rtc2yxUTrImP/VFC6luOF1ORePat9zG2i+K4Ki6Bhlvrue3y+Yom 1Uiw== X-Gm-Message-State: AOJu0YywDZ+NBiNJlWF5dfhQEaJ6N4wZlLx2O/UIj1ZjGizr7yjmjqt3 e/Oa5fHGCRtfV6ja7tB7pohsk9DrPiUIUbJcSb4V9gbQadfql4E01zWeJmj9pcZRnTub21MU5yr I X-Gm-Gg: ASbGncuOPHHsIgf2UU1/UDRfwk1DbcGDrrZDgWGIDgFwVRGtNeZa1OAtCP1XVWHzerI ++AvpXtoY+xTXPz91lP7uM96ixm3zwfy/N46pqDAsCrT5JuaHfwBrWS2a/1BfXe2hJ94T+gfpqO PDbsI0wsMLETUFpf2r6Dg1777wttfwZP9dCKbOMhXaVR3A5b0OnQ9yDdRS6IvPDk+GHoAzz/BjE LsgvBnaFkyDj10WrRlELnf/tgvhdGjAjPglPriTlw/HKNlHZo94ceTSBRT2 X-Google-Smtp-Source: AGHT+IE1ick7m4mMya0WtwTJ0c/ZxZ3PSSt2qNlagb89RN7ntcbgIvxiAwKt7jcl0KdQSh86XKXfXg== X-Received: by 2002:a05:6000:71e:b0:385:f631:612 with SMTP id ffacd0b85a97d-3878768e1eamr191041f8f.17.1733934017038; Wed, 11 Dec 2024 08:20:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd Date: Wed, 11 Dec 2024 16:18:59 +0000 Message-Id: <20241211162004.2795499-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org If the target sets default_nan_mode then we're always going to return the default NaN, and pickNaNMulAdd() no longer has any side effects. For consistency with pickNaN(), check for default_nan_mode before calling pickNaNMulAdd(). When we convert pickNaNMulAdd() to allow runtime selection of the NaN propagation rule, this means we won't have to make the targets which use default_nan_mode also set a propagation rule. Since RiscV always uses default_nan_mode, this allows us to remove its ifdef case from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-3-peter.maydell@linaro.org --- fpu/softfloat-parts.c.inc | 8 ++++++-- fpu/softfloat-specialize.c.inc | 9 +++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index d63cd957a19..aac1f9cd28c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -77,9 +77,13 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_invalid | float_flag_invalid_imz, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + if (s->default_nan_mode) { + which = 3; + } else { + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + } - if (s->default_nan_mode || which == 3) { + if (which == 3) { parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c557c41b2af..81a67eb67b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,13 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ + assert(!status->default_nan_mode); #if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN @@ -578,8 +585,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } -#elif defined(TARGET_RISCV) - return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { return 3; From patchwork Wed Dec 11 16:19:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7960E7717D for ; Wed, 11 Dec 2024 16:27:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRn-00009u-SD; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result Date: Wed, 11 Dec 2024 16:19:00 +0000 Message-Id: <20241211162004.2795499-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IEEE 758 does not define a fixed rule for what NaN to return in the case of a fused multiply-add of inf * 0 + NaN. Different architectures thus do different things: * some return the default NaN * some return the input NaN * Arm returns the default NaN if the input NaN is quiet, and the input NaN if it is signalling We want to make this logic be runtime selected rather than hardcoded into the binary, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. Note that four architectures both use the muladd softfloat functions and did not have a branch of the ifdef ladder to specify their behaviour (and so were ending up with the "default" case, probably wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set default_nan_mode, and so will never get into pickNaNMulAdd(). For HPPA and i386 we retain the same behaviour as the old default-case, which is to not ever return the default NaN. This might not be correct but it is not a behaviour change. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-4-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 11 ++++ include/fpu/softfloat-types.h | 23 +++++++++ fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- 3 files changed, 95 insertions(+), 30 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 453188de70b..0bf44dc6087 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, + float_status *status) +{ + status->float_infzeronan_rule = rule; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -137,6 +143,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) +{ + return status->float_infzeronan_rule; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f39691dfd0..47bb22c4e25 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -207,6 +207,28 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * Rule for result of fused multiply-add 0 * Inf + NaN. + * This must be a NaN, but implementations differ on whether this + * is the input NaN or the default NaN. + * + * You don't need to set this if default_nan_mode is enabled. + * When not in default-NaN mode, it is an error for the target + * not to set the rule in float_status if it uses muladd, and we + * will assert if we need to handle an input NaN and no rule was + * selected. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_infzeronan_none = 0, + /* Result is never the default NaN (so always the input NaN) */ + float_infzeronan_dnan_never, + /* Result is always the default NaN */ + float_infzeronan_dnan_always, + /* Result is the default NaN if the input NaN is quiet */ + float_infzeronan_dnan_if_qnan, +} FloatInfZeroNaNRule; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -219,6 +241,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 81a67eb67b5..f5b422e07b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -482,14 +484,68 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * specify. */ assert(!status->default_nan_mode); + + if (rule == float_infzeronan_none) { + /* + * Temporarily fall back to ifdef ladder + */ #if defined(TARGET_ARM) - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero && is_qnan(c_cls)) { - return 3; + /* + * For ARM, the (inf,zero,qnan) case returns the default NaN, + * but (inf,zero,snan) returns the input NaN. + */ + rule = float_infzeronan_dnan_if_qnan; +#elif defined(TARGET_MIPS) + if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + rule = float_infzeronan_dnan_always; + } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + rule = float_infzeronan_dnan_never; + } +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ + defined(TARGET_I386) || defined(TARGET_LOONGARCH) + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + rule = float_infzeronan_dnan_never; +#elif defined(TARGET_S390X) + rule = float_infzeronan_dnan_always; +#endif } + if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the default NaN here, + * and some return the input NaN. + */ + switch (rule) { + case float_infzeronan_dnan_never: + return 2; + case float_infzeronan_dnan_always: + return 3; + case float_infzeronan_dnan_if_qnan: + return is_qnan(c_cls) ? 3 : 2; + default: + g_assert_not_reached(); + } + } + +#if defined(TARGET_ARM) + /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ @@ -508,13 +564,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } #elif defined(TARGET_MIPS) if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - if (infzero) { - return 3; - } /* Prefer sNaN over qNaN, in the a, b, c order. */ if (is_snan(a_cls)) { return 0; @@ -530,10 +579,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -550,11 +595,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } #elif defined(TARGET_LOONGARCH64) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -570,11 +610,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_PPC) - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ @@ -586,10 +621,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_S390X) - if (infzero) { - return 3; - } - if (is_snan(a_cls)) { return 0; } else if (is_snan(b_cls)) { From patchwork Wed Dec 11 16:19:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F0E9E7717D for ; Wed, 11 Dec 2024 16:22:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRo-0000AT-Ps; Wed, 11 Dec 2024 11:20:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRn-00009l-9Q for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:23 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRl-0007eM-Np for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:23 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4361fe642ddso6093395e9.2 for ; Wed, 11 Dec 2024 08:20:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934020; x=1734538820; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=p5mifZl5EPC5sQJMN5FD/oN3NC4zCFa51s7YMRd5p/0=; b=pxRzqmf8lqIaNb4l0lnSJAM9rbVMDzjPinbxy+LwjZPtuS2asErk/AeX/5enfCgPuJ bWRLties6+24yrQBLL/oeF8LkDqxmiVhexoatSxy1WCkcVMG2Auw0qc+ts8Oulzfw9Ka DXLzQlPD2B+7Wkge9PJWn25fWxzDvK30je0WXsIJtjO50KOz84TJEOXjxW51nNBflMQj KqtYQcC+K7wMgwO2HEJv1Xm+DoFJFOTVJmZj0Ai8l1KdtbaKtlfRX4nxVOm1DrbzEW6y yIb0mjqX+bxYfh3B07+8zzr0Gbe6sHFJWECPmpgwSSEuM2mCb4pQytp3u4ByjKoP9PIN onGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934020; x=1734538820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p5mifZl5EPC5sQJMN5FD/oN3NC4zCFa51s7YMRd5p/0=; b=SeY/n/lNQunNjeALOhwOGCsYPPtpKUGSQ/VEEIlR1aYt56zma1Tjt2L/VEh6aMUzvA PABX6EYOUxpLRmAUgo//Hioo5hCa8SVdF2BHQFvNWm7RK+xbnX/gyaCoWIQj4TQIPKQw y8KAgMvJ+gts7HzDJQVV3lOtiiiB7QvxPAJttm/59dIopfAP/pePiqNa9yMkYNF5ZWly eGFDGgKWPsMAbGXkLCB+ufIQq9ebdlQe8jbQVYOaD+w+Abiz/Q4P3I40elcOIOLahG58 z1xwzu0+lHAp2ft7pK7KcSFLO2Oei0azHalbfbodQeW3ZmfrkrvqodCk5517L99NuYKt lboQ== X-Gm-Message-State: AOJu0Yw44mF4QPcO3+lzw1s/tFVUHwBR4V9izW88tI2FBteoJW8EcAHI 5ObYK8MBPP0sb/hILkdYGxL0urfIXPaK0tCKeKgdw5j3/EoHjvbFb9uGZ4/LWOuRJQST98DnBze o X-Gm-Gg: ASbGncsJ8yoWUHdp8/Vlo0ZgbOv4ulSKmUuQMvKLD2bKT/AjTMKj1MzX4ovPEV4Ez+K 0NvulVWOWOnSXzgGBOEYyuiWugU8REsVDxp4i35wbRvbYVnIve3F3UuC2smPpTYng4e3ZEKAnRB 61A7e5CIL7Le0lDa3ek6TYci4WdRY3nBYKXcmj4tujJv4Vmb5oBYYtccw/jKNCySS49BO57EP9h nYPwYVa0808lWrHLUjshOe9o01dvnXEnFphrNJYztKrqKbj8eaEYimiQGer X-Google-Smtp-Source: AGHT+IG2x20y7IXHmYEDNXAUQ/i6F9ZDryZ1wi9fmNj+GVdERx/d2pZKGGasNMcYkAc8fhcif99mig== X-Received: by 2002:a05:600c:c89:b0:434:f5c0:3296 with SMTP id 5b1f17b1804b1-4361c3a35f8mr28252145e9.18.1733934020139; Wed, 11 Dec 2024 08:20:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule Date: Wed, 11 Dec 2024 16:19:01 +0000 Message-Id: <20241211162004.2795499-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Explicitly set a rule in the softfloat tests for the inf-zero-nan muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_infzeronan_dnan_if_qnan. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20241202131347.498124-5-peter.maydell@linaro.org --- tests/fp/fp-bench.c | 5 +++++ tests/fp/fp-test.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 75c07d5d1f1..fde64836194 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -488,7 +488,12 @@ static void run_bench(void) { bench_func_t f; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5f6f25c8821..251c278ede9 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -935,7 +935,12 @@ void run_test(void) { unsigned int i; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); verCases_maxErrorCount = n_max_errors; From patchwork Wed Dec 11 16:19:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B16BE77183 for ; Wed, 11 Dec 2024 16:27:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRq-0000Bc-Uv; Wed, 11 Dec 2024 11:20:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRp-0000B5-D3 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:25 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRn-0007f3-DX for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:25 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-434e69857d9so5480595e9.0 for ; Wed, 11 Dec 2024 08:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934022; x=1734538822; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HwP8TsYkVd3ug07uHGZQT6C7fkoiKCntvbbFB7VRiRM=; b=DZHzssuVjca7VgnxECv0fUA6YJXkeZ2KptEetogI/nyuix2MSh41DGA6hADSGlu7SZ v1/Ioxs3omiAQPw9D23lfIvYjWqjYiY34Z9+JleNRWT21+GIQB3THprRnclsF51W1TLm 1cwtytUVCbXMdZ0b4yTEHEfj9op/GmVwy9D0WI2feukE9ipPo+uRkwGXGi+kEfTfQSw9 Gin4dwicjLO+sPIpxJ7o2lG5tpq/Fz6vBOENSyOgLXS00ABPEK+Y6SOTxp+c8DSP7RHY smen17Jjzs+zk5mMv2eCzNk+Zt6vu1hrgvb8NJ0XC+EOxqO4IRTw7RIybVg0g2nFuWI2 KFBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934022; x=1734538822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HwP8TsYkVd3ug07uHGZQT6C7fkoiKCntvbbFB7VRiRM=; b=k4SEY/lxYhLGbrgxqQ7QdjAsuFIRuu39COWC/7Kb87o1WoKJI0QeFhYGSLJoNKLQS/ 7QILRGan25wZL+0DTRLx5u/ehxVZnMTjnF38PQJMhjloSKlFfW0mvsxvpdPgBf0pXeRR Ht9HQ0h3sU8Cb48amEL0SqhlY6z2HUMWOqs5p6tbWr0QKj7owdb8Dm19q9Dp5Kt8p09Q eGBmHZAGjdcUpYN4xjMfQE8+uIAxXXQuf+CqqIm6c2Tv2ZPIpYjLpuVbkM2F9TseoAEI 9HMi2UoF+k6QoF/6UhdJ0QFsKVKVIC2YXNmD12qtjXLnMMIUjXprNDVHihYNrtkk+Ynv Ph4g== X-Gm-Message-State: AOJu0YwRC+1r49zN9oVs8LvM8dfv6L9pEtBPEuwPEPRT8roSslJ/0Ob5 qxCQkfLA0bEVDi5JuJCdYrU+jbewJukX6zalJ6YtwgUzyDgaUuM4VoCfMsdzSHXO74BSqoukIRQ A X-Gm-Gg: ASbGnctT0yYXpB8hJKd759bg4M65CqkKq5DpxaUwEW/A2AxBCwzuOjPB/t3PWmJdOrc LDquik97dBiyabQ7DIe2b1jq8QM6qyHDI7Oe+nI+Lnzk2Nkh6atSgaLVG+hpZYW0CGm3yyrFUch ERmzOn/gw6tyt1K3uMTwZq0Cv7C9kaxBGfgocY/TNg7mRtbc6CsxWAloMCXiqNeFEXs8gEWQs7M UuRzSf+bXonbj/mypDtaeD/OOimbf1m0qoskKRNiXj1wQfMLzuzr/odjkLq X-Google-Smtp-Source: AGHT+IHqujr6LDYPAIU588RSQdkszuKNI+S0uu5dToBz7fIob4k9VzuRud7sgur0CPV20l51Ob6Fzg== X-Received: by 2002:a05:600c:1511:b0:434:9ce6:3ec with SMTP id 5b1f17b1804b1-4361c5b1b37mr23498465e9.7.1733934021831; Wed, 11 Dec 2024 08:20:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:02 +0000 Message-Id: <20241211162004.2795499-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-6-peter.maydell@linaro.org --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..ead39793985 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,11 +173,14 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, + * and the input NaN if it is signalling */ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f5b422e07b5..b3ffa54f368 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,13 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_ARM) - /* - * For ARM, the (inf,zero,qnan) case returns the default NaN, - * but (inf,zero,snan) returns the input NaN. - */ - rule = float_infzeronan_dnan_if_qnan; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { /* * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) From patchwork Wed Dec 11 16:19:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C316E77180 for ; Wed, 11 Dec 2024 16:20:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRt-0000Cm-Vc; Wed, 11 Dec 2024 11:20:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRq-0000BL-2W for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:03 +0000 Message-Id: <20241211162004.2795499-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for s390, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-7-peter.maydell@linaro.org --- target/s390x/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..d5941b5b9df 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_infzeronan_rule(float_infzeronan_dnan_always, + &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b3ffa54f368..db914ddbb1c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -516,8 +516,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ rule = float_infzeronan_dnan_never; -#elif defined(TARGET_S390X) - rule = float_infzeronan_dnan_always; #endif } From patchwork Wed Dec 11 16:19:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCE95E7717D for ; Wed, 11 Dec 2024 16:25:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRs-0000CV-FT; Wed, 11 Dec 2024 11:20:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRr-0000Bl-Cl for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:27 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRp-0007fn-7S for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:27 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-434a1fe2b43so69473975e9.2 for ; Wed, 11 Dec 2024 08:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934024; x=1734538824; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NzL75CnGj5vekrbIr9hglljRLm1m2p+xEVNazCq4Ld4=; b=cHL8z/LUrCRtD9qa0YyEZx75V3wFAfjqb30uAJUBG8FJCEFuMUGl+RpLUEnnksbbrI 9vB5nq019YnsggiONu+46s4e603pyXeoM5/KBlPZMiJFhhwpHDIlYd2nhfAG5y4k6Y0h +yumFy2FuAeqeXDkzU4c0d+HDQeJncp/msyWIq958Nx9LIBgVFfDPEqk/+X+pciOE3OM n9iIwNs0een0ngQffnArU9akaTutqaxw05Q4KFVDadjggop7qhFfTThyJZvWQ4KTiZGg pp2yPSA8bez8JgcsnOw8b+FtqkJqwO0n+IMRoctFl4yX1761POvZG6ypd/Gy0VXvZnWl EcBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934024; x=1734538824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NzL75CnGj5vekrbIr9hglljRLm1m2p+xEVNazCq4Ld4=; b=Vk1nWbTr2WhabZz4Be0Qn35QSE93Qbr4p63Kot/eumoCqtdJig1pxqMrToHtfeu2he B0W2YV9d7dRkGiiROLbH2NB/vu7zBXYcLm+Guwww3JKufR1IyTgrvPWeA5F/vfgLsm4Q tE6HoKvImdKgL3sNYlupZuOeqTiIXV0+Gy1FzDTrGWlB8RALgYe9O19Z1/CC+Ct5/n6U BSfQuGyvfW+qYM0TqGkyt1g0UaagtWQGD47qFSEkhp3/tTQZV/CDunwDU9nOthCToj7S 8DYQMnx/KRBuD9gWJk/7YMXmqyC7vhzo7lfSsHe39BkPdNpuWtCKsKiUd2AiTbsYdYbK oS6Q== X-Gm-Message-State: AOJu0YxpnYRN7I3xh54r1nkQ+P3Ag22lOMKT9qDYc+safRKYdDUuEbOZ 1yjppmzHsvuoDpoy35v/PxbGwhCo6qr/IShefdXuqKvLGIR8wLpBPrv6QmB1LEhtxRXAqkBbqR0 t X-Gm-Gg: ASbGncuBm6Hg4tc/j2vTUrChNSEQMCa+3SV+lsvB3drz+PBPmaVJxPH+x2ohQSPnn0H vl8kuwXoZWSgmMKvCxH2P2wDdZmI5pcIprlYhd25SSISWmzFjDMzpmo7y+G8V+9mqz9IkRrDNKp 3VsXFYtkYDiZUG8BIeZ7BpHEGH6AFMCty+3WGhkbyqgFPCDc47yUOY+DLrcUYnN4RP2aMr4EMKO 0rj+49KBzFVa2RCyQT89ap+0j65tUVSmwO1+yLTs6ylEGv9d4DMy7Z5Q5IK X-Google-Smtp-Source: AGHT+IHTiwk9eU+nrzUPzCgj8K0EAwb9ioBxTaxU05mzYZC5W0u8HurII+kNgURYVzbEyXD5iY8H2A== X-Received: by 2002:a05:6000:a04:b0:386:42a6:21f2 with SMTP id ffacd0b85a97d-38787685148mr237671f8f.10.1733934023671; Wed, 11 Dec 2024 08:20:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:04 +0000 Message-Id: <20241211162004.2795499-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the PPC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-8-peter.maydell@linaro.org --- target/ppc/cpu_init.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c25..f18908a643a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,13 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db914ddbb1c..2023b2bd632 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -503,18 +503,13 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ rule = float_infzeronan_dnan_never; } -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ +#elif defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - /* - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ rule = float_infzeronan_dnan_never; #endif } From patchwork Wed Dec 11 16:19:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E82BEE7717D for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:05 +0000 Message-Id: <20241211162004.2795499-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the MIPS target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-9-peter.maydell@linaro.org --- target/mips/fpu_helper.h | 9 +++++++++ target/mips/msa.c | 4 ++++ fpu/softfloat-specialize.c.inc | 16 +--------------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 7c3c7897b45..be66f2f813a 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -28,6 +28,7 @@ static inline void restore_flush_mode(CPUMIPSState *env) static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + FloatInfZeroNaNRule izn_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -35,6 +36,14 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN. + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c'. + */ + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index 9dffc428f5c..cc152db27f9 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -74,4 +74,8 @@ void msa_reset(CPUMIPSState *env) /* set proper signanling bit meaning ("1" means "quiet") */ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + + /* Inf * 0 + NaN returns the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, + &env->active_tc.msa_fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2023b2bd632..db9a466e05b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,21 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - rule = float_infzeronan_dnan_always; - } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - rule = float_infzeronan_dnan_never; - } -#elif defined(TARGET_SPARC) || \ +#if defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* From patchwork Wed Dec 11 16:19:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB8B0E77183 for ; Wed, 11 Dec 2024 16:26:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRw-0000Er-LM; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:06 +0000 Message-Id: <20241211162004.2795499-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-10-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..61f2d3fbf23 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db9a466e05b..7e57e85348b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_SPARC) || \ - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Wed Dec 11 16:19:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36780E77182 for ; Wed, 11 Dec 2024 16:20:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRy-0000FL-0M; Wed, 11 Dec 2024 11:20:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRu-0000DL-71 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:30 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRs-0007gt-4L for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:29 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-434a852bb6eso66240395e9.3 for ; Wed, 11 Dec 2024 08:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934026; x=1734538826; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CQjRicSg/XdHnvLYpOYP7psZ4EG5XIl4wxja3fhCd1M=; b=Bhh0bEpME3bKFrEtMe+SBaQYO6t/Epy8JMJjA/L5AJ3SPQN+dmvFzb73oyeL2VOepR WkFxnnsJ/35nQfUe6RjtAohlH45ekjmxG9kQaVB1nOMVFmA57Mmtm9P1oT2sZmhuuFY6 v3g2V0ZkeVP4upRmtzoSgrrb6wSmRdgdrqjScRhXderCP75T6K+jCCENayLpUXnLJkus GTzPIbivolsA/WGr2EADz0pye9ZDjI+BQPFcJz0XAU9hUfI5SofWLWqhmzeDjXOxcWWZ 7RvtZHcggvioDLgbJnn4YmyWs6ZH1jmvkABCPw0gG1AXPAtrKjAKzjpHlYO2Z7lP6L3I cFNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934026; x=1734538826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CQjRicSg/XdHnvLYpOYP7psZ4EG5XIl4wxja3fhCd1M=; b=Ozyuy7T3rY8vuBiOcWyM9+sLzdLirZcQkDaDikvk63Cin4ct2HOY+7AEUqEatKpAWF 3XWSE+EeFvs+3pthZuFDxdwfAUwM7v6Jng4U0EkPF4pM7YpbD42oYvUMICNayuWry1s+ nAW+Js4fWT4wNVtCljRHou8iCeYVkAYvI7K9M5oJknmPxHdB0PKs4r+J1apTzTsea72I 8a1eC07Ez63FYNOHYm21vOL0ELlnGlaWsnC0yF0y9ug8Pm/IQhJvIeM77D9knxAwWscT 3qkRSW7yO/PNsCCsf/Z4gHAP5aoGfLHx2JhzBuAmSpXdeXDiNOtzegmKERUY2zRZlzAN Ilew== X-Gm-Message-State: AOJu0YysuS2PyXM3vunLK8/WX8qHCoYQzS5iZPPncoi/bvNU2RZyd71g Uq/gK/9i2kfct6XwW8Gd1xX1wFPs/YF9q26AWFauPqvW2hnlRLcqQlCBqkWKz3zkEXJbLn3SmMt Z X-Gm-Gg: ASbGnctadv6rQ3zzRUURV3V/qKT+CFN2iXRWum2Nf8gxr++5ouc8JtkiOFYJaKCltit kgT/8eZQxKE8Wdmy+W75TshhVq0LP2z9o0D7g8aDlC5z+3DcuzLFhg5uioYBSGsbAj0SJlYSokk Oa2OUSb9vAKqks7TMt3YkSGQnNydWmFfKnFxNvZ36S+PSyDWGpoetOn4A/GvDMac0kpSLcEgEGh ssZA2H0cJQ4qE1V0ssZHeCUQ7c8tuQqKGAL/9ljVuWDUFhw0ERKlnbPj35U X-Google-Smtp-Source: AGHT+IGKkyCTGismVk1cmEz9ugWa/XTFjU+N/gh5NKLd5yjFhRDEPhNDifYAagPiN4abwtKPyxxBaw== X-Received: by 2002:a05:600c:4e4b:b0:434:a0bf:98ea with SMTP id 5b1f17b1804b1-4361c35cc4bmr27283155e9.9.1733934026456; Wed, 11 Dec 2024 08:20:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:07 +0000 Message-Id: <20241211162004.2795499-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the xtensa target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-11-peter.maydell@linaro.org --- target/xtensa/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abaee..3163b758235 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -133,6 +133,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) reset_mmu(env); cs->halted = env->runstall; #endif + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7e57e85348b..3062d19402d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,7 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Wed Dec 11 16:19:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D480E77182 for ; Wed, 11 Dec 2024 16:25:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPRy-0000Fl-Mz; Wed, 11 Dec 2024 11:20:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRv-0000EU-Fz for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:31 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRt-0007hH-T1 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:31 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-434a2033562so59602725e9.1 for ; Wed, 11 Dec 2024 08:20:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934027; x=1734538827; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=A6eEv6wPqQgMdCISzrXsTLaQsxZwE/ao0DoOYZ7nU5Y=; b=wTvk6kRju3/QRk+MNdPvj4gp6ndsvDAy4r/MBGjR2frKYxpIVvecgb+QhyORK8AE/2 FIpcCuP3fgrX2HVNUPwTwrmqa3DPcp+QVzmitgG4JU7FhWOuhn/uoKntYzHZv5QPiOjz nq360azh/p7N0FUcNLo5Jc1nizhlllqAzE6mpc6UV8+b6Wz0igJCUOBEflJbZzP9QBc9 5Q9+tSfbkkjBvdZyJ6751zRO5IyEmoVV75js8jWh9HwlmLuP/xoVO8xPiAGcjKQk/84P yukAenqpzWR/xlT8C0SqIECZthJYdUhXEO0fm6lmASOnP9GYrgJvwVLRTcYmOpi+Bo/V ZCog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934027; x=1734538827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A6eEv6wPqQgMdCISzrXsTLaQsxZwE/ao0DoOYZ7nU5Y=; b=IPQOsbIoN/zK3v7fXSf2ZadT+XWUlIyv2Yn85XAY3tE6g9pot3sRHvMiYmUb7lEIyt Zm+qoPxnX27RgNVsQQtA1ucy85wno2brLkltz6bl02/lTmXhs/o3u1bHr4yvAFySvAWJ YSmrtuQ2hrihqb2nTvaUgEydIgkBtRvsnl0dk95BNTbLwfwf5T0UuQJHmM6zfbKv1yP+ q6hka+VXCSIcxApY7O3LFvenGgcQgw5qs7O5E80k83wTNhlF2AlHv0IfuqqH7iXT8wnB l2YAJPSSPsX7vNGtB/kgar+Jqx8J7uE91TU0+9gUI2Bht9gq6/dShtxgQmveFebEVTss UMLg== X-Gm-Message-State: AOJu0YwTChZFmLbbaGfhyzFzRhcwrv/HRPabhfESn3xGjVRffRf688Io UUbxfeEdSsLWluu85zJ0jmBVHPHZB5JSvKtcPawdBKbhGkObRZC4O6MBkE9qMZ5QebthquosvEH 3 X-Gm-Gg: ASbGncu58d+D4HU/aTK6es9waOpvPxDvjpQosMAMFBAHjWEJEodtK3Sgxr72Zw6aOtS d90lnawsyaYDNQzxvcS66pCvM42jIxPOhjk65P9qphD0VruA3wahuf8bgnR/tMkaRSxDDXoUAZE FO32if/54O8jtNSaeIMEdtpVluHkBc/AMDv7f1aggFdAalczXi6FHFffVxQUbk3pHIiq1ZpM3N9 6oDF7bc4jtXFN/+LxpP1vYdd9D8+uhuFNKD+73OsS/6jWcAVtaayLI+HMDN X-Google-Smtp-Source: AGHT+IGZ6RGcHkUrzCICWBlKUuLRdM9mM8MTsLxlKPWMyWobX7I4XCANwFdR0CJarDz6rLsFyNBeRQ== X-Received: by 2002:a05:600c:548a:b0:434:f609:1afa with SMTP id 5b1f17b1804b1-43622823a9bmr3473915e9.4.1733934027369; Wed, 11 Dec 2024 08:20:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:08 +0000 Message-Id: <20241211162004.2795499-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-12-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb2977..3295753e075 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is + * specified -- for 0 * inf + NaN the input NaN is selected, and if + * there are multiple input NaNs they are selected in the order a, b, c. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19402d..ad4f7096d09 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' From patchwork Wed Dec 11 16:19:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 267E0E77180 for ; Wed, 11 Dec 2024 16:25:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS1-0000GJ-Qx; Wed, 11 Dec 2024 11:20:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRv-0000Eb-Jd for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:31 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRu-0007hR-09 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:31 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3863703258fso522114f8f.1 for ; Wed, 11 Dec 2024 08:20:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934028; x=1734538828; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MfZN52pgrp+/nZeB9BI1gMkKMPo4Kihy7pjqat+nckw=; b=E2JLlQaIAuqbzeFZ3JhjoeF/ZjSGhgRg9iv/883rK2P9H7etyeWzoeB6t63HAZvSz/ ke5kJqqPk8mYvMsOL4OzDFhcNw45L/WxvJrz1Ma9LML3TlEtBimYShTi1B9h8jTJ2p0m KicPlSjcSY9eA4zs3kl6Zmq6BGhUZSM+GNU8sMKpwHzDPA8c4ybuPWHaRltR2CUAAaOp cHIL1PxLezMlF6golkUeaFPqe+oQJOGvnXnzWMyNr/KiS905ywMU/U0gmYxd5lxOps2o LOanluM08I/BjeUKeA6XIYWtkGlYL1KSnC02OCV84lv0698PnkgiQ8A5tb+gy37uqm+5 hjMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934028; x=1734538828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MfZN52pgrp+/nZeB9BI1gMkKMPo4Kihy7pjqat+nckw=; b=PJ1ftIvQ2fVyWOLW7Ngv1LjY591iW1hOu5ik9Nv+rq/gjZD05ZsDmgImz2G/OzmVuZ 00Duo02hGS4rQB188RGt4nlMYg/npA6tN+2L7d9kjzhEAVSRTCxh4Eh9fAPa3IOldWrL rlxjEF5xv1w+dqqJnI5xlv8rY5ri/k/t+4gVIAP6rY+c6X1WpTPIwfNXXEbe7kVI06t1 EBJQp0H8+4Iu8T2r5VUSaBILM6qHw/yvxJm45gIRAde23lMLssAap64y0bR/7aBCqjpr DONaXj6jhnZaCNH9XMmJ2JP2RdOqSeRqFO14Z4Gaug6cGj+kcwvjmhKleoBxMm3Nk1TH r6Mg== X-Gm-Message-State: AOJu0YxDyjNJFhdHtfRGqonswiNV3wuqQ4qFkC39CTgNhG8lB0lcXRUx RJOO/Tq5tyiYioc53V2w4iysCtClUdIk3mIqIhM8D9VWwXxAPOAmgwk9ix470Wnv4sF8hZjgWa/ v X-Gm-Gg: ASbGncvUN7i5iA0ZnEPBV9pt2nebjHytYqZdSOzQta4Et+TFEHj+P52NJgrhFc6Tpdm ObF+Mc5cWJk6BMbYuuE8kmTJYJ1CfOFo/KlpW0wAxLptZskbsmbX2j7o9sR6HO/QpYZDh9Dmcx5 1Ozp5aHCjc495CXTIrfTfGJ/wFuaVbYeyiGnPcfjW/WnxBsKkgXmEHBkpo3okPVztJMa4oz/6qZ 6jcUmTv7QUwJ6tUvgRw/vzJkCcdA4FUrfl3Q3IJGHAUHcfeuW7uxf7qcL+S X-Google-Smtp-Source: AGHT+IGYPYT9QaEVX/rw9RpTTkQaovLiWIPuafnp3z7jNi3SJTpu3hXN+wWLOF6LW9Gvp4GxYA6oBA== X-Received: by 2002:a5d:584a:0:b0:386:3afc:14a7 with SMTP id ffacd0b85a97d-3864de9e223mr2310317f8f.7.1733934028379; Wed, 11 Dec 2024 08:20:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:09 +0000 Message-Id: <20241211162004.2795499-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-13-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 5 +++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 21bc3b04a96..6a2c4b5b1db 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -32,6 +32,11 @@ void restore_fp_status(CPULoongArchState *env) &env->fp_status); set_flush_to_zero(0, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ad4f7096d09..05dec2fcb4c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,12 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ +#if defined(TARGET_HPPA) rule = float_infzeronan_dnan_never; #endif } From patchwork Wed Dec 11 16:19:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2053BE77180 for ; Wed, 11 Dec 2024 16:25:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS1-0000GI-QT; Wed, 11 Dec 2024 11:20:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPRw-0000Es-OW for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:33 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRu-0007hY-Q2 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:32 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-385e06af753so3068563f8f.2 for ; Wed, 11 Dec 2024 08:20:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934029; x=1734538829; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=129ef8vVSPhcYKXwuPVUePnnMXZtavBkurzU5VPKzhM=; b=rHcRkOb4wgFbhFF0GnbW2XBMuIYq5ELpnnjRTyhZ+U37BIj/ES4khs2gn8PneRLj1x tIdASBVVzvqxQgGfGlXeVzSMQ0ZydMAqqkERK7Ip0XCHUPKysNfrpZyd71kBW+CakDcW 1tZlDlqZ1/KE677lA5TMcKi+vMi2I9Vl9qLMzH7HdRRK9+YP+qP5tHS0iOs9XFivBkEH vbNyTVYdP1J4h8TAArn1hR//EknMc/+d85R/E93C5jipL9nq1aTEnSap1GSMPmhR1Ph+ UsmHDcRMnMJ49Q4hBA2VrSO4x5NEEJGjz6WbRIc8So7plrj05bpz1LV4HkHJLb4dbuo+ XiZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934029; x=1734538829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=129ef8vVSPhcYKXwuPVUePnnMXZtavBkurzU5VPKzhM=; b=sLP59tY91tBsUgiLBAgMzAgVtzY6AjnUwe19NTiLMyx+Kxmcdf2NV4cPk/SZwbNX/a t3Poa++g+YIrUU8nK5h28ofl/lZEZxiDMKJ2LwidNk8kZpcbiv9h37B6PvBbXh0ybt6U NLiq/3UC3LFJHMOQFxBvMZEjEHjlV/uXg6BCdYwja0zMADTzFei8Kta++912s8zKPUd2 UBVr8eEVeVFEC0m05n8B+/JEQ+20KYYg3MVOsp4TFXxB2uQXRTXo1GYjW0kuxZhAH+Em vJ0wHPToRoRKKdKatrZHD7R+EZIwE2vHfqSuJFNXU9VE6V0QcAfH8KlPe7g825pAgDRY 21fg== X-Gm-Message-State: AOJu0YxtJPR3rEIEs63Q5sLfa7Re+5XdFyC9OXszjyuwIJAkltJAQOB/ 8OUoY6E2kJN2pZOSE8H8dnyd5f1M5sG9BMFjnnYXE+feOcQp9XfZrAEwE0PhkePj/5WwUxFMCNO O X-Gm-Gg: ASbGnctvwaDHpSoYTuPeWuaesPBES5plyhx+aNfrzpf8BUHxjPuzHtzzI8R0+3SVfB9 dCWdn3oEtVB8Ce4Ewx6wgtjLKaf2iIgNRWMFwiMPihTpZMq8hMJdN05LgICZVA+5npjIct2U9BI 61DVJecuvL8goU9+IUuFMBJ0sPLadGzSg0ip/Zqt2ri0u3o3J4D0FOtGCW314I4i3trvDZXdcSb ezjanohhjhEpUaS0u5TqDyhV/0fNbsvODog/QnjWu0WUWPgqx/AZI2to5b6 X-Google-Smtp-Source: AGHT+IHawayYOLRoJVyOTs7hXbcV8NUwQ5+tFgdwmnnncbnmg2QktS3knJYw/k1h8+v8DS9ORsqNvw== X-Received: by 2002:a05:6000:144d:b0:386:1cd3:8a0b with SMTP id ffacd0b85a97d-3864ce968f8mr2280236f8f.17.1733934029265; Wed, 11 Dec 2024 08:20:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly Date: Wed, 11 Dec 2024 16:19:10 +0000 Message-Id: <20241211162004.2795499-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-14-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 13 +------------ 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 0e44074ba82..393cae33bf9 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 05dec2fcb4c..3e4ec938b25 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,8 +475,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; - /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -485,21 +483,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ assert(!status->default_nan_mode); - if (rule == float_infzeronan_none) { - /* - * Temporarily fall back to ifdef ladder - */ -#if defined(TARGET_HPPA) - rule = float_infzeronan_dnan_never; -#endif - } - if (infzero) { /* * Inf * 0 + NaN -- some implementations return the default NaN here, * and some return the input NaN. */ - switch (rule) { + switch (status->float_infzeronan_rule) { case float_infzeronan_dnan_never: return 2; case float_infzeronan_dnan_always: From patchwork Wed Dec 11 16:19:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A718E7717D for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd Date: Wed, 11 Dec 2024 16:19:11 +0000 Message-Id: <20241211162004.2795499-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The new implementation of pickNaNMulAdd() will find it convenient to know whether at least one of the three arguments to the muladd was a signaling NaN. We already calculate that in the caller, so pass it in as a new bool have_snan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-15-peter.maydell@linaro.org --- fpu/softfloat-parts.c.inc | 5 +++-- fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index aac1f9cd28c..655b7d9da51 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -67,8 +67,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, { int which; bool infzero = (ab_mask == float_cmask_infzero); + bool have_snan = (abc_mask & float_cmask_snan); - if (unlikely(abc_mask & float_cmask_snan)) { + if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } @@ -80,7 +81,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, if (s->default_nan_mode) { which = 3; } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3e4ec938b25..a769c71f545 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -473,7 +473,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, float_status *status) + bool infzero, bool have_snan, float_status *status) { /* * We guarantee not to require the target to tell us how to From patchwork Wed Dec 11 16:19:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 307EBE77180 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd Date: Wed, 11 Dec 2024 16:19:12 +0000 Message-Id: <20241211162004.2795499-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 3-operand fused multiply-add operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pickNaNMulAdd() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. It's valid not to set a propagation rule if default_nan_mode is enabled, because in that case there's no need to pick a NaN; all the callers of pickNaNMulAdd() catch this case and skip calling it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-16-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 11 +++ include/fpu/softfloat-types.h | 55 +++++++++++ fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ 3 files changed, 107 insertions(+), 126 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 0bf44dc6087..cf06b4e16bf 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, + float_status *status) +{ + status->float_3nan_prop_rule = rule; +} + static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, float_status *status) { @@ -143,6 +149,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) +{ + return status->float_3nan_prop_rule; +} + static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) { return status->float_infzeronan_rule; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 47bb22c4e25..d9f0797edaf 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -80,6 +80,8 @@ this code that are retained. #ifndef SOFTFLOAT_TYPES_H #define SOFTFLOAT_TYPES_H +#include "hw/registerfields.h" + /* * Software IEC/IEEE floating-point types. */ @@ -207,6 +209,58 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * 3-input NaN propagation rule, for fused multiply-add. Individual + * architectures have different rules for which input NaN is + * propagated to the output when there is more than one NaN on the + * input. + * + * If default_nan_mode is enabled then it is valid not to set a NaN + * propagation rule, because the softfloat code guarantees not to try + * to pick a NaN to propagate in default NaN mode. When not in + * default-NaN mode, it is an error for the target not to set the rule + * in float_status if it uses a muladd, and we will assert if we need + * to handle an input NaN and no rule was selected. + * + * The naming scheme for Float3NaNPropRule values is: + * float_3nan_prop_s_abc: + * = "Prefer SNaN over QNaN, then operand A over B over C" + * float_3nan_prop_abc: + * = "Prefer A over B over C regardless of SNaN vs QNAN" + * + * For QEMU, the multiply-add operation is A * B + C. + */ + +/* + * We set the Float3NaNPropRule enum values up so we can select the + * right value in pickNaNMulAdd in a data driven way. + */ +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ + +#define PROPRULE(X, Y, Z) \ + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) + +typedef enum __attribute__((__packed__)) { + float_3nan_prop_none = 0, /* No propagation rule specified */ + float_3nan_prop_abc = PROPRULE(0, 1, 2), + float_3nan_prop_acb = PROPRULE(0, 2, 1), + float_3nan_prop_bac = PROPRULE(1, 0, 2), + float_3nan_prop_bca = PROPRULE(1, 2, 0), + float_3nan_prop_cab = PROPRULE(2, 0, 1), + float_3nan_prop_cba = PROPRULE(2, 1, 0), + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, +} Float3NaNPropRule; + +#undef PROPRULE + /* * Rule for result of fused multiply-add 0 * Inf + NaN. * This must be a NaN, but implementations differ on whether this @@ -241,6 +295,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + Float3NaNPropRule float_3nan_prop_rule; FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a769c71f545..b4f3f0efa82 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, bool have_snan, float_status *status) { + FloatClass cls[3] = { a_cls, b_cls, c_cls }; + Float3NaNPropRule rule = status->float_3nan_prop_rule; + int which; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -500,145 +504,56 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } + if (rule == float_3nan_prop_none) { #if defined(TARGET_ARM) - - /* This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. - */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + /* + * This looks different from the ARM ARM pseudocode, because the ARM ARM + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b + */ + rule = float_3nan_prop_s_cab; #elif defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; + if (snan_bit_is_one(status)) { + rule = float_3nan_prop_s_abc; } else { - return 2; + rule = float_3nan_prop_s_cab; } - } else { - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - } #elif defined(TARGET_LOONGARCH64) - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(c_cls)) { - return 2; - } else { - return 1; - } + /* + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + */ + rule = float_3nan_prop_acb; #elif defined(TARGET_S390X) - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 2; - } + rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order C, B, A. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } + rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) - /* - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns - * an input NaN if we have one (ie c). - */ - if (status->use_first_nan) { - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; + if (status->use_first_nan) { + rule = float_3nan_prop_abc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule Date: Wed, 11 Dec 2024 16:19:13 +0000 Message-Id: <20241211162004.2795499-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-17-peter.maydell@linaro.org --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index fde64836194..39d80c9038f 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -493,6 +493,7 @@ static void run_bench(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 251c278ede9..f290d523ab1 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -940,6 +940,7 @@ void run_test(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Wed Dec 11 16:19:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A91F7E77180 for ; Wed, 11 Dec 2024 16:27:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS4-0000Ia-NG; Wed, 11 Dec 2024 11:20:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS0-0000GZ-SL for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:37 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPRz-0007iT-9A for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:36 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-434a736518eso77686155e9.1 for ; Wed, 11 Dec 2024 08:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934034; x=1734538834; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8h/sNzFR5aix6eqqSQJk01xGJeoXIpNBM9AztS4My+s=; b=TuWWeRexXXrk76kKkCxLwM4F7eOdOfigWGCsD6P4QgwRMHTG+Ve1KHFAXUP2U7eP/E OlmMvLSQcpcMfgfXVUJuu+jl9M0DmUzSQM1jrmucyw5FnW6DqhwsJYR12hIjxi1sncYk JZToVAKTY8z6AKH97Dv9/FvSIGYTh8gZnQL9+PdGd82hVe45c6Q2nYkPWaqlcPLEy402 nFWLGX6s28JAcw9vnQvM3m/hBEYBy1pQPTkmTH8TYuSq5zX58qgOdoHzup6YlCOWMS/H bHJMRF05p+rLZ2pf6LrLtmOuHUK3y07dX7NQI8SQpuoyKkb+xfO3riVPlmZYXx24hq43 NWPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934034; x=1734538834; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8h/sNzFR5aix6eqqSQJk01xGJeoXIpNBM9AztS4My+s=; b=tw8oFojwqb5rVoXEZnyuHnxfq5ejUZbyhw1MnMsysNo+7nlwpZaw8XdDbnjQiZhqOU aijYsw46Gop4RdV0pvSLIdaJjrOuXXAyvwnjgAGW048/Ig8za/U68HPewGT4E7G1OjjL 8/fqPcg7Lq/eYdfJk+YF9ovzDSdpG4B+1FZ5MUOp1YHHyU12Dgh1qFaQyMVrCCuq6cqi gTEPchySBNGBlNxxw2oQ1P2b5T/SbSfAyS6Ej7L8Jk0Bzuz3FYJ9XG42fPE4WRrt5Psb UIekxzOvTv4t1/8JtTnQ7WXyr4QdNkfKm6+fnbiyrbf4zc8dFfBM6UfdX+22+EkBGe+x pN+Q== X-Gm-Message-State: AOJu0YwiREC0XaoRlG0hv6a3CZNRMFUmxv5d2yvVHCtewOVHcop9y6Pp JI3Xe6bFQ9Idygj+svNBWIVYSuo40a62aaa5L84QT7kgLw5mDVUShkjJVVJcwyVOgtE3jULJmjX F X-Gm-Gg: ASbGnctMPCUdXPRiaIKKXgFfmIMQAlkJk3uH2Qdr2WUala6Kb9zTyeSX+toUU6NIZDj LqL8d4BXK75W30zMcS6h59rxbz66/MwA/TxXLYe3iKYYL0l78eEIcGJJ5sTIluZXtP5k7JBWfZX 7wdPSS8HqhbQAzEiXqm1plnQrGekDXt0Gyxf+2u5PllVHJhI3tprsqDyltVnrbNmajq1fqm/YHX SNEwJp+bEDfddI+1waGNOdvrxJFTNfAx0wQySh+9exlzEkmDfo2jccAYm3c X-Google-Smtp-Source: AGHT+IGiUgtzoA8+arzXkLvcNYtHp6a3gfZSuV8SqjzDcj1xGWPN8trlAwhznSqVYTwDpGxA4tF91g== X-Received: by 2002:a05:600c:4f13:b0:434:ff45:cbbe with SMTP id 5b1f17b1804b1-4361c3c7df9mr32567785e9.18.1733934033839; Wed, 11 Dec 2024 08:20:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/72] target/arm: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:14 +0000 Message-Id: <20241211162004.2795499-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-18-peter.maydell@linaro.org --- target/arm/cpu.c | 5 +++++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ead39793985..c81f6df3fca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,6 +173,10 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 3-input NaN propagation prefers SNaN over QNaN, and then + * operand C over A over B (see FPProcessNaNs3() pseudocode, + * but note that for QEMU muladd is a * b + c, whereas for + * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling */ @@ -180,6 +184,7 @@ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b4f3f0efa82..3a2d0444475 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_ARM) - /* - * This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b - */ - rule = float_3nan_prop_s_cab; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { rule = float_3nan_prop_s_abc; } else { From patchwork Wed Dec 11 16:19:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D30BE77182 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:15 +0000 Message-Id: <20241211162004.2795499-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-19-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 6a2c4b5b1db..37a48599366 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -37,6 +37,7 @@ void restore_fp_status(CPULoongArchState *env) * case sets InvalidOp and returns the input value 'c' */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3a2d0444475..d610f460026 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_LOONGARCH64) - rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) /* * If fRA is a NaN return it; otherwise if fRB is a NaN return it; From patchwork Wed Dec 11 16:19:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB2AFE77180 for ; Wed, 11 Dec 2024 16:44:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS7-0000JV-6N; Wed, 11 Dec 2024 11:20:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS2-0000He-J6 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:38 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS1-0007iu-0R for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:38 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-434a742481aso59513105e9.3 for ; Wed, 11 Dec 2024 08:20:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934035; x=1734538835; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Lo7VMCHiiH9lz9IaE5gLakal324n4TYjmC+cVkhARM4=; b=VWuzXDw3J372qF9uhZGF5RhgaW49DhFXExiWVsPIMFmha4VdXqspBQyfCjRBdvRlB7 8FQ3RhLkfYOeG3Utno5MrqadmrtUnXmD6csSH7tNDJKp8df8bw/poANClRdm/l+m5VU/ WMLzFfBFdWdfLu0NcrFve3WSxlXUGsUVD1cMpv+nGkTY4+iw0ldrnrwhGaFdRJKw1itL WxE9uSQr94OvbzlQwZ3CC0d28zxfENtEIADUYiY2zoRaVA0aT4NxJSMTKohc+uUktR7T 3pnmkSmi3+gbL5dAx4Lo21RfF60wPui3mCWV7ouWLJGYNC/zGawq67a+/vWWO27nNYPP M23A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934035; x=1734538835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lo7VMCHiiH9lz9IaE5gLakal324n4TYjmC+cVkhARM4=; b=oDpdW4VGwd03qWuHnR4PQFPaYU2CI8XJIFPBLT9bny0UeXlTRzsJ0WjJXVRkqbYqX/ d82A2kuwXxop8WGwjZDTx4R1v56WFfFjqzCOO2ouHK/i9nw4ZbvaXwrmh9/+MR5Y4Ctz /kFrR/6VpFUl7372Z7WOHHN4uVt2bAwWKyRZzL5zEy5B3d1vDnTPfm9AdwGrnP1fc3JM aAQVK1Xb206iebsGYGuBLQCccRl5VR14aJYv7Y4aVScNQye6RN1nWXK3+n/ZaQFHSOHI o2SPGmFPXDfwoXngyqZcho74i48VftKkZ34WX0HmLRBMqvqe4ZyLPZxcBGgGbhFxjza/ FULQ== X-Gm-Message-State: AOJu0YyzBOqWjp+0E5kRoroYDXKrT/MObCDYfOK3DjyHlaFvszDmpHkY GG75hWAizli45emRDWlRbzM1U5lSvYGBbAsskamLkJ6l1YyqlpYBUodumfwcF/GbM88ntA5QCAt 2 X-Gm-Gg: ASbGncv2a/MtN9h71jCAxDgN6dz7Lusd7LHO/+UCJ08QAILnblH7dq39XpfzeMEua3X Mh+ORB0DrVth3sSfCYJR5oWOwumSWw4R2aSIEjCW+yyYoz+ih2Sr9sCA03Zv9I6tQv4qtnBK7vf 8ldAqYsrhy8jweGcY4puKhg1IGlR4t9cqoSyJzP9aQQvRpyxDfJNdu4M7obilkgG+R0ffpvHhIt f22WrjPk0HD+1UyddXMqh5sJOcXeqZw/jiW6q/JiD/cuzuoq3sgAGU6/azf X-Google-Smtp-Source: AGHT+IHlIi7VqqJ2r6ts+BLVySRQ3BfFDjj9D2fk17VKus71AXS/NQjwXP0n96IVlMYsRoNX3JnqrQ== X-Received: by 2002:a05:600c:5116:b0:435:b064:7dce with SMTP id 5b1f17b1804b1-43622845ca2mr3219485e9.18.1733934035660; Wed, 11 Dec 2024 08:20:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:16 +0000 Message-Id: <20241211162004.2795499-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for PPC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-20-peter.maydell@linaro.org --- target/ppc/cpu_init.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f18908a643a..eb9d7b13701 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,14 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * NaN propagation for fused multiply-add: + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + * whereas QEMU labels the operands as (a * b) + c. + */ + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); /* * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d610f460026..173b9eadb57 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,12 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_PPC) - /* - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - rule = float_3nan_prop_acb; #elif defined(TARGET_S390X) rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) From patchwork Wed Dec 11 16:19:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B58A4E7717D for ; Wed, 11 Dec 2024 16:41:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS7-0000K2-M5; Wed, 11 Dec 2024 11:20:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS3-0000I1-H6 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:39 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS1-0007jD-WE for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:39 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-434a736518eso77686775e9.1 for ; Wed, 11 Dec 2024 08:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934036; x=1734538836; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lcAFP9saDoRzm67hcihtav0796Gpanslu14kzIrlvT4=; b=kmArW4WldtOYa5I6enP9PfqmzalRogqdIR/IQS3T3dgoPW4IzUCncR3ztlD/2G1/aR NGoEWUxvAiqtIXpRr1p4ye9W0V7oMiBgr0CygkADJ4FEFSUoBjik1U/+aYgoND/o8li+ fmfpv0E5O7ngRaQN/Dl8vIVynuIpdheF335SW6NDAhoDxt3NRN1xSQnyaGQXleYXylWw +kRILpfKdPcQH9K/VvuQq6b2ngsSEvu0ID0af+Sor7sX1LuZpzdiJCU6ZUAx42Y1Fjh4 0iMmqd03Cl+/n721Vzjt24zIfZ/WPjl6PLRK8nTyjv5DMwwfvbfKVSEpEHOWgNJPb37q EtPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934036; x=1734538836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lcAFP9saDoRzm67hcihtav0796Gpanslu14kzIrlvT4=; b=HmfgQKobMBIaU16q/veybYGwCUDKyDOhidFs6A+WICZS8lUm4A+c09pXJ4vrGa6yrw fbx+zQMnuoDRkVPtG70fH17XKp1Pmab937+IZTxN5996RgKy6ez0YIbEfE778j4ZFvUg IqDo36WSt0lzkoY+bZUjJJ14eHzFFQqRCEcEYZTAK0l4Lo3O9mdj+DHQxzsituXnFd6K qrGO4V+93VAAYHCAt63+jGY8GFEC+6icnU/PlUIZ5SKq1ThE7gzCg9bvtbf7zeGTk9ae +xRXzug97dqpOHKfuR3CFAOb5JIIYdDE7EZD54TvJu6qvORJ9r1Wo8U9SFsuWpc6k+Jq z2ng== X-Gm-Message-State: AOJu0Ywg7SXI34tAIeyqhonBB4PHv0Qq+7TXYzQrHg+sIdvQkeI4w+Wk CNckxJtlzDEvCaGH919T81Mmg1jQ0VaNLL2MQvZVK59sxMxlac4Hti8k3BlGqlL0u8Hvwjf1S0Q 2 X-Gm-Gg: ASbGncswL+kmzGRqKXpw3XxH61CsBu213NHeXnMiYlWg56V0BSudtubOpA+l3ES1kcA kCdLDs1hGQtKV1jBxauAk0R6kFpMcJAlniJ/ZEkD8lzw9UWsMdtgEG1q+2hIwx9jVsUQf82FtPi JulaM8XJdqiIribED8yM5n1YC7FBu4vz7Uj89KzMpth1MhacZXicYsptjBaZB1jtWjdu6M4PEZz 0Qq2oTtLh/eI63VGdtSETw+nXFqJNqNv8cjgRpkv3SDERxdk5Q9jr0992Fh X-Google-Smtp-Source: AGHT+IHlK9WFYqz7Mg4NZlPtcMQJUX2ZHEgRIU8qWfr5Hc7M36rVj7uZE6tsZgIuHiXTKnsoBVmNRw== X-Received: by 2002:a05:600c:3acf:b0:434:fddf:5c0c with SMTP id 5b1f17b1804b1-4361c393cc1mr33932175e9.4.1733934036565; Wed, 11 Dec 2024 08:20:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:17 +0000 Message-Id: <20241211162004.2795499-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-21-peter.maydell@linaro.org --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d5941b5b9df..e74055bad79 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); /* fall through */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 173b9eadb57..8a36280df1a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_S390X) - rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) From patchwork Wed Dec 11 16:19:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CA8FE7717D for ; Wed, 11 Dec 2024 16:24:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS8-0000KR-Cw; Wed, 11 Dec 2024 11:20:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS4-0000Ic-EL for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:40 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS2-0007jT-V2 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:40 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-43618283dedso16746635e9.3 for ; Wed, 11 Dec 2024 08:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934037; x=1734538837; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=elThihR9o8htBA19kSW3jQQIVfaQiQSaHPvk+cMrk5s=; b=EvFITmLkbf9/a+6VXSCWi+R3P6p+1Qu/hzAXgVdQbEsDAUby8QEzMYt/HQQff6UXf0 zcZLzOqUUW+S/sRNW2PakzxY/KmjBU95xvmTH5UoNxfJiF/kcp169KuxCyUjMeruGdil 7oAOQlTpF1TUOGPEHT6wq/+1bMMiPxcZe7QVZvf4CEvqTOxZBEJF+PEZxEGZFEecAAm9 OM80TLReaBmmIzMEQBF4BjI0ciIBMDqNkfHZlvAtKuvVWhmJbEzbFhLWe7Vo4H1PDSE6 X3ziIpZ23aSpY5LBsK+XszQoNSDQ23VzbUbfsU0+8EQWhS2RxgZnaLyadzr7XYfygBYd vVmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934037; x=1734538837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=elThihR9o8htBA19kSW3jQQIVfaQiQSaHPvk+cMrk5s=; b=LZW7uRdkPeJpSSKFy3l0IE/Yu/+ox3ithVNoT10jZzF2MKdQ7iq0ZH85nfzghJKyxy Wtr10v0CAaxJeUsCU2MTERZWocDnSJofyBeJUF4vCkb1cx86iKTc4O0I1ttKB5Iqx61m 2ycpu88VNoYJXIkAnAXc3BDAd9dgQS/LOcJNdymJkR2MXTg+sge7l16HrsTgDA7C2GzD L3L3D3gROE3BHbMtV+SCFJawAmiB5d8yjx6er68JuabwaWhO9R0B9ZZ9xAM/DVP3+3XT 8EwtnsY5mC4T1usGGaIo8ymGrfAynO+fq5JojHW9GzGxksjXROyBBABQvkL331BcvDyM s0vQ== X-Gm-Message-State: AOJu0Yw+reL53an6y4NVaU2uEpxOOq0NI01MZPJBVy8eTViv5HT4/NX/ A+zwMj7BOJnOuP2DJDDL+6td19M4VB5Ru+DTmk+Bk+w0b6ZCi1AKWV93YBnDHWkDMdOZjQUrg+F A X-Gm-Gg: ASbGncuo8Azi6NYUsrHsXHHrx+tJMTpU6hPa6GbJ//DeNVo7cYn4PEJPv5DeT/EN1Rn sP93RZkVA++sFsGsoSDfPtt024Wgl3n8JlVV3dvfxcZVMs0klMOEZjBZLDd991SIZd6tD1YNODk +3JYpofPwnXIFPFYcJEs1lV/MDvI3dzsuc10CuNPadG4Hbx5bB4p7Ii/dpkeM2wlY7bK+VnsNrY Czln71wSU5mX1JvwJdkgC67mC+tWyQ5AJ06Hx71iZvGvB7454SqU1L/IZTx X-Google-Smtp-Source: AGHT+IGyBaDe78Wr9sep2EcncJJ7qhKeEhQqq14eN8kgeSBhUv1xJYAiw2XTtP2UsimzoTQB0/s6Vw== X-Received: by 2002:a05:600c:1d2a:b0:434:a781:f5e2 with SMTP id 5b1f17b1804b1-4362282ab63mr3103675e9.8.1733934037628; Wed, 11 Dec 2024 08:20:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:18 +0000 Message-Id: <20241211162004.2795499-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-22-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 61f2d3fbf23..0f2997a85e6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8a36280df1a..c4d8d085a98 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_SPARC) - rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; From patchwork Wed Dec 11 16:19:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C35B9E7717D for ; Wed, 11 Dec 2024 16:51:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS7-0000K3-MR; Wed, 11 Dec 2024 11:20:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS5-0000J6-E5 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:41 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS3-0007jd-Ul for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:41 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-435004228c0so31043345e9.0 for ; Wed, 11 Dec 2024 08:20:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934038; x=1734538838; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IY8zOoALtZnJGd9D02lgKKAFGzmZzVDZQ3xBBMlHM34=; b=zqwNghzmbrwHuZj+5gwNxIyPhJqL+IvyIk3UKTMq1+/odZOtpFk/vkvj+Tm9S7tzdA njDJSLX3Ey8KIYDhBmu/2Yeuh/olSfDsZP+Niz9U2Mkaz+pq2SPn8uNArxQu9/sCFptj rYENTxT9T0q61HoKeTVh4AZej0VwrvoHjJC2DeLzRvran51Pih0KVI+svxCN/Xd2m3ps V1b+reXBA3Ttk9w14Vv/wkjP/ogF9tDaui/k0PirHYTktx1Z4d0tQCB7lz8u/cp0ZHih R0X9talSyC2jVGxGfFJaF/jwjIR3e0VEWedA7dXKgdeg/dSLrbxCYr82uOlBSzC/R+iY 72wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934038; x=1734538838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IY8zOoALtZnJGd9D02lgKKAFGzmZzVDZQ3xBBMlHM34=; b=RMr9ggzxUvNIxNdnjoqqf4GzohTMomgBsFLf/tZbmr0j4r1H55IGDLGXfeUCpT/tLx fxi/DYjK2pqG/LEATWsXFLMZnygEdnZyNK/VJarLFLew6Ssro9IhJHyx2pdHUs6RUZBx 4NdnxKsr66ilLdzWjF1hSZi0K6ImJaqH+hnWlznquueIHCD2O0FHD2stwej1lZEzJbm3 cxcZVudpBMb2m4xWUPdtEGjKA2Ah+iAJ4cSlFh7Nw4c4Ij0dx+i6CMDkDFrQCIipG8Db ZOZtMd/+B176QRolNGiF/WkjEXXuTRPIulzmY17RTVIlI7C5B9Xpb2eotFOfYp6mIudw M2kQ== X-Gm-Message-State: AOJu0YzS8IHM4BnOwQPdb3x9etO1xUvNvNPcdZL4FjHLOnB+xUUK1k5n 3Jx/r+TUlH9mpUK+SislVKCHSuZvhYbgoXqN1fwc9nS2VLOejp0ZNDkWb3rdEKCefH4UrFwlhoY b X-Gm-Gg: ASbGncvM7wvqWxJ/q+5eCn8Zbw0qEBGYi7tESywEn/YFrELscE8dGkrpI2SHIKOTPzP DF6z7OSKScymu6uADsIimoB0rmX6bAXutvmySmhfd6k026Xe+r+lUou3FX2DyIRyCrMbTa3LCO8 8CoMw5TKo0q9I8Wq1Q5LMAbKTDICAlg4sc2x/E3OX+AC1yTgmL0I8F3OT3HxnyTanLDIaSp6Goe sp/lUBrqpj0U049/djxx2d4oaFut5PEoyY0bZAnFa98L+p1hd1c8uWV7oGn X-Google-Smtp-Source: AGHT+IGYD9kPipiYTMlbmMegKbD5JIvjAUNuGQMrGulbALQVopxxnTegzRU4enBocm0rHCsjxQr+8g== X-Received: by 2002:a05:600c:34cc:b0:434:fbe2:4f with SMTP id 5b1f17b1804b1-4361c430b5cmr30266215e9.23.1733934038605; Wed, 11 Dec 2024 08:20:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/72] target/mips: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:19 +0000 Message-Id: <20241211162004.2795499-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-23-peter.maydell@linaro.org --- target/mips/fpu_helper.h | 4 ++++ target/mips/msa.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index be66f2f813a..8ca0ca7ea39 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -29,6 +29,7 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); FloatInfZeroNaNRule izn_rule; + Float3NaNPropRule nan3_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -44,6 +45,9 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index cc152db27f9..93a9a87d76d 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -66,6 +66,9 @@ void msa_reset(CPUMIPSState *env) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->active_tc.msa_fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c4d8d085a98..28db409d22c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - rule = float_3nan_prop_s_abc; - } else { - rule = float_3nan_prop_s_cab; - } -#elif defined(TARGET_XTENSA) +#if defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; } else { From patchwork Wed Dec 11 16:19:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A01E77180 for ; Wed, 11 Dec 2024 16:24:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPS8-0000KA-9E; Wed, 11 Dec 2024 11:20:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS7-0000Jp-2J for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:20 +0000 Message-Id: <20241211162004.2795499-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-24-peter.maydell@linaro.org --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 -------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index f2d212d05df..4b1b021d824 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -62,6 +62,8 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, + &env->fp_status); } void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 28db409d22c..67428dab98a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,15 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_XTENSA) - if (status->use_first_nan) { - rule = float_3nan_prop_abc; - } else { - rule = float_3nan_prop_cba; - } -#else rule = float_3nan_prop_abc; -#endif } assert(rule != float_3nan_prop_none); From patchwork Wed Dec 11 16:19:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D0D5E77180 for ; Wed, 11 Dec 2024 16:24:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSA-0000L4-D2; Wed, 11 Dec 2024 11:20:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPS8-0000KV-Cw for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:44 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS6-0007k7-Tq for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:44 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43621d27adeso2074495e9.2 for ; Wed, 11 Dec 2024 08:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934041; x=1734538841; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=klkjETkK46JGPy4cr1z4ranKH2QbJ9BDEJxJzYH0IXk=; b=q4qWPh94sCdPCFM4DBiNt1lhYJqFAAn4xD9CfEBrEpR5nKv0RtF8l4XgQKMiMZG/Nv ndpM1FkMZmZ3Dx3jBbe6/zZExI7dC7Hponu7bg3LI0jA3CPoAbPXP+3n/R416ftMrvbm /1u73rjqt54z0VW9VwbSkNdJHKJ/TM7omsStlCrr0EngZE6BFrWqNAay9SkkEwRuRTw8 fh8eH+ucq0TpnELrGjdkwX/IlW3jpIHQp9C1YnL2FKllrPZWZrrKolSsJ2wx7avd8WI7 YwbbqTQVf6kyfY57SzdM+TpT61sZI6Kq9tup5mfiOeQrAM/YE2MxHZSdnb2Hm/mq9JVG kYOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934041; x=1734538841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=klkjETkK46JGPy4cr1z4ranKH2QbJ9BDEJxJzYH0IXk=; b=TylJQ10qcWixTlbrEtjJ00FnTG/KPvrXnRQu4+XJy24bMQibnQgeJZ0cuDQbknCj5B meh4X6Wq0A9ELps5focMRhMcyiwKziFoWmwWtxgfM1b4a/oAEBxyFn3aZbSM9tx1GGtv j3JVY3VtQs5tKaiRZoKk/uNs2k/u3unJVFJb5hyJiGR/fPHfmfHvfejfsYH7mbc768SA DR7SvruLMEDxJjvcTXSCWnBb/nEbySWo5MQK5TLu/Zo+aYWFhZnjb1u0zUtRZ96LAG/h MMYyVKbwm/eobqG9grPYnSo6ATzGxUPhKGb7nM4XB3h82vlQli+3MZiJHia97HjCbXX4 Ibgg== X-Gm-Message-State: AOJu0YzDp2jSjgxh8D+iWTuioDDEA1kaIe69ZkjNuYEws/F8TPnXtyZt /qKh2I6Sd3tmCxbJzWZnS9AxnNBm4kwwL/2qxSbsG7TlpiEed329sF64yfioq+3UGF1gRfIN1m+ B X-Gm-Gg: ASbGnctTpj6jHaUXdrhp9K9xUXwtHdr6JxgR1Pjo3u+u1Js6C0DL51EdpXBmejNXg7k 2gLbMjOIY9bPpmwynDjheP6TDOmmlQLJlxw4RtjayYcHb+/7IvfhZ5hq6FGuQDxmT3hCGcLIDw9 aRMSnUQOngnoLj0M/l7b+8oU2cKN6BJ1SuY7Zl15n/05m0nl96PcPb8Y+fAGew+A9Vz8F/pGae8 FcxtQTaQqNgc+vlI+UK9YSb2SDo4bVeW0/MTfPiRJ7qY4tzif/PfDTd3GEs X-Google-Smtp-Source: AGHT+IFQE0RJDaztCcgLF64vEcbBGI9BO8Eo66BkUXxZ/4ZzeMrWkZw/u0ESYgGWRor+BQV1DgXttw== X-Received: by 2002:a05:600c:3109:b0:434:f335:855 with SMTP id 5b1f17b1804b1-4361c441e47mr21076895e9.28.1733934041313; Wed, 11 Dec 2024 08:20:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/72] target/i386: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:21 +0000 Message-Id: <20241211162004.2795499-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback; this is actually the correct per-the-spec handling for i386. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-25-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 3295753e075..4303b3356aa 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -180,6 +180,7 @@ void cpu_init_fp_statuses(CPUX86State *env) * there are multiple input NaNs they are selected in the order a, b, c. */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) From patchwork Wed Dec 11 16:19:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A739BE77182 for ; Wed, 11 Dec 2024 16:22:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSB-0000Lu-VD; Wed, 11 Dec 2024 11:20:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSA-0000L5-FC for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:46 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS7-0007kC-Pw for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:45 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4361b0ec57aso12767135e9.0 for ; Wed, 11 Dec 2024 08:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934042; x=1734538842; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3myRINrKnQas6bU6fv1OR23zH4Adyf999B3PUNZnQ7Q=; b=Gjuf9Ml6Ui5L9NM1cajl55/8r3ugGLUJ0nWAmcjC2h31ljbFpeB7lYViE6XMu1mHRH ADEIo0j9NwEBEdVCkzExkhZdq6obvK8eCr0X1TiHs4lJay/bO4UtGI7rFUvGXq+A4MF+ fF35A5hrbrXV4VCo16Tbr+vcfLDau9UZn0Mzpd20G+/jfUrsbhsJH4XHKzsoGbSSRTE2 TorfSKjb3HNODnV3Dnyn+r6f/X5cU8CfhJa5L2xayHm37hrKjmhEuxhiT34rxnuseI6c vyJgwn2UL8H+1YwJoeT/SZX33KoZXZqjDUi025enpWkxY76Dw1EmFKFTz+D60pen/pUB dDXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934042; x=1734538842; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3myRINrKnQas6bU6fv1OR23zH4Adyf999B3PUNZnQ7Q=; b=Uq80389bKXIuvji49QodIVK8nRhhBLV9XAH3RzevT/RXgbXC5j/Rd7wl5z1a32Trz8 4y3lOrmus/AEQXGc/kjgC6C4SzAuoApUtn3HexHkeSFJIBTDRIkR7p2UcTka257MXrcY HDNxjpLGZJGnE+KPex0w+cTnZTOuQqDQf1v2/EBOpaxT1lt28vKI+OSTqg9Y9eX1Z2Gq +wEehrc+J+xY+tDjMs1RKYjyjUkr26/JQrQ0qwpTlqvbhfHt2ZTkp6QoHGaHXsslivYt olDxBeXDE5f/m9BwZ7H9pv6+dujHjPOzgpIM3/IRydhRi0DDphV4QlrG7q8JvrZDgZxw MTWg== X-Gm-Message-State: AOJu0Yw758lDiy1lleWYfh6v2rOFU2vSCd40v9Dvgo/UZJFlON+w0eY1 eKt1PdnXFWXzvpr0hlHYM5H3dpsXD7Is5m4mi1aniJhzv0RlwZ+waOLVj781YkvidZCpiR+RbEx 8 X-Gm-Gg: ASbGncsNmYGgQX/8lq0a1rtTkOjl3LjT0hCOPJFxZXsWODLSiAaCCfKi4T2VMazl/Gm 2ehelipwM2Zf9rQvvx3FvlXmXp3spTYty4RPT//2wxdxU8EN0j0t9eg6CDqJpRwCRt9TBx33bFL a1RZWhWo6mBresEE9BIKd//nWBAGA9WY+ShXC1FLhLAjEw0zBuZHkwiUz6TZ6x78+y+2tvoB4v+ klKgsiruwd3T05GpzwGS9FXPbqvD880i1drlI+u9CEqxfKdMLNELgi+PWxY X-Google-Smtp-Source: AGHT+IEq2dBx7lNRjY88CNf7LqhOf1y2krPpozZp6PR0HieNaAAIoFcPmQ2OCJMgfKWv9pQZ7dJdAw== X-Received: by 2002:a05:600c:1e0b:b0:435:330d:de86 with SMTP id 5b1f17b1804b1-4362256d085mr3832545e9.0.1733934042275; Wed, 11 Dec 2024 08:20:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly Date: Wed, 11 Dec 2024 16:19:22 +0000 Message-Id: <20241211162004.2795499-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the ifdef fallback entirely now (allowing the "rule not set" case to fall into the default of the switch statement and assert). We add a TODO note that the HPPA rule is probably wrong; this is not a behavioural change for this refactoring. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-26-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 4 ---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 393cae33bf9..69c4ce37835 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,14 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * TODO: The HPPA architecture reference only documents its NaN + * propagation rule for 2-operand operations. Testing on real hardware + * might be necessary to confirm whether this order for muladd is correct. + * Not preferring the SNaN is almost certainly incorrect as it diverges + * from the documented rules for 2-operand operations. + */ + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 67428dab98a..5fbc953e71e 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -504,10 +504,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } - if (rule == float_3nan_prop_none) { - rule = float_3nan_prop_abc; - } - assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ From patchwork Wed Dec 11 16:19:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 873D8E77180 for ; Wed, 11 Dec 2024 16:22:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSE-0000NX-PZ; Wed, 11 Dec 2024 11:20:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSA-0000L7-GS for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:46 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPS8-0007kM-QX for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:46 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-435f8f29f8aso13109345e9.2 for ; Wed, 11 Dec 2024 08:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934043; x=1734538843; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lRJiit52f5redlFxi2z3tbKksS9bryLnGPt7oPWvzf4=; b=WpFfEk0rPbrsbyKKT5O8ghIn+v419hyksvspTIqLrw1G8tXQ6aw3jValVKRqmOdatw 14asKTgKUQGQlTqAd6UbvNTWMsqgtuzyebQxfOcK+/S+vlEdOykMpUhtxSvyqmk/3Auf +n+K9wCDf8U+3/JuegwsO+UkYtAI1aUGHeDGLmKzKt1X9Qi/NAkt3KOmBn8rTBWnPmqU CBJENw0ccF4eN/UwcqFkUnaqNJ9gzc4btZANdg7Qm4R32VdygSrD+e/yuR0kgnAZAPKN 5igqYT3pKnV54Ag0ITUI5tglJrJBrMT8dPM1tXEhcoDoXjOyGv0ufdIEx0I0AdD7Rihf q7BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934043; x=1734538843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lRJiit52f5redlFxi2z3tbKksS9bryLnGPt7oPWvzf4=; b=SnuFZEq1vnhvFQP2lgN/jkGO8mCOfuCVB+SYLCIi/QUq5FY4enVUkjGTsj+Bq4kg7W 2HmDPIraPz4qaGXwm8TqAr6l1kjIS4yhGIzeVsSUNYSGuOdgiesVOUUFjrjjR0u+yc+4 /1yLk9Z9/6kJmXtMgwBIFoo0vMNqQ9GkEf1i91pA7uKB5VlqXHYjjqEDAyeDdlfbkKVr XHMTUlpaLiJsTwjNC9/4hYfjOMy9fWihP3XYuS8crDtkbCLf2JsFvbUqk3ptxRyLfpi9 5tv3ZuJgs56Zr2HqOy38NuS3ZLFHbT7IDgIsilS6tP1PnsZJUqv8xF0sI4MY+uv5+L6t oOlQ== X-Gm-Message-State: AOJu0Yy6oHk9YqzKEbcj/zeBZJrR9zqlRshI5ZLUWxrBYjVosAG4BErj b921j145kGXJe2HbU7ZhvCEUVufZekng5CQ+OX8/3BABqca3DqVHOrXGsuXqBL37ktYKE27jS9a o X-Gm-Gg: ASbGncs2yHv+H1pDLHeR+7Pn0c6L+J+zhL8sBQAlz4facsCiTbMLKeh56+jEYEfOwS0 JIHunRXFptW00vEKCJmCN3elPGnAZRRWrTPUxQaD+5HTphJI+n7SexhfxbkPFP1AD4/ebrejEQr wsW7Yh9CpXEIo54t2S75bqT1CSbyTSaViqWNJAne6Q4Uqz27Rv7I5xL6svxmg7IY6k6BG/qwvJx CduVtyU7mjL8oAYjz09rYZOzTBZ52OAm5xtyWePtTV975R8TnFPy71whqdm X-Google-Smtp-Source: AGHT+IEIqQMUMC0Nwx+cFm3rDUovTqBfmGq/iSOyqalSgzGVrTHBYb5LRHb7XRT4v/5+2fwPhLFdfw== X-Received: by 2002:a05:600c:1d20:b0:434:a529:3b87 with SMTP id 5b1f17b1804b1-4361c36f5ccmr34039695e9.10.1733934043288; Wed, 11 Dec 2024 08:20:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/72] fpu: Remove use_first_nan field from float_status Date: Wed, 11 Dec 2024 16:19:23 +0000 Message-Id: <20241211162004.2795499-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan, because there is no longer any code that reads it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-27-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 5 ----- include/fpu/softfloat-types.h | 1 - target/xtensa/fpu_helper.c | 1 - 3 files changed, 7 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index cf06b4e16bf..10a6763532c 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -113,11 +113,6 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } -static inline void set_use_first_nan(bool val, float_status *status) -{ - status->use_first_nan = val; -} - static inline void set_no_signaling_nans(bool val, float_status *status) { status->no_signaling_nans = val; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index d9f0797edaf..84ba4ed20e6 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -309,7 +309,6 @@ typedef struct float_status { * softfloat-specialize.inc.c) */ bool snan_bit_is_one; - bool use_first_nan; bool no_signaling_nans; /* should overflowed results subtract re_bias to its exponent? */ bool rebias_overflow; diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 4b1b021d824..53fc7cfd2af 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -59,7 +59,6 @@ static const struct { void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) { - set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, From patchwork Wed Dec 11 16:19:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C817FE7717D for ; Wed, 11 Dec 2024 16:22:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSE-0000Nc-SD; Wed, 11 Dec 2024 11:20:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSB-0000Lm-Nt for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:47 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSA-0007kg-93 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:47 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4361a50e337so11081045e9.0 for ; Wed, 11 Dec 2024 08:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934044; x=1734538844; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PQNG0n9NXp4YCePXcFiDn3lq3sTBy07a0OMkjgz62Dg=; b=RV4aXd6oVb0WVa0Ty7yxIusirNNcLOQuvXWR6rWBILzelVvJB+MLkdLjnwNpBB9KKi bPyo6bbFDREzlOJBFdMjXuG94Q6ePrEpMd52x7zbN0XkhoNlt84SCDkzU7LwqHXs4LBK io3f+9WsraXUwVFWmbiVIYODLDuTK6y5QQPNmtKSC8tNyi/IKeAvP46tXY48X3zv7Srq r2uonUD6EjBHPOBrYN3pMJcavoU1g+cNKPFwCEIxVyrf6BHYvgHRvkRMreHYQ9ek71R0 j0rc2jns5VewDaTNipfr4+GLtPy6OONuKn8EGecGfOAgPMCUASafBHOJ/MhLvwa/6L4w TP4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934044; x=1734538844; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQNG0n9NXp4YCePXcFiDn3lq3sTBy07a0OMkjgz62Dg=; b=afMqszqWQ4bLMrzZphbrrUex40/gjzvcHxG9vt3CwDqldhHvcMny/Ogb+VO8IaUpqb 6FNLvrc78JdCfgS43+p68VXxvL+Hyqfpalke66mIShZCZ+JUvYVfR2EX7wRymF7ZWhjD gPQ1tt9t6QtiWQCsqSOuKci+qD28zslMfRWg+Y2CZ8dtxRp8VI4hPqUot8yPY/dxNdBV wgzjVGlcFJHbtk0fvER9DXV9Uvnysgq/gxa7v36k1+sqzubry8NP2bTLDXNhUJapnofH Kzalbpu80eu/vBnXBAeZOMp60gbD+lwMb15U/Ik6meHO4beDKNgIuuVwC4L4Y//72ftW Wgug== X-Gm-Message-State: AOJu0Yzbmiz3CHgQWL+1MNu0WkEqjsLPkx5T892tYZF8IsAwwK9y/jrn 0c1nGZrwZ0W//jvzCJzlVFrdD6cDFfWvxpOgUJZ5gn547KvhVDE1ytgFXv6mNutxDw+x9fI+/hQ V X-Gm-Gg: ASbGncvNnmH2roH9/mllPn09pjoayxZWrSzLkzlbwOvI0Wji0Hb4hMVwYgXvRGRZ3JO i0HBEbIdVA3o+tT0bRGmyYX7RZx4K9VNuU3FVDiCxgNDC5YWSztgixCDGRFdjSX6RJ3pH8Hoh5E rvexpTmhrdfTnAKiyL9D5Ri/pulGooA5lsAJAR8tkcKBLkLNjsR4ffpH1KSQol/EgMqCwQTjvi5 dL1hKUdxvpzyL4ZznSmMILN7Iym7vvzA3BnNzFtsxW3sVi3Xn0ivwyuSfxz X-Google-Smtp-Source: AGHT+IEdIQiUrZIYja9QH+zoTtxMLbB4W1ont84ve0ojlABOwwVHlYTPaK3yLtRHgnhDKSmSglTzaQ== X-Received: by 2002:a05:600c:5122:b0:42c:c401:6d8b with SMTP id 5b1f17b1804b1-4361c38d8edmr26397295e9.7.1733934044326; Wed, 11 Dec 2024 08:20:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan() Date: Wed, 11 Dec 2024 16:19:24 +0000 Message-Id: <20241211162004.2795499-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) to get the NaN bit pattern to reset the FPU registers. This works because it happens that our implementation of floatx80_default_nan() doesn't actually look at the float_status pointer except for TARGET_MIPS. However, this isn't guaranteed, and to be able to remove the ifdef in floatx80_default_nan() we're going to need a real float_status here. Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status earlier, and thus can pass it to floatx80_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-28-peter.maydell@linaro.org --- target/m68k/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558aa..13b76e22488 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) CPUState *cs = CPU(obj); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); CPUM68KState *env = cpu_env(cs); - floatx80 nan = floatx80_default_nan(NULL); + floatx80 nan; int i; if (mcc->parent_phases.hold) { @@ -89,10 +89,6 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) #else cpu_m68k_set_sr(env, SR_S | SR_I); #endif - for (i = 0; i < 8; i++) { - env->fregs[i].d = nan; - } - cpu_m68k_set_fpcr(env, 0); /* * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS @@ -109,6 +105,12 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + + nan = floatx80_default_nan(&env->fp_status); + for (i = 0; i < 8; i++) { + env->fregs[i].d = nan; + } + cpu_m68k_set_fpcr(env, 0); env->fpsr = 0; /* TODO: We should set PC from the interrupt vector. */ From patchwork Wed Dec 11 16:19:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3293AE7717D for ; Wed, 11 Dec 2024 16:26:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSD-0000Mo-1i; Wed, 11 Dec 2024 11:20:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSC-0000M2-AU for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:48 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSA-0007kp-Lb for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:48 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-434ab114753so46291045e9.0 for ; Wed, 11 Dec 2024 08:20:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934045; x=1734538845; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gHqtgcXwaXzVvVdsrCBhcuw/gjNtZbZ0W54PPbBKVlI=; b=wR9HS04S8ZIam90w+foN226+sn5clRA45Z4F/yJDhk2+LXe1CCXyzuELjOS/rcl59S hIiG7/PS1jetZSmJXW5ZSaeCHvgZdBv/Xe6sZKLYwWyqhuHqbmD+hqYHjviknwlu9qul 6gIdYuEgsX86XBoSh7JyV8cNAt02xEdBW2EbDdtd1pM1SiKEmamwXqEjJhhRFIvOXzi3 FCtYkZwH2sNzdzVkSw6qv1lXAdgER+yFWP5ibNoAjGFZcWNi/obhqp+XtyyeiyCrJM2d Lbx+9NqC1eu/cRehLXDvpAkOFWTXdS+cemYuQJmIXNypqZBNtLW3B6bYIRtwOIPiV9nU Xr8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934045; x=1734538845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gHqtgcXwaXzVvVdsrCBhcuw/gjNtZbZ0W54PPbBKVlI=; b=VF7L864i4+ssR6IxmXtOMe93iI/Nf4ntfEgUK9kUtnfQ75IAk4PFYtAfFq+je5NCKE GDqsi/ZXnFWms9SUpRrLBxdJcmAcEAs7KM7wwDC0hPKCj8qttUoAhRuwype8yp3XB1z3 F0Wuf6VAg1U0B2kQpmMFa/n/XQWveTSKdG5JOWkVOub1uHg1aUHH/1fmcJUU5pxHCk9V dNOUU+L9CeEb5lgYPWzXov0xhC9s8COotOy6Q3tamprrpXkXyJAVshwUoOePqkUgLtot hSH8QIp3YVACUmvFAlNWA2DRlksJioVjtGMKnx59ISWwY/boU8UDPWA+rX2zk4xV6/KX wCIA== X-Gm-Message-State: AOJu0YyfwgzMJ5CuRtLKzhkVjSsPvqaqfxlNB/QPD8RmP/s1VJGisa2o 5QwwnMweoMem6uTXQVDuMprT6umAKS7ZXIyIRm7vfA2Uh8sp3lFerDvOp3K/3VEWD9nnxrew1D7 v X-Gm-Gg: ASbGncvSFHY92PYujctOsiIN+2K+Rw9h7IjwjT0OVncyK1EAZhTqGP9dX7lDm6kdwdG 6CF+HmSrm5v+leUC+IMvdIU8Wt3Tv+77CUiS94b25EjjWXXLxrQaHeD+S5wyFr8YyJC5qgl+JiK g28pO48Rwcc827HX1cKn+ym+vL9Wl/obgDNrRD4iABGtQQY3jy2YRRogB0ZzhqJ/+EMnz1moVe4 Knd8a79yGb0NXmhYiUwwxBkA0CWvFLIdugOmxRSL59VmGXMiPM3+uNHHO56 X-Google-Smtp-Source: AGHT+IHtrwz2LUY9f7DYGq8SMxTQSn7blz5yzVFyX+oxfkbj/mfPGZrx84ALjbjaEwXQFvanRezRLg== X-Received: by 2002:a05:600c:3b9c:b0:436:1af4:5e07 with SMTP id 5b1f17b1804b1-4361c3444a2mr27137875e9.1.1733934045309; Wed, 11 Dec 2024 08:20:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan Date: Wed, 11 Dec 2024 16:19:25 +0000 Message-Id: <20241211162004.2795499-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We create our 128-bit default NaN by calling parts64_default_nan() and then adjusting the result. We can do the same trick for creating the floatx80 default NaN, which lets us drop a target ifdef. floatx80 is used only by: i386 m68k arm nwfpe old floating-point emulation emulation support (which is essentially dead, especially the parts involving floatx80) PPC (only in the xsrqpxp instruction, which just rounds an input value by converting to floatx80 and back, so will never generate the default NaN) The floatx80 default NaN as currently implemented is: m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 These are the same as the parts64_default_nan for these architectures. This is technically a possible behaviour change for arm linux-user nwfpe emulation emulation, because the default NaN will now have the sign bit clear. But we were already generating a different floatx80 default NaN from the real kernel emulation we are supposedly following, which appears to use an all-bits-1 value: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 This won't affect the only "real" use of the nwfpe emulation, which is ancient binaries that used it as part of the old floating point calling convention; that only uses loads and stores of 32 and 64 bit floats, not any of the floatx80 behaviour the original hardware had. We also get the nwfpe float64 default NaN value wrong: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 so if we ever cared about this obscure corner the right fix would be to correct that so nwfpe used its own default-NaN setting rather than the Arm VFP one. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-29-peter.maydell@linaro.org --- fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5fbc953e71e..9f913ce20ab 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -227,17 +227,17 @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + /* + * Extrapolate from the choices made by parts64_default_nan to fill + * in the floatx80 format. We assume that floatx80's explicit + * integer bit is always set (this is true for i386 and m68k, + * which are the only real users of this format). + */ + FloatParts64 p64; + parts64_default_nan(&p64, status); - /* None of the targets that have snan_bit_is_one use floatx80. */ - assert(!snan_bit_is_one(status)); -#if defined(TARGET_M68K) - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); - r.high = 0x7FFF; -#else - /* X86 */ - r.low = UINT64_C(0xC000000000000000); - r.high = 0xFFFF; -#endif + r.high = 0x7FFF | (p64.sign << 15); + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; return r; } From patchwork Wed Dec 11 16:19:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA370E7717D for ; Wed, 11 Dec 2024 16:24:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSF-0000O0-BC; Wed, 11 Dec 2024 11:20:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSD-0000Mq-3S for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:49 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSB-0007lC-Ie for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:48 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3862d16b4f5so545897f8f.0 for ; Wed, 11 Dec 2024 08:20:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934046; x=1734538846; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jSuOu2n5x/+mHXTv9G32cuk510bUbTH6keT/6j4dWJk=; b=VP59xEBmncdJDStrrZo4x/oPBIClc5vGzMSuTGJ3BoKx9eqz62TPj8Rg4Lj/fjULuC RZfbkVXrnH7QqN8Cc3j5BJqidB4gezC3i8fjSp7oz6IlNXFwz7HByy8YuajF8d4rEpNf fB5CRCn02GB8hmxzTn1rhcafGb2+pYl2fcrZU6tG411/N74a53ucMvJ5fwoOPxb3DYpK GiWJsCMwxXmChmMijNydbaiaRd2qgEmY9SUcf0F57YOm3vrRpa5mD5Qv/0GXIq1tlZXl xIOzfBL5Wtyp0IC/902pE4whB6dXTqvTWpA3DWT3P8a7saQzg748BCNhnO7NMLyrWpC9 /Aig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934046; x=1734538846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jSuOu2n5x/+mHXTv9G32cuk510bUbTH6keT/6j4dWJk=; b=Wt+q89TseUUiooovrMs1tEiLvfagUUBeO9jw50XYcHdvFGZHjLHpA52LcCQ57eh2J4 Z2g6LtpxM6toAisQ/4V6y3xUmeCWxjx0dRP4Y9EXx7OUIb9UPAlstxNh3YBII6U6h1Vr GiSCCkxLWVW8Xwi61RGVcuOkHffA5Rf5HcQGTwJRmxo5AvGA0VV6PEjQFZXTGg6dIiAr zndn1IRNiuO/GjRc45/5ilv7Cd4WLOr8fCmHv33s6GJdmGEQIczkNzwwbaJ2blXhGFa6 O1eXEAU/3e1SrHK1Pg/0dDXlhqdnHEM0nigqXgVrGLHJqk7QuVLkNO1d2u+rqUqiufoI rXTg== X-Gm-Message-State: AOJu0Yy3pmFQ1qe9mzduLvh8uhiy8EGzsS05cYazciYdvXCVU3zFjh5q guNcjLAFdFE3qk4dk9NXxrDhSj9xypuV0d9d0dBTpzyKAgVSNmKWm04vFGm42IrQQBjOxn+VhYp n X-Gm-Gg: ASbGncsG2XxzgZJQhacGCw7rEPi6rsDJJ87rBjrz0sH3h5+v9vLjg6Hf/sii9jre1Ir ppgqwt5cMLVC4d3X9jiBpQcLLABPkl8ZhNx6AB6ab37UuRKSBOIs54DjOTI8yWOXp92ftfIkWcZ TvO6TLrQR74gxeZ4JV5qVyWSQutpyNCgQ6A3cIv8TWLn6q6I1w/cyO1e9ftn5nyaLW7jktD9aF9 SKFWDy6n5drr5z5HWAj4wPlCUrevxOsuoakE+q8RswEQzeQRCWasbLUlWZV X-Google-Smtp-Source: AGHT+IFs6i00E1V4Y3ueYPMb6K18RaWiU6pPPVjNRpjsaKZ+xZQxej9u1yCMzn4PjHSGSaHVaoWQsg== X-Received: by 2002:a5d:47aa:0:b0:385:faf5:ebc8 with SMTP id ffacd0b85a97d-3864dedfe22mr2254661f8f.21.1733934046202; Wed, 11 Dec 2024 08:20:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers Date: Wed, 11 Dec 2024 16:19:26 +0000 Message-Id: <20241211162004.2795499-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass a zero-initialized float_status struct to float32_is_quiet_nan() and float64_is_quiet_nan(), with the cryptic comment "for snan_bit_is_one". This pattern appears to have been copied from target/riscv, where it is used because the functions there do not have ready access to the CPU state struct. The comment presumably refers to the fact that the main reason the is_quiet_nan() functions want the float_state is because they want to know about the snan_bit_is_one config. In the loongarch helpers, though, we have the CPU state struct to hand. Use the usual env->fp_status here. This avoids our needing to track that we need to update the initializer of the local float_status structs when the core softfloat code adds new options for targets to configure their behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-30-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 37a48599366..aea5e0fe5e6 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -359,8 +359,7 @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) } else if (float32_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float32_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } @@ -378,8 +377,7 @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) } else if (float64_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float64_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } From patchwork Wed Dec 11 16:19:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E78F9E77180 for ; Wed, 11 Dec 2024 16:25:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSG-0000OK-CE; Wed, 11 Dec 2024 11:20:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSE-0000NK-7e for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:50 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSC-0007lR-Lw for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:50 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-43618283d48so12310835e9.1 for ; Wed, 11 Dec 2024 08:20:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934047; x=1734538847; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GJ2MxfIn+bPI815lGa0YYGJVtmHJ6iQzs9ubSygVReI=; b=CKD0pyToKz8Ks8RSiTY/CmPYRr/AG2YmNukOVTtp3o+bZeGGLNvYrD9rfFVUIW89MK jHV7H6QBBuezFCy9xXunhE9i4NOAgW0AVcf5zVndWy8LWKxj7xgjfhQqvlKUokB+NQvs vbXyaYTBoXhMdTwHm+O4dy4CKBn2SkwQFcfgkT/EMWFbm7vkun9Cn9dZPYYGHCmcYmwn 78MfS93sfJ9XF3wKVb+yM2J+dOhHA8iEq1mjf+Jxd2ulJlHVe4+rn8sS2QbrEqJlpxoS X+EvmdWw1NZqDG/W8mdohVtrE/gjXyEHsK4zIIiL74FxfJamwDq4hiMCI3zXXwDS4Ztz RfRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934047; x=1734538847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GJ2MxfIn+bPI815lGa0YYGJVtmHJ6iQzs9ubSygVReI=; b=qv1Agj8Ndl0VacNwQu73U/ZTyxL5pjpWPpwp/CLQ6NvNmogEo5KazBBNDLKRH/FPgN 6i494/2UA5PnZ9fRpTjDyf5lrZTsyjVfBa0Q9/lNpe+nK4l8DPBaD4HV9IU3T8f7tDxn 2QYQy3oxWfiIRJOhKfRiGZeJUmMKbKELnt3eDtBvgjXzeECbxL2ObUi+aykHBn7YtaAZ ffqKOVlK0lRydeznZXycbMxkzNxTj24nyKe9VosN7rZ7eUi7HLno+Aps8buwAWx1Dn6Z Eitgqf6HFqEjQ4vorsXXL027rR4hxlsTHmVET36NWHNXCXqKJrwZjRIaqVBsdSVGE5U5 LhBw== X-Gm-Message-State: AOJu0YxvXoif+EAAU0ucqoxh+L+9OU+J5tJASgA/Vw51YbVx6Nyd8D89 ljp4VMmVQgbLZBQld9sYEfKUIdOq8tyHqLQaLMN7HJsRjb1mEK/ZryXdvFIe6NVdIzqIBjYk6Wp U X-Gm-Gg: ASbGncsvIb7HL6FLBTNlvwTIAwK5KAn651+fT0CK9L51DzaKCFlvyUn2YE8p1yQt+Qo 1Z23nqjs01UHejzdyOVV8Gs2GIervC6kxpL++Dwhv/5h2+0enHG7xaiBzB72OzDhji++KfEJkBl RkFx/zD+hmLPFERQy8j1L0TJsoUV7wXAPjenPGUl1tO1zUppf3q5ejJ/TbOQcR8CQ8LIYYll8SB alEcTKyz3v7gXdpJyf2DX3NYLgx4i61CDdN4glAkT3U4Qzgjl3BokmD2Rxk X-Google-Smtp-Source: AGHT+IHbNwGi42RPHzPeAaV49J8dicMj7ttfd4ajM7NNaERdDyTJxMh7R4KmYLPDXNvJqGuhIl91RA== X-Received: by 2002:a05:6000:1565:b0:385:fd24:3303 with SMTP id ffacd0b85a97d-3864cdeb18bmr2513796f8f.0.1733934047296; Wed, 11 Dec 2024 08:20:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status Date: Wed, 11 Dec 2024 16:19:27 +0000 Message-Id: <20241211162004.2795499-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the frem helper, we have a local float_status because we want to execute the floatx80_div() with a custom rounding mode. Instead of zero-initializing the local float_status and then having to set it up with the m68k standard behaviour (including the NaN propagation rule and copying the rounding precision from env->fp_status), initialize it as a complete copy of env->fp_status. This will avoid our having to add new code in this function for every new config knob we add to fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-31-peter.maydell@linaro.org --- target/m68k/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index a605162b71f..e3f4a188501 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -615,15 +615,13 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); if (!floatx80_is_any_nan(fp_rem)) { - float_status fp_status = { }; + /* Use local temporary fp_status to set different rounding mode */ + float_status fp_status = env->fp_status; uint32_t quotient; int sign; /* Calculate quotient directly using round to nearest mode */ - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); set_float_rounding_mode(float_round_nearest_even, &fp_status); - set_floatx80_rounding_precision( - get_floatx80_rounding_precision(&env->fp_status), &fp_status); fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); sign = extractFloatx80Sign(fp_quot.d); From patchwork Wed Dec 11 16:19:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F33CBE7717D for ; Wed, 11 Dec 2024 16:25:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSI-0000Pi-Sp; Wed, 11 Dec 2024 11:20:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSG-0000OH-5C for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:52 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSE-0007lh-Lj for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:51 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-435004228c0so31045765e9.0 for ; Wed, 11 Dec 2024 08:20:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934049; x=1734538849; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+U+8i8q/4gXE3A3yYLQmyNCA5wUq2DI1uSwKXqmKO3k=; b=hJePzYhzrZ2M69iwOF+slc5pXWWiOjZNYiURPs6P2JXo0rvIJNtfkwhtxVlxcGql6d viync8E3ZniH53oqVqa9SYs4hIqV8Pqy/MRJNd0y1XGioFGUoZP929mk20CHQDm8kCt+ 7x2TAJeA48rWUzuSjO0o+dN/pE8JcUBxJ6iXyHjRB0hGHtGyHcMoFbfFIP/XUSWgw4l5 3bigSZa9c8e2SMqhD9n8JHXHfSXHbwO8OHRWE41H7ivqgpkcsEHw8PcgPjEtY6s8E2VT OaJMQnh8NGvz8NP5Mjpbu2FT29cMplDao1FBvo1LnKx5PCaBw9oW12m6Jg1pCJzn9vh0 NcvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934049; x=1734538849; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+U+8i8q/4gXE3A3yYLQmyNCA5wUq2DI1uSwKXqmKO3k=; b=LMBRoqo6OEGG3W4r/l2HukeiYPuuFgLgbVfgUsC6W8XnxNTmlnPOToLRMAScH4FYZv OSci2a3KbPzoksTE9CTKxUlYIBkHfuDRZTwyipTmbNbQs4o2pUjKx/CrT5tkV+Y16pc9 waId/ow6/hxirrMrsmLg5XR5ZKeohfeUD8qjO+Eb0B5y7hHjWiPqaly0sMcwVePIhT4w swrhpdgX2V2tOxBlb/bfOXjxoUXwh92P62+Nt+AHpZ7jMmWjx9vUe9hr/bpn/tnwwznE ZXHHVG+WPEwtfeLwS45RmRGgtkFu0xVbdT+jfNSDspgXKsm4783Q3mi/gpWy3IMbJTIz OjmA== X-Gm-Message-State: AOJu0YzuU0lRwnMHoHgZYANG5GgqdRxm0Ly6SPRn3BZG9ZDu8E5nptAb Ckz5GPtlMot2PRgpk9G8Dxxlbl46DWRiFGm8jTsD4LTz5DXfITIBzuXw9yCLz+F82X/4jqvGS6/ m X-Gm-Gg: ASbGnct90R9VMSxstj/mfri9UOem9udgL/LL6u/ZhWv6AZiZPH5Ua2NZiZCua5zZfHd IjlKz155VxrIbMVWimhb0HHA9BTBUsxNrgiWL2z0U9/gSV+A2y4nb5SN7F9nQXXlvsj5WaG83lj 1ApnlV3f9do1iodnVQb8+4duNIA5ysa/0q2NeG5P3K9noEsFOClEWMhDssOShtQmhpvtVqlenGx LIHsluSC5MOpDYzMcs8Tqk6ytXE1blTAQ3kqpOmqBeA3S9OsIWVJUVsHGo9 X-Google-Smtp-Source: AGHT+IFKtzJvQ6sUnbqCaP1iE3nvgUiHFSPqtWzWWiUtqkXm1NudkNm8FI9ZrnNaxGumgI/nfj02nQ== X-Received: by 2002:a05:600c:1f0d:b0:434:f753:6012 with SMTP id 5b1f17b1804b1-4361c3c7155mr35342975e9.17.1733934049030; Wed, 11 Dec 2024 08:20:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg Date: Wed, 11 Dec 2024 16:19:28 +0000 Message-Id: <20241211162004.2795499-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion from float64 to floatx80 using a scratch float_status, because we don't want the conversion to affect the CPU's floating point exception status. Currently we use a zero-initialized float_status. This will get steadily more awkward as we add config knobs to float_status that the target must initialize. Avoid having to add any of that configuration here by instead initializing our local float_status from the env->fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-32-peter.maydell@linaro.org --- target/m68k/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c0..beefeb7069c 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -36,7 +36,8 @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); } switch (n) { @@ -56,7 +57,8 @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); return 8; } From patchwork Wed Dec 11 16:19:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A294EE7717D for ; Wed, 11 Dec 2024 16:23:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSJ-0000Ru-KQ; Wed, 11 Dec 2024 11:20:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSH-0000Oh-2m for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:53 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSF-0007lt-DQ for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:52 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4361f796586so8313945e9.3 for ; Wed, 11 Dec 2024 08:20:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934050; x=1734538850; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8QtRpOUDdXPykNSh2kSGznv4CfLLLfE60kE3MXT1yOA=; b=M9yWJlEwukpshEj1U/ur3z3IYS1UtPiNoC6M6q8zJOTkUw7Q2y8EMK25WV9H/S/Qxd 5H5g5AIPWUIAKQBGKCFRGDDOvJDGmf3t+A7t8PgsqgGNurF2ZIG2ILdwoF2chcoAfy03 EF7MqickGN3tZEVNsDsuROLnjOtAC0QuptRwWylEuWGCOXSN1C100fJmB+TJl5KKiMDi mweU10w17dyfanyV6WcF/jefbGl1MUlnKzzKeLdEzMF2BKZpMeO2Z814gHyYAPlp0xyr uxoaXMrtdTe1el/Sdv0x6jhv2L8arJNoFqkrbDLyFmZkfNawsGAuE9Xq2tS5ZW35jyih l/0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934050; x=1734538850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8QtRpOUDdXPykNSh2kSGznv4CfLLLfE60kE3MXT1yOA=; b=LXhPbH7AzC4bHIPyr/bkAUWkE2L6HKqtqo3az6D3nqdyj7okfBdr8JxZx3Z9jnZvuS 55x4c4tXYp5dJ/xFd5BHBae0uOd2zDur1jfjw6lPJZY3z36UvsfRPR+zGTAkEGgZ3vKr i1vJduToaKzd9UKkCtBqo5ujTVIt7HrVzOJfDuGqyGjv9log5qr3zt03R7iGWBr1LMd2 d5n/fxn+z5ZLukdzQMOuVeNpqCzr+T7UMAcc4+rear9oPyJXdq/UbfF4mLMXc4uKRYfB q1NpBS7c5gMWPDr8/bxvWwh+f7z7lGTFONjMwub2z8/5FU20r9x+Sgb1P/1h9gxGOhAQ 9L2Q== X-Gm-Message-State: AOJu0YwSfIlr+KR1XNxxO3EHXZU5g2FE+Yp374A6p0wyYCMEhqep1DGq +TOT2nQxGVP1KVzXJ5NRyA0Qz6Q1J3iZNI8IQvJWHL8KlldMnHIIwswc6bxBVjLSaagi1mCsp3h Z X-Gm-Gg: ASbGncsdsmtXMG6zXUEG8Iik0G1v3wI1IjDKrKtwO4/hlxm4JsKXiJNfW4Ig8r6SgvX vOh3QGBm9mjkUye+C8HzpT8ff96hKZMWfcCdyc4hAWqXV5wIua6kI0GMz8xg+18pkD/MBBtGVo+ JaVsfRFtE58+4Ow7+kwOBPYLpgcf5g5gFq+BftNvTTdZt1n4DZtJEBpvi31o0BGLoQJtnItH2Od 62LV0BUVQGSdDF/BHv3zPO8OSg2IXVzSTBwG4UvGJZxx+gUfsUFslNKTVIf X-Google-Smtp-Source: AGHT+IGqe2Jk3lhh2qLkyM5RMDAP9f2H1rkBZ9KLKERjGbP9zuqck1KpOTmb+r83N39oEVs0sG1I1Q== X-Received: by 2002:a05:600c:4450:b0:434:f5c0:329f with SMTP id 5b1f17b1804b1-4361c3bd9e8mr34947935e9.14.1733934050014; Wed, 11 Dec 2024 08:20:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status Date: Wed, 11 Dec 2024 16:19:29 +0000 Message-Id: <20241211162004.2795499-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to explicitly initialize settings like the NaN propagation rule or others we might add to softfloat in future. To do this we need to pass the CPU env pointer in to the helper. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-33-peter.maydell@linaro.org --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 134e519a377..1ae3f0c467d 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -51,8 +51,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) DEF_HELPER_2(raise_exception, noreturn, env, int) DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 6f9ccc008a0..236d27b19c1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -490,13 +490,13 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) return finish_fcmp(env, r, GETPC()); } -uint32_t helper_flcmps(float32 src1, float32 src2) +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) { /* * FLCMP never raises an exception nor modifies any FSR fields. * Perform the comparison with a dummy fp environment. */ - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); @@ -518,9 +518,9 @@ uint32_t helper_flcmps(float32 src1, float32 src2) g_assert_not_reached(); } -uint32_t helper_flcmpd(float64 src1, float64 src2) +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) { - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd0a95c03d..322319a1288 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5584,7 +5584,7 @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) src1 = gen_load_fpr_F(dc, a->rs1); src2 = gen_load_fpr_F(dc, a->rs2); - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); return advance_pc(dc); } @@ -5601,7 +5601,7 @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) src1 = gen_load_fpr_D(dc, a->rs1); src2 = gen_load_fpr_D(dc, a->rs2); - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); return advance_pc(dc); } From patchwork Wed Dec 11 16:19:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EDA8E77180 for ; Wed, 11 Dec 2024 16:24:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSJ-0000TC-Nj; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions Date: Wed, 11 Dec 2024 16:19:30 +0000 Message-Id: <20241211162004.2795499-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the helper_compute_fprf functions, we pass a dummy float_status in to the is_signaling_nan() function. This is unnecessary, because we have convenient access to the CPU env pointer here and that is already set up with the correct values for the snan_bit_is_one and no_signaling_nans config settings. is_signaling_nan() doesn't ever update the fp_status with any exception flags, so there is no reason not to use env->fp_status here. Use env->fp_status instead of the dummy fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-34-peter.maydell@linaro.org --- target/ppc/fpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 230466a87f3..d93cfed17b4 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -155,8 +155,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ } else if (tp##_is_infinity(arg)) { \ fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ } else { \ - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ - if (tp##_is_signaling_nan(arg, &dummy)) { \ + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ fprf = 0x00 << FPSCR_FPRF; \ } else { \ fprf = 0x11 << FPSCR_FPRF; \ From patchwork Wed Dec 11 16:19:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 649BAE7717D for ; Wed, 11 Dec 2024 16:26:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSL-0000YZ-Et; Wed, 11 Dec 2024 11:20:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSK-0000Tm-0t for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:56 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSI-0007mR-9t for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:55 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-43622267b2eso1762885e9.0 for ; Wed, 11 Dec 2024 08:20:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934053; x=1734538853; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0hVwJ7PhWgaa1nanKp9sPo09AWgYuiJDE+Q3tkgukF8=; b=jTM8UaFk+YYbnx302Iyyb8Ca9z0sKEc2LNLLf11EMk716N8eJYua8FQmnomQT0pA+6 Z5BKgz9ER3U+S9AlXJW65g+2NSls0F5D61B29n88xjJ/W2ZOJsWIdiv88joZg60daUNE bIHcvTFJ2wnQgzrqzKCymUZW6a/uhK2P3Dk9eaDmrQqdjwCtPHKG1ZTFfgvpHdUjvfYQ V11WzPoQ2TBYVB3w8VaBA224vlF4syMZgOXwmHG2gzQrfIuUgwquGbqL1GXtKDoYi46s HpNzC3iYlqYRt+bmhCbm423EcRpREJHYgDJsy9ZI1etjZdwttATq+cDOBVQAlW2JBoYV gY/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934053; x=1734538853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0hVwJ7PhWgaa1nanKp9sPo09AWgYuiJDE+Q3tkgukF8=; b=X0CSRJpINUYzp0vCHXajLTYzPbO0Jqen+juGU/KcfsVoZLDvvegSQUJLcj00dqsjoh LQ/xFeZhekBvQ1CfdscTt85QrO+tk8c+6AylIpQt2wE+zZ1wKLS4wTpghcauWIY+OPVa R1+5L4ShhN6EHpWe8xvmUBH4PnET/eY2Kv4eNU9j8q+YuzNVnyzOlaBV0UCTuhD0WwiX FsZEzLtSoSMUEIRUFHCFq4T8P+n/0uBnPZgSKXjVQuxKZY911uyP6/7M+5WRY3se48a5 sEbsKp90PYH3EU9FsCD5Hl97EAg9C4eNu98AWPM0sGVPApj+mqZR7sf2v3LpIzbeQ+h3 Ds3w== X-Gm-Message-State: AOJu0YxZMNawmbSiyGFmBaOr4Dl2T3abyhXcaNIOO3T53pAGDp2+ZKwb esy+4FSRlOhqcB9COuTiyzAAU3bNvNo7hqpawQCG5m9Gb/xIR+eckVlmtff2rZpr0ELyoSmcKKU 7 X-Gm-Gg: ASbGncue4WlUabmuvyBu9b5o9+StZCW1Lz7WmPV73HeiU5iE5oS24/u/R2gtctJuktx XRe579GEWPFk6QcYZrDu2Lu9vDZ5fIoIiNYknmkWSPVLm97UsW0nojum9Lyl+x7QGhvwdVL3ipa 26OR54qqWpfZXja+9SHaLT2GPH0jdIlW4vFW7QBr65Qq7eGugQYw+rizMXG++M7J91Nn8e/Tw25 4KsxVoToDAneQLdry6uyZjUqB03+ybWsaTqbUnipq1M9STx9rk1dP9yjkAv X-Google-Smtp-Source: AGHT+IF5CcG0bjD68FvO5pJZdYKWWSFxhbSN+FQR+p1QriUsNZQYX2UJuRDOIx5TcJyjFG1UqJZiPA== X-Received: by 2002:a05:600c:5101:b0:434:ffb2:f9df with SMTP id 5b1f17b1804b1-4361c3a6550mr30727475e9.17.1733934052743; Wed, 11 Dec 2024 08:20:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/72] target/arm: Copy entire float_status in is_ebf Date: Wed, 11 Dec 2024 16:19:31 +0000 Message-Id: <20241211162004.2795499-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Now that float_status has a bunch of fp parameters, it is easier to copy an existing structure than create one from scratch. Begin by copying the structure that corresponds to the FPSR and make only the adjustments required for BFloat16 semantics. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/vec_helper.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index e825d501a22..ad6f26545ac 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -2813,25 +2813,19 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) * no effect on AArch32 instructions. */ bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; - *statusp = (float_status){ - .tininess_before_rounding = float_tininess_before_rounding, - .float_rounding_mode = float_round_to_odd_inf, - .flush_to_zero = true, - .flush_inputs_to_zero = true, - .default_nan_mode = true, - }; + + *statusp = env->vfp.fp_status; + set_default_nan_mode(true, statusp); if (ebf) { - float_status *fpst = &env->vfp.fp_status; - set_flush_to_zero(get_flush_to_zero(fpst), statusp); - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); - /* EBF=1 needs to do a step with round-to-odd semantics */ *oddstatusp = *statusp; set_float_rounding_mode(float_round_to_odd, oddstatusp); + } else { + set_flush_to_zero(true, statusp); + set_flush_inputs_to_zero(true, statusp); + set_float_rounding_mode(float_round_to_odd_inf, statusp); } - return ebf; } From patchwork Wed Dec 11 16:19:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 617E6E77180 for ; Wed, 11 Dec 2024 16:21:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSM-0000Zu-I5; Wed, 11 Dec 2024 11:20:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSL-0000Yb-DN for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:57 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSJ-0007mt-4o for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:57 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43540bdb448so13925305e9.2 for ; Wed, 11 Dec 2024 08:20:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934054; x=1734538854; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5/6kEX1gNzfQ+l4QKWLxGw2T4UU2uunALU33y3cz//o=; b=CrX+O6rwAy5yXlF9AIsv5HHgjV9lhHGCsgS2jRqg/M/rHSO7i8jVYbOTVZUWSvtfDF hQT5W10FftL2lmaHPKsj3vHg12L8DEFQh21xjToH6QHy1bvcza+NRePmUQqqkpFI+vkc hpoKMtUxR5mgBXbZ2OeKnIZ3nsMyhvI7GH6+HgF2cLaUyAtoZAGQex9K4T8pR2PQsbXb Dq/ASWoatV5e4qusgINldYJx24xapLkPTXw4W2qCyKNFrjNLLgPr4NUiU5txTKlSjzBF LgOm9iXaxqtNv1Rgn72UNR25W3P5fzrkEYfIWXEZHq+nwyxOT7mXieLecm1Jdy9QuTrb P8mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934054; x=1734538854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5/6kEX1gNzfQ+l4QKWLxGw2T4UU2uunALU33y3cz//o=; b=iQHYcFluTZ7D9R5H3Ui+ZbuuStAxMvNW/hXH76X8BVIJVPX0F1eSnbQd7BoXHNFaFg gCfsjQ02MwtKL9720WrDzs/MMXpFH63t1g1juITskxQs18aB8iaPqS0WYiZr3YkmXz96 Uair/3GaHtQfaGHiLiTD2mU0RRzAgkqcfzi/j086ZQVNDa45Nsuk0GHRo+d3uqqF1zcF ou/vdamPCTHfWwHvfo36YX8DCXk4pwpum2YgFO/RZ1zdm2RjDZ9JwaBbF3ZvPac876UY arRyQcUp9lyg/BeV2uBqpYPJphY0XAeIXOlvfDUzp0ikUJ7cF0M/oD0NcZ6PtC7/67pj ZEPA== X-Gm-Message-State: AOJu0Yy17dc7u1m30gbyQ6guLPedx4kgrwBiVnJeAtLfOG6K87KidmnZ d7v5Wk3JYD5Ph3emWWYZaXv/MoPU+gc7n6tn3wQai8b28cD+DJeDz7dFhx64h5xcYH5bjeC4nrN 8 X-Gm-Gg: ASbGncskZD0u5cSy53VDft8z4Ev8HGuoto1XexLDgUmRFcNquLf7A6uOTbO+Q4gKnEh wJ+3AkcfpwqoCubY9ZQRL+CaFrrqXYMNUWIqpU40I6iktCVT0XAqc+c9bA0g9ojKppE2S2mnIE1 x9fjNA+taCOLvNshiqSv1QTDG31VT0CALTlH9PSFn6MyQ7N28ZXeVZlJnlQjVS1AS+rBYU+HrPY pHxQDfPEJxErXBWAdjV1B4E6VQc1qFilZh8xqtLuECQsJ1vjlMeZSmYMfjx X-Google-Smtp-Source: AGHT+IET9rGDP9injVxIbSKRt7+C4pG/oxZP8NBRVm40qBj3z4X2FYVXQqgYvUQb0vkI+LYAx0Vv3w== X-Received: by 2002:a05:600c:3552:b0:434:f131:1e6d with SMTP id 5b1f17b1804b1-4361c360e94mr33908025e9.10.1733934053683; Wed, 11 Dec 2024 08:20:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/72] fpu: Allow runtime choice of default NaN value Date: Wed, 11 Dec 2024 16:19:32 +0000 Message-Id: <20241211162004.2795499-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit is different) Add a field to float_status to specify the default NaN value; fall back to the old ifdef behaviour if these are not set. The default NaN value is specified by setting a uint8_t to a pattern corresponding to the sign and upper fraction parts of the NaN; the lower bits of the fraction are set from bit 0 of the pattern. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-35-peter.maydell@linaro.org --- include/fpu/softfloat-helpers.h | 11 +++++++ include/fpu/softfloat-types.h | 10 ++++++ fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- 3 files changed, 54 insertions(+), 22 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 10a6763532c..dceee23c823 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -93,6 +93,12 @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, status->float_infzeronan_rule = rule; } +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, + float_status *status) +{ + status->default_nan_pattern = dnan_pattern; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -154,6 +160,11 @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status return status->float_infzeronan_rule; } +static inline uint8_t get_float_default_nan_pattern(float_status *status) +{ + return status->default_nan_pattern; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 84ba4ed20e6..79ca44dcc30 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -303,6 +303,16 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ bool flush_inputs_to_zero; bool default_nan_mode; + /* + * The pattern to use for the default NaN. Here the high bit specifies + * the default NaN's sign bit, and bits 6..0 specify the high bits of the + * fractional part. The low bits of the fractional part are copies of bit 0. + * The exponent of the default NaN is (as for any NaN) always all 1s. + * Note that a value of 0 here is not a valid NaN. The target must set + * this to the correct non-zero value, or we will assert when trying to + * create a default NaN. + */ + uint8_t default_nan_pattern; /* * The flags below are not used on all specializations and may * constant fold away (see snan_bit_is_one()/no_signalling_nans() in diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9f913ce20ab..b1ec534983c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -133,35 +133,46 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign = 0; uint64_t frac; + uint8_t dnan_pattern = status->default_nan_pattern; + if (dnan_pattern == 0) { #if defined(TARGET_SPARC) || defined(TARGET_M68K) - /* !snan_bit_is_one, set all bits */ - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + /* Sign bit clear, all frac bits set */ + dnan_pattern = 0b01111111; +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ || defined(TARGET_MICROBLAZE) - /* !snan_bit_is_one, set sign and msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; + /* Sign bit set, most significant frac bit set */ + dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) - /* snan_bit_is_one, set msb-1. */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); + /* Sign bit clear, msb-1 frac bit set */ + dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) - sign = 1; - frac = ~0ULL; + /* Sign bit set, all frac bits set. */ + dnan_pattern = 0b11111111; #else - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* set all bits other than msb */ - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; - } else { - /* set msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - } + /* + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. Our other supported targets + * do not have floating-point. + */ + if (snan_bit_is_one(status)) { + /* sign bit clear, set all frac bits other than msb */ + dnan_pattern = 0b00111111; + } else { + /* sign bit clear, set frac msb */ + dnan_pattern = 0b01000000; + } #endif + } + assert(dnan_pattern != 0); + + sign = dnan_pattern >> 7; + /* + * Place default_nan_pattern [6:0] into bits [62:56], + * and replecate bit [0] down into [55:0] + */ + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); *p = (FloatParts64) { .cls = float_class_qnan, From patchwork Wed Dec 11 16:19:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2F47E7717D for ; Wed, 11 Dec 2024 16:21:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSN-0000aH-G1; Wed, 11 Dec 2024 11:20:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSL-0000ZW-UT for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:57 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSK-0007n1-Cc for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:57 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-434f3d934fcso25241495e9.3 for ; Wed, 11 Dec 2024 08:20:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934054; x=1734538854; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=t++4ywN2N/TpqmWSD8grbRREKM5vsqH/rZ/w1M5vhhs=; b=XG/uyIZLkOvxY0J8yUgWM9n13YqyjA/qYClNPiRnB0JK2nBT419W9O9LPZ4ob9Pe5D nAa03KdTPiQj+ndiqXY3UABmnO/FX20+LpoqgkrQ23Y/+Q3mXb76KvuS5wtuKW4yumby 98boHSufO1Tc9MIVPxtWXyXuHXTuarnrSoHMcYkFJFgGhJFms66T38fRrK9CG/PVbVhm w9cHbZ3E0AFjHuLJcbon9AymEFBMxynMJvUkTZ+8kV3UfKsgg5IxGR1f3Ewut5ZBpJKd S/2dr1Lzp5JTM6wSwSWpBqCQLPtRLzHC7CRSSXCBRwbC0A359jxjInLm5FJDCUrTbh7E yQVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934054; x=1734538854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t++4ywN2N/TpqmWSD8grbRREKM5vsqH/rZ/w1M5vhhs=; b=gC3ZdW8LnEsMM8V2Ev5fPFe4Wj/kqYvhpZ0vTMoexuL3sfQmEyc4TeiBDVvfrN3LtU W+iNyfxJhQcLIfJ1GRo21kmA+L7r7wPOMh3YaUKjlZ2vmKeyN4BHoux8Chur2486fCvi cAE79xI37d8waDgEPK47s7NtQX5AAY3teBaukc0nMGXZULLbxw+Fs/DKR87v1P0w+2yu +XyPW9/zDtO4+F9RZVWCiYI6Kz4s6z77etIhPgo5R4JItKKZMGu9OebvUd6eokOTwuGX FQ6nUVBGNXKyduOoYbNvUpHhhoc32vd40Cqxh3h03t7aF9phVDLTntG9oJrI18a9T5g/ /dbQ== X-Gm-Message-State: AOJu0YxcwdfFwPQPaTKSpw9ZhX84arazCKt5kiPSrn29pII2cSd5wQMs vGZjF3Wmjvy2jDK4dsXUhwiPMXLXEp2NyNu5qxbThZdcRRMSaN5XRpjoN4ZAS1HxXRI/Abd8RTr 0 X-Gm-Gg: ASbGncsVKISJAN/0ItHPLEZmvu0mQjo0fPlCkiuUrjQXh5rHpRXYfHjx3OtvA0G9YN1 HfMvCtChXCl6wDkGE3XADUyiTdJRYTl2ASXU/aHvXpLZK9KvXaHJajngzW7D8qRx6WKyhsCM4S1 s0n87RHamhoBk4XS9JqfhWiRS9FAnJaI4z+3ROfYg2eoPR5dyhHkfmQqg2/lE/UvtvPvaOEhNLt lnVmR5Chts5om1ME9pjqEwgEPwrXUUT8f9evJi+2YjHQiCtGs9iEGlhWZrB X-Google-Smtp-Source: AGHT+IHUChZ15ytVFY+Hqz4T4vUPpjGhKb4AAb1hXszC8aQ9IYRryQ+IykTLkc+KOdg/pM3Pn5zqtg== X-Received: by 2002:a05:600c:4f11:b0:430:563a:b20a with SMTP id 5b1f17b1804b1-4361c3aa6demr26312385e9.11.1733934054601; Wed, 11 Dec 2024 08:20:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-36-peter.maydell@linaro.org --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 39d80c9038f..eacb39b99cb 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -495,6 +495,7 @@ static void run_bench(void) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); + set_float_default_nan_pattern(0b01000000, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c index de702c4c80d..79f619cdea9 100644 --- a/tests/fp/fp-test-log2.c +++ b/tests/fp/fp-test-log2.c @@ -71,6 +71,7 @@ int main(int ac, char **av) int i; set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/72] target/microblaze: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:34 +0000 Message-Id: <20241211162004.2795499-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-37-peter.maydell@linaro.org --- target/microblaze/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c1..0e1e22d1e8e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -207,6 +207,8 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) * this architecture. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b1ec534983c..d77404f0c47 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,8 +139,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ - || defined(TARGET_MICROBLAZE) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) /* Sign bit set, most significant frac bit set */ dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) From patchwork Wed Dec 11 16:19:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F176E77182 for ; Wed, 11 Dec 2024 16:24:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSP-0000bJ-3D; Wed, 11 Dec 2024 11:21:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSN-0000aI-9A for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:59 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSL-0007nQ-Qo for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:20:59 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-434e69857d9so5483865e9.0 for ; Wed, 11 Dec 2024 08:20:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934056; x=1734538856; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mgg20eSIrnOO5pFUHw3GiJXeV9/eizL/vriHmsBEKfE=; b=txfUR1EPDLwkLsg0hB1aiX6Uk1iLyt/AJpqA3RRqWRiM8MS/HRFnaYMMeD8JEGZ1nn Cwz3fAyFVzppPq9143lcnY5K6jA55Wzn/AakOxUiMzioENv78Zva2HgrLKcKsRgzdP4n BScStUK2yRoXlGxwJQfYw8dXWfbT2st+0/GnWhcPYaqqucaTGv7QsHbnO9szoLAmQjGZ FUwNRF2Uuo+KGMoaTGRjXi0g9NX46YeOtvUm4DKoDYX46fVeYImzecEpWJzkWWp13t99 lcAVgQHLCatntRxJ2DU0MgP72x8QHZ1CgagOvcrXcz6lO/rIgNou6i+rtOQso4gkr0ma Es+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934056; x=1734538856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mgg20eSIrnOO5pFUHw3GiJXeV9/eizL/vriHmsBEKfE=; b=v2+mzRU9Bk9SvXrLNRsqbPxacXEQ1aguq9ValAHKscp6puop79vaAG7RGYcvSUbxDG NHNB3qC4AZV01w7X5MwuVdhDUdVlU2+AV0SkhYah/6m1mqmPArR9DLS0RvFAHejHHxrX gi1WHPSUeZNxrdhKlcvpV69iLdQMw3FYOqPn0O8k7nMVQXUFzS5RO1I2ltsSvYlFaB6l 8/mYSjbWxSbcN6rr5PbNnajxkrgzcFldfgLqI/lfD92aIqg1Q7Bm/QlFDJTimzT9V01G VYfMde96fwbXQeacV4ECmSpVrFMJoZGx4MVRlP/jpLN/CrzohRjYBy7juJd/nnezkVFG 0bGg== X-Gm-Message-State: AOJu0YwsDPwsr8UZdcVAkJgHigq2Ikv/bZ277HRutwmvYxBG3gRtQQIv QdUuwMK4+ZqK5o/6HlNaz8+WljmrvB4jTDE25Wt9rLQrNFC3TtjzhvnmyCmN/VPjf4IaD12NPwV Y X-Gm-Gg: ASbGncsqDlQOdMcaf20lvQrE0jAozGzq8iIW9GoIxWVEvuN8g1kmzBykqfmtMMEjG3v 0131SNAV4nZA9nkOcP2/QBcV6IeqsVSpSfnsAqM+jEELgQemB7nouVvqXCtM0IEBMMNLXVTSOl7 i1t475jwRadINwwlnL26ebu1xoMv6IFzNvUB+FV5tMka6Gg6gaKd71oEed9jVjGHXhuACPVQ2J6 ek66m/Ymb9nGujQonWq7oD1AEHuD0xmcgCTxv3RsxfRhee7f2kSZogc+TMQ X-Google-Smtp-Source: AGHT+IFuD6xbDKVA01OFDi2TVLbvP1/LhUc6aVTS7LriGFTQeXFI24WOqX7pisXpghIUYn+3Hj2XBA== X-Received: by 2002:a05:600c:3ca2:b0:436:1b0b:2633 with SMTP id 5b1f17b1804b1-4361c6050b9mr24329085e9.9.1733934056472; Wed, 11 Dec 2024 08:20:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/72] target/i386: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:35 +0000 Message-Id: <20241211162004.2795499-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-38-peter.maydell@linaro.org --- target/i386/tcg/fpu_helper.c | 4 ++++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4303b3356aa..d0a1e2f3c8a 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -181,6 +181,10 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); + set_float_default_nan_pattern(0b11000000, &env->mmx_status); + set_float_default_nan_pattern(0b11000000, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d77404f0c47..452fe378cd2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) - /* Sign bit set, most significant frac bit set */ - dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) /* Sign bit clear, msb-1 frac bit set */ dnan_pattern = 0b00100000; From patchwork Wed Dec 11 16:19:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C839FE77182 for ; Wed, 11 Dec 2024 16:24:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSQ-0000db-9c; Wed, 11 Dec 2024 11:21:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSO-0000b5-FE for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/72] target/hppa: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:36 +0000 Message-Id: <20241211162004.2795499-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-39-peter.maydell@linaro.org --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 69c4ce37835..239c027ec52 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -65,6 +65,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN: sign bit clear, msb-1 frac bit set */ + set_float_default_nan_pattern(0b00100000, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 452fe378cd2..b5ec1944d15 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_HPPA) - /* Sign bit clear, msb-1 frac bit set */ - dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; From patchwork Wed Dec 11 16:19:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49D83E7717D for ; Wed, 11 Dec 2024 16:26:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSR-0000iS-41; Wed, 11 Dec 2024 11:21:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSP-0000bK-0h for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:01 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSN-0007nq-MB for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:00 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-434f80457a4so5276995e9.0 for ; Wed, 11 Dec 2024 08:20:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934058; x=1734538858; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yKsdVA6fFVWyT5C4g+dHlzCsxIZ5/YpoZTGllaXzw58=; b=RnNtyQ1KYdFWvoTPB1fp71ZgEDmuhkgaEWtYtpcU0Npjx4LzphBh9jNvE+2djRcUMe ///GK6IMf2/VcmHIDGz9wW6i2w46aS9bgTaZY8lfHPxX4WVnXBe9IijPHOW09iiMjOrW 4fRq9ZxJpqM5KFgzRLGDYusk9iIlcMWBsSIQKVUqXUp7sB+uAp73AoV9dm/CRK57a//M 9Q8IVahlNINovWyueOILa399yDkJ2FO+4FpRav8hkS2C7ZvDMDjqMtkv4e6s6B5ftj+1 puU64JCbxr9xJ0oo1CunYBwclwY0oQcdGHoFIfwtTSGURnFspcLARSju3NGC/mqTdOhc qvbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934058; x=1734538858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yKsdVA6fFVWyT5C4g+dHlzCsxIZ5/YpoZTGllaXzw58=; b=hMyRRLsOIeqN8hBPxoQC4WJkd8kXk/Q9ln2kFg0Uou9fM3zkVP/quGuXaYCoultMrB VJiyhYz7CvJFWiTuNCoWILj8WSJPCltEjgYXmhwDgSkwA069ephgQEuOqC8zofvAS8KV T0hjQvxokkZKualZJqkyVQfa+yPkLiyZYmzq1fZcE3bg+M2dUtqRsZbh6hV4GsJf8PtO iz7/FAE2P+r/RMh8AvK7kNYgZEN8p6YyAeAdVd9RAC5XN9fpXnxuZyucn3/rNhtdyeP9 CX33KBjiTuwadmcB9zG/y74K2+6kGcPlkDjuEUD8LAhUDwL961uUXGO7sVbFdcE+Fare N2BQ== X-Gm-Message-State: AOJu0Yw89BgXg/TDCkdIO6DUKthvtpLS9xLF6RdFDyJ7aosboLYcGYVZ 4avLkVgnKdtVxlRNsIn2KCBTMPk2XPbknX2yag0ED7wi1g12FWiZ++pLcsrx3sf1Ybopaj6Ap20 L X-Gm-Gg: ASbGnct4n6yxwB7kZxnC20Xcl8rGVZ7I0KcKD45GxpO3czM8iy7XsCwAhgXUD54HEiz We6+ZGgUTr50dvdpnN3wLqY1wJI9F2im78OwD1qkUPNOS/2mf3c8v5oWNynRKTkJ7vsYLmjRBkf tIcdNzalh0DWJxEVABIM3DK8f88g2a5Enfu8AHwMKMs+T4SG9k9cgRVZ4F1QFxz1jPKLgkcJSzs xn7lxgYrNh2Voa1igthSOecfnzqPP44JMn57/IkAT6qWxpMObvFjl4KGsaP X-Google-Smtp-Source: AGHT+IGY5PnuMiQwL4T7BYPB/CzCoU0Dr8jpBgzgX+zTvZx0wyTWXDHw5lbm8V1wlJY3nBxfYc0OTg== X-Received: by 2002:a7b:cd15:0:b0:434:ea1a:e30c with SMTP id 5b1f17b1804b1-4361c80b03fmr27112725e9.13.1733934058372; Wed, 11 Dec 2024 08:20:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/72] target/alpha: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:37 +0000 Message-Id: <20241211162004.2795499-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for the alpha target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-40-peter.maydell@linaro.org --- target/alpha/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7a..70f67e6fd4e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -199,6 +199,8 @@ static void alpha_cpu_initfn(Object *obj) * operand in Fa. That is float_2nan_prop_ba. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD From patchwork Wed Dec 11 16:19:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EB75E7717D for ; Wed, 11 Dec 2024 16:22:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSS-0000pa-GN; Wed, 11 Dec 2024 11:21:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSQ-0000eL-9u for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:02 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSO-0007o8-OZ for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:02 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-434a2033562so59606215e9.1 for ; Wed, 11 Dec 2024 08:21:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934059; x=1734538859; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2r0htTAsE1i09Hw2gTl/jAfOrYRUikK5HNqJfN6jEc4=; b=EeXbrkHz9M2cZDkTlKNI0j0ea905Hj6Q06yG1/YdZv2XOrh03FHbzJSwIUvfZ8Tk+2 lMeh0aDnhpJez3zM5vmdZt5x8CBe8tPXhs0eGfSq5Kbkd0fAmEh+onCnjTwnxAZ3DfgM AqCsRe4QA4zsKLXaE6Pf5R4DvJVkld/rxJiQ8gcxcawE/XoSXOGRoH9BBpdIofbShOsd a1vFsFXW49iUHRcIWicQEOiG57HGA7Tio+Mgqvr8g9WdMW9CEqic+quU9r8FYudscmXU KpXVD7pZzKA8eLh2Zqusu0dM0HCEBJ4SEVN+1tZgfrhx7AoP4KAfIhBmsWFl4X9hc+se C1AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934059; x=1734538859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2r0htTAsE1i09Hw2gTl/jAfOrYRUikK5HNqJfN6jEc4=; b=QKsfiPF+mNHV6iEXQka3/QKH7Vum5r/nBdLpEWqJDFgC5grvG19pt3uLuvjKSyPp3t y0/SnYMrZbV+2M7ltJXad2Z/w95wKulwxtLe06ODjQ5FMooJRzmx/40lf2K38fD+bHrw C1sQ+f8ttAIBHMIVXxT6yAb8+ls4i/9TdL7LWMphyAE1pmzgWwFW5NgSTE85nHD7EutJ 4jWGbFLo+0CK0RsQo49npq9I5FC8yRyQc7AEujW/EcmRL/n0BdAnkwH07Zi3+wicri8B 221pRAVjzCBUF89NEDv4AtvLNSf2+odrYmS6o8A8eImClbWUrFU+p6hqs5wK7kieBju3 X0Kg== X-Gm-Message-State: AOJu0YwgrtohC2dWGpofE68kqza+f8/Or/wwmGSDAxM2mo9vP0i0o7hi 6gZCPPKqcbU+BmOSq4AOhhVzCZ0zmgYkZFUMVAvfmF2YO7Fm5D7msck8b0jHeWNvBRrZrbw17yi M X-Gm-Gg: ASbGncs8NADYYmLuVPj1dUoQZqfsZpqRU3Q5lfGBw5EFoQxpFHQDnpx/vGx0KY2ygdP LxeyjpujsnRHzqRqQHkU4yBviFR6jpsqlzD/Tu82DjisphMV19TH9ujfcENSE+RVEnqHrKKP62c 1FHFgOtyHeKnMd76t+HVy358OctVjN3u0SxA0/BBdpNjsLfcwljQKpD5S9NJYrt73BwMM1Oa4O6 8KGChijxU4bJNLAOObS2wqQ7rEh6bd2m8in2sFW0QTDo1ePXCZRaThqCn5P X-Google-Smtp-Source: AGHT+IGicDoON8JVH8qMnUREn/zOv49DSlfdqE5T6ajVKh/yLOQV5Agf8aplpG2SMQvO7JgCWMxkmg== X-Received: by 2002:a05:6000:1f82:b0:385:fb59:8358 with SMTP id ffacd0b85a97d-387876c38b0mr161289f8f.53.1733934059340; Wed, 11 Dec 2024 08:20:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.20.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:20:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/72] target/arm: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:38 +0000 Message-Id: <20241211162004.2795499-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for the arm target. This includes setting it for the old linux-user nwfpe emulation. For nwfpe, our default doesn't match the real kernel, but we avoid making a behaviour change in this commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-41-peter.maydell@linaro.org --- linux-user/arm/nwfpe/fpa11.c | 5 +++++ target/arm/cpu.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index 8356beb52c6..0f1afbd91df 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -69,6 +69,11 @@ void resetFPA11(void) * this late date. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); + /* + * Use the same default NaN value as Arm VFP. This doesn't match + * the Linux kernel's nwfpe emulation, which uses an all-1s value. + */ + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); } void SetRoundingMode(const unsigned int opcode) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c81f6df3fca..4f7e18eb8e6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -179,6 +179,7 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling + * * Default NaN has sign bit clear, msb frac bit set */ static void arm_set_default_fp_behaviours(float_status *s) { @@ -186,6 +187,7 @@ static void arm_set_default_fp_behaviours(float_status *s) set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); + set_float_default_nan_pattern(0b01000000, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) From patchwork Wed Dec 11 16:19:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABDEBE7717D for ; Wed, 11 Dec 2024 16:25:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPST-0000wX-VY; Wed, 11 Dec 2024 11:21:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSR-0000md-Py for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:03 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSQ-0007oR-79 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:03 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso5904925e9.3 for ; Wed, 11 Dec 2024 08:21:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934061; x=1734538861; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CCObb/UU4fUvkP8uNIWpNMWZoNgBU5AdL8ALELaxgBI=; b=wqooi2zhqE3Yh1iivZaouwgpxTQNYr8xNHCdRDiMH2UwV6B7M11xhuTifE9Z6Y6NbM PqLOdmS8Ek6DiuDzbOcTaFcRHGZv9pYBBLkKcRCUTnnC6cFaxq0vdXUv4dRLeuUIo1vt 4Ir5L06OSv/KrkmYq2K0nknRLl6VP+Kf1CH0YLYmXIbGMdNdwCC6KxTisHx3Ut+WDtaw 1U7vxu7RguZo7xSRUxgfDrgTMaMRJlI7q85Y/xY1jsRX/+34j7iDzJKpoxHjsJoQmfGY T2sMYY3LXJ9NhdLYAymDouQMmCCtQ0nbQA72VQjctSHYAD2qT8jdnU53UMZk8NCFpNpQ ROig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934061; x=1734538861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CCObb/UU4fUvkP8uNIWpNMWZoNgBU5AdL8ALELaxgBI=; b=MbdfZkZM8NzG3AF07iADMjvV9CcVvidGqNUPB0GAjVs5aBkleDxhgZLUtD/GdUKFnW 6z9tzXPtCYHQj4ZCTjyfkPC6nb4Kb2nSLF2rMzSKvexX5x1EI3JCo6d0saSVTsa0IhUp GG6WfY80RAjf5uLtXQA9/DWgCA6PcNSuAvQXkQmCbLPRi57PJtsjaK//pm33Wy538Wfw zQ6Fwy8bOl9Xl0MQhXxstDJfbccoV0wHCNayTzFxWVS2VRrQIe1eT3C7zaZre1mQ2X7Z ZBOHNrMW0LLVYPx2+tczNVcu56rLbH2TEp1m1IIpINTj0T8JKSnvCPMHvr93qo180UXY gDBA== X-Gm-Message-State: AOJu0YwRy1hX7zvoVvm4BpEsqi4Fq5DbOI6MGlG018rEzfu7BYGUK6AD KMNbKgsN9zjLUu+R2QBIdA0zxuKv5Hg7dYCYGB0ozzUTqMIqdwZpGS2e9rp4JyNN5UZJxIKZiJ5 f X-Gm-Gg: ASbGncskRQYAwUBYsov3EEum5yKsGS+662XT54ySty7oY8yD3bKhrC4rxlR7ZPoU309 3YRPOjDv2t6MoDKi8zP/1YpfB0DegwylnGjad7f3VUD1Rhh5jEvH29obzUqpI/8WKafjNZcsMGk 14qQpBN/1Wd9IGI2Fz3VKnDSG9MkvwVTJ+pkPhnnXRTltWRY/GKLNBDVNmRFPo2nfw07nVI6hfh 5qfUEgDfwkKrcmtHdNXCSM7IoDloQeyp2JT/WW2+Z5DxR2YxLXwfJCoQ3LJ X-Google-Smtp-Source: AGHT+IEyHXd0OoHMwMKJ5998KjNjdvlGHORV0UMxv4sDXyuNj02SMCxNvbeWvqfp0yyt//iINNNUew== X-Received: by 2002:a05:600c:b86:b0:434:f2f4:4c07 with SMTP id 5b1f17b1804b1-4361c373f5fmr30240815e9.15.1733934060860; Wed, 11 Dec 2024 08:21:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-42-peter.maydell@linaro.org --- target/loongarch/tcg/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index aea5e0fe5e6..a83acf64b08 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -38,6 +38,8 @@ void restore_fp_status(CPULoongArchState *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) From patchwork Wed Dec 11 16:19:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51D45E77184 for ; Wed, 11 Dec 2024 16:27:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSV-000114-Ku; Wed, 11 Dec 2024 11:21:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPST-0000u2-6Y for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:05 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSR-0007oj-Gq for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:04 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-434f80457a4so5277395e9.0 for ; Wed, 11 Dec 2024 08:21:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934062; x=1734538862; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HIBxigbccU9+srEWhsNqTCAiXYWvyJ1k1YE9ZXRBOPo=; b=pFZzpuNVGMlxnpu8Eevj1DEw6e9DFU4Rg1KQU6ptjj5QWgx/+kqfdvNZN1VUDdsz4P XsKE07LTYpHJ5U1fGaC9077DP2NJCDvkUdZlx5FRz63RzyMVEhZ6tRhI+b4pEviQ4sdc vCMDX62Nfbosy0SbYIE1wxprzjqmEjVrjGv2g9oPlZMjgCpalUym86d4pEJfQIoeRQIb idVzCbimjJovtXemMZ4itS5pR6Cw3W3PPKGv+20g4kZRsC7Vd3IRyMXiK99LVFprKCQx im3MjtjkCVVAAw/jpn6HFxnw1pXZ4TyDAJfTM4xNEp+AEL7j4RgHUFvUoQyW9L2W4Rqz kvEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934062; x=1734538862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HIBxigbccU9+srEWhsNqTCAiXYWvyJ1k1YE9ZXRBOPo=; b=DI0RrfE4UfBTwqaFT3utkQ7SMAhrRUa+Sp6cy3fiFn6KbQXJn5Mz6hisuVLKHgxuuA WCLSz3yi0r53JQOksSPVDaZpMGZDVWlc/SyXHGUb7qk9eaWlKfIRKER4FTkDxAqoLcq2 bzOj/55sB0SyWTjud3gHBNSwYezC2qPBSPq4ZIDzACnAqazBub4NbgI2P7qO6Ufpgblo hP3DJtKsgsIKyVedFKveX/b7uvgHetMnVbgdaAdp0YofMg/heQzCSDB7XhPmdx+c0QIv xb67zYa7hbtJMQ8l397yEZPLnFeS9HSB6k0HaGbG/L49sigzx5rmMB12p6E3tgD6siq+ wc2w== X-Gm-Message-State: AOJu0YyAA0aXfKCJbANFm5AaTdKw/M8iNZZJQWZOUcq/t2RSEuKzkSxi n2nTjcarK+0Gu+NXwagEG+/CvBksBrJS4qnmtz1DzzjCa5EtBovwdM/EwLbvfl/VDLZxhwdTeX3 9 X-Gm-Gg: ASbGnctmnN8hg20vSwdJsbMcKBukGZU4+rOogs/TpxMWDvUzRVRGjeqrkYS6MCjWGgz pLCx1G0oXUAmBytQXMJ4QepQukHGW1JlB7ZWBrD5OmCVqOb33uc1NoyaYf3q7eB+nx0yv6FDIZ9 BCi/JG4OCAYhgASbl1r0JcIkLw/X4B3CQWLOJC6qdWNTjEpay5wjalTH78/7FuSzKJXxPu0cNlF ZlRSgcySOGuERt0tUa9m76FWPFx1sWUW2Qul3CfVRt2FmJPl6laMNFmMvZt X-Google-Smtp-Source: AGHT+IGygqbbCn1Jp9P4lAi40VvkMrtCkLfXMP9gKPqOgQVEPWCjnH9TouyPrWl7qrG6I4zcKphR8A== X-Received: by 2002:a05:600c:a0f:b0:434:9e17:190c with SMTP id 5b1f17b1804b1-4361c49e9c7mr23039425e9.0.1733934061989; Wed, 11 Dec 2024 08:21:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/72] target/m68k: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:40 +0000 Message-Id: <20241211162004.2795499-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for m68k. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-43-peter.maydell@linaro.org --- target/m68k/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 13b76e22488..9de8ce67078 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -105,6 +105,8 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + /* Default NaN: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); for (i = 0; i < 8; i++) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b5ec1944d15..ecb7a52ae7c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,7 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) || defined(TARGET_M68K) +#if defined(TARGET_SPARC) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; #elif defined(TARGET_HEXAGON) From patchwork Wed Dec 11 16:19:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79357E77180 for ; Wed, 11 Dec 2024 16:27:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSY-00015N-Kr; Wed, 11 Dec 2024 11:21:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSV-0000zX-1N for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:07 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPST-0007ow-Fc for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:06 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-434ab938e37so45369095e9.0 for ; Wed, 11 Dec 2024 08:21:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934063; x=1734538863; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kqc/nDYRVw371GtkZwgUaEiTpivDb51JFPpNFEa+LMQ=; b=xxGLLGaXYK13mgR4nfwgD6INDqMIX9ENoBWteZKtSHMF4tPgeZRnAiuGpXBgeNZ//3 T2wpNlbHsaug+dR0zjsBzcY9eC5xKzI4N4J1HbJP3pfcFt0HABj+nQ575XyNz8UzWuox N4zDovXGtixje29XB2iq6FOZfEhSchEpOHPN7/C+kJMSDwN8qoanTnZqXZvBVgY9FDMG Q2xZRcIdTumNyIxETQyqRI1pBwVVa73DWpHozRJc2Lv3d7IAU6He12nBoroyCsLG73Hi rSzNakI308o2bqU5nx1ZOuJjwFSWFaVixOEMuyklHVlxzT+1pHXJz717W1V3QBId8cT3 yA+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934063; x=1734538863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kqc/nDYRVw371GtkZwgUaEiTpivDb51JFPpNFEa+LMQ=; b=ic3gJJl1gWzukHIaRirInF6Hdb/6ruq/vw4bgSuUzFeJsxpVfBl1rOE09vJRxv7qVo +mdqtaRHZGyYOvkGBS8l9jShIk8XldlAvSA4egxAexdECpuqizYYWOjZQV6kwH2ztfwk 9xdDUNF/7itO0RYCpT87bls8SzrB+T8wMiook5hZgwO3RQipMxWADZ4Nv6OJXGjjgzqv k2bBl3si2voH74rAaU++tJ9AIDaGaQlzJDVOojkpLK7NeEqHUTDKczpAidRlz6rJ7E0R asq9VUoZP7P/pRwmuhJDSqlXXdiFocLg4Z3Wid4hd/LSwnpvcaaElbH63Y0paNyaXxl7 y4lw== X-Gm-Message-State: AOJu0YyEkpxkmi1HPyrryKGvNZfBMr5VuXHUY6EKDxG9PWJzH/poD5Fr jPBasp+rqHJyd0xIQZOunLllCpWgUEq/rJoomPo02lP+ei4egBE+zviMBJMHGzOJ1TfuZ3vELx1 p X-Gm-Gg: ASbGncvNLD9aEQKyF1eQ89S5vuNV4bk3on5GRGf+xyh8w/At7Nb3EIewLqY1sk5F2kg T0iX3juf4GIQy+/R0kvIyF2+eedFn5eAuAk4mORxbHiavYbnPdjavZggG2sC6kj93Fs0tYnAjEn ua3g7xOQVRk04iZ9RgDziarozUjBUuTJSvOxO4ptxUcLxEu1lNxuA+bAXqc/wNzpbArxSNlylkZ IcSq6A6IX+g8nEz/yvLy0tg5/sftQMKyf2RMUMY++Ges6+PgWsvk1grpbnj X-Google-Smtp-Source: AGHT+IFkNT6ajNQiw37UOXkrZQZcTWgzSClLDeuJS/Kb9zBFtRLWPuteNWN9r3Gp2AUoxH3rfEq/pA== X-Received: by 2002:a05:600c:3541:b0:434:f131:1e64 with SMTP id 5b1f17b1804b1-4361c36f796mr27470055e9.9.1733934063021; Wed, 11 Dec 2024 08:21:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/72] target/mips: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:41 +0000 Message-Id: <20241211162004.2795499-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-44-peter.maydell@linaro.org --- target/mips/fpu_helper.h | 7 +++++++ target/mips/msa.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 8ca0ca7ea39..6ad1e466cfd 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -47,6 +47,13 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + /* + * With nan2008, the default NaN value has the sign bit clear and the + * frac msb set; with the older mode, the sign bit is clear, and all + * frac bits except the msb are set. + */ + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, + &env->active_fpu.fp_status); } diff --git a/target/mips/msa.c b/target/mips/msa.c index 93a9a87d76d..fc77bfc7b9a 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -81,4 +81,7 @@ void msa_reset(CPUMIPSState *env) /* Inf * 0 + NaN returns the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->active_tc.msa_fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, + &env->active_tc.msa_fp_status); } From patchwork Wed Dec 11 16:19:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A763CE7717D for ; Wed, 11 Dec 2024 16:24:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSX-00013g-2d; Wed, 11 Dec 2024 11:21:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSV-00010s-I5 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:07 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPST-0007pC-Ub for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:07 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-432d86a3085so46141855e9.2 for ; Wed, 11 Dec 2024 08:21:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934064; x=1734538864; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QOZvZF6lfd13HN9sGqs8XH84RBO0cCUPe2GnmCUxM8A=; b=pnpPf5zPG18jPY8dWJaRPuzWSQwBfXLlxlXkcwRCZrtB8yjHIk+fnyDt1Swk7fv1O1 vu90chxusvWeWIk+aKYYwQPu3HtwjOFbsAD4kKdnJ2Dt1CXjtwTpqWySKQ6sAmLjJugv lZGJl+gZwEpz1choFBhBxo9mGpMdPyfm3KzYKee+D9OenXGwH8ojpMIQ7kJe8aCEYCPV LhWJLcaWyFI/bamz7/bTHAPjWYSiaXCk14dAC7Gub6v6VJPgVFtZz8VmyB+L76yElgsY DLYI9mig3lpMX+DfMLxqX+uDpPSgF74BAXNu5t8PB4CMLIiQD0IAp/xKK/0kWinlYD5z AV5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934064; x=1734538864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QOZvZF6lfd13HN9sGqs8XH84RBO0cCUPe2GnmCUxM8A=; b=vVNNhYP1/CATWHtGyEeux0KFLP4XGfl+EcMc/bGaWMO/STpiTuFVb5kAvDVASKhvEh MO+tmIuheLAs9QRwXeg9fuYaiFiE93NcZA3ECRK4+sgjfqYmeNJcTYcOwNIaQax8oP06 JrqSc4Fb1nEgL9aj06g6do/r1S8jUCjv/uywnURvG6igiLOipfhKxl3E3qA21HqGQQ6B WXQJoW5DTdw5j/KA/nTTwk9JvS3HchSSIpP/fKTxcU1MK3q4khr2jHvYMFa5P9cf488J cxGEp5HE7Esyq5r3d7ZoXLh1L1GB+1PnESNBZEpi8dwa7oXgOQHkIpWLYOiZQ362HsWh dMXA== X-Gm-Message-State: AOJu0Yy/cYJBpv+4uHGj86mc3lBfd3KkVhsBFYrsJt/j2ojFl2/3xLwZ RegOieEwtD7+tim32vyP2bVj5j4GHkcr7PAY8Dk6aJUxfm5QDj6lwpo9aX4pqxpJbrGRjznUCfq V X-Gm-Gg: ASbGnctu7neprQ1i+dP4eLYfi8HvCWE0OVonuf11PnXkndDr1LeLyQC7IOMnE8Qu+lB 3n2KzqedOZqL764zTfQMK9xegil7MwWauBUCQr8SbMmuahnIljCGSaa413koUdQW+STuIjifgUX MHRZETfAXBCQ9Y3bdOkPv0jXpwHO3+OSFRU2Dpo+r67EasQ8sv7n7kD9k42yReqF2SHhrQ7k0FD 1dnEZUPUq0wW11aDp/vxF4MEehyFLK8A6qZsSHhmdcKA/juQtjtH/XISWMg X-Google-Smtp-Source: AGHT+IFQrHdSfh4uQwEiwZk1opfLaXFZGV+Drf4WLkYL5n0pxUJKq7F54DkFHkMWpsM7QWSNH3Dk+g== X-Received: by 2002:a05:6000:2ae:b0:386:4a16:dad7 with SMTP id ffacd0b85a97d-3864ce495c9mr3622598f8f.10.1733934064670; Wed, 11 Dec 2024 08:21:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/72] target/openrisc: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:42 +0000 Message-Id: <20241211162004.2795499-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for openrisc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-45-peter.maydell@linaro.org --- target/openrisc/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..3ccf85e95f0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -111,6 +111,8 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; From patchwork Wed Dec 11 16:19:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C698E77180 for ; Wed, 11 Dec 2024 16:26:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSY-00015m-LB; Wed, 11 Dec 2024 11:21:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSW-00013T-OG for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:08 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSV-0007pT-Ap for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:08 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-385ef8b64b3so5589194f8f.0 for ; Wed, 11 Dec 2024 08:21:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934066; x=1734538866; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=upixniKzEOa/S8RuV1mPlSnfanTUMOTGZth3cr6koyg=; b=wweJC04kThYMzGYHF+xt221pAitEWwFwb/kxhw0Vjw8kqXg7P4qZg6KDwx81oMZyJV XJ4UR6G1cTgmonPslH+I44/mqJS1sT8Ez0I4BzS2AbQW05JAe4UFmw3kBq638yfrWDa+ ag8jsYCFY9734RrPWcl4ES2ZmSMH4QP4xswUNC3iw25dJUtsvT+6Kz8RRmig0xuitLuG 7wnik7/DA1oqr1ZNa+G3JrPsDOexw9xBWQCMiOS458OGIyPcVhcTvrVBRMeAlnmMhrgv I2dzzLVfDMXK20kWRd2n8E9KorNKUP30lLPvQYUB+a9P2sTE3YR5cfiuHC2AqQuZ9dbn 3CTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934066; x=1734538866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=upixniKzEOa/S8RuV1mPlSnfanTUMOTGZth3cr6koyg=; b=sZjbo7M4WijXahJo9HLHZlcOIe+dksKtMmIbFruC3bqCSL2I5TjB81Q/EoBgnBsKQh fXz6KMVFne06p7A0vP0uuG6YV59U/AvRmz20lfwUJlS+jLOZ6y5H0w6XJTgduVw1VaVd TOGX9rTwmFxs3Nq7o9Lto+xw53FRpBn3DU06ypI0e+01266iL+glD5p2Q7HVZEqsBuQ7 foeQQbnYmEKVsV7iQHnemJHU2yH23KNb5q6fQEVnj5tAvScOUWNSU8CV5P0Xy03O0Qax 4kiNN1WUqz88EoVmP8/5Qn2i80o2fnGGJmJhu/YCxglb28iaxlIAaJgjvulJJv7XaEw7 Aj+w== X-Gm-Message-State: AOJu0YysPOkb0m/6fiEvNVngdPmD4jE1EFyjLKr6hCHdq6d5zGebJA/h zOoc4gJ9FaZdVcCktdJVINNQDzE0SP+zhhrQnUWqXVg3zztXdWlmlQDu7EMAfjHsm3LtfdbLBZU z X-Gm-Gg: ASbGnctE1A9CFjJmVxDw1fjdhLooFpJXZJIAh32XGwVaMhXFAO2MzONSgO0RRNiE3hg b6hEI1XOxR87NMaABKMK3EGWebPHRhEPrI/vxWHAlkqGo+KEJzVMPXPt1vyQzOVEx7w/Hm7XO+x F9o5xu42cm7kTQbqIBHz4b/1CcuWFNJ/bXXdut4mS93lTtkvtrmoazDtfqKdRwWkNBZiqdyU1fU ns1NsUqnFUBJNYTQ8ElKTLWs7Tn9zNDQdtAa8sw5eEsHmVPZRqHuyXWq0pA X-Google-Smtp-Source: AGHT+IFG2SVLjAz1bdN+gruzFUiAnqPE3iQv2Lj1DysdWGswMOPVqOy4QL8Ek6WmiBalhgbTan2y6g== X-Received: by 2002:a5d:5f8f:0:b0:386:3e3c:efd with SMTP id ffacd0b85a97d-387876af743mr186911f8f.44.1733934065661; Wed, 11 Dec 2024 08:21:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/72] target/ppc: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:43 +0000 Message-Id: <20241211162004.2795499-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for ppc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-46-peter.maydell@linaro.org --- target/ppc/cpu_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index eb9d7b13701..1253dbf622c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7286,6 +7286,10 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); + /* Default NaN: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); + set_float_default_nan_pattern(0b01000000, &env->vec_status); + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; From patchwork Wed Dec 11 16:19:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34C5AE7717D for ; Wed, 11 Dec 2024 16:22:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSc-00016t-2f; Wed, 11 Dec 2024 11:21:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSX-00014r-Hj for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:09 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSW-0007pn-01 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:09 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4361e89b6daso5563285e9.3 for ; Wed, 11 Dec 2024 08:21:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934067; x=1734538867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ugtcp/+++sWtSJ1G0yYLp/YnlSvG52c5wPGIqMMfBnk=; b=EI5pQMr1/4+fc9qL2TtV9PbfCHi2k1xWzOsv0CW0zdx7QbBeugroDHhLvXKAjSlsiM 9AR4vtiVm1pslW15XLpjAxdKpNAU+tYGaj9sZmn142n0iHzq0qHJ4y4nhbU3DhpG6+To CTXbJQp/TXQ5i9kLuxNFRNDnUCBqYo7X81T88zWKK890u07EWaUiIIP78OlODEtQCGt4 pdp6yVGCAkd+zCE220NhdVkTcde9tsSecx31qoOv56wPFC20vNrBaxA53H3vC+jrZ2Fa zw2xNMSmpVJXardY07qkN40Ub3SBrvTRbA69HKQXsl9WumVzMd231Vr8XtMZEPVcU/B8 CwZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934067; x=1734538867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ugtcp/+++sWtSJ1G0yYLp/YnlSvG52c5wPGIqMMfBnk=; b=r8504lJycQL/uyhpflgJWDsfS33yzQqnDVEq9olv0rziii+RwJY6VLOpueG0hgYkDm UusQd2Y+U7rt3KJuSFrbWCyD13+L0egwy7iIpeQpH3mWI9TmKsGeTjHgOOsU4gED/A3Z Ey4rXJ/QJlOp5pMYz2Vf4pwEFYUNyQJawAjkW3dRVWfAuh1j23U1EF9Y9I2k7H8sg23O fC/wTDnlwN/KcP3FsWMolR4orHAPZWFJndELS4C/gyXd09jbphUnxlUPX/AtxkHdXllb o9rbsfJlQe05K7l+5CVaNcq/EZeHJhudchsixLX23HbAQGCcusGyfSU9Fskdetvt614Y gpOA== X-Gm-Message-State: AOJu0YwYoRmzO7e0ilPnMoeHvKkWUfO8XB7Ff52ZHJGewEIgYvVbgAYb OsMqRfQwceT2a89AOTAsKVboil5KKBuvviAHwqZroU3enmcsTf0l2HDcpzEJv2g86Ngiqk2wvia 6 X-Gm-Gg: ASbGncuDfgKyC+MyZ6qO+agGEbkvHtIXwSeFsurIdzuBBeOPG6ADnrSw8iC+eb3Hup/ 6qSPEy2b81wF604llfFeffpfR1OFWW7NEdplh9Gn91aaBZlYEXyrx5TBgurb5oXG7g8MF9AOBxx 9bRcAY9g4BtCCJFbWgecvbUnYBfsXySY+eUApMJUGHjzTbkFnLEcxvRcac0PgYXr5cyPtGNYeJS Sh6+ruX4brCU3Ryq/Jlow9+J8GY5aXH7rcsBV0ojeqcryhlF1A8hjPnaqF3 X-Google-Smtp-Source: AGHT+IHMmrNjBQKmiT5rg7Y2Wbnn06mxx+QvUxc4VYq53zXyRFnP5NZ/S/65803KHQGUC7v3KzuuLg== X-Received: by 2002:a05:600c:468c:b0:434:9936:c823 with SMTP id 5b1f17b1804b1-4361c387b63mr28773025e9.18.1733934066682; Wed, 11 Dec 2024 08:21:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Note that sh4 is one of the only three targets (the others being HPPA and sometimes MIPS) that has snan_bit_is_one set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-47-peter.maydell@linaro.org --- target/sh4/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd..d5008859b8e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -127,6 +127,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); + /* sign bit clear, set all frac bits other than msb */ + set_float_default_nan_pattern(0b00111111, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) From patchwork Wed Dec 11 16:19:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D293E7717D for ; Wed, 11 Dec 2024 16:25:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSw-00029d-VY; Wed, 11 Dec 2024 11:21:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSY-00015w-PL for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:10 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSX-0007qA-0K for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:10 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-434a044dce2so77598405e9.2 for ; Wed, 11 Dec 2024 08:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934067; x=1734538867; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lp6ND6RqUxytAfiDR0J13A4aL9KjQfAUqGM2pRH1+ko=; b=l4/DQnHRs5EkyrXQFQfH/oIlUmI8nWfM13sO6tztd9u/9uuQoa5xi0ZZVA0eZviGua ZPGjNSyH5rkHff+a+KmnT9QZvL2oE3hTtEU0qHJPc9reyJTDAiEreeKZ0ihU7E4jWY80 5G/aZ5KTT0d1Kf/ajRLFR6bXCjGnWCZk2IIeRBOp9wNn/K6n/F5vpWjaXvwgFVUObt2/ 8wJfCRU9xh1nCY+quHwJGwdh3d9oB5w/UKmKe4xP+9xFWiYBLvKaXL+z/p0pvQNgbbz6 nsPm+QYhtl27Adcnxyarjn9pgdg5aLy1qZlxAfBnNRjkjFzNJCREQhbYECUejs71crGm QHyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934067; x=1734538867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lp6ND6RqUxytAfiDR0J13A4aL9KjQfAUqGM2pRH1+ko=; b=pTclqnMGnaNOkqWrrJWMcFa9bvYUeln7S3N2y2Zij6SZ0S5iBb7dFW2PECoMLSakPU 47QBc8vBckgZlCQ6cd556jea1QTQiTwjhK45qc0Eedb9sLCETKB9d2A6hASZTAescDBv Aze2UJr/ZgynI6JkmRrSwLpERV0CoK0xm4KfsGwJf+2pBMSCBbqRvKH7j90VvSllsWnH VfKQEItrribbPezxcPHWwr7N14yL4A00ev6bdBS7EJDNWD1Npq3Kpvv3M5DVNplScu6o NyjcK1NhU3UGWqtARTuiHobLhDaXmA10WqNhXpGORT2oj9gtULYcOQksIF5XM7GfZ1On +KEg== X-Gm-Message-State: AOJu0YwKm+RXMYeccp+H3cbhmK8rg6Cx0cIB3U911gmaN34RusHgdMzP G2WqT/B4NU5EwyS5qh6fU4EAAK9E60uppYV9+4ryquevtVVSdzHUmE8CdUrJzqMZkzDVkB6Ahxh c X-Gm-Gg: ASbGncuShOlhoyrtIZ+SyqeKRDPWIST4Sce6m6xVrThSyGDvsTiR9zvA7WU4S3+g0fL 0cHeIskrC1x4Ju0ipjOVofJhTTraQYxysIxL+wEu8ol63rAa9Wmex7F1BP3nnHeXSaGmiDJQWil lWH5lkxDosKgymFu67RW0/07TouMdrbA2ADf5XdDXSrJVxWFDw6nvV8hV8NJrutWufK206lf6FY /CBi14ZEvkzjn85rAE6SqAcMQzOQNzns+GxPt78Rkref+1jKxFxVQU6fbX+ X-Google-Smtp-Source: AGHT+IEoT6geVVer9wEv0tcAkw+ech4MwQIsRJdOgPTp9GEztdsmdFvXJCa11fPeMcnnypooBSv+/g== X-Received: by 2002:a05:600c:468c:b0:436:18d0:aa6e with SMTP id 5b1f17b1804b1-4361c396ad1mr30778415e9.5.1733934067663; Wed, 11 Dec 2024 08:21:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-48-peter.maydell@linaro.org --- target/rx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f..69ec0bc7b3d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -100,6 +100,8 @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) * then prefer dest over source", which is float_2nan_prop_s_ab. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) From patchwork Wed Dec 11 16:19:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6622E7717D for ; Wed, 11 Dec 2024 16:21:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSk-0001Jy-Cp; Wed, 11 Dec 2024 11:21:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSZ-00016P-DG for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:11 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSX-0007qT-Us for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:11 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-434ab114753so46294045e9.0 for ; Wed, 11 Dec 2024 08:21:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934068; x=1734538868; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vq/x7YW4KLHoHlW1YH3eegjJxd8Sl/753I0gqQuiK/A=; b=eWku/iYwaUdCwwpAx/5hN//jkB/PnVIVMTuLzIDGcpl9mPI+NpD4Gd8Yu0yQdi9eFR yeU1Js2Lnoa25tvG7Ii/87GCh4rl87bYw2MM0C4P1vb0x4ZQMvQRUN3Hi8pH9zs8hlWT +AjMSxnCkCS0VFz/c8DPMX1YPGZHigVwBHp/g/y88xSaXDZM50tS8jJsKqRSEb9LlekG 1S7jzp9zr8IPcQI9wB9D2wEvjz+OMlMbX2yO4Ws5Cn9Hic4Nfwdsb8/z3kiAvDhImsoM OQ3lLIiyDdAZDY0zlawBnfmLs5vghWtUDiSGIQUYQLLZSrgZzvfD/fKD8ZCYy4C2X1PR 64KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934068; x=1734538868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vq/x7YW4KLHoHlW1YH3eegjJxd8Sl/753I0gqQuiK/A=; b=wuA6sXrbP5uUb5U6Gs72R5pwkgE28Wxiw58DAGKUQDmLrM14yrzX09cgmtLJOBTdv6 xwx8MF8uenPat0s/1g7SL6E3PqMXvkVEG8vBf+Ci8whbD+1mTlwTKpGBnw1MFbqTc+Y9 xIQ+0aODrHdsBrcQYUGnykfa525C4okSa4BKepoAimAOwynPAVaFNCl1M0lWL4/hjI0L +NdkyC0cKlHo4b0XVveg+Yy1sx6IuS1sgCfJg+SvxuqBGHI8yhYuBqrZxhgV7g+UJsKB IYOoJMYOzngZ/YzTiC6nW690j8Xf6LuZbEucNfiA02nbN7qqjtS62NRthIbQEI6oGt8u 892A== X-Gm-Message-State: AOJu0Yx6rtr3lIq9qxCeDfpArkiMYUNViqGXI0HKTEJHCkZbDDD5TGSS wxiAeEw7zy6D0MyslN9g0K2la05hIzScMF6AHODHb9xFRInMxlYyi0TJ43i0rIFJygGW61VzEf2 a X-Gm-Gg: ASbGncsYq62dND4/uMpsh/3/f0trzorZIFMJIgs99MlIFLjql0sd9/gE8VzThXT7Wa+ uGTRcSjNBAfnXwDJ2OBYdmvw7N034efjYPFok6qI2HvsVsinCUrllFuEfJNYwIki3rHZRhXFn8h 4nW+XgmKAriHhRzMQZl2VOZYautTtAn/8RJAhkFslJEfl5DS0HJaeV1mPXZRuIkAktcOqKEejz/ dpeh3IguJNOAYSJa3lWrjMJ8Zlj6eQmiFiiSA5VU3653QKGEqY81zCdk7Zg X-Google-Smtp-Source: AGHT+IF27evuIVwc3KpsFFGiZrKpOnRemS/MHgCAONqWUYewZWizlXehc83Oo4NJT0UDGLjVelQmZw== X-Received: by 2002:a05:600c:1e23:b0:434:fbcd:1382 with SMTP id 5b1f17b1804b1-4361c35cef2mr27444385e9.11.1733934068595; Wed, 11 Dec 2024 08:21:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-49-peter.maydell@linaro.org --- target/s390x/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index e74055bad79..adb27504ad5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -209,6 +209,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; From patchwork Wed Dec 11 16:19:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B74ACE77182 for ; Wed, 11 Dec 2024 16:27:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSu-0001ns-5r; Wed, 11 Dec 2024 11:21:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSc-00017V-5j for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:15 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSY-0007r3-Th for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:13 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-434e3953b65so32390595e9.1 for ; Wed, 11 Dec 2024 08:21:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934069; x=1734538869; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9o6ZrjR1RXdiifOcsykBiN0/Ne/2VfOey1zb2DGye7w=; b=nbCQ141YnlGsGTxPBqyHsTALXTdBHXmDUpH/Tb0PDeOeTNIti+i8b4TUp+RwMCMmrX 7EhXk2AXp0VlZ7dGbgY6kq50hPseGEQKiYUFPp4hr9ICXD7+NLDZPzzDnnOFAAoppon1 EZY5hQV3g5h5aq3oW666SkvUuWBxi0RlIcYewesVrQSdp2lvb3UAF12WCYqCfJI7y7qG FQDBtJDWvvfx+GbcxQNFJefOi2OUKfxoNMwMYijDY+uoqZdo/NwPZJ7ivwFuMf45lp25 yLKsfmnkBO/7lld4PrbDUW0Y4lAjMXnF4FdnWZXZ62R3dcL6e0bJpJNZS61/KBfffccZ fvzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934069; x=1734538869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9o6ZrjR1RXdiifOcsykBiN0/Ne/2VfOey1zb2DGye7w=; b=UtCIQfVw0Bbkbc/vzM+DPG/oLF4bE35ktK65qM704JNNxLyhhp6PvtO60PKPtvpCzb TfRvn00CEVF6vACiIYLYvcfmuTVh2zIlh4FajbNKc6bsthZ/8qq2kYYrs8+hvRz6sT1p wb07aqYzNIO2nay658La/hv7ramUX1Dq4MWKdleDr+i/li+VZwpgibZzPJ6qW+yQXYPS HpNSjWDoaRAdledGnhBr+IJohzDy7Ss34odBTiSXDQRNgFjiUiCCDB0NAvTjt1crsfki 6D+ts8Y1qYqP/peoMiF2QgQRw2c0aGr46NxZMQVqj/UEqdpnPRhDCVBydzFj+TNLFI8Y LX3w== X-Gm-Message-State: AOJu0YzfLcq8faK+6h7A2uWOVaCTmsN+iCfF4MiAilvwa/KKP0ibPNL4 80GvO1ht+twcjoJtfr3p9ySTdNHgcjFUE4p7FP6bWt9cjhSf8OYSKPkjpfKhy85CeAWoP/yepZh L X-Gm-Gg: ASbGncuhzMMjTff/aBiTAC67Doy4d9QmMn9Jayyx+WCGXX1PodcfLyPZGWrZNfHUNAs J5I6NY6A6SKzEle+0Tc3dmmHDeZ/1bClyUz/f3kC1H0Umj/I1fX6YI2gYJ1zNOtGFjeCZD6ERvJ x4UmyxR1hAXs6R0qGVzZ27l4Ko6PE51oMqNw6T89OMehmp33NoKteDu4VhEg6oW80XiPg2geUjr k9DKrv7/Z1xM+0/I1LgnqlOr5G8O1NXy6n0jPdp9Fhhuhi8TmfnwtVFRGoO X-Google-Smtp-Source: AGHT+IHqVR88LkgRBnC6+5ARv7C3/HiWXj7511XV75AsnDMYaXnkkpS2Gd65CSgTwrvX1clpp51mOQ== X-Received: by 2002:a05:600c:8507:b0:434:a29d:6c71 with SMTP id 5b1f17b1804b1-4361c411ab0mr25219625e9.27.1733934069518; Wed, 11 Dec 2024 08:21:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 55/72] target/sparc: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:47 +0000 Message-Id: <20241211162004.2795499-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-50-peter.maydell@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 +---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 0f2997a85e6..6b66ecb3f59 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -818,6 +818,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN value: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ecb7a52ae7c..06185237d0f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) - /* Sign bit clear, all frac bits set */ - dnan_pattern = 0b01111111; -#elif defined(TARGET_HEXAGON) +#if defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; #else From patchwork Wed Dec 11 16:19:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 823D5E7717D for ; Wed, 11 Dec 2024 16:27:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSw-00024H-CW; Wed, 11 Dec 2024 11:21:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSc-00017Y-5r for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:15 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSZ-0007rK-Te for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:13 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-434a766b475so66350645e9.1 for ; Wed, 11 Dec 2024 08:21:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934070; x=1734538870; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XpM+Fzv5WnqhGSvzHLutaRhswGeDxDx6i0Qnjz1mXt8=; b=PnNTz+YeLienfdHbuvWPM5mftwXfTWbwfo6jOyHx5L+88ZToN0ci6RKfdoC0vLbXpi nH7ObMZ3zdp2m3YiTBYVRWml7nFGXRmTjO37lR7z/VxGNZuAwNup39LhYMbPTCGceAeE yr02uqQbGr+6Wtfje1zkG4t3oJbSYvXBkPmC8RX9FNAHlIrEAMGSVQUu5dHe3SFDjb5R wDMFdRydveZcMV2pG5iIrt8LFiF5IbRpb8VL/Pi3NnjTev5N6upmS5VGCLkCWNXTi2oP 7RRs3hbbD3Tv6VdFrNjBRQ2MUrEXCW9m81QzVjkDsyu1VIjUJ9SsTh6GQ2GLUKQZyHkx 1SlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934070; x=1734538870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XpM+Fzv5WnqhGSvzHLutaRhswGeDxDx6i0Qnjz1mXt8=; b=X52QdD/ptpvhtRTMM/rrRQQgUHX9a9oNfeLXPkolYQAZuNBYOx7FreFfSr4NBh9kpS fNvkxzoM9+WXLR3l+FmZfePWyOCkTpo3nmKgR3abjL4jBFm7ffABc+8yI1g6DXDcYpnz hJ5Zpa3aNsQMbmmMnfTHHXGgK48tsNrY6e8IGwUGpQ93eNnEIBY8i9bEt/tkRAcMD0I/ aGgdqZmFnTSog67/L3j1M65wKR86ioQ0i5cVd4mFm0kW/mQMkSSa3AmLfXPoTmv2VS9p TPN3KfEcaAkaUmtVeYkF/rCKgd2HpZExWyqd22ahJbt4+aEvHkuHxfDf14zdQ+Qtb0D0 O0uQ== X-Gm-Message-State: AOJu0YwR9iwbAO+E+0McTJ6+aNDd9DIwunfKiuDBZHcvxe7utwfxkZTv LUzw/7Unxtunin7zOIqtuZv1dZQMRd5VIMrc4lFsL7QtxibX0DmhIHJBbG3jFTq+WdOOXSZtzS7 w X-Gm-Gg: ASbGncsQqm+W/RHvwXzIb8HSM8r1vp95eHkm7zcajNstyDrfjeLJJgHo0HODuv5TG8V DQEXgAQXafptBSLofKJeowctUmGg99BCu7gy9bP9se6fIqOOxQ047PUBf58uWE+oa30YYwNGqjQ YPbeQ7DwtGsi/EqLwYjF3Nymk8umG7kj8zGzNWFR6MjtVunSpiQSX6/Q0GacmV+KIIXo/MCZu3H Cx5RtTB6HlRiR/H0aqafx/hHjJeW88sUOBfXTREz192Eo125xgnVmkqM3La X-Google-Smtp-Source: AGHT+IG6jpYoL8nXZRFPcUDg27VSevSz8bvaJZWXLGwW9xicghk3Ie+thgAXNUNmhA1grjsjd7DDrQ== X-Received: by 2002:a05:600c:1d20:b0:434:edcf:7461 with SMTP id 5b1f17b1804b1-4361c42c97fmr31285685e9.30.1733934070547; Wed, 11 Dec 2024 08:21:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 56/72] target/xtensa: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:48 +0000 Message-Id: <20241211162004.2795499-57-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for xtensa. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-51-peter.maydell@linaro.org --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3163b758235..0d4d79b58b4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -136,6 +136,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } From patchwork Wed Dec 11 16:19:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903768 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8C55E7717D for ; Wed, 11 Dec 2024 16:25:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSy-0002FD-Hh; Wed, 11 Dec 2024 11:21:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSe-0001C9-3T for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:17 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSb-0007rr-Gn for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:15 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-436202dd7f6so6283315e9.0 for ; Wed, 11 Dec 2024 08:21:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934072; x=1734538872; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IFPKx6cYxrOvlpHIeqyqWQFosyF9dmEm3zNoKTLP07g=; b=iCAD+7vpeNZ/9IrqtOG5bA6q2iOm009NOckFR+ZiYLY2vKwp2+XxDwJcFTAGMJMygt WdLWBHYjWqm1myyp+jjsuCRnl0FLmLYVfoBfly+qWHqXrlr2B8BEVQXOwTSgWyTKCac2 J3yTjIUSy0huTinqHGJGu7/VHLbiCtk3VAHh7fV6LOwgqCMfHatmTck6fLJ5EJ1ZqE2E 8xbHZNLnJ+cqYospH/3LFaB4YwEMy39d5lbdDYmev84noJQwDvmbZ63KL5TmWyn/DI1P /0JctsF1/opeOG+KfPbURehpE1uX6cfqsqyYTGhw0JHMjB4H+lQemgfHvioN/Trht2uL ur8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934072; x=1734538872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IFPKx6cYxrOvlpHIeqyqWQFosyF9dmEm3zNoKTLP07g=; b=BpUm4WpUs45pBxdM8J9FiD5uWOjOX0WtjVmq+03yezd79yT+HSu7KIken2vVQvleTb Hm3JLWzZT+blgi5qMrTjWo0cxgGNcHj2q/TQkXgt63daHoiqz4rQf743fe/R2s+fJ4J/ hMOLmZv8fCRFlmrw1cCaEP6mGZdl+3ZNr0+5S4IjR1LDl4z1uiwPD+DC6xzwF4oxbEg/ o+UZ5zvvyC/VQkVregXWh57whxC2KvRsKIuZFp3FCyW3Mm9HVR84lgYaOzjes/QsblG/ lelcZhSYEF9i0kZf2zftFMgfm7M/797RWbQCR3GGIUqwa386VnJgUXgOlh9djQ7Zp1Ls 6kmA== X-Gm-Message-State: AOJu0YxzHuaKIHa0A2udWgnc0HTdZRQWF4Jhj/9osk2Hcz8lQsXShA+V CCo/FZ/MAOyGWyrEdUwO+g6KYN3q+smuGAc4wVkkcYMxX8iNv7RgVz7FnuoHqAiBW9Y3xqxf+FA 0 X-Gm-Gg: ASbGnctJ0VnefmLcd1Ft/zkLiTBKdK2zDQwmBgE3R/efg4ySY2UK8yvWV4uYWuiznJ+ m+IXpEiyfSMQqRBmt4dNTOoSXTZe72aqr+vN2AuhwFeMPxTZOkGzUQ1r8i4EgkOSDevkAY6VoSN v3dI3we8jOFh5OlU0yqVKkdl3NFXqfEjzLmeE/iRPyZs2Olp8sWZMo4fcRibQzbyrSOlacqHowQ Zs8QpvytvxyUUknQlrcq6W3l/4/7zNkNCXfvXjczLAs2lFU4wPrX2DBaAV8 X-Google-Smtp-Source: AGHT+IFgALN1tr+hGo70Nn9IjutlVZg2DSV8/SNXwZN3p4s5bLCivPQIv+sT6nQ/dpQB2Hh/IR/CAQ== X-Received: by 2002:a05:600c:1d2a:b0:434:ff25:19a0 with SMTP id 5b1f17b1804b1-4362286c0eemr2809375e9.21.1733934071983; Wed, 11 Dec 2024 08:21:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/72] target/hexagon: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:49 +0000 Message-Id: <20241211162004.2795499-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for hexagon. Remove the ifdef from parts64_default_nan(); the only remaining unconverted targets all use the default case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-52-peter.maydell@linaro.org --- target/hexagon/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc490..c9aa9408ec8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -286,6 +286,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); + /* Default NaN value: sign bit set, all frac bits set */ + set_float_default_nan_pattern(0b11111111, &env->fp_status); } static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 06185237d0f..5954a6213b9 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_HEXAGON) - /* Sign bit set, all frac bits set. */ - dnan_pattern = 0b11111111; -#else /* * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-53-peter.maydell@linaro.org --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b52..80b09952e78 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1022,6 +1022,8 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); env->vill = true; #ifndef CONFIG_USER_ONLY From patchwork Wed Dec 11 16:19:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B097E77180 for ; Wed, 11 Dec 2024 16:25:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSs-0001jm-SS; Wed, 11 Dec 2024 11:21:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSg-0001Cs-2G for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:19 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSd-0007sh-Sd for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:17 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4361fe642ddso6103015e9.2 for ; Wed, 11 Dec 2024 08:21:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934074; x=1734538874; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zslQ1Gnt7shcKGxYg5Es0RVybgupAdobUOUAJLVJUTs=; b=m+XpC6JuQha1T21EEYcFJNdYZio1FJwhfVVMECyz/EXZSzp5Gqg75htOhVbTbt3LwY oZE5zGTyWQz5CkHgQBt5o3v17NKiPyPerDRlfZQ/3JExjJz2BoBLay19vJpHhQjPX8p3 RagNSvQxw+HAjijJVCaXNq+Z13XHHO0OXV9VknIrI7R16dSi3tzRobS2j3Kn5XlexoKc LOwM7wjy+/3OiLvmoyxJ0pUXkhmAvwzFwXVjlYxhFkuRLYZ2vLd2EeoHrbSTHsJ1n1Oy ZHwUYIYM14GOfS7bqFFaF6BammIdQ/kq4JuFQRfdY2kru3uueGwyU5rma7s8Uj7Vf3+q m1ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934074; x=1734538874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zslQ1Gnt7shcKGxYg5Es0RVybgupAdobUOUAJLVJUTs=; b=fg8OfArnvmTX0UTzVYL8p5ty0FxfvxNVuTT3PVB7/8jI5pplWYVdcWn6LqjOvKpynV GNZUsfSm78IlLOf/qrGBTiyPBVBesUesk9BaUFAuz2gzxojSG40sCtk5h5PjTIbFMnzd EmYdJ/H6aQ3KcKA8jGgnFhX8uoPs8xr6Qj8bBnWSQo3dJ/Gg3WFPDfi27e1K38jnUWFB AhMt8zqKLvFn6X0A/x7OYNB3s7BK2GRXkh8Jtqyl/oNJkV6cNXnaLD6LIGiFW2EnOEEq rnJP95AXn+pC+0b51y/AEa9wo/KCQ3s7DFp8aCLZ7eoCDRwU67kXVLYSzI53ce1tRpA6 xg3A== X-Gm-Message-State: AOJu0YwgHpB8/77j1OrQoIFsLHRMzMxiUXxra0G8EhUeY7w85FlkYM0d rLt3UA1kQAs+nFpqe9iZdF8H/dc4i1IwdRrbHJqi/9newWJUsO/ZG/FaTrEKYn9X9ESmIekzHXk B X-Gm-Gg: ASbGncsjGIiMW53tEHAwN5XFx1MfCa+xtvnaHxzULBjg1cVKL0IV6dEExS4lZLKV79W eehP9I+NRnGki7BnURnuzQOnQAtcD6mySfTVaIOkup+thZ5jARrz6ueY8rEcwWSAkAeZ7j7N2wL z3M9/lvPckI+KHpfUjYkKOmQ+ujX9vBxNw6E9DkKb+jMozdKf35QFfm7T/Y2UgcGw6tq4rS7ldL 7k3APnIruNbCEiChGdB+i5MZBPyQKNK54cBwt6OfWvIYmXM1FBNYIdgV92B X-Google-Smtp-Source: AGHT+IG93sTCS7pfpSte1qaP5ez/rcmVcmwYaqRdTzFjp4auZSL7sdpPOtDZUS/ioLH5aUnPF1W6jw== X-Received: by 2002:a05:600c:468b:b0:434:fd15:3ac9 with SMTP id 5b1f17b1804b1-4361c3e3aacmr23674805e9.22.1733934073890; Wed, 11 Dec 2024 08:21:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 59/72] target/tricore: Set default NaN pattern explicitly Date: Wed, 11 Dec 2024 16:19:51 +0000 Message-Id: <20241211162004.2795499-60-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for tricore. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-54-peter.maydell@linaro.org --- target/tricore/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77c..e8b0ec51611 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -117,6 +117,8 @@ void fpu_set_state(CPUTriCoreState *env) set_flush_to_zero(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); set_default_nan_mode(1, &env->fp_status); + /* Default NaN pattern: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } uint32_t psw_read(CPUTriCoreState *env) From patchwork Wed Dec 11 16:19:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CF80E77180 for ; Wed, 11 Dec 2024 16:24:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSp-0001Wm-E5; Wed, 11 Dec 2024 11:21:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSi-0001IE-2e for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:20 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSf-0007sn-Qw for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:19 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-385deda28b3so5144678f8f.0 for ; Wed, 11 Dec 2024 08:21:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934075; x=1734538875; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+m7UpkWXOD0kaMSleyeT/gE67bFfwBTpfKeuDgBDdb8=; b=HFBgsITz8lrQ7HgtPeEsRx8aXiJZdJGA/DaNzap5B/mQO01xx6FyuFEt7rOQK8KNtG 7T+zTQmbETUZjMRjWNyVw7oOw9DRO/jbU2uke5at99ZTuVf6NOl1dtoSvB5w0TKCPou7 PQC2WXPCEHFTYiIe9dxFUMMi5J4kv196Od2EPrAvCOrzSxtFxkpAkZZYQZsCDdd2tODj ooZA+nrEA+PUHqm976+G46fjPWrBE0vOWeArSV5o4CYoQuhaoeE44twb6p0FYXC3DACe Ncw9pF4tFJeZ4bsRrUZVDbMwc0Tg/EvmZbcaedYyuqfpeVStLpc3NWCctqxjNcK/6jaO dzbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934075; x=1734538875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+m7UpkWXOD0kaMSleyeT/gE67bFfwBTpfKeuDgBDdb8=; b=HfdmrxjgH8hEjHgNduCc8wB6Vg4cT9lTvXTdI40NnH7rnJ0gQLR0hxHp/ArHXm/ue0 TGvCPvQnEKaqLMRnH0oT0Qo7Q0cX23KA4jLTzjXi2kzJdBhxm5LFLrsedgLc9lrAfkei Tj4cLLrb9CeD69ALzWHJmKcLNhDd4nVhrWHJ8fmA7I4xe3iFQbYLzoEd24fkhfcMUbti dZuUxbW3ma0Na4QWiml5IJU4ZMR0NNC3kg6FDI2Pur7G0veudRGKHXUeWWshsQtbUHmr gondn5sAYlo/c8z5WwbPdJVGIKnru0AA2ide7yhdtDS+HKdaRG6f9mELmsBOtPq1u3xL GH6A== X-Gm-Message-State: AOJu0YyC7hwWZGW5rM2+ndZeDNKLhghUdWg2gkUgBPrrCkDjzOgmuJhj W1SCW7xIKws9KZqaY/nddY3+i+iNYAgZxNhjtmUksqn+lpFDP8fEc2tPMfGnOtGCAGQeRC9ufXB c X-Gm-Gg: ASbGncuI7/bthH1AooEFMA8W+vMhR6rXLkFnfy9Zsma7i5w3cKunEdcBbyUeTtrliGV dkHCiOZN2ijBkvWL+hGyhm/bt0DsjDcLkUPqHKU48xtH98NWzTJlR6XCqOFttxSV6y6R5TncAuj 6dW28wY6BqEN/gj1M1i7n7FIi/QK6XesXVweX+V9+TsiHrOyy1xafRjXi4BGmhAMSRm04Dgb6cz 5N68esho8aAqB83LjLi0FdSvQtPHvWBB8ZkP2kQC1o3LVyrsGZiAp+Lajus X-Google-Smtp-Source: AGHT+IEMfZL6b5VV69W+JW/c0lvj4LORiteHdoaWiUeafzKSnSELulH5iEbr7d9LOvHB+4DkGx9cgg== X-Received: by 2002:a5d:6f16:0:b0:385:ee59:4510 with SMTP id ffacd0b85a97d-38787688638mr208420f8f.9.1733934074780; Wed, 11 Dec 2024 08:21:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 60/72] fpu: Remove default handling for dnan_pattern Date: Wed, 11 Dec 2024 16:19:52 +0000 Message-Id: <20241211162004.2795499-61-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that all our targets have bene converted to explicitly specify their pattern for the default NaN value we can remove the remaining fallback code in parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-55-peter.maydell@linaro.org --- fpu/softfloat-specialize.c.inc | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5954a6213b9..e075c47889a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -135,20 +135,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint64_t frac; uint8_t dnan_pattern = status->default_nan_pattern; - if (dnan_pattern == 0) { - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* sign bit clear, set all frac bits other than msb */ - dnan_pattern = 0b00111111; - } else { - /* sign bit clear, set frac msb */ - dnan_pattern = 0b01000000; - } - } assert(dnan_pattern != 0); sign = dnan_pattern >> 7; From patchwork Wed Dec 11 16:19:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2A13E7717D for ; Wed, 11 Dec 2024 16:28:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSq-0001eg-Qu; Wed, 11 Dec 2024 11:21:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSj-0001KO-Pi for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:22 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSf-0007sy-R6 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:20 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso5906855e9.3 for ; Wed, 11 Dec 2024 08:21:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934076; x=1734538876; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=D00DSruytulbxjjJ4e78+Qdhi69cDsAe2XaYdtO6NTo=; b=a1xpGjNlSG5xouRdtwNQ5CKigMBpMpaOvgWTe1gWlcNe0dPfGJjYizSTFXL5/QKa52 wQhJ2/yfWy9II3X8WXj6kPYI/8vkhE1/wk1J5Q42Y57M+9P4WT5EU4VSq7864lYQogSW xNoXCwf1hhWjEm9LVWGEfjaqDn5LJyAiqZk3XwxrKbkOVKanE4fQ7mf1Buemce+hdKep BO9YANPoMsjcWMZ12JrcYHqiCQycUF9TWDFD+d3dhHbpFFwHn+CmybZz9r86PNNVvJLr pAvsKi5XOLwihy5VdLjoSx05SGlInIfGSAjAOWSzNKYN/NBSlTNUG3M3WkhK1UckB2vw 9Fbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934076; x=1734538876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D00DSruytulbxjjJ4e78+Qdhi69cDsAe2XaYdtO6NTo=; b=nXyizC3SOPEvaTbPOwBSYaITcyerRcCf+qavOZGWH+YnXx0odO2v88SvzLoNs2Zo3A InVBGYNy0eODTjFTNJ2x+6GjgMKm9iP0eNenU9rDD6/dRdTatOKSvVHqYZKme88EcSg1 +Poa50EQPpx2C0uNGZWsbXx/WfpxjHQqnfNmW/vaMZ9ZNz1qO3CmGV4f5gFrBGNd6DqE 9gSgEp4esF7kYktXecgNXJ07TH2zbF5HsvpkfYMJuPiKHQOiH3avk12E1ks9OccZ8UKq 0ceJICaCc+w34AOAE6o18iwBDMP9tDhfT9GmfgvmOLZQkQyYfIIAF7UM0RcF0egBCfTW tA/w== X-Gm-Message-State: AOJu0YzHdKoISzq8IFKdXh/Wc58Huc6awyci6KXKICKkFCD08jvSaeXZ hMTkt+IhxlHMHcmoOWvoxdb7EipjSk/IbuNe+t3+ZUJ8vH04gos0cXrhrH8ZY7xagvdv+6vvXX8 E X-Gm-Gg: ASbGncv1X4mOs/Zv/sbuV8UPWnjA57+XRtCwmQAPdzI9urwDbUqJFnKSBwoAz6gmyt1 gE2ye712tssQM50jVht0qKKfLkIGqIkJ7z8fGSO31s9OT9l/0DMh0Y3ceBxcYW2m5Lk6sbgeQVK fzEjbU10MXCGJHqXBBfI1NdgUdTdTc5sKjKJ7wmA7ykeqUTa22c26bddCa4KNmgpXVOIcxPiu5C 6tCK46QgUfDxpFBiOBJQv3FBJ0PLZoYHOMD5TqBWRO0eNNFXQIEl5pRIRDu X-Google-Smtp-Source: AGHT+IEK5K4s41L+y15+QchqtoBbbgh+OSPX2oonZ29eXnyvngqJfQejFrzcuPoC8wAe5kvgHP5fPQ== X-Received: by 2002:a05:600c:5108:b0:434:a4fe:cd71 with SMTP id 5b1f17b1804b1-4361c35d6b9mr28382815e9.12.1733934075760; Wed, 11 Dec 2024 08:21:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 61/72] softfloat: Inline pickNaNMulAdd Date: Wed, 11 Dec 2024 16:19:53 +0000 Message-Id: <20241211162004.2795499-62-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Inline pickNaNMulAdd into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-3-richard.henderson@linaro.org [PMM: keep comment from old code in new location] Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- fpu/softfloat-specialize.c.inc | 54 ---------------------------------- 2 files changed, 40 insertions(+), 55 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 655b7d9da51..c1a97c35b20 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -79,9 +79,48 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } if (s->default_nan_mode) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ which = 3; + } else if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the + * default NaN here, and some return the input NaN. + */ + switch (s->float_infzeronan_rule) { + case float_infzeronan_dnan_never: + which = 2; + break; + case float_infzeronan_dnan_always: + which = 3; + break; + case float_infzeronan_dnan_if_qnan: + which = is_qnan(c->cls) ? 3 : 2; + break; + default: + g_assert_not_reached(); + } } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); + FloatClass cls[3] = { a->cls, b->cls, c->cls }; + Float3NaNPropRule rule = s->float_3nan_prop_rule; + + assert(rule != float_3nan_prop_none); + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { + /* We have at least one SNaN input and should prefer it */ + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_snan(cls[which])); + } else { + do { + which = rule & R_3NAN_1ST_MASK; + rule >>= R_3NAN_1ST_LENGTH; + } while (!is_nan(cls[which])); + } } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index e075c47889a..f26458eaa31 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -448,60 +448,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, } } -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a three-input operation. -| For the moment we assume that no CPU needs the 'larger significand' -| information. -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN -*----------------------------------------------------------------------------*/ -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, bool have_snan, float_status *status) -{ - FloatClass cls[3] = { a_cls, b_cls, c_cls }; - Float3NaNPropRule rule = status->float_3nan_prop_rule; - int which; - - /* - * We guarantee not to require the target to tell us how to - * pick a NaN if we're always returning the default NaN. - * But if we're not in default-NaN mode then the target must - * specify. - */ - assert(!status->default_nan_mode); - - if (infzero) { - /* - * Inf * 0 + NaN -- some implementations return the default NaN here, - * and some return the input NaN. - */ - switch (status->float_infzeronan_rule) { - case float_infzeronan_dnan_never: - return 2; - case float_infzeronan_dnan_always: - return 3; - case float_infzeronan_dnan_if_qnan: - return is_qnan(c_cls) ? 3 : 2; - default: - g_assert_not_reached(); - } - } - - assert(rule != float_3nan_prop_none); - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { - /* We have at least one SNaN input and should prefer it */ - do { - which = rule & R_3NAN_1ST_MASK; - rule >>= R_3NAN_1ST_LENGTH; - } while (!is_snan(cls[which])); - } else { - do { - which = rule & R_3NAN_1ST_MASK; - rule >>= R_3NAN_1ST_LENGTH; - } while (!is_nan(cls[which])); - } - return which; -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index c1a97c35b20..be7e93127d4 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -85,7 +85,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, * But if we're not in default-NaN mode then the target must * specify. */ - which = 3; + goto default_nan; } else if (infzero) { /* * Inf * 0 + NaN -- some implementations return the @@ -93,17 +93,18 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, */ switch (s->float_infzeronan_rule) { case float_infzeronan_dnan_never: - which = 2; break; case float_infzeronan_dnan_always: - which = 3; - break; + goto default_nan; case float_infzeronan_dnan_if_qnan: - which = is_qnan(c->cls) ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd Date: Wed, 11 Dec 2024 16:19:55 +0000 Message-Id: <20241211162004.2795499-64-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Assign the pointer return value to 'a' directly, rather than going through an intermediary index. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index be7e93127d4..525db617411 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -65,9 +65,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, FloatPartsN *c, float_status *s, int ab_mask, int abc_mask) { - int which; bool infzero = (ab_mask == float_cmask_infzero); bool have_snan = (abc_mask & float_cmask_snan); + FloatPartsN *ret; if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); @@ -104,42 +104,30 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, default: g_assert_not_reached(); } - which = 2; + ret = c; } else { - FloatClass cls[3] = { a->cls, b->cls, c->cls }; + FloatPartsN *val[3] = { a, b, c }; Float3NaNPropRule rule = s->float_3nan_prop_rule; assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ do { - which = rule & R_3NAN_1ST_MASK; + ret = val[rule & R_3NAN_1ST_MASK]; rule >>= R_3NAN_1ST_LENGTH; - } while (!is_snan(cls[which])); + } while (!is_snan(ret->cls)); } else { do { - which = rule & R_3NAN_1ST_MASK; + ret = val[rule & R_3NAN_1ST_MASK]; rule >>= R_3NAN_1ST_LENGTH; - } while (!is_nan(cls[which])); + } while (!is_nan(ret->cls)); } } - switch (which) { - case 0: - break; - case 1: - a = b; - break; - case 2: - a = c; - break; - default: - g_assert_not_reached(); + if (is_snan(ret->cls)) { + parts_silence_nan(ret, s); } - if (is_snan(a->cls)) { - parts_silence_nan(a, s); - } - return a; + return ret; default_nan: parts_default_nan(a, s); From patchwork Wed Dec 11 16:19:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB4E0E7717D for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 64/72] softfloat: Pad array size in pick_nan_muladd Date: Wed, 11 Dec 2024 16:19:56 +0000 Message-Id: <20241211162004.2795499-65-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson While all indices into val[] should be in [0-2], the mask applied is two bits. To help static analysis see there is no possibility of read beyond the end of the array, pad the array to 4 entries, with the final being (implicitly) NULL. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 525db617411..5fcdbc87fd7 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -106,7 +106,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } ret = c; } else { - FloatPartsN *val[3] = { a, b, c }; + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; Float3NaNPropRule rule = s->float_3nan_prop_rule; assert(rule != float_3nan_prop_none); From patchwork Wed Dec 11 16:19:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D9EDE7717D for ; Wed, 11 Dec 2024 16:26:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSw-00021x-4m; Wed, 11 Dec 2024 11:21:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSl-0001Lz-Nj for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:25 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSj-0007tn-J9 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:23 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-434f30ba149so25943045e9.0 for ; Wed, 11 Dec 2024 08:21:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934079; x=1734538879; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5+3C2AdZ9fftwrmxk/ig7qIyG/mfuZxKLEQCuOb4ibU=; b=FSY9KYZhsZrqA9lgHwinrmbX6KXWluu1gDZjh1FGbcmaMa1FhBbi7sQIQGATZpt8V0 AvsiyuN905+58RVrnDKTKBv5/Y38TplRGsElsv9pzi33f/JLBQH3bjrXeGQOrgbD0yOc 0JxT+jrrIKskWBSS0h0LskCi+jv+G+8Y0DuvAnr4G2cvYWapzp3SbPvsVslRjO7NiEXG HMT2yq/JPnH2zySYv88Zy72kt/T5BTHPUoX5c6kcq4P51yqOrtE5FsWc8WtB2bQ1/IIh eT9MGJSbS8wLcNS+mJ40+E/6ivSygDSbvla1a3d1uOX9qcB1EyOVSz3InYcmvjm02ol0 b2Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934079; x=1734538879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5+3C2AdZ9fftwrmxk/ig7qIyG/mfuZxKLEQCuOb4ibU=; b=GJ31I7KEZ2DueWGCdSddU6P3TTph9RCTUIYs5UP4gl9dHJ3wty7b7t11b8SppZs0LS yOTgBHSJIESb5yqW7z0g+pjcoz71qHM4zcu6g2kUAGnHeZ4ByydevcThQhQzpVJflFyI kXgF3gBS7X6L7wNV+8GExxcbUx5zZtE1FJgNScoN4qpmUOqiY90zcNcIjiqOZ0NB9Bfx I2FuFlCsR+joPqM3rREIDOZkcAoQoW8FEcA4h93TXLW8d1OVhh6sQgTgU1FjzG8x2CRn 5JnyO9GGFZMpIxYBML6methmOh5Es7lfcb7ZVbmF0C1kWgKv+fuThgKyRvvZ2wdzFM6u 0QQw== X-Gm-Message-State: AOJu0Yz26YYkJuZY/K1LayFoi4CiRq7z0fOOdMCygQoZPDdm7Ut9L8xy zA3/aNiE8Efq0GPvtY0QcvezOZBk+cuh9Yyb1IP2dPeu666KnooF29vDQwxNAiPDWhL1Q7DADUw Y X-Gm-Gg: ASbGncui/pAZnRFjTYHnciYvs6sO/Axy3EBS5Z61oInQMdMZAHFsdoQjUmkXWc1l4Od E6V41E91Vpwwh9/BJ7XR5SZ8D4zVXFS0L+z9EMniti2AYXLJ3ywCyaev6VCt/uMRkkdqGq4rFfo wh5PkOVUwxy6G5QhenutiFGgoWaaTXh/cOrvVxseyAPpOOccq4pD9hfr3QbnsER5q0dLi1ALodc n4EZvh8VLArp3JJBzf9MeQ694cSpnIbocBuKjjuFBo4/rbiI4KKXE8wYgpm X-Google-Smtp-Source: AGHT+IFEkKKRg30SD0pVjKVuw93S1OtWePsFg+1Qz9W1gtupLPJX6/FD2k6buc3HrzWevg9Gt8KSfQ== X-Received: by 2002:a05:600c:4f86:b0:434:f871:1b97 with SMTP id 5b1f17b1804b1-4361c42e258mr26904065e9.33.1733934079514; Wed, 11 Dec 2024 08:21:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c Date: Wed, 11 Dec 2024 16:19:57 +0000 Message-Id: <20241211162004.2795499-66-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson This function is part of the public interface and is not "specialized" to any target in any way. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ fpu/softfloat-specialize.c.inc | 52 ---------------------------------- 2 files changed, 52 insertions(+), 52 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 027a8e576d3..6ba1cfd32a0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4920,6 +4920,58 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Takes two extended double-precision floating-point values `a' and `b', one +| of which is a NaN, and returns the appropriate NaN result. If either `a' or +| `b' is a signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) +{ + bool aIsLargerSignificand; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); + + if (is_snan(a_cls) || is_snan(b_cls)) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return floatx80_default_nan(status); + } + + if (a.low < b.low) { + aIsLargerSignificand = 0; + } else if (b.low < a.low) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; + } + + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { + if (is_snan(b_cls)) { + return floatx80_silence_nan(b, status); + } + return b; + } else { + if (is_snan(a_cls)) { + return floatx80_silence_nan(a, status); + } + return a; + } +} + /*---------------------------------------------------------------------------- | Takes an abstract floating-point value having sign `zSign', exponent `zExp', | and extended significand formed by the concatenation of `zSig0' and `zSig1', diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f26458eaa31..f7a320f6ff9 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -551,58 +551,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Takes two extended double-precision floating-point values `a' and `b', one -| of which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN Date: Wed, 11 Dec 2024 16:19:58 +0000 Message-Id: <20241211162004.2795499-67-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Unpacking and repacking the parts may be slightly more work than we did before, but we get to reuse more code. For a code path handling exceptional values, this is an improvement. Signed-off-by: Richard Henderson Message-id: 20241203203949.483774-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- fpu/softfloat.c | 43 +++++-------------------------------------- 1 file changed, 5 insertions(+), 38 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6ba1cfd32a0..8de8d5f3425 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4928,48 +4928,15 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; + FloatParts128 pa, pb, *pr; - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!floatx80_is_any_nan(a) - ? float_class_normal - : floatx80_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!floatx80_is_any_nan(b) - ? float_class_normal - : floatx80_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { return floatx80_default_nan(status); } - if (a.low < b.low) { - aIsLargerSignificand = 0; - } else if (b.low < a.low) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return floatx80_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return floatx80_silence_nan(a, status); - } - return a; - } + pr = parts_pick_nan(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); } /*---------------------------------------------------------------------------- From patchwork Wed Dec 11 16:19:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0161E77180 for ; Wed, 11 Dec 2024 16:29:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPT0-0002J1-1L; Wed, 11 Dec 2024 11:21:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSo-0001RT-1l for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:26 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSl-0007uR-HH for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:25 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4361c705434so6524955e9.3 for ; Wed, 11 Dec 2024 08:21:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934081; x=1734538881; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=E0giBM/EpXvNpQdM8VbewBXwD4I1LGLbeL66q1YYWe8=; b=y2h58+qP546ZgI1/ki+Ul0S+bK6Wch1eRTEkmj7ZdpuHCF0OXYPJ2uETy5fuPoUFl1 DvTP5eXbeEY9cK07sq9as62GHeWSJ9WMdXsv2rFDvXr19qOreOt+snf93y4ieRrzgZIs KnyXkYl1phFCmqUDU4upKGmOaX/yzxKTnqiIOIezVuf8nFhDhJNiIg1+nQDHPY3aolX9 61P5E+V+TdoLEIgjdecz+R9RKgGv6ImQwghGp4V82PEpiiqtP0R7gHsabk+bXS0fbG0B TIGmjnVRUb1TbrROaz+tjf4T4m6SuQukoD5mZsrpoB0E3mqclwDeFRY9YIOqzsb4FZFo WADA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934081; x=1734538881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E0giBM/EpXvNpQdM8VbewBXwD4I1LGLbeL66q1YYWe8=; b=ox8BZKTeh0E8DfkpaAlR+FWXK60PlYD/wXjFoqwzM+0Nu5pMl+NNVjBvHHxHt3MGDb Ml5KSw+G8UhlCcqcwAsEP/B1xS+Qg9QzB5SYt21u0n/y2/tWPGMbyljrIoD9xfAcBDGI JBpgeje1ezC7GlmPAk9VIwspPI/yD3A6X3ISs6GowZuMupj9gKb9rSB1zZ4DknZLC0RR 5tUQDH2td7kHF+OKLz+Rl/Ns4zl6sPMw2oIlQBh2RhHN1YpRPCazk4f8R32GHQCOay32 Npcz4qTA3eOE7hlYhI5CPpTVoJKybigfegFtf3y6umkqD+rw9EAKEeB+9aIjXe0zLman khRQ== X-Gm-Message-State: AOJu0YwUZvO12P84BY2URRX6Q9tNfzB1NTvRuSBTwg/xV74eKKFmv/Xw ihm8KkdJ31u1Zm/lafeStNyj19RbJQHimEADnQXfcab6ozq8Axb2NATJpOdihLDhNmRuh6MtNmu l X-Gm-Gg: ASbGnctoc2sswdOAmvGeHtst8Ai4K9HzRWZFbflvNH8IhDICQh6Wq5TYvF83DobUzwq ch6zaQuFBXScXOEj7fZPRpw3mSzbtXBlo2W2GRCJisSz0e2XyF5ATd48wqKyGM0XSFZ7ZERPnyy rinowlqm6D7006ulrYiWb5Pcj8VMIQp4bCHeBz6QDtQy3BUT8GVxOwGGvv5lqtB73htIP0uhj65 UYljBrxgKOWW3PAcISUagr8JhT696HCSR29rqxgS+t3GmmSnt9g+OmhfHha X-Google-Smtp-Source: AGHT+IGq4/1upfXFgIlB/bxNmYSvLA3vR6ZM6nCu+I9obc5PHJo0UuRNQb9M8kEtmNHPs6DIIgt/vw== X-Received: by 2002:a05:600c:3b09:b0:434:f609:1af7 with SMTP id 5b1f17b1804b1-4361c346a89mr29631275e9.4.1733934081439; Wed, 11 Dec 2024 08:21:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 67/72] softfloat: Inline pickNaN Date: Wed, 11 Dec 2024 16:19:59 +0000 Message-Id: <20241211162004.2795499-68-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Inline pickNaN into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- fpu/softfloat-specialize.c.inc | 96 ---------------------------------- 2 files changed, 73 insertions(+), 105 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 5fcdbc87fd7..a1b148e90b9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -39,24 +39,88 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { + int cmp, which; + if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } if (s->default_nan_mode) { parts_default_nan(a, s); - } else { - int cmp = frac_cmp(a, b); - if (cmp == 0) { - cmp = a->sign < b->sign; - } + return a; + } - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { - a = b; - } + cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + + switch (s->float_2nan_prop_rule) { + case float_2nan_prop_s_ab: if (is_snan(a->cls)) { - parts_silence_nan(a, s); + which = 0; + } else if (is_snan(b->cls)) { + which = 1; + } else if (is_qnan(a->cls)) { + which = 0; + } else { + which = 1; } + break; + case float_2nan_prop_s_ba: + if (is_snan(b->cls)) { + which = 1; + } else if (is_snan(a->cls)) { + which = 0; + } else if (is_qnan(b->cls)) { + which = 1; + } else { + which = 0; + } + break; + case float_2nan_prop_ab: + which = is_nan(a->cls) ? 0 : 1; + break; + case float_2nan_prop_ba: + which = is_nan(b->cls) ? 1 : 0; + break; + case float_2nan_prop_x87: + /* + * This implements x87 NaN propagation rules: + * SNaN + QNaN => return the QNaN + * two SNaNs => return the one with the larger significand, silenced + * two QNaNs => return the one with the larger significand + * SNaN and a non-NaN => return the SNaN, silenced + * QNaN and a non-NaN => return the QNaN + * + * If we get down to comparing significands and they are the same, + * return the NaN with the positive sign bit (if any). + */ + if (is_snan(a->cls)) { + if (is_snan(b->cls)) { + which = cmp > 0 ? 0 : 1; + } else { + which = is_qnan(b->cls) ? 1 : 0; + } + } else if (is_qnan(a->cls)) { + if (is_snan(b->cls) || !is_qnan(b->cls)) { + which = 0; + } else { + which = cmp > 0 ? 0 : 1; + } + } else { + which = 1; + } + break; + default: + g_assert_not_reached(); + } + + if (which) { + a = b; + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); } return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f7a320f6ff9..cbbbab52ba3 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -352,102 +352,6 @@ bool float32_is_signaling_nan(float32 a_, float_status *status) } } -/*---------------------------------------------------------------------------- -| Select which NaN to propagate for a two-input operation. -| IEEE754 doesn't specify all the details of this, so the -| algorithm is target-specific. -| The routine is passed various bits of information about the -| two NaNs and should return 0 to select NaN a and 1 for NaN b. -| Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_silence_nan() before -| returning them. -| -| aIsLargerSignificand is only valid if both a and b are NaNs -| of some kind, and is true if a has the larger significand, -| or if both a and b have the same significand but a is -| positive but b is negative. It is only needed for the x87 -| tie-break rule. -*----------------------------------------------------------------------------*/ - -static int pickNaN(FloatClass a_cls, FloatClass b_cls, - bool aIsLargerSignificand, float_status *status) -{ - /* - * We guarantee not to require the target to tell us how to - * pick a NaN if we're always returning the default NaN. - * But if we're not in default-NaN mode then the target must - * specify via set_float_2nan_prop_rule(). - */ - assert(!status->default_nan_mode); - - switch (status->float_2nan_prop_rule) { - case float_2nan_prop_s_ab: - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - break; - case float_2nan_prop_s_ba: - if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } - break; - case float_2nan_prop_ab: - if (is_nan(a_cls)) { - return 0; - } else { - return 1; - } - break; - case float_2nan_prop_ba: - if (is_nan(b_cls)) { - return 1; - } else { - return 0; - } - break; - case float_2nan_prop_x87: - /* - * This implements x87 NaN propagation rules: - * SNaN + QNaN => return the QNaN - * two SNaNs => return the one with the larger significand, silenced - * two QNaNs => return the one with the larger significand - * SNaN and a non-NaN => return the SNaN, silenced - * QNaN and a non-NaN => return the QNaN - * - * If we get down to comparing significands and they are the same, - * return the NaN with the positive sign bit (if any). - */ - if (is_snan(a_cls)) { - if (is_snan(b_cls)) { - return aIsLargerSignificand ? 0 : 1; - } - return is_qnan(b_cls) ? 1 : 0; - } else if (is_qnan(a_cls)) { - if (is_snan(b_cls) || !is_qnan(b_cls)) { - return 0; - } else { - return aIsLargerSignificand ? 0 : 1; - } - } else { - return 1; - } - default: - g_assert_not_reached(); - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 68/72] softfloat: Share code between parts_pick_nan cases Date: Wed, 11 Dec 2024 16:20:00 +0000 Message-Id: <20241211162004.2795499-69-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Remember if there was an SNaN, and use that to simplify float_2nan_prop_s_{ab,ba} to only the snan component. Then, fall through to the corresponding float_2nan_prop_{ab,ba} case to handle any remaining nans, which must be quiet. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a1b148e90b9..3c77dcbb154 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -39,10 +39,12 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { + bool have_snan = false; int cmp, which; if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); + have_snan = true; } if (s->default_nan_mode) { @@ -57,30 +59,20 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: - if (is_snan(a->cls)) { - which = 0; - } else if (is_snan(b->cls)) { - which = 1; - } else if (is_qnan(a->cls)) { - which = 0; - } else { - which = 1; + if (have_snan) { + which = is_snan(a->cls) ? 0 : 1; + break; } - break; - case float_2nan_prop_s_ba: - if (is_snan(b->cls)) { - which = 1; - } else if (is_snan(a->cls)) { - which = 0; - } else if (is_qnan(b->cls)) { - which = 1; - } else { - which = 0; - } - break; + /* fall through */ case float_2nan_prop_ab: which = is_nan(a->cls) ? 0 : 1; break; + case float_2nan_prop_s_ba: + if (have_snan) { + which = is_snan(b->cls) ? 1 : 0; + break; + } + /* fall through */ case float_2nan_prop_ba: which = is_nan(b->cls) ? 1 : 0; break; From patchwork Wed Dec 11 16:20:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38A36E7717D for ; Wed, 11 Dec 2024 16:26:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSx-0002A6-2Y; Wed, 11 Dec 2024 11:21:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSo-0001Si-JP for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:26 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSm-0007uq-LX for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:26 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-434e69857d9so5486795e9.0 for ; Wed, 11 Dec 2024 08:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934083; x=1734538883; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=doRTkzLWp9CB3fDTzYDP5bn9+hyyRKBZGVgyCVKSal4=; b=sBH+xyer+4c0o2Dv1L66d4LSbAgPDGqhduB1yQiyLB2U5HwXBL8Xxp81JGIju5qk8/ gRky1G2woe/gVFMeXpj521j1hA3RoHD14Xh4VHfxUsOKd3d4r0qycblnVjFqtSq+iGv8 +STAuEAHVSBHj6gmFAEkQgmBgrcO+clC6Jc3IUjtargYm1U856w9l30yUVnhGzH1Qru6 VEb1NRMJkWQpg+BPJu8COm6lePsKV/d3aMZKuBi3702Tc8u9yoONvIpJ0Hppv44qsj6s 3PLXOWAv0Skt8RQEtaJMiGLJxnQH44I5TikiG+336IfwI6X56/sPSGtjapNdUb5PNhnt YISg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934083; x=1734538883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=doRTkzLWp9CB3fDTzYDP5bn9+hyyRKBZGVgyCVKSal4=; b=iPCc7M3VxV+EUVisBGj6/rZI63YJUETOX2LbISY0A5fz2T4q2thJlQafpaVU80qnof A0KKHrAzeN0Dp0Br5zByxhBB8x2d4PHHMmqrqqSz4vsVgjALXfDcM6smrzpnEqgsakVI rqoUdevRdsjeATrHzYgD+Ktlh/hdB0dZFk+w1D2fiNVpPnyMRbuFYCDIS6NXLa1EHV+u veyO/z0AOkZAObep20AbXCnrt8rOwVtnPiEQs+WSHl/G5iEHkBJRvlla8kgwvuDwzBKC /HvvsFBfugNONc1gmdZiVwVDDM+OrnwfqpRHA1WkCdDcwiKOt8HmET7XvTdWzU83LXds uIcw== X-Gm-Message-State: AOJu0YyfFg3IHN4Vvgv9QsLict1f1gh8i1o1kOOs6gkKoZuXypTe9acR RkiJ4/kzwUpq/j9Paid3sNZj/XwNayaH4WVWEZCwP1yG1as/9QsIhSCzmFoq/lYiw9WQJYdG1BU B X-Gm-Gg: ASbGncupf38z8khJ+bCp2KAku9EMZouyRSK9rm2QVgPHdKcgMooAhZYuKxZQVU845f+ X2VGLduwwYVF/FQLQ5laNkUyHoojxN2PzpdBk9EG4B/UEpj2z7VyHuOeU3R2SknjLruBId/GPys jNWt9Vj9o6F1/6lrQg2M+T0daabfimva0yFQILg5TJ7mwEddcGHyk27UGGbxVr7S8mnXPbPDf2D ouN+K2w30dK1RRVmXBrbrlxn559o0hZ2Z/TCNojTZK/n2+eLyVc5x0goGb4 X-Google-Smtp-Source: AGHT+IGZk0AK0IjKsvlbFKBNy84R/VVcxn9ZjMkUpngAEIQcm5aH6bJ+cITVGoddelnqsozCJmqZ/Q== X-Received: by 2002:a05:600c:c8a:b0:434:fddf:5c06 with SMTP id 5b1f17b1804b1-4361c5b8720mr25750205e9.1.1733934083222; Wed, 11 Dec 2024 08:21:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed Date: Wed, 11 Dec 2024 16:20:01 +0000 Message-Id: <20241211162004.2795499-70-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Move the fractional comparison to the end of the float_2nan_prop_x87 case. This is not required for any other 2nan propagation rule. Reorganize the x87 case itself to break out of the switch when the fractional comparison is not required. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3c77dcbb154..abe24aeaa00 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -52,11 +52,6 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, return a; } - cmp = frac_cmp(a, b); - if (cmp == 0) { - cmp = a->sign < b->sign; - } - switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (have_snan) { @@ -89,20 +84,24 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, * return the NaN with the positive sign bit (if any). */ if (is_snan(a->cls)) { - if (is_snan(b->cls)) { - which = cmp > 0 ? 0 : 1; - } else { + if (!is_snan(b->cls)) { which = is_qnan(b->cls) ? 1 : 0; + break; } } else if (is_qnan(a->cls)) { if (is_snan(b->cls) || !is_qnan(b->cls)) { which = 0; - } else { - which = cmp > 0 ? 0 : 1; + break; } } else { which = 1; + break; } + cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + which = cmp > 0 ? 0 : 1; break; default: g_assert_not_reached(); From patchwork Wed Dec 11 16:20:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77088E77183 for ; Wed, 11 Dec 2024 16:24:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPSy-0002EY-EM; Wed, 11 Dec 2024 11:21:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSp-0001XS-A2 for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:27 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSn-0007ux-GR for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:27 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-436202dd7f6so6285435e9.0 for ; Wed, 11 Dec 2024 08:21:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934084; x=1734538884; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=E85lj8XRhj/Fk3RQPB/aLYeRqkABA8VMdndxVbT9joA=; b=mqD6/oj+XSZNoVUCkC0+isFlnMbSzIcX+c+HNJlL8hBXVYC0OWGB3mD0RtDlXvrnUL PsjFX6O9A37As22gLkvN/tAfYY0nZFczVnRD72ZBA0f6iQDY5qXJ1GhXgLaJd6SN3yYx G29NxsLkit/3Rro/JjbydmEfY2hX9xvZ0avEZeeBVyeLe647FaKrFOBaQAU3fo8PZ9j0 vWNFo7ept3+UxuDMzae9QDGWrYk96kgwm7ikaY0vpBPkRaO2l1b2q5B7jDuxgFHRCkO1 Yfn4QUV5X2rhZYpBAJ2a6RB9lo+rzMe2RihwFczWSUSdvdEFvXCisG0T/xNzLXnujRei /myA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934084; x=1734538884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E85lj8XRhj/Fk3RQPB/aLYeRqkABA8VMdndxVbT9joA=; b=H8eF4aueI66PEiBXrpPls2I7V7I8LOXF22y3snvKBQKq7kLX9UxCikGWtfFJv4rwBU y3vBVzXuBovzcesRTc+2tbUxQCmyWzQo1pxXMGiYEgk5kCMgmvHZlG3kNHcfcByz0dD1 yRXKmrsnNHdneoTcfPAgQ9YDmOUvVApA/a8TCiH1E79lt9+u4e2jLchTC4Xii4tcD9M6 pD+JfCfJ3tTUAb/l4T0NtI6QGsVW1vNI0FRAxd8HhAIbHtU+50/JqW9EPLE3O+rAJowq ziMPwAz7HkzJ4J5n7twdsNUU7JwuLogLuWkIAxb675bPquFloaNq2ltBtxJvkuCdK2Il 7e+A== X-Gm-Message-State: AOJu0YyNTEm7agtE70uY967UkJ4p/gT+NJ+7Aumv0zfi5nCryEy9TR97 nfZPfUvHGccAge3sUP+9lVmM1v78pH/znYPbjbyGH0Yi7l1wHfZJVjhYeQEVPWkusj8xCrWplVL a X-Gm-Gg: ASbGncseOvAVUw//tbOpsqJ1lOkfuWYheTALBOC8E656AfVvM1FEaYoLAhWfWSBoB1J hePme0SGqpI9Zi3GoByF6a+HoKaZCwQSyvRY6sSJhvv1oJeezToVtHAG8EGkdJ3vAm6Xc/r26nD NJ9ac7PTrgcnDWDJsDEongzIpluGj9iztYPRLOujYeuBj2t38hHRx9q4aKt88Pf1jU3bpDeCFo/ ygv+NW5nRvo9d6ij/8UWmU/B0u/kLsQheT7nG7lmHUKeZtKHL06n2SoDPng X-Google-Smtp-Source: AGHT+IHi5cWI9HumJccejp+wfPPknBU5WEKTBa1FEGvsjA+YUOV6I/k2m11jg3kEUIWFYlpsCdabRw== X-Received: by 2002:a05:600c:4e50:b0:431:5df7:b310 with SMTP id 5b1f17b1804b1-43622832e88mr2983255e9.8.1733934084148; Wed, 11 Dec 2024 08:21:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f4dfdcdfsm121460595e9.39.2024.12.11.08.21.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 08:21:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan Date: Wed, 11 Dec 2024 16:20:02 +0000 Message-Id: <20241211162004.2795499-71-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211162004.2795499-1-peter.maydell@linaro.org> References: <20241211162004.2795499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Richard Henderson Replace the "index" selecting between A and B with a result variable of the proper type. This improves clarity within the function. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index abe24aeaa00..ba8de7be76e 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -40,7 +40,8 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { bool have_snan = false; - int cmp, which; + FloatPartsN *ret; + int cmp; if (is_snan(a->cls) || is_snan(b->cls)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); @@ -55,21 +56,21 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, switch (s->float_2nan_prop_rule) { case float_2nan_prop_s_ab: if (have_snan) { - which = is_snan(a->cls) ? 0 : 1; + ret = is_snan(a->cls) ? a : b; break; } /* fall through */ case float_2nan_prop_ab: - which = is_nan(a->cls) ? 0 : 1; + ret = is_nan(a->cls) ? a : b; break; case float_2nan_prop_s_ba: if (have_snan) { - which = is_snan(b->cls) ? 1 : 0; + ret = is_snan(b->cls) ? b : a; break; } /* fall through */ case float_2nan_prop_ba: - which = is_nan(b->cls) ? 1 : 0; + ret = is_nan(b->cls) ? b : a; break; case float_2nan_prop_x87: /* @@ -85,35 +86,32 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, */ if (is_snan(a->cls)) { if (!is_snan(b->cls)) { - which = is_qnan(b->cls) ? 1 : 0; + ret = is_qnan(b->cls) ? b : a; break; } } else if (is_qnan(a->cls)) { if (is_snan(b->cls) || !is_qnan(b->cls)) { - which = 0; + ret = a; break; } } else { - which = 1; + ret = b; break; } cmp = frac_cmp(a, b); if (cmp == 0) { cmp = a->sign < b->sign; } - which = cmp > 0 ? 0 : 1; + ret = cmp > 0 ? a : b; break; default: g_assert_not_reached(); } - if (which) { - a = b; + if (is_snan(ret->cls)) { + parts_silence_nan(ret, s); } - if (is_snan(a->cls)) { - parts_silence_nan(a, s); - } - return a; + return ret; } static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, From patchwork Wed Dec 11 16:20:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CC13E7717D for ; Wed, 11 Dec 2024 16:27:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPT0-0002K2-NS; Wed, 11 Dec 2024 11:21:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSq-0001bz-5E for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:28 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSo-0007vJ-Gq for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:27 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-43618283dedso16754255e9.3 for ; Wed, 11 Dec 2024 08:21:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934085; x=1734538885; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gSbZ33dYhUCvriB7gJIYOSjh0uJ7qwYxR0y7su+tpkc=; b=KRE/1KwIeFrD58JIyaLgz64RScARneDJwpxkS/FS6ViUjeELV/trhloF/8vDyzA1ci i3LEzNpUUHiXRPmYaNTkb2wwyOyJWi23R0SZFsxyIG86apvEVlOFcrl6fNMA9Z+IUmpT gnG5nJzIYJJB4b7TyUjwFTrYPX4LUgNKenjgoizJq3yW46yL7FwY6U86KXC94i0OE83h c/q1NPx4eDUUWXMV/jQPn4XqVdP+XM2XxHBKxgKebaUuA4RlCoSbWKG0kLJ1ObyWW8jP 4NfalotmV8UYdqxlflzXaxTCuUSPTSGBmv7Wbpcv4KzyONGjQM+AvyDAQt7f8U3MuZWy pCpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934085; x=1734538885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gSbZ33dYhUCvriB7gJIYOSjh0uJ7qwYxR0y7su+tpkc=; b=s05U8bICx92m4aRPcv+z0ppH+MyzHn3Qe0dLi8T6xlyRYSKSa5SVbsJ8xQ7Ufgtumx m8MypPVA1xdAfrP1yU+7C6D26NwBVFOT9QK20q8FUFfxgRyaDLCkHJV/8EKc/tVhBWgv dtA0srs3SLNEq0yyYXJfSc0vHIECq0LkETlRbmh6cAKQVc0ATIGZBY3eLQ98RtF6wX48 DXpAqMBzEnEAezyAWiwLfKen3hMYRwdRv7FCm+BUxosU4vf0ouka3i5jOM7pz79xkF8P 9OSqebMDy+d2dBiuLlZTCQoRBR1HH5ILGx7OkRWZQJoQb0NTk9SjYmh7Cwf0TAAyIjft 8UxQ== X-Gm-Message-State: AOJu0Yx7QaNRg75iDceTGZu57arMf7RsOf3JREUuVCB2b+kB3Fq2gsYI WLqcbfIbZNwNhe0ZtrUxmDPuctq2UQO1QHBoS46PHUVVl5ncWmI4ZUV46wd1v9+4HHArlwzIWfx F X-Gm-Gg: ASbGncuDfdMTiDxKi7t8WCLlGSOPVFN63RMvdlCmE40yH5NandBY2Ze2dqcilCla61I s+osy8iiAZMosT9fRl/FZz3PXyQbEE2zZA1zknrkrvUhy0rOos3l/dpK8V9hizFjrc0zlFDs3rO +RFf9xz1uasSRGxB8/NguTtULnlwpTvqkrOWGj8vmVkWA9Fchqtab7vfe0Fx9xiHNlH4work5r7 I4bYHb0hd6qrH6hJqj9nIL+BTymF74L9zqPvX3FN3k6HMPylyd17n1BieFA X-Google-Smtp-Source: AGHT+IFFUD4MdrOm47MBTREZv0Zu8sIiii5xNVD/e17gQHbodrAbO1lH2rK0zKCh3+rQDQnVfzSVRQ== X-Received: by 2002:a05:600c:4f48:b0:426:647b:1bfc with SMTP id 5b1f17b1804b1-4362286dca8mr3464295e9.30.1733934085039; Wed, 11 Dec 2024 08:21:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Signed-off-by: Leif Lindholm Reviewed-by: Leif Lindholm Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 +- .mailmap | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index aaf0505a214..9ae6a78ae9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -915,7 +915,7 @@ F: include/hw/ssi/imx_spi.h SBSA-REF M: Radoslaw Biernacki M: Peter Maydell -R: Leif Lindholm +R: Leif Lindholm R: Marcin Juszkiewicz L: qemu-arm@nongnu.org S: Maintained diff --git a/.mailmap b/.mailmap index 727ce204b2d..5f6df414e1f 100644 --- a/.mailmap +++ b/.mailmap @@ -87,8 +87,9 @@ Huacai Chen Huacai Chen James Hogan Juan Quintela -Leif Lindholm -Leif Lindholm +Leif Lindholm +Leif Lindholm +Leif Lindholm Luc Michel Luc Michel Luc Michel From patchwork Wed Dec 11 16:20:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13903794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFE74E77182 for ; Wed, 11 Dec 2024 16:28:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tLPT0-0002Jz-G6; Wed, 11 Dec 2024 11:21:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tLPSr-0001h7-Jw for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:29 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tLPSp-0007vn-Qf for qemu-devel@nongnu.org; Wed, 11 Dec 2024 11:21:29 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3863703258fso522697f8f.1 for ; Wed, 11 Dec 2024 08:21:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733934086; x=1734538886; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ht1nZ84ts/9AMVIYYfAfz6P7yX4A1c2tCexcQoTh5N4=; b=aZMCrW3stth5tQ0wyh6z0J4LuE9aWBaDRpFESp5A3inu0MD4zlqKSK2erN9sJVPOrF 1RjWZ9fE+luFqWCrQOekkspEiGZBo/if/iA/WjphajQHVLHZuLFEYu5U3mmjXeE4dNo8 MYJulhTWUO05l9w92CvnKCXkHa4oApY8Y7TanWxQgB+oyXYS47OrUNNK34j3AR8mN5pV r2YsdzN8Z9ss5e60UQ4Z086KjOLKowm55lMEZFa3JeU1eGrx+YT5ydcgxm+2ra3CGJ/i DgXWnWZMzL24y/jbIlmOMGM3ub822IOZWsYWKTaQOgbp9auJm+9IEBFmdUypq1tE/zTQ dD3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733934086; x=1734538886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ht1nZ84ts/9AMVIYYfAfz6P7yX4A1c2tCexcQoTh5N4=; b=q1TqEwLEulunE1ytCfiqpSObBn12LznOOD8OK+TRGaEi7uFbobO4aThEDX430j8Sh1 j84Ffqg4bvQ8+oYix9sf1JfSltO+aCCIGCyCD63uiFM9Q/d6z/Xq7nJkXUPP2RgiTd87 naeDgzmKMgt4SXy5JrAMulXjuBXerqWnul/IkfIYt960TBJG2LV7Haum+YlqrNmWrHWG 9Wq/oDKMxlj9jiBRClsAxGZq10uLEIUL63/hcGMuS0vaYHZt4HWKktUMK/I1El7EaSMr HhbjJQKqjjcBLkH6XERSVr60YBLUKwAkisvRKIuofWKuJ9CZW93brSo5mnDCZgcCTd1d r3Ew== X-Gm-Message-State: AOJu0YzvH5SMeT1+geE+K0g9bm8ZXPfVBLG9N2BIukfw4IKiSh4FUTCw g5la1kxG9bsTVkkWe7g91rLxpdYbZCvajG33zq6NdXPIIKIN4TUT5/KVE0oCZbxWdEtl02GFAyx S X-Gm-Gg: ASbGncs3vfixMm5cFg2vG0G8iNx3FezDp/zdV0AcQcJ98gZpZa9/mKoA3wlhEle1c8d XdUGWI1sXBYyP1m4TLmrPm0LSkHju/3uxyv8yuQYADL0RyAD1fkcUDuEOn3UYakbVSql36PvQek vA5B/o0fN+3BQ+o2AFrRH9pfszdWy858ySeBC+S1MlFoAXaN2AhlmDOPLt8o/4do6GLFkP047t3 2y/cHNeEVIIP6PDlgvhzzoNrMFFTPbrRMrwVKjd/Ac/z4n2zolBsuctN2oi X-Google-Smtp-Source: AGHT+IGZSf7lVbD0dwuOtt/JRrKF1T3d3PVRZt8EufCiTHqETbuo9S0V3TSKEqW52tRdCYsxcHSKpg== X-Received: by 2002:a5d:5f4a:0:b0:386:34af:9bae with SMTP id ffacd0b85a97d-3864de8eccdmr2861516f8f.4.1733934085978; Wed, 11 Dec 2024 08:21:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Commit id: c009d715721861984c4987bcc78b7ee183e86d75. Signed-off-by: Vikram Garhwal Reviewed-by: Francisco Iglesias Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9ae6a78ae9c..1d2003a9a1d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1914,6 +1914,7 @@ F: tests/qtest/fuzz-sb16-test.c Xilinx CAN M: Francisco Iglesias +M: Vikram Garhwal S: Maintained F: hw/net/can/xlnx-* F: include/hw/net/xlnx-* @@ -2673,6 +2674,7 @@ F: include/hw/rx/ CAN bus subsystem and hardware M: Pavel Pisa M: Francisco Iglesias +M: Vikram Garhwal S: Maintained W: https://canbus.pages.fel.cvut.cz/ F: net/can/*