From patchwork Thu Dec 12 06:57:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13904736 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A42B8204F76; Thu, 12 Dec 2024 06:57:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986647; cv=none; b=J6hCHIJl8SkAbjMCRHpqa8gNgfQLmuihvyQWE4hmKpOD97MyaMWwe4t//NKHgT67IVLn3XuFBe3HdLDTrplJuONFWxTnMKCkYfb8PpeQACtSU+kHJCgDg068GG68iAclmaCJwGXgjylpQYvX5F/dFJdYH4rTcM5M8dw/bhpkXWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986647; c=relaxed/simple; bh=r1boVyI0fpZDL7gD/4Uo8Jj/l76Exljk4VjOn7uHTX8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=NBAooWZO3G9VHgx+mcTv9RSKzuUfND4NQc5w9d89zh4nQS3JQchd7fOy/ySymWAIVDeJgIQpG0NINRPWRJnZBI+cz2U5qDy1FqRVl3nYq5GGyoEzHdxXSf+8uDVhFZWwXuDqMMRkbAEWCcvZ5/9Dvt4M4cd550fqXfec/SMtPBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mktYEr1o; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mktYEr1o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733986646; x=1765522646; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=r1boVyI0fpZDL7gD/4Uo8Jj/l76Exljk4VjOn7uHTX8=; b=mktYEr1ohBmPUGnQBoEfH47R5K3AnH8p6+YK5c111QUsGwFx8g9ioCaL phVmRGNZHWyTerxLd4tKw2ketDqRxVk5kPItA3PuHgsGmdelz4R3z8Ic7 r/cfCa2CwsP9ue0fvydt1yTInF6SmMXYpGQ4BymRpnNsu9bZITk2kHYXt 3wVXZLm+FvObYgUBlAD1QPLfFSabOOeNj0SzyBWeaZkfJ+o5r8jgz0g3o M562bNdgOZV4cWjSU7aM8FCy/gueIKbgH+0z4is2G9wlm1axgcqI+kpP/ RMy7Uu4PtzhK3+3zOX02zOIu51xb1/Lf0/PbG5dkJEuQnqUxiCi+cvlkY g==; X-CSE-ConnectionGUID: ZFTz+QU5TsmJkaR2e1VKXw== X-CSE-MsgGUID: PxG2sSXXSe6ZpWHqnmJzXw== X-IronPort-AV: E=McAfee;i="6700,10204,11283"; a="59786313" X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="59786313" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:25 -0800 X-CSE-ConnectionGUID: qOw2JYMdRBuFNenhEH4qOg== X-CSE-MsgGUID: I+vSvhekQxGunY8kLuFUkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="96372289" Received: from unknown (HELO desk) ([10.125.145.3]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:24 -0800 Date: Wed, 11 Dec 2024 22:57:24 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 1/9] x86/cpu: Prepend 0x to the hex values in cpu_debug_show() Message-ID: <20241211-add-cpu-type-v5-1-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> The hex values in CPU debug interface are not prepended with 0x. This may cause misinterpretation of values. Fix it. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/debugfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/debugfs.c b/arch/x86/kernel/cpu/debugfs.c index 10719aba6276..9c8142ddd481 100644 --- a/arch/x86/kernel/cpu/debugfs.c +++ b/arch/x86/kernel/cpu/debugfs.c @@ -16,8 +16,8 @@ static int cpu_debug_show(struct seq_file *m, void *p) if (!c->initialized) return 0; - seq_printf(m, "initial_apicid: %x\n", c->topo.initial_apicid); - seq_printf(m, "apicid: %x\n", c->topo.apicid); + seq_printf(m, "initial_apicid: 0x%x\n", c->topo.initial_apicid); + seq_printf(m, "apicid: 0x%x\n", c->topo.apicid); seq_printf(m, "pkg_id: %u\n", c->topo.pkg_id); seq_printf(m, "die_id: %u\n", c->topo.die_id); seq_printf(m, "cu_id: %u\n", c->topo.cu_id); From patchwork Thu Dec 12 06:57:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13904737 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B6311F37C5; Thu, 12 Dec 2024 06:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986653; cv=none; b=qde2L0+fqpeV2v7PSYHFK6e/6A4U2lw3BdH0Ke3c/SWEh1vtZ3LT3gjxIVErzY2C0dp4a4qW1aPrwYEBqo0bU37jJrk+Yu/n0x5mCeQwPc2VHDFK49NM0yPgsFsDXHRqqeEbEbcxhOqugfNr5TPja66LaD9Rv9qkO/x7K2zf9yo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986653; c=relaxed/simple; bh=Lo7FysfxpdbAhJ5Br5uh/0z/2AfqddNm+WK8FwzxFkg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=q4nHKnoSyc8fEUr2/F4HbCgE6Qc9sXeyVl7hSPr+TMEDDZpp11D6drjvZmnJeBF9oZpjQaJodK232zstgTSt9naf6adtcJIjLDzbhiDJK7Bi19zT1M0iiPatuKi6NrW6hx3qzobSIycu2aQdARf6kPRWC2/49dxBvuL1uIAZhOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=C7AbxUcc; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C7AbxUcc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733986652; x=1765522652; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Lo7FysfxpdbAhJ5Br5uh/0z/2AfqddNm+WK8FwzxFkg=; b=C7AbxUccXAXPLXNECuiGHV4XVa0zpxKt3yjS2mq9D9i/Q9bgi80KuvWz B+KSGOBTxLNQlQ5zCawWIWSvy+YYDwbwaTm1WXdymDjtz1DGq1aFtF6b6 Y5A2x5vF1Sc91tbeNW25m/Ilac8shLcEv9QWkSEo/3wYA00ZqIQK7aLS4 EghcTZJlJWCrq+AF1POx5tFp6j1dGcCbFa1nlJp8IheC111JTpgtIvvYS gKbPxaVx9ee1m9W7yNqQyZGK4cHE2YC8F3SAf3iAfGFYJFBlA7v7PqdUT HmIigxYS3slB1ABSd1WoY2L001atll2okPOlr22A7YstEk6sX1YbnGwiF Q==; X-CSE-ConnectionGUID: dy7Stwg2Si2Yefk188Kqow== X-CSE-MsgGUID: 3C2ePYppRFKZichQ7yOm7w== X-IronPort-AV: E=McAfee;i="6700,10204,11283"; a="59786328" X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="59786328" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:32 -0800 X-CSE-ConnectionGUID: 19zjN0qVRpujMghuBWxiAw== X-CSE-MsgGUID: ty9UeVlPQmalsexxyNZcxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="96372377" Received: from unknown (HELO desk) ([10.125.145.3]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:31 -0800 Date: Wed, 11 Dec 2024 22:57:30 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi , "Rafael J. Wysocki" Subject: [PATCH v5 2/9] cpufreq: intel_pstate: Avoid SMP calls to get cpu-type Message-ID: <20241211-add-cpu-type-v5-2-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Intel pstate driver relies on SMP calls to get the cpu-type of a given CPU. Remove the SMP calls and instead use the cached value of cpu-type which is more efficient. Suggested-by: Dave Hansen Acked-by: Srinivas Pandruvada Acked-by: Rafael J. Wysocki Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- drivers/cpufreq/intel_pstate.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index b8e2396a708a..c767680daa03 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2202,24 +2202,17 @@ static int knl_get_turbo_pstate(int cpu) return ret; } -static void hybrid_get_type(void *data) -{ - u8 *cpu_type = data; - - *cpu_type = get_this_hybrid_cpu_type(); -} - static int hwp_get_cpu_scaling(int cpu) { - u8 cpu_type = 0; + struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); + u8 cpu_type = c->topo.intel_type; - smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1); /* P-cores have a smaller perf level-to-freqency scaling factor. */ - if (cpu_type == 0x40) + if (cpu_type == INTEL_CPU_TYPE_CORE) return hybrid_scaling_factor; /* Use default core scaling for E-cores */ - if (cpu_type == 0x20) + if (cpu_type == INTEL_CPU_TYPE_ATOM) return core_get_scaling(); /* From patchwork Thu Dec 12 06:57:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13904738 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEA81204F60; Thu, 12 Dec 2024 06:57:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986659; cv=none; b=EYeNM9pv456A0Vc5zQQBGxRm7JcunTq7VekO+eXHt0IFn5rLD7kfECSFJ3l2O2ZtHrPCNRohD8E8+yqO114M88pWmGFH0N5OVgvkgWC3Dcr1ZIfO7OpuH6+YU7Y2c+mQHdLilE3qeiaoajUfrIKvLB0S8RrXWCQwix2V/nB0Xqw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986659; c=relaxed/simple; bh=SK/+JtQICpEJjfQtv2u02HuEDGoEPxUqFzCzGowfj88=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=qTduDxwd6NNRbNZZqeoXROQ1x0pjkGlBC/+jFBTIUHmZJ5tDZfwUJvyxsRjbCx4b49nuLf707IvtAdk2NarhsM2NON2A3gFFa+ZLYN9y4TydyHwWks00ivVx557h3PlE/ocYah9R42lXVUI+5kL0pV7b7wjN1U07DpVpcFEha+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Vws8QZ/t; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Vws8QZ/t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733986658; x=1765522658; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=SK/+JtQICpEJjfQtv2u02HuEDGoEPxUqFzCzGowfj88=; b=Vws8QZ/t1iwUKjvQ2abBplxCXgep1ZQJirhlNf+gKLJdcqDyU6Sec1n6 rnEgLvGLoQ3Vnk/+nX6bksudZ9ixLDuKQ63aCbjuQZsVRlwOoZvOcrpXH 7x3BwqT/GLCK5uLMyoi4LhCDtMvRf+MzIxj9ozR7kaQEYqal1DN9f4odA GY1Od4dqqXILkwSQ6Hb0J5iMXY9a8RNEak7YvilMoujULVSb1AWBnSwYU MnE/LSBv2GgUTkS6znuuOAIHrOn/crBr71Bs0ARiG6RN9k2vMnILUFMxu I55LC/TPHQKW30nW3+CKghCb8Dgz2gtv+E7ULeJ2vew5bG4ORc9aLKjZC Q==; X-CSE-ConnectionGUID: hFOzFKBySkmaeZAb/lk4zQ== X-CSE-MsgGUID: fsdk6Hb4Q+uctdefZOaL4w== X-IronPort-AV: E=McAfee;i="6700,10204,11283"; a="34533430" X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="34533430" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:37 -0800 X-CSE-ConnectionGUID: HGZ+w1bbSw+w1norqgHTmQ== X-CSE-MsgGUID: bNlpoya6R5GVxi5VQVXvqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="96223518" Received: from unknown (HELO desk) ([10.125.145.3]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:37 -0800 Date: Wed, 11 Dec 2024 22:57:36 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 3/9] perf/x86/intel: Use cache cpu-type for hybrid PMU selection Message-ID: <20241211-add-cpu-type-v5-3-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> get_this_hybrid_cpu_type() misses a case when cpu-type is populated regardless of X86_FEATURE_HYBRID_CPU. This is particularly true for hybrid variants that have P or E cores fused off. Instead use the cpu-type cached in struct x86_topology, as it does not rely on hybrid feature to enumerate cpu-type. This can also help avoid the model-specific fixup get_hybrid_cpu_type(). Also replace the get_this_hybrid_cpu_native_id() with its cached value in struct x86_topology. While at it, remove enum hybrid_cpu_type as it serves no purpose when we have the exact cpu-types defined in enum intel_cpu_type. Also rename atom_native_id to intel_native_id and move it to intel-family.h where intel_cpu_type lives. Suggested-by: Dave Hansen Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/events/intel/core.c | 19 ++++++++++--------- arch/x86/events/perf_event.h | 19 +------------------ arch/x86/include/asm/intel-family.h | 15 ++++++++++++++- 3 files changed, 25 insertions(+), 28 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index bb284aff7bfd..9e9ab9d1938e 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4588,9 +4588,9 @@ static int adl_hw_config(struct perf_event *event) return -EOPNOTSUPP; } -static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void) +static enum intel_cpu_type adl_get_hybrid_cpu_type(void) { - return HYBRID_INTEL_CORE; + return INTEL_CPU_TYPE_CORE; } static inline bool erratum_hsw11(struct perf_event *event) @@ -4928,7 +4928,8 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) { - u8 cpu_type = get_this_hybrid_cpu_type(); + struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); + enum intel_cpu_type cpu_type = c->topo.intel_type; int i; /* @@ -4937,7 +4938,7 @@ static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) * on it. There should be a fixup function provided for these * troublesome CPUs (->get_hybrid_cpu_type). */ - if (cpu_type == HYBRID_INTEL_NONE) { + if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { if (x86_pmu.get_hybrid_cpu_type) cpu_type = x86_pmu.get_hybrid_cpu_type(); else @@ -4954,16 +4955,16 @@ static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; u32 native_id; - if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big) + if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) return &x86_pmu.hybrid_pmu[i]; - if (cpu_type == HYBRID_INTEL_ATOM) { + if (cpu_type == INTEL_CPU_TYPE_ATOM) { if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) return &x86_pmu.hybrid_pmu[i]; - native_id = get_this_hybrid_cpu_native_id(); - if (native_id == skt_native_id && pmu_type == hybrid_small) + native_id = c->topo.intel_native_model_id; + if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) return &x86_pmu.hybrid_pmu[i]; - if (native_id == cmt_native_id && pmu_type == hybrid_tiny) + if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) return &x86_pmu.hybrid_pmu[i]; } } diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 82c6f45ce975..3c7d2ef5963a 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -668,18 +668,6 @@ enum { #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) -/* - * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture - * of the core. Bits 31-24 indicates its core type (Core or Atom) - * and Bits [23:0] indicates the native model ID of the core. - * Core type and native model ID are defined in below enumerations. - */ -enum hybrid_cpu_type { - HYBRID_INTEL_NONE, - HYBRID_INTEL_ATOM = 0x20, - HYBRID_INTEL_CORE = 0x40, -}; - #define X86_HYBRID_PMU_ATOM_IDX 0 #define X86_HYBRID_PMU_CORE_IDX 1 #define X86_HYBRID_PMU_TINY_IDX 2 @@ -696,11 +684,6 @@ enum hybrid_pmu_type { hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny, }; -enum atom_native_id { - cmt_native_id = 0x2, /* Crestmont */ - skt_native_id = 0x3, /* Skymont */ -}; - struct x86_hybrid_pmu { struct pmu pmu; const char *name; @@ -993,7 +976,7 @@ struct x86_pmu { */ int num_hybrid_pmus; struct x86_hybrid_pmu *hybrid_pmu; - enum hybrid_cpu_type (*get_hybrid_cpu_type) (void); + enum intel_cpu_type (*get_hybrid_cpu_type) (void); }; struct x86_perf_task_context_opt { diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6d7b04ffc5fd..8c7076445893 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -182,10 +182,23 @@ /* Family 19 */ #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ -/* CPU core types */ +/* + * Intel CPU core types + * + * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture + * of the core. Bits 31-24 indicates its core type (Core or Atom) + * and Bits [23:0] indicates the native model ID of the core. + * Core type and native model ID are defined in below enumerations. + */ enum intel_cpu_type { + INTEL_CPU_TYPE_UNKNOWN, INTEL_CPU_TYPE_ATOM = 0x20, INTEL_CPU_TYPE_CORE = 0x40, }; +enum intel_native_id { + INTEL_ATOM_CMT_NATIVE_ID = 0x2, /* Crestmont */ + INTEL_ATOM_SKT_NATIVE_ID = 0x3, /* Skymont */ +}; + #endif /* _ASM_X86_INTEL_FAMILY_H */ From patchwork Thu Dec 12 06:57:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13904739 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 970C3205513; Thu, 12 Dec 2024 06:57:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986664; cv=none; b=b4ujXErr3BeVK8wB3BI/wvKdw/G751DTkqUR4G+Z4e/gtasuYhLz09Lh5ntxUToCBLGliPUhNC4/nqlDlYL/sjwzaW35fWv/fW1JT951pbc8HX6w1lb1ctnIa30gufHjbBhtRlC97L6I+ITmtbndHE4Bvv7TlydT7M56sXDAutA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733986664; c=relaxed/simple; bh=0ZzOq2V4e+YFlxsyQdyiOKg5eryGrazxHADgZpLlQZY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=A1oOeh2cp6RcHw8MW5daD2qUoKdM93ybRZVW8YyhiboGVbI9TV0R3fAliP7FikB0gj6ZWNYwWKbCqDGDrkuLRqaZXXvv1Z9vJXKFLEYRZXPrrEPywdVoH02M4K4IA15JkESZEjoKf2fWs6RuOZKIs2+HNQWsv8dHjlOqIj212FY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SdZ9+RXq; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SdZ9+RXq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733986663; x=1765522663; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=0ZzOq2V4e+YFlxsyQdyiOKg5eryGrazxHADgZpLlQZY=; b=SdZ9+RXqImyPZ47Fyylv3uJhrQn+DhP7lSGfJay+jUagYB0V60bp76lN ldEYetEmnFwaXNsow8H6RsdQK+uXS+tMEMbYot2Yf2iaECMUqkr5fcjf7 h5bycjshpwUXqfoH/7k5zNTy3WU02xIpIJ85b1CS1lkTqbXqzHqvZOIHu ugmpHb9OsIFLFtBt5K3lBFd0xVC9/ugKjr1RBpWuu35TRYeO/eEO0uJNh Uw9s8pyzgq1aKdMtMNPwdqnVSN+NLG1NmCjHBpgABrg7BpCP64o22pSgS xnZfRYg4If5Tx84P0Ysyf7d22PO3wLFXcANMduqt15IumqAlfHvlz+HnC A==; X-CSE-ConnectionGUID: 5tlB9qHyT6Sz/ARp8I45eQ== X-CSE-MsgGUID: Ymqo3dDZQPqnAMOmTpBWcw== X-IronPort-AV: E=McAfee;i="6700,10204,11283"; a="34533443" X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="34533443" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:43 -0800 X-CSE-ConnectionGUID: XtP5uTU3RgiQDUa0Afba8Q== X-CSE-MsgGUID: Br6hWtE3SsOQdWdjiLZJVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="96223529" Received: from unknown (HELO desk) ([10.125.145.3]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:57:42 -0800 Date: Wed, 11 Dec 2024 22:57:41 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 4/9] x86/cpu: Remove get_this_hybrid_cpu_*() Message-ID: <20241211-add-cpu-type-v5-4-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Because calls to get_this_hybrid_cpu_type() and get_this_hybrid_cpu_native_id() are not required now. cpu-type and native-model-id are cached at boot in per-cpu struct cpuinfo_topology. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu.h | 14 -------------- arch/x86/kernel/cpu/intel.c | 31 ------------------------------- 2 files changed, 45 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 98eced5084ca..0c8ec62789a1 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -50,20 +50,6 @@ static inline void split_lock_init(void) {} static inline void bus_lock_init(void) {} #endif -#ifdef CONFIG_CPU_SUP_INTEL -u8 get_this_hybrid_cpu_type(void); -u32 get_this_hybrid_cpu_native_id(void); -#else -static inline u8 get_this_hybrid_cpu_type(void) -{ - return 0; -} - -static inline u32 get_this_hybrid_cpu_native_id(void) -{ - return 0; -} -#endif #ifdef CONFIG_IA32_FEAT_CTL void init_ia32_feat_ctl(struct cpuinfo_x86 *c); #else diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index d1de300af173..adb34184c74a 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -876,34 +876,3 @@ static const struct cpu_dev intel_cpu_dev = { }; cpu_dev_register(intel_cpu_dev); - -#define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 - -/** - * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU - * - * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in - * a hybrid processor. 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Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 5/9] x86/cpu: Name CPU matching macro more generically (and shorten) Message-ID: <20241211-add-cpu-type-v5-5-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> To add cpu-type to the existing CPU matching infrastructure, the base macro X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE need to append _CPU_TYPE. This makes an already long name longer, and somewhat incomprehensible. To avoid this, rename the base macro to X86_MATCH_CPU. The macro name doesn't need to explicitly tell everything that it matches. The arguments to the macro already hints that. For consistency, use this base macro to define X86_MATCH_VFM and friends. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 100 ++++++++++------------------------- 1 file changed, 29 insertions(+), 71 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h index e4121d9aa9e1..dee45332b682 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -58,7 +58,7 @@ #define X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins) /** - * X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU matching + * X86_MATCH_CPU - Base macro for CPU matching * @_vendor: The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY * The name is expanded to X86_VENDOR_@_vendor * @_family: The family number or X86_FAMILY_ANY @@ -75,19 +75,7 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _model, \ - _steppings, _feature, _data) { \ - .vendor = X86_VENDOR_##_vendor, \ - .family = _family, \ - .model = _model, \ - .steppings = _steppings, \ - .feature = _feature, \ - .flags = X86_CPU_ID_FLAG_ENTRY_VALID, \ - .driver_data = (unsigned long) _data \ -} - -#define X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _model, \ - _steppings, _feature, _data) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _data) { \ .vendor = _vendor, \ .family = _family, \ .model = _model, \ @@ -107,13 +95,10 @@ * @_data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * The steppings arguments of X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE() is - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ - X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(vendor, family, model, \ - X86_STEPPING_ANY, feature, data) +#define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ + feature, data) /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CPU feature @@ -124,13 +109,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, \ - X86_MODEL_ANY, feature, data) +#define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -140,12 +122,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ - X86_MATCH_VENDOR_FAM_FEATURE(vendor, X86_FAMILY_ANY, feature, data) +#define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -153,12 +133,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_FEATURE(feature, data) \ - X86_MATCH_VENDOR_FEATURE(ANY, feature, data) +#define X86_MATCH_FEATURE(feature, data) \ + X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -169,13 +147,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, \ - X86_FEATURE_ANY, data) +#define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ + X86_FEATURE_ANY, data) /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -185,12 +160,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments to X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set of wildcards. */ -#define X86_MATCH_VENDOR_FAM(vendor, family, data) \ - X86_MATCH_VENDOR_FAM_MODEL(vendor, family, X86_MODEL_ANY, data) +#define X86_MATCH_VENDOR_FAM(vendor, family, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ + X86_STEPPING_ANY, X86_FEATURE_ANY, data) /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -198,15 +171,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * Stepping and feature are set to wildcards */ -#define X86_MATCH_VFM(vfm, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) +#define X86_MATCH_VFM(vfm, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, data) /** * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping @@ -215,15 +183,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * feature is set to wildcard */ -#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - steppings, X86_FEATURE_ANY, data) +#define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + steppings, X86_FEATURE_ANY, data) /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -232,15 +195,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * Steppings is set to wildcard */ -#define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) +#define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, feature, data) /* * Match specific microcode revisions. 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Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 6/9] x86/cpu: Add cpu_type to struct x86_cpu_id Message-ID: <20241211-add-cpu-type-v5-6-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> In addition to matching vendor/family/model/feature, for hybrid variants it is required to also match cpu-type also. For example some CPU vulnerabilities like RFDS only affects a specific cpu-type. To be able to also match CPUs based on their type, add a new field cpu_type to struct x86_cpu_id which is used by the CPU-matching tables. Introduce X86_CPU_TYPE_ANY for the cases that don't care about the cpu-type. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 33 +++++++++++++++++++++++---------- include/linux/mod_devicetable.h | 2 ++ 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h index dee45332b682..f50377a32cb6 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -75,13 +75,14 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _data) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _cpu_type, _data) { \ .vendor = _vendor, \ .family = _family, \ .model = _model, \ .steppings = _steppings, \ .feature = _feature, \ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, \ + .cpu_type = _cpu_type, \ .driver_data = (unsigned long) _data \ } @@ -98,7 +99,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - feature, data) + feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CPU feature @@ -112,7 +113,7 @@ */ #define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -125,7 +126,7 @@ */ #define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -136,7 +137,7 @@ */ #define X86_MATCH_FEATURE(feature, data) \ X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -150,7 +151,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - X86_FEATURE_ANY, data) + X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -163,7 +164,7 @@ */ #define X86_MATCH_VENDOR_FAM(vendor, family, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -174,7 +175,7 @@ */ #define X86_MATCH_VFM(vfm, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM_STEPPINGS - Match encoded vendor/family/model/stepping @@ -186,7 +187,7 @@ */ #define X86_MATCH_VFM_STEPPINGS(vfm, steppings, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - steppings, X86_FEATURE_ANY, data) + steppings, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -198,7 +199,19 @@ */ #define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) + +/** + * X86_MATCH_VFM_CPU_TYPE - Match encoded vendor/family/model/cpu-type + * @vfm: Encoded 8-bits each for vendor, family, model + * @cpu_type: CPU type e.g. P-core, E-core on Intel + * @data: Driver specific data or NULL. The internal storage + * format is unsigned long. The supplied value, pointer + * etc. is cast to unsigned long internally. + */ +#define X86_MATCH_VFM_CPU_TYPE(vfm, cpu_type, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, cpu_type, data) /* * Match specific microcode revisions. diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h index 4338b1b4ac44..b8a2e88f966f 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -692,6 +692,7 @@ struct x86_cpu_id { __u16 feature; /* bit index */ /* Solely for kernel-internal use: DO NOT EXPORT to userspace! */ __u16 flags; + __u8 cpu_type; kernel_ulong_t driver_data; }; @@ -701,6 +702,7 @@ struct x86_cpu_id { #define X86_MODEL_ANY 0 #define X86_STEPPING_ANY 0 #define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ +#define X86_CPU_TYPE_ANY 0 /* * Generic table type for matching CPU features. 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Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 7/9] x86/cpu: Update x86_match_cpu() to also use cpu-type Message-ID: <20241211-add-cpu-type-v5-7-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Non-hybrid CPU variants that share the same Family/Model could be differentiated by their cpu-type. x86_match_cpu() currently does not use cpu-type for CPU matching. Dave Hansen suggested to use below conditions to match CPU-type: 1. If CPU_TYPE_ANY (the wildcard), then matched 2. If hybrid, then matched 3. If !hybrid, look at the boot CPU and compare the cpu-type to determine if it is a match. This special case for hybrid systems allows more compact vulnerability list. Imagine that "Haswell" CPUs might or might not be hybrid and that only Atom cores are vulnerable to Meltdown. That means there are three possibilities: 1. P-core only 2. Atom only 3. Atom + P-core (aka. hybrid) One might be tempted to code up the vulnerability list like this: MATCH( HASWELL, X86_FEATURE_HYBRID, MELTDOWN) MATCH_TYPE(HASWELL, ATOM, MELTDOWN) Logically, this matches #2 and #3. But that's a little silly. You would only ask for the "ATOM" match in cases where there *WERE* hybrid cores in play. You shouldn't have to _also_ ask for hybrid cores explicitly. In short, assume that processors that enumerate Hybrid==1 have a vulnerable core type. Update x86_match_cpu() to also match cpu-type. Also treat hybrid systems as special, and match them to any cpu-type. Suggested-by: Dave Hansen Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/match.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c index 8e7de733320a..0c259efff490 100644 --- a/arch/x86/kernel/cpu/match.c +++ b/arch/x86/kernel/cpu/match.c @@ -5,6 +5,34 @@ #include #include +/** + * x86_match_vendor_cpu_type - helper function to match the hardware defined + * cpu-type for a single entry in the x86_cpu_id + * table. Note, this function does not match the + * generic cpu-types TOPO_CPU_TYPE_EFFICIENCY and + * TOPO_CPU_TYPE_PERFORMANCE. + * @c: Pointer to the cpuinfo_x86 structure of the CPU to match. + * @m: Pointer to the x86_cpu_id entry to match against. + * + * Return: true if the cpu-type matches, false otherwise. + */ +static bool x86_match_vendor_cpu_type(struct cpuinfo_x86 *c, const struct x86_cpu_id *m) +{ + if (m->cpu_type == X86_CPU_TYPE_ANY) + return true; + + /* Hybrid CPUs are special, they are assumed to match all cpu-types */ + if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) + return true; + + if (c->x86_vendor == X86_VENDOR_INTEL) + return m->cpu_type == c->topo.intel_type; + if (c->x86_vendor == X86_VENDOR_AMD) + return m->cpu_type == c->topo.amd_type; + + return false; +} + /** * x86_match_cpu - match current CPU again an array of x86_cpu_ids * @match: Pointer to array of x86_cpu_ids. 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Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 8/9] x86/bugs: Declutter vulnerable CPU list Message-ID: <20241211-add-cpu-type-v5-8-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> The affected processor table has a lot of repetition and redundant information that can be omitted for brevity. Like: VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), can easily be simplified to: VULNBL_INTEL(IVYBRIDGE, SRBDS), Apply this to all the entries in the affected processor table. No functional change. Disassembly of cpu_vuln_blacklist: objdump -j .init.data --disassemble=cpu_vuln_blacklist vmlinux doesn't show any difference before and after the change. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/common.c | 143 ++++++++++++++++++++++--------------------- 1 file changed, 73 insertions(+), 70 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a5c28975c608..6c45b8bed9fc 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1126,7 +1126,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) #define VULNWL_INTEL(vfm, whitelist) \ - X86_MATCH_VFM(vfm, whitelist) + X86_MATCH_VFM(INTEL_##vfm, whitelist) #define VULNWL_AMD(family, whitelist) \ VULNWL(AMD, family, X86_MODEL_ANY, whitelist) @@ -1143,32 +1143,32 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), /* Intel Family 6 */ - VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), + VULNWL_INTEL(TIGERLAKE, NO_MMIO), + VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), + VULNWL_INTEL(ALDERLAKE, NO_MMIO), + VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), + VULNWL_INTEL(CORE_YONAH, NO_SSB), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY), + VULNWL_INTEL(ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), /* * Technically, swapgs isn't serializing on AMD (despite it previously @@ -1178,9 +1178,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { * good enough for our purposes. */ - VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), /* AMD Family 0xf - 0x12 */ VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI), @@ -1201,8 +1201,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define VULNBL(vendor, family, model, blacklist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) -#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ - X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues) +#define VULNBL_INTEL(vfm, issues) \ + X86_MATCH_VFM(INTEL_##vfm, issues) + +#define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ + X86_MATCH_VFM_STEPPINGS(INTEL_##vfm, steppings, issues) #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1227,49 +1230,49 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define RFDS BIT(7) static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { - VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS), - VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS), - VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS), - VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS), - - VULNBL_AMD(0x15, RETBLEED), - VULNBL_AMD(0x16, RETBLEED), - VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), - VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), - VULNBL_AMD(0x19, SRSO), + VULNBL_INTEL( IVYBRIDGE, SRBDS), + VULNBL_INTEL( HASWELL, SRBDS), + VULNBL_INTEL( HASWELL_L, SRBDS), + VULNBL_INTEL( HASWELL_G, SRBDS), + VULNBL_INTEL( HASWELL_X, MMIO), + VULNBL_INTEL( BROADWELL_D, MMIO), + VULNBL_INTEL( BROADWELL_G, SRBDS), + VULNBL_INTEL( BROADWELL_X, MMIO), + VULNBL_INTEL( BROADWELL, SRBDS), + VULNBL_INTEL( SKYLAKE_X, MMIO | RETBLEED | GDS), + VULNBL_INTEL( SKYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( SKYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( KABYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( KABYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( CANNONLAKE_L, RETBLEED), + VULNBL_INTEL( ICELAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL( ICELAKE_D, MMIO | GDS), + VULNBL_INTEL( ICELAKE_X, MMIO | GDS), + VULNBL_INTEL( COMETLAKE, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS( COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), + VULNBL_INTEL( COMETLAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL( TIGERLAKE_L, GDS), + VULNBL_INTEL( TIGERLAKE, GDS), + VULNBL_INTEL( LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), + VULNBL_INTEL( ROCKETLAKE, MMIO | RETBLEED | GDS), + VULNBL_INTEL( ALDERLAKE, RFDS), + VULNBL_INTEL( ALDERLAKE_L, RFDS), + VULNBL_INTEL( RAPTORLAKE, RFDS), + VULNBL_INTEL( RAPTORLAKE_P, RFDS), + VULNBL_INTEL( RAPTORLAKE_S, RFDS), + VULNBL_INTEL( ATOM_GRACEMONT, RFDS), + VULNBL_INTEL( ATOM_TREMONT, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL( ATOM_TREMONT_D, MMIO | RFDS), + VULNBL_INTEL( ATOM_TREMONT_L, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL( ATOM_GOLDMONT, RFDS), + VULNBL_INTEL( ATOM_GOLDMONT_D, RFDS), + VULNBL_INTEL( ATOM_GOLDMONT_PLUS, RFDS), + + VULNBL_AMD( 0x15, RETBLEED), + VULNBL_AMD( 0x16, RETBLEED), + VULNBL_AMD( 0x17, RETBLEED | SMT_RSB | SRSO), + VULNBL_HYGON( 0x18, RETBLEED | SMT_RSB | SRSO), + VULNBL_AMD( 0x19, SRSO), {} }; From patchwork Thu Dec 12 06:58:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 13904743 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BACF204C2D; Thu, 12 Dec 2024 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Jgj70ZZjblCGIr1LJw1EHklN4KlOZ8Q1PTNLxXMjxl8Lx3wcFwKxJ9ad2 w==; X-CSE-ConnectionGUID: iWVQH/MfSy+UJHs22kjMww== X-CSE-MsgGUID: 4ASbv9jpQAifrHP/SC7MYA== X-IronPort-AV: E=McAfee;i="6700,10204,11283"; a="37231041" X-IronPort-AV: E=Sophos;i="6.12,227,1728975600"; d="scan'208";a="37231041" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:58:11 -0800 X-CSE-ConnectionGUID: qDCc1EIfQI2BpWkROLzIOw== X-CSE-MsgGUID: BloVe2i4RwG3tFszWvxFaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="127127232" Received: from unknown (HELO desk) ([10.125.145.3]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2024 22:58:09 -0800 Date: Wed, 11 Dec 2024 22:58:09 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v5 9/9] x86/rfds: Exclude P-only parts from the RFDS affected list Message-ID: <20241211-add-cpu-type-v5-9-2ae010f50370@linux.intel.com> X-Mailer: b4 0.14.1 References: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20241211-add-cpu-type-v5-0-2ae010f50370@linux.intel.com> RFDS only affects Atom parts. Vendor/Family/Model matching in the affected processor table makes Alderlake and Raptorlake P-only parts affected (which are not affected in reality). This is because the affected hybrid and E-only parts have the same Family/Model as the unaffected P-only parts. Match CPU-type as Atom to exclude P-only parts as RFDS affected. Note, a guest with the same Family/Model as the affected part may not have leaf 1A enumerated to know its CPU-type, but it should not be a problem as guest's Family/Model can anyways be inaccurate. Moreover, RFDS_NO or RFDS_CLEAR enumeration by the VMM decides the affected status of the guest. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst | 8 -------- arch/x86/kernel/cpu/common.c | 9 +++++++-- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst b/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst index 0585d02b9a6c..ad15417d39f9 100644 --- a/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst +++ b/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst @@ -29,14 +29,6 @@ Below is the list of affected Intel processors [#f1]_: RAPTORLAKE_S 06_BFH =================== ============ -As an exception to this table, Intel Xeon E family parts ALDERLAKE(06_97H) and -RAPTORLAKE(06_B7H) codenamed Catlow are not affected. They are reported as -vulnerable in Linux because they share the same family/model with an affected -part. Unlike their affected counterparts, they do not enumerate RFDS_CLEAR or -CPUID.HYBRID. This information could be used to distinguish between the -affected and unaffected parts, but it is deemed not worth adding complexity as -the reporting is fixed automatically when these parts enumerate RFDS_NO. - Mitigation ========== Intel released a microcode update that enables software to clear sensitive diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 6c45b8bed9fc..a82d6184e1d0 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1207,6 +1207,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \ X86_MATCH_VFM_STEPPINGS(INTEL_##vfm, steppings, issues) +#define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ + X86_MATCH_VFM_CPU_TYPE(INTEL_##vfm, \ + INTEL_CPU_TYPE_##cpu_type, \ + issues) + #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1255,9 +1260,9 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL( TIGERLAKE, GDS), VULNBL_INTEL( LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), VULNBL_INTEL( ROCKETLAKE, MMIO | RETBLEED | GDS), - VULNBL_INTEL( ALDERLAKE, RFDS), + VULNBL_INTEL_TYPE( ALDERLAKE, ATOM, RFDS), VULNBL_INTEL( ALDERLAKE_L, RFDS), - VULNBL_INTEL( RAPTORLAKE, RFDS), + VULNBL_INTEL_TYPE( RAPTORLAKE, ATOM, RFDS), VULNBL_INTEL( RAPTORLAKE_P, RFDS), VULNBL_INTEL( RAPTORLAKE_S, RFDS), VULNBL_INTEL( ATOM_GRACEMONT, RFDS),