From patchwork Thu Dec 12 16:11:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya Kakitapalli X-Patchwork-Id: 13905539 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C068F226532; Thu, 12 Dec 2024 16:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734019936; cv=none; b=Th7bVwd+YHlDnpZUgbUDVkwGfRBd803xUbmiWzXhTR/dS39fkSU2DJxYS3/qcpnXsCu//0TBW2OnqVjpD1WXniMdIZnwqCCjoicG3IPFkC6oErn0v/8sgfg5f1XHvLCKH8JIzv4nIEy4HgzxyrgQ4eR6+ql9UcE/5dVfd0z4UaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734019936; c=relaxed/simple; bh=rd8fp4VsV4P2ptymQhw3Czw8pNECLpb/dwGUWYs4XKU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pTluiBJvC+8U98Y3avj9aRiizOGERPq8cMYoyifAQFbfl9ufY9mor6ZhSJBVWc5UYXVqAnNv0Mw+HDMzk5iR39cetLXsE6QU+aeUAln91ah9VvBQKL9VLVvV4OTy2PBBLRm+5pt9JnRXB3GXWLy5uXlaiq9lCyKpm2/F+F7uQHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GURF4VEB; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GURF4VEB" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BCCwg7i001149; Thu, 12 Dec 2024 16:11:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= tuIkjDGpJhJYcxij2AvgiY7SW1AjlBtYi3wg/so3dYU=; b=GURF4VEBlaxQuIsv 46I4/FUurh2jAynoqg6PMu+Kpw2Ey5drJnybctP+j1rJF6UKMMqX9+ZL9qTGoBvw n5x+WWvBknlhdnPpkIOQwrcSobPP/e67rr4+UDBxRhCJOw+529QS4jAxaffUgt4a pWneim79xZm0dOREbEmSU14EAzdpVxw5niUpxSuNMmZHFOgMubM+iLTBg9WPbgNb ilNtXxeGp2HihIfoDJGA/eAxLFHVSILVzaPh/RHDF6PuQu2hxim7rQJS7XVkQVHd yuB3q2FHgr8Hj5sdWuzlkgD+DN2I6XwobXYLwk/6UCAhnWftKKgusZ57vRtDj3wE qWvTqQ== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43fqes21hq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:11:54 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BCGBrSC026023 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:11:53 GMT Received: from hu-skakitap-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 08:11:46 -0800 From: Satya Priya Kakitapalli Date: Thu, 12 Dec 2024 21:41:20 +0530 Subject: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241212-mbg-v2-support-v2-1-3249a4339b6e@quicinc.com> References: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> In-Reply-To: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Lee Jones , Stephen Boyd , Amit Kucheria , Thara Gopinath , "Bjorn Andersson" , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Jagadeesh Kona" , , , , , , , , "Satya Priya Kakitapalli" X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fCpaz4gR5quQb4vlL5VxYxuuN3mmoKNV X-Proofpoint-ORIG-GUID: fCpaz4gR5quQb4vlL5VxYxuuN3mmoKNV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1011 malwarescore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120117 Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp alarm peripheral found on PM8775 pmic. Signed-off-by: Satya Priya Kakitapalli --- .../bindings/thermal/qcom-spmi-mbg-tm.yaml | 86 ++++++++++++++++++++++ .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h | 41 +++++++++++ 2 files changed, 127 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..909373eb758e4a8b7c2bbd0022c56ab2e823ca13 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom-spmi-mbg-tm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SPMI PMIC MBG Thermal Monitoring + +maintainers: + - Satya Priya Kakitapalli + +description: + Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die + temperature and generates an interrupt if the PMIC die temperature is + over a set of programmable temperature thresholds. It allows monitoring + for both hot and cold, LVL1 and LVL2 thresholds, which makes it different + from the existing temp alarm peripheral. The interrupt comes over SPMI + and the MBG's fault status register gives details to understand whether + it is a hot/cold and LVL1/LVL2 violation. + +allOf: + - $ref: thermal-sensor.yaml# + +properties: + compatible: + const: qcom,spmi-pm8775-mbg-tm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + io-channels: + items: + - description: ADC channel, which reports chip die temperature. + + io-channel-names: + const: thermal + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - io-channels + - io-channel-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_0_tz: temperature-sensor@d700 { + compatible = "qcom,spmi-pm8775-mbg-tm"; + reg = <0xd700>; + interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8775_1_adc PM8775_ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + pm8775-mbg0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_0_tz>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; +... diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h new file mode 100644 index 0000000000000000000000000000000000000000..33f5454367777b10fda248476a0abd17da86ecf6 --- /dev/null +++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H + +#include + +#define PM8775_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND) +#define PM8775_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF) +#define PM8775_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC) +#define PM8775_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP) + +#define PM8775_ADC5_GEN3_AMUX1_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM) +#define PM8775_ADC5_GEN3_AMUX2_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM) +#define PM8775_ADC5_GEN3_AMUX3_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM) +#define PM8775_ADC5_GEN3_AMUX4_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM) +#define PM8775_ADC5_GEN3_AMUX5_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM) +#define PM8775_ADC5_GEN3_AMUX6_THM(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM) +#define PM8775_ADC5_GEN3_AMUX1_GPIO9(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO) +#define PM8775_ADC5_GEN3_AMUX2_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO) +#define PM8775_ADC5_GEN3_AMUX3_GPIO11(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO) +#define PM8775_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO) + +/* 100k pull-up2 */ +#define PM8775_ADC5_GEN3_AMUX1_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX2_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX3_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX4_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX5_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX6_THM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU) +#define PM8775_ADC5_GEN3_AMUX1_GPIO9_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX2_GPIO10_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX3_GPIO11_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU) +#define PM8775_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU) + +#define PM8775_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */ From patchwork Thu Dec 12 16:11:21 2024 Content-Type: text/plain; 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Signed-off-by: Satya Priya Kakitapalli --- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 11da55644262fada1bcd215943078330332156aa..3a1acb658960329e881d67e264d221764bcec57e 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -209,6 +209,10 @@ patternProperties: $ref: /schemas/leds/backlight/qcom-wled.yaml# unevaluatedProperties: false + "temperature-sensor@[0-9a-f]+$": + type: object + $ref: /schemas/thermal/qcom-spmi-mbg-tm.yaml# + required: - compatible - reg From patchwork Thu Dec 12 16:11:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya Kakitapalli X-Patchwork-Id: 13905541 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A06223DEAD; Thu, 12 Dec 2024 16:12:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734019950; cv=none; b=ndxTJWkiLAodcsREfUh3v7g3vVBqcN9EqdRk6+i6/LihlUL2u5L7FjnhxjbOBUEBi/6CiY67AKEOc3hpxoWf/CLdeeb7pRp1HF+oz69rd899Z7e8tna37pG/PMtQhGLqlONMtJ2OUf7LnNqr73m0sdL+IFOMdCWsKwOkFK747S4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734019950; c=relaxed/simple; bh=PuTpqT1yUejAmNrWw0Gt2DDNR8C7pkoc74P+nCmm1B8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=MRZhf2WB9iWncol1r9H9lgVU0oweevzdwW8oVSBuY7vcZOan0zAYZL8o9WjyNOxzIgQ4hIL2LDwXO0WVLo+oo/M+iUQ3K9+qJ2YWEm+9PFDZ+vJObkPFdQgAferhy69No/tdxboXMbALLCBsqOmZ4jK4MIlL8WdkXet3PnX8FJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Jt7wqa6L; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Jt7wqa6L" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BC7kTQ8019578; Thu, 12 Dec 2024 16:12:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= IQJZIYvE26ZSVfYbzs/vp584m25GdY5CFu9wfMMKJos=; b=Jt7wqa6LALVvvX9K /6IFX5HSxtFfr9nScWYZKNNuTm+Dk0SQZCC4zh4zxewyM77P775v+KUIsNj+qduS Ki/rwuUVTcs1O53iouFth72hPmATJBJfL19eYGVmFKXtCIkWRcfkn0wJtOGDA/Vi P7FlxYKFwrgMuesHe8A6/a4y4u6quwNF5Pkdv2TmzHw1J6VuJ29NG8hiEqi0PPVr HTs5l4NDXaMJM73w+hwLWXgkrTyZqWixmBlYU1Jtc+z37cF89iJs1dtWycOz+xfj VkpJbR3V5lYBZ98tcFNmxe1FAwAX3LmBOml4+VFLC7ILTEBnRkAFTYUimKUjm6p6 YyVuoA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43ffdyu4q7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:12:09 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BCGC8ef026419 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:12:08 GMT Received: from hu-skakitap-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 08:12:01 -0800 From: Satya Priya Kakitapalli Date: Thu, 12 Dec 2024 21:41:22 +0530 Subject: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241212-mbg-v2-support-v2-3-3249a4339b6e@quicinc.com> References: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> In-Reply-To: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Cameron , Lars-Peter Clausen , Lee Jones , Stephen Boyd , Amit Kucheria , Thara Gopinath , "Bjorn Andersson" , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Jagadeesh Kona" , , , , , , , , "Satya Priya Kakitapalli" X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kt1VHi5_COCCdZcNys2dOb3IO-biqVmU X-Proofpoint-GUID: kt1VHi5_COCCdZcNys2dOb3IO-biqVmU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120117 Add driver for the MBG thermal monitoring device. It monitors the die temperature, and when there is a level 1 upper threshold violation, it receives an interrupt over spmi. The driver reads the fault status register and notifies thermal accordingly. Signed-off-by: Satya Priya Kakitapalli --- drivers/thermal/qcom/Kconfig | 11 ++ drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-mbg-tm.c | 245 ++++++++++++++++++++++++++++++++ 3 files changed, 257 insertions(+) diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index f9876fb8606dd05022bd5ace56a0804f5a8cbfce..2ddfb6228edc7369355d9091fba3b1c130cad459 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -32,6 +32,17 @@ config QCOM_SPMI_ADC_TM5_GEN3 Thermal client sets threshold temperature for both warm and cool and gets updated when a threshold is reached. +config QCOM_SPMI_MBG_TM + tristate "Qualcomm Technologies, Inc. SPMI PMIC MBG Temperature monitor" + depends on QCOM_SPMI_ADC5_GEN3 + select REGMAP_SPMI + help + This enables a thermal driver for the MBG thermal monitoring device. + It shows up in sysfs as a thermal sensor with single trip point. + It notifies the thermal framework when this trip is violated. The + temperature reported by the thermal sensor reflects the real + time die temperature through ADC channel. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 828d9e7bc797094453566f310b1aea558294162b..937ba0fe2801325592ba8e4354ba1f0ec3109c32 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -5,5 +5,6 @@ qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) += qcom-spmi-adc-tm5-gen3.o +obj-$(CONFIG_QCOM_SPMI_MBG_TM) += qcom-spmi-mbg-tm.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o obj-$(CONFIG_QCOM_LMH) += lmh.o diff --git a/drivers/thermal/qcom/qcom-spmi-mbg-tm.c b/drivers/thermal/qcom/qcom-spmi-mbg-tm.c new file mode 100644 index 0000000000000000000000000000000000000000..22ca331a6de355af22f270d6e047167ce1bcb55a --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-mbg-tm.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-only +//Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_core.h" + +#define MBG_TEMP_MON2_FAULT_STATUS 0x50 + +#define MON_FAULT_STATUS_MASK GENMASK(7, 6) +#define MON_POLARITY_STATUS_MASK GENMASK(5, 4) + +#define MON_FAULT_STATUS_LVL1 BIT(6) +#define MON_POLARITY_STATUS_UPR BIT(4) + +#define MON2_LVL1_UP_THRESH 0x59 + +#define MBG_TEMP_MON2_MISC_CFG 0x5f +#define MON2_UP_THRESH_EN BIT(1) + +#define MBG_TEMP_STEP_MV 8 +#define MBG_TEMP_DEFAULT_TEMP_MV 600 +#define MBG_TEMP_CONSTANT 1000 +#define MBG_MIN_TRIP_TEMP 25000 +#define MBG_MAX_SUPPORTED_TEMP 160000 + +struct mbg_tm_chip { + struct regmap *map; + struct device *dev; + struct thermal_zone_device *tz_dev; + struct mutex lock; + unsigned int base; + int irq; + int last_temp; + bool last_thres_crossed; + struct iio_channel *adc; +}; + +struct mbg_map_table { + int min_temp; + int vtemp0; + int tc; +}; + +static const struct mbg_map_table map_table[] = { + /* minT vtemp0 tc */ + { -60000, 4337, 1967 }, + { -40000, 4731, 1964 }, + { -20000, 5124, 1957 }, + { 0, 5515, 1949 }, + { 20000, 5905, 1940 }, + { 40000, 6293, 1930 }, + { 60000, 6679, 1921 }, + { 80000, 7064, 1910 }, + { 100000, 7446, 1896 }, + { 120000, 7825, 1878 }, + { 140000, 8201, 1859 }, +}; + +static int mbg_tm_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct mbg_tm_chip *chip = thermal_zone_device_priv(tz); + int ret, milli_celsius; + + if (!temp) + return -EINVAL; + + if (chip->last_thres_crossed) { + pr_debug("last_temp: %d\n", chip->last_temp); + chip->last_thres_crossed = false; + *temp = chip->last_temp; + return 0; + } + + ret = iio_read_channel_processed(chip->adc, &milli_celsius); + if (ret < 0) { + dev_err(chip->dev, "failed to read iio channel %d\n", ret); + return ret; + } + + *temp = milli_celsius; + + return 0; +} + +static int temp_to_vtemp(int temp) +{ + + int idx, vtemp, tc = 0, t0 = 0, vtemp0 = 0; + + for (idx = 0; idx < ARRAY_SIZE(map_table); idx++) + if (temp >= map_table[idx].min_temp && + temp < (map_table[idx].min_temp + 20000)) { + tc = map_table[idx].tc; + t0 = map_table[idx].min_temp; + vtemp0 = map_table[idx].vtemp0; + break; + } + + /* + * Formula to calculate vtemp(mV) from a given temp + * vtemp = (temp - minT) * tc + vtemp0 + * tc, t0 and vtemp0 values are mentioned in the map_table array. + */ + vtemp = ((temp - t0) * tc + vtemp0 * 100000) / 1000000; + + return abs(vtemp - MBG_TEMP_DEFAULT_TEMP_MV) / MBG_TEMP_STEP_MV; +} + +static int mbg_tm_set_trip_temp(struct thermal_zone_device *tz, int low_temp, + int temp) +{ + struct mbg_tm_chip *chip = thermal_zone_device_priv(tz); + int ret = 0; + + guard(mutex)(&chip->lock); + + /* The HW has a limitation that the trip set must be above 25C */ + if (temp > MBG_MIN_TRIP_TEMP && temp < MBG_MAX_SUPPORTED_TEMP) { + regmap_set_bits(chip->map, + chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN); + ret = regmap_write(chip->map, chip->base + MON2_LVL1_UP_THRESH, + temp_to_vtemp(temp)); + if (ret < 0) + return ret; + } else { + dev_dbg(chip->dev, "Set trip b/w 25C and 160C\n"); + regmap_clear_bits(chip->map, + chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN); + } + + /* + * Configure the last_temp one degree higher, to ensure the + * violated temp is returned to thermal framework when it reads + * temperature for the first time after the violation happens. + * This is needed to account for the inaccuracy in the conversion + * formula used which leads to the thermal framework setting back + * the same thresholds in case the temperature it reads does not + * show violation. + */ + chip->last_temp = temp + MBG_TEMP_CONSTANT; + + return ret; +} + +static const struct thermal_zone_device_ops mbg_tm_ops = { + .get_temp = mbg_tm_get_temp, + .set_trips = mbg_tm_set_trip_temp, +}; + +static irqreturn_t mbg_tm_isr(int irq, void *data) +{ + struct mbg_tm_chip *chip = data; + int ret, val; + + scoped_guard(mutex, &chip->lock) { + ret = regmap_read(chip->map, + chip->base + MBG_TEMP_MON2_FAULT_STATUS, &val); + if (ret < 0) + return IRQ_HANDLED; + } + + if ((val & MON_FAULT_STATUS_MASK) & MON_FAULT_STATUS_LVL1) { + if ((val & MON_POLARITY_STATUS_MASK) & MON_POLARITY_STATUS_UPR) { + chip->last_thres_crossed = true; + thermal_zone_device_update(chip->tz_dev, + THERMAL_TRIP_VIOLATED); + dev_dbg(chip->dev, "Notifying Thermal, fault status=%d\n", val); + } else { + dev_dbg(chip->dev, "Lvl1 upr threshold not violated, ignoring interrupt\n"); + } + } + + return IRQ_HANDLED; +} + +static int mbg_tm_probe(struct platform_device *pdev) +{ + struct mbg_tm_chip *chip; + struct device_node *node = pdev->dev.of_node; + u32 res; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = &pdev->dev; + + mutex_init(&chip->lock); + + chip->map = dev_get_regmap(pdev->dev.parent, NULL); + if (!chip->map) + return -ENXIO; + + ret = device_property_read_u32(chip->dev, "reg", &res); + if (ret < 0) + return ret; + + chip->base = res; + + chip->irq = platform_get_irq(pdev, 0); + if (chip->irq < 0) + return chip->irq; + + chip->adc = devm_iio_channel_get(&pdev->dev, "thermal"); + if (IS_ERR(chip->adc)) + return dev_err_probe(&pdev->dev, PTR_ERR(chip->adc), + "failed to get adc channel\n"); + + chip->tz_dev = devm_thermal_of_zone_register(&pdev->dev, 0, + chip, &mbg_tm_ops); + if (IS_ERR(chip->tz_dev)) + return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), + "failed to register sensor\n"); + + return devm_request_threaded_irq(&pdev->dev, chip->irq, NULL, + mbg_tm_isr, IRQF_ONESHOT, node->name, chip); +} + +static const struct of_device_id mbg_tm_match_table[] = { + { .compatible = "qcom,spmi-pm8775-mbg-tm" }, + { } +}; +MODULE_DEVICE_TABLE(of, mbg_tm_match_table); + +static struct platform_driver mbg_tm_driver = { + .driver = { + .name = "qcom-spmi-mbg-tm", + .of_match_table = mbg_tm_match_table, + }, + .probe = mbg_tm_probe, +}; +module_platform_driver(mbg_tm_driver); + +MODULE_DESCRIPTION("PMIC MBG Temperature monitor driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Dec 12 16:11:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya Kakitapalli X-Patchwork-Id: 13905542 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A72A23E6F1; Thu, 12 Dec 2024 16:12:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thu, 12 Dec 2024 16:12:16 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BCGCGv3015206 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:12:16 GMT Received: from hu-skakitap-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 08:12:08 -0800 From: Satya Priya Kakitapalli Date: Thu, 12 Dec 2024 21:41:23 +0530 Subject: [PATCH RFC v2 4/5] arm64: dts: qcom: sa8775p-pmics: Add vadc support on SA8775P Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241212-mbg-v2-support-v2-4-3249a4339b6e@quicinc.com> References: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> In-Reply-To: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> To: "Rafael J. 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Signed-off-by: Satya Priya Kakitapalli --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 94 +++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index 1369c3d43f866de9d8cd5cd4985241b99c0a0454..e87f95e9ba9f59e3f067af0d5565b8e3ed4b37fc 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -1,8 +1,10 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include @@ -105,6 +107,29 @@ pmm8654au_0: pmic@0 { #address-cells = <1>; #size-cells = <0>; + pmm8654au_0_vadc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc-sdam0"; + #thermal-sensor-cells = <1>; + #io-channel-cells = <1>; + + channel@0 { + reg = ; + label = "pmm8654au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "pmm8654au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_0_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -162,6 +187,29 @@ pmm8654au_1: pmic@2 { #address-cells = <1>; #size-cells = <0>; + pmm8654au_1_vadc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc-sdam0"; + #thermal-sensor-cells = <1>; + #io-channel-cells = <1>; + + channel@0 { + reg = ; + label = "pmm8654au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "pmm8654au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_1_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -186,6 +234,29 @@ pmm8654au_2: pmic@4 { #address-cells = <1>; #size-cells = <0>; + pmm8654au_2_vadc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc-sdam0"; + #thermal-sensor-cells = <1>; + #io-channel-cells = <1>; + + channel@0 { + reg = ; + label = "pmm8654au_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "pmm8654au_2_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_2_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -210,6 +281,29 @@ pmm8654au_3: pmic@6 { #address-cells = <1>; #size-cells = <0>; + pmm8654au_3_vadc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "adc-sdam0"; + #thermal-sensor-cells = <1>; + #io-channel-cells = <1>; + + channel@0 { + reg = ; + label = "pmm8654au_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "pmm8654au_3_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_3_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; From patchwork Thu Dec 12 16:11:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya Kakitapalli X-Patchwork-Id: 13905543 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9360323EA7D; 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Thu, 12 Dec 2024 16:12:24 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BCGCNGT026621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 16:12:23 GMT Received: from hu-skakitap-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 08:12:16 -0800 From: Satya Priya Kakitapalli Date: Thu, 12 Dec 2024 21:41:24 +0530 Subject: [PATCH RFC v2 5/5] arm64: dts: qcom: sa8775p-pmics: Add support for MBG TM Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241212-mbg-v2-support-v2-5-3249a4339b6e@quicinc.com> References: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> In-Reply-To: <20241212-mbg-v2-support-v2-0-3249a4339b6e@quicinc.com> To: "Rafael J. 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Signed-off-by: Satya Priya Kakitapalli --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 116 ++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index e87f95e9ba9f59e3f067af0d5565b8e3ed4b37fc..eade5784f18629dc9f7ebf0257551bf96bea9a4c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -89,6 +89,58 @@ trip1 { }; }; }; + + pm8775-mbg0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_0_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_1_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_2_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pm8775-mbg3-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmm8654au_3_mbg_temp>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; }; reboot-mode { @@ -181,6 +233,22 @@ reboot_reason: reboot-reason@48 { }; }; + pmm8654au_sail_0: pmic@1 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_0_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,spmi-pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_0_vadc PM8775_ADC5_GEN3_DIE_TEMP(0)>; + io-channel-names = "thermal"; + interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8654au_1: pmic@2 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x2 SPMI_USID>; @@ -228,6 +296,22 @@ pmm8654au_1_gpios: gpio@8800 { }; }; + pmm8654au_sail_1: pmic@3 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_1_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,spmi-pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_1_vadc PM8775_ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; + interrupts = <0x3 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8654au_2: pmic@4 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x4 SPMI_USID>; @@ -275,6 +359,22 @@ pmm8654au_2_gpios: gpio@8800 { }; }; + pmm8654au_sail_2: pmic@5 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_2_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,spmi-pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_2_vadc PM8775_ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; + interrupts = <0x5 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; + pmm8654au_3: pmic@6 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; reg = <0x6 SPMI_USID>; @@ -321,4 +421,20 @@ pmm8654au_3_gpios: gpio@8800 { #interrupt-cells = <2>; }; }; + + pmm8654au_sail_3: pmic@7 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8654au_3_mbg_temp: temperature-sensor@d700 { + compatible = "qcom,spmi-pm8775-mbg-tm"; + reg = <0xd700>; + io-channels = <&pmm8654au_3_vadc PM8775_ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; + interrupts = <0x7 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + }; + }; };