From patchwork Fri Dec 13 17:38:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907567 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E620F1E47B3; Fri, 13 Dec 2024 17:39:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111558; cv=none; b=CnqW4WUmRbZtwHgaS3OrumsHkwb7fBWOI+vqPB/MbHaxuTOKjyvN3xSy7ykoSNz1cxi8+t8hM4eoaSo0szlrqclkuAYb5lFhGUFSz16xiiIfCqSx31hk6MsMZ2lR6/xF6BxXo4U0u1+3fyOmg0fD303jhAgjKcFuIbI8rAKxcF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111558; c=relaxed/simple; bh=lhNhP45ZTLMQAi2yKYEhHH5b8qx/kJBfcFhCheu4fiw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q2H2sfvRDqKrjL20XfnhKHm799a4vfUseJQ8GwAVaku/PMyYvvNeaqYh+tbD1dOqRAp9+ZsJ4+Jdk8ezgdeNqlKDNQcZlZmNI68srchF0zCLisWobvmgGeo04Z9odh6luf7nAeCnq1F75LAI6tsodzWLJZmgp2srLoa8dm1/Me8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: jEL9vfi3TbetmM6cTJYyrw== X-CSE-MsgGUID: h9lz8ijuSTeYnLO+MqonKw== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="227797724" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:14 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 51D28400514D; Sat, 14 Dec 2024 02:39:08 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H Date: Fri, 13 Dec 2024 17:38:47 +0000 Message-ID: <20241213173901.599226-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical ports in DT using RZV2H_* macros. Add PORT_P* macros based on PFC_P_mn offset. Signed-off-by: Biju Das --- v3: * New patch. --- include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h index c78ed5e5efb7..c70308961dfa 100644 --- a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h @@ -11,13 +11,29 @@ #define RZG2L_PINS_PER_PORT 8 +/* PORT_Px = Offset address of PFC_P_mn - 0x20 */ +#define PORT_P0 0 +#define PORT_P1 1 +#define PORT_P2 2 +#define PORT_P3 3 +#define PORT_P4 4 +#define PORT_P5 5 +#define PORT_P6 6 +#define PORT_P7 7 +#define PORT_P8 8 +#define PORT_P9 9 +#define PORT_PA 10 +#define PORT_PB 11 + /* * Create the pin index from its bank and position numbers and store in * the upper 16 bits the alternate function identifier */ #define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) +#define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(PORT_P##b, p, f) /* Convert a port and pin label to its global pin index */ #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) +#define RZV2H_GPIO(port, pin) RZG2L_GPIO(PORT_P##port, pin) #endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ From patchwork Fri Dec 13 17:38:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907569 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CCCAE17B505; Fri, 13 Dec 2024 17:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111571; cv=none; b=Di07ULobCRo+Hp0eLZ1eMY54OkeQI7ZycFAI3bmz5Ok5JLN1tl+7SA9YCbQNGZLK2Kb6vAO737RoosxgGL5DdoHYWBUpinRI80yMpGuyLqJbRmaBRWanwbJGEbFk46fXeuy1DtG3sEYWrY59DpBuS4JkJiEo0dJTwLltiRh9yPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111571; c=relaxed/simple; bh=n2JhVDjflUMEtHO9FTHZxGaP8ZpXeCDSpDPSjPdaGAw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K/188BnA2evXrnn9mW/AueTI/svK3yotWaC9Hy3yKnql1wsUEmPZPSIMdeFlguHBvz56huqVw5Jp4+SuXv6jnD97QzXqeFxS3INWPMqwLXhG60CHdCJqzGhsSJ4IMSPKIVmNiPIO7K6QQ2roqZDZPM45Va9Vl6/fmDQgG0JXheQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: iUskIyrsTD+s2/9bP7wmoA== X-CSE-MsgGUID: ZnxeHr2IRXOTrJoiY+AkIw== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="231774194" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:27 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0ADFF4009BE2; Sat, 14 Dec 2024 02:39:11 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v3 2/7] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC Date: Fri, 13 Dec 2024 17:38:48 +0000 Message-ID: <20241213173901.599226-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add documentation for the pin controller found on the Renesas RZ/G3E (R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more pins(P00-PS3). Acked-by: Conor Dooley Signed-off-by: Biju Das --- v2->v3: * Updated the macros with hardware indices in the hardware manual. * The changes are trivial, so retained ack tag from Conor. v1->v2: * Fixed the warnings reported by bot. --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 7 +++++-- include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index a1805b6e3f63..768bb3c2b456 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g057-pinctrl # RZ/V2H(P) - items: @@ -125,7 +126,7 @@ additionalProperties: drive-push-pull: true renesas,output-impedance: description: - Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this + Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this property corresponds to register bit values that can be set in the PFC_IOLH_mn register, which adjusts the drive strength value and is pin-dependent. $ref: /schemas/types.yaml#/definitions/uint32 @@ -142,7 +143,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g057-pinctrl + enum: + - renesas,r9a09g047-pinctrl + - renesas,r9a09g057-pinctrl then: properties: resets: diff --git a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h index c70308961dfa..ab6f71d9504d 100644 --- a/include/dt-bindings/pinctrl/rzg2l-pinctrl.h +++ b/include/dt-bindings/pinctrl/rzg2l-pinctrl.h @@ -24,16 +24,35 @@ #define PORT_P9 9 #define PORT_PA 10 #define PORT_PB 11 +#define PORT_PC 12 +#define PORT_PD 13 +#define PORT_PE 14 +#define PORT_PF 15 +#define PORT_PG 16 +#define PORT_PH 17 +#define PORT_PI 18 +#define PORT_PJ 19 +#define PORT_PK 20 +#define PORT_PL 21 +#define PORT_PM 22 +#define PORT_PN 23 +#define PORT_PO 24 +#define PORT_PP 25 +#define PORT_PQ 26 +#define PORT_PR 27 +#define PORT_PS 28 /* * Create the pin index from its bank and position numbers and store in * the upper 16 bits the alternate function identifier */ #define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) +#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(PORT_P##b, p, f) #define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(PORT_P##b, p, f) /* Convert a port and pin label to its global pin index */ #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) +#define RZG3E_GPIO(port, pin) RZG2L_GPIO(PORT_P##port, pin) #define RZV2H_GPIO(port, pin) RZG2L_GPIO(PORT_P##port, pin) #endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ From patchwork Fri Dec 13 17:38:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907570 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1D48C1E5018; Fri, 13 Dec 2024 17:39:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111572; cv=none; b=a/cJEnVCRc4jXNbXqD2BNRDMZqjRvrcEXa7FxN99iaPhNTIgUhazRsTY61bSq1YDdZ6hiVINLfY2dErLg+o7SzcBGHj/7xqTK/K0DULbRuonZO/klqepcQKm9iUlbDFlF4HLskYWKR1xjuo4NiPj3zaTy7d46i7btgOt6HBrmYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111572; c=relaxed/simple; bh=v3EGrAGGDM80tSIv2wUo5naY6BCzldYafsuJC2o4BFc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qV/02/2lhkao5DFuf9OnAZdz2a+aEViyDpfUvMGplIvHIls8cMOj+DhHJjYfhO/GR844K4cWkGnkZmCtPd8mEL1pUi6ceCTUKiy24vmSfMOL0ZokBQSpW9w891vohyYSI1aPbCD2f3FJzy/8h+tGe+ydwGdBDEzk+h3+f6+KK7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: sEK98c/yT1yymOAc+1Ctmw== X-CSE-MsgGUID: wZ528GqrRVGA5Oyj5XazhQ== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="227797735" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3C0454006DF1; Sat, 14 Dec 2024 02:39:15 +0900 (JST) From: Biju Das To: Linus Walleij Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 3/7] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table Date: Fri, 13 Dec 2024 17:38:49 +0000 Message-ID: <20241213173901.599226-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg table with alpha-numeric port names to match with the hardware manual. Signed-off-by: Biju Das --- v3: * New patch. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 1a7be7d7b520..67d776feb42d 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -382,12 +382,12 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, } static const u64 r9a09g057_variable_pin_cfg[] = { - RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), }; #ifdef CONFIG_RISCV From patchwork Fri Dec 13 17:38:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907571 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BCCAD17B505; Fri, 13 Dec 2024 17:39:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111574; cv=none; b=dfNf5z3ng+J56zSIErKPVFg1PecjMlQmc3kZ92/m9xWiIesbTxzZ7GQH5bMj3FZ6LC0lT8AyZYtuy6prJcU7qIuWEu2SDU0gNz0vzXuyLELUaZ24Da20Lf+FvjsVSCoXde6dJzyMvILz3TOSP/89XeZNYdKaoVbtxb9VV2+qzKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111574; c=relaxed/simple; bh=CjCmZBmNLqXF9l6SabDGRULfRVIhHaPzM7BYTEJqFrQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aN9IhZ2elgPaIHJWWaP/8vyDowbxcir/J0Ps1CsW5x5W8E7cJ2F9CSNPnZVPgH5qDIu21v5VwqssYIimpROqXQcOZr9frczIDLcx/1ioH+AddYuaU9RG4QXlR/lQmTUGI+9a+N+QmD+cqZIbMM5f4zTDv+8sIfRA8DKNmOpdqEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ReSZc+GBSACs14fK6m0NUA== X-CSE-MsgGUID: LKRl6F/WQ1Gv23jPvqFgqg== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="231774199" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D6F8A4004BB9; Sat, 14 Dec 2024 02:39:18 +0900 (JST) From: Biju Das To: Linus Walleij Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 4/7] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC Date: Fri, 13 Dec 2024 17:38:50 +0000 Message-ID: <20241213173901.599226-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pinctrl driver support for RZ/G3E SoC. Signed-off-by: Biju Das --- v2->v3: * Replaced RZG3E_* macro with generic PORT_* macro. * Added ports based on hardware indices. * Replaced macros WDTUDF_CA->WDTUDFCA and WDTUDF_CM->WDTUDFCM. * Replaced macro QSD0_*->SD0*. v1->v2: * No change. --- drivers/pinctrl/renesas/Kconfig | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 172 ++++++++++++++++++++++++ 2 files changed, 173 insertions(+) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 7f3f41c7fe54..3c18d908b21e 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -41,6 +41,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0 select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_RZV2M if ARCH_R9A09G011 + select PINCTRL_RZG2L if ARCH_R9A09G047 select PINCTRL_RZG2L if ARCH_R9A09G057 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 67d776feb42d..5870ddbe78f9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -381,6 +381,44 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +static const u64 r9a09g047_variable_pin_cfg[] = { + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 1, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PA, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 1, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PD, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PG, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PH, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PJ, 1, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PJ, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PJ, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PJ, 4, RZV2H_MPXED_PIN_FUNCS), +}; + static const u64 r9a09g057_variable_pin_cfg[] = { RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 0, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(PORT_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), @@ -1962,6 +2000,73 @@ static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ }; +static const char * const rzg3e_gpio_names[] = { + "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", + "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", + "PI0", "PI1", "PI2", "PI3", "PI4", "PI5", "PI6", "PI7", + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", + "PN0", "PN1", "PN2", "PN3", "PN4", "PN5", "PN6", "PN7", + "PO0", "PO1", "PO2", "PO3", "PO4", "PO5", "PO6", "PO7", + "PP0", "PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", + "PQ0", "PQ1", "PQ2", "PQ3", "PQ4", "PQ5", "PQ6", "PQ7", + "PR0", "PR1", "PR2", "PR3", "PR4", "PR5", "PR6", "PR7", + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", +}; + +static const u64 r9a09g047_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ + RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS | + PIN_CFG_ELC), /* P1 */ + RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | + PIN_CFG_NOD), /* P2 */ + RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ + RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ + RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ + RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS | + PIN_CFG_ELC), /* P7 */ + RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ + RZG2L_GPIO_PORT_PACK(0, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ + RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */ + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ + RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */ + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ + RZG2L_GPIO_PORT_PACK(0, 0x32, RZV2H_MPXED_PIN_FUNCS), /* PI */ + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ + RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ + RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */ + RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ + RZG2L_GPIO_PORT_PACK(0, 0x37, RZV2H_MPXED_PIN_FUNCS), /* PN */ + RZG2L_GPIO_PORT_PACK(0, 0x38, RZV2H_MPXED_PIN_FUNCS), /* PO */ + RZG2L_GPIO_PORT_PACK(0, 0x39, RZV2H_MPXED_PIN_FUNCS), /* PP */ + RZG2L_GPIO_PORT_PACK(0, 0x3a, RZV2H_MPXED_PIN_FUNCS), /* PQ */ + RZG2L_GPIO_PORT_PACK(0, 0x3b, RZV2H_MPXED_PIN_FUNCS), /* PR */ + RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ +}; + static const char * const rzv2h_gpio_names[] = { "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", @@ -2252,6 +2357,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, }; +static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { + { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, + { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, + { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; @@ -2762,6 +2904,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg3e_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzv2h_gpio_names)); @@ -3160,6 +3305,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; +static struct rzg2l_pinctrl_data r9a09g047_data = { + .port_pins = rzg3e_gpio_names, + .port_pin_configs = r9a09g047_gpio_configs, + .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs), + .dedicated_pins = rzg3e_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins), + .hwcfg = &rzv2h_hwcfg, + .variable_pin_cfg = r9a09g047_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg), + .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), + .custom_params = renesas_rzv2h_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = renesas_rzv2h_conf_items, +#endif + .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, + .pmc_writeb = &rzv2h_pmc_writeb, + .oen_read = &rzv2h_oen_read, + .oen_write = &rzv2h_oen_write, + .hw_to_bias_param = &rzv2h_hw_to_bias_param, + .bias_param_to_hw = &rzv2h_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g057_data = { .port_pins = rzv2h_gpio_names, .port_pin_configs = r9a09g057_gpio_configs, @@ -3196,6 +3364,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a08g045-pinctrl", .data = &r9a08g045_data, }, + { + .compatible = "renesas,r9a09g047-pinctrl", + .data = &r9a09g047_data, + }, { .compatible = "renesas,r9a09g057-pinctrl", .data = &r9a09g057_data, From patchwork Fri Dec 13 17:38:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907572 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E1331E5018; Fri, 13 Dec 2024 17:39:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d="scan'208";a="227797737" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C2E00400514D; Sat, 14 Dec 2024 02:39:21 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 5/7] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Replace RZG2L macros Date: Fri, 13 Dec 2024 17:38:51 +0000 Message-ID: <20241213173901.599226-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace RZG2L_* macros with RZV2H_* macros, so that we can define port names in alpha-numeric. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v3: * New patch. --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 34 +++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 4703da8e9cff..182191a2c5ca 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -56,7 +56,7 @@ reg_3p3v: regulator1 { vqmmc_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; regulator-name = "SDHI1 VccQ"; - gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; + gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios-states = <0>; @@ -158,38 +158,38 @@ &ostm7 { &pinctrl { i2c0_pins: i2c0 { - pinmux = , /* I2C0_SDA */ - ; /* I2C0_SCL */ + pinmux = , /* I2C0_SDA */ + ; /* I2C0_SCL */ }; i2c1_pins: i2c1 { - pinmux = , /* I2C1_SDA */ - ; /* I2C1_SCL */ + pinmux = , /* I2C1_SDA */ + ; /* I2C1_SCL */ }; i2c2_pins: i2c2 { - pinmux = , /* I2C2_SDA */ - ; /* I2C2_SCL */ + pinmux = , /* I2C2_SDA */ + ; /* I2C2_SCL */ }; i2c3_pins: i2c3 { - pinmux = , /* I2C3_SDA */ - ; /* I2C3_SCL */ + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ }; i2c6_pins: i2c6 { - pinmux = , /* I2C6_SDA */ - ; /* I2C6_SCL */ + pinmux = , /* I2C6_SDA */ + ; /* I2C6_SCL */ }; i2c7_pins: i2c7 { - pinmux = , /* I2C7_SDA */ - ; /* I2C7_SCL */ + pinmux = , /* I2C7_SDA */ + ; /* I2C7_SCL */ }; i2c8_pins: i2c8 { - pinmux = , /* I2C8_SDA */ - ; /* I2C8_SCL */ + pinmux = , /* I2C8_SDA */ + ; /* I2C8_SCL */ }; scif_pins: scif { @@ -199,7 +199,7 @@ scif_pins: scif { sd1-pwr-en-hog { gpio-hog; - gpios = ; + gpios = ; output-high; line-name = "sd1_pwr_en"; }; @@ -219,7 +219,7 @@ sd1_clk { }; sd1_cd { - pinmux = ; /* SD1_CD */ + pinmux = ; /* SD1_CD */ }; }; }; From patchwork Fri Dec 13 17:38:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907573 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 90DE01E5713; Fri, 13 Dec 2024 17:39:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111574; cv=none; b=N3SzUBjSpPEMambEkfnEStH+UaFuzJh+pDXV0JLGOQumEhOhXBKSaQNOLK77pfGJomG+42Y8CO+/RUWZynZRsqffvCaI/6CHhWcqj6a8N9oOuIvmtTeaVzdyCoStpefUJRmSdg2wCKT2/tkWacAWfW7vuMrUrcsOxv1LcheU6BY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111574; c=relaxed/simple; bh=bxFb0855ZpFKiH/50oJC7pVLfu4RpabMlPcyF9/WWko=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kv4f8V2RNcaH5H4S7GJiS3W5AN92agjAMVuxRiDkCcfMbrsxrsSjaps0haRI1Ofu2+Q0sNZUpzvlBeZdXtNYswU7kWSUjA3y0v2zxthj283TFOPXWHSyhdQsV82GZ/IyDx9vbsG5Ar9JigkCZuZba+0cwIZ3tpxv/zcYWhhuLXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 8ywrZXyzSgCdUzr/h4b81A== X-CSE-MsgGUID: mD7gw2jbTrWzlfNF9eJhcw== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="231774201" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3713C4009BF1; Sat, 14 Dec 2024 02:39:24 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 6/7] arm64: dts: renesas: r9a09g047: Add pincontrol node Date: Fri, 13 Dec 2024 17:38:52 +0000 Message-ID: <20241213173901.599226-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Updated gpio range from 176->232 to match the port number based on harware indices. * Added Rb tag from Geert. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 39a7cfb3095b..15711f9b6038 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -131,6 +131,19 @@ soc: soc { #size-cells = <2>; ranges; + pinctrl: pinctrl@10410000 { + compatible = "renesas,r9a09g047-pinctrl"; + reg = <0 0x10410000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 232>; + #interrupt-cells = <2>; + interrupt-controller; + power-domains = <&cpg>; + resets = <&cpg 0xa5>, <&cpg 0xa6>; + }; + cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>; From patchwork Fri Dec 13 17:38:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13907574 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CBA9F17B505; Fri, 13 Dec 2024 17:39:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111582; cv=none; b=Pp/3LbpV+B7hUUrGVWdRNN5ep6/Uzs+WYYnBFpu48AQafW3kisRm3/6jtyZiEa78SAsdS6lmm5G3F2LKek4XSW9IzlytSmtUQRGlj3Kq0SvVxmvKTDTFdouEupw/4BRvS8uUaoI+L4vcuxyWKCYG39wSCJWk1d6jKQnN9dBFGiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734111582; c=relaxed/simple; bh=q3Kjt5+AQFkXshyqGkJMlt2HCcswIEexmWXNmMysYuw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Iw13VqC9RwCkPQilD7HidC0YItq0z8i1dnjaW/e1wo1yWwkZE4NTQx/MtqHbTnYlV4x+4EPno6ODOHvp9LHav2aY8wQS3RceqGldjOj7k2qhHxVJPf0ctJVzcBn1xxhp1DCc0X3G18bWxmCHMrmM6TC1yeoa5MZAbfG+uIBPZg4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 2AF/s2PjScmK6aHVfAoVbA== X-CSE-MsgGUID: YLfpzA6NTC+CO9WLmNQq8Q== X-IronPort-AV: E=Sophos;i="6.12,231,1728918000"; d="scan'208";a="231774204" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2024 02:39:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.203]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9E4614009F63; Sat, 14 Dec 2024 02:39:28 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 7/7] arm64: dts: renesas: r9a09g047: Add scif pincontrol Date: Fri, 13 Dec 2024 17:38:53 +0000 Message-ID: <20241213173901.599226-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> References: <20241213173901.599226-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add device node for scif pincontrol. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2->v3: * Added Rb tag from Geert. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index d4d61bd03969..e33e1e80c6d5 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include "r9a09g047e57.dtsi" #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" @@ -16,3 +17,15 @@ / { compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; }; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance = <1>; + }; +}; + +&scif0 { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; +};