From patchwork Mon Dec 16 19:53:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910267 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 836F520765F; Mon, 16 Dec 2024 19:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378828; cv=none; b=XGsOSzigcT97KGpNYjRQD22I7/Hd4Y5sugw4a9XXahl1W92oTLTms7OmGU8mphKnqPrsTfYZwbjzxfAloQ0NEgOQSMKZvok/FyoA9600aHj2DRiutDkPR+bLVvLjBGaPbshFCHDdv9Zmdw770CeR3fCfKYQfUETLNy143bU+k+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378828; c=relaxed/simple; bh=TDSQNZcr8os0qRW79wXqC62W3vnvQSRbJd0a3V8vOlU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GFuaGWv8Dir5GHhAr1H5Ckb/4UGpGbI2rurGyaA1cH1Y1eGzNAbRsDL3UMDcFP/B2fCL5JS3e2Pp5N4/gI9LnNZdv3hKaOB+iaaZ9SVyy+j4iRdBU1InzphrH5Dy2jX8tYhMc77K+2E+2jBY/Y5GovPNH4w5CwxjhCtY5MOf+dA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: Xfyo3feqQhmq0Py2ILNUEA== X-CSE-MsgGUID: DKwQVNqrSbO1dkjUeCUgQg== X-IronPort-AV: E=Sophos;i="6.12,239,1728918000"; d="scan'208";a="228014620" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:43 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id A6F8E406320F; Tue, 17 Dec 2024 04:53:31 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 1/7] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H Date: Mon, 16 Dec 2024 19:53:11 +0000 Message-ID: <20241216195325.164212-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 RZ/V2H has ports P0-P9 and PA-PB. Add support for defining alpha-numerical ports in DT using RZV2H_* macros. Signed-off-by: Biju Das --- v3->v4: * Added new header file with separate RZV2H_P* definitions. v3: * New patch. --- .../pinctrl/renesas,r9a09g057-pinctrl.h | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h new file mode 100644 index 000000000000..9008a7e71609 --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/V2H family pinctrl bindings. + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZV2H_PINCTRL_H +#define __DT_BINDINGS_RZV2H_PINCTRL_H + +#include + +/* RZV2H_Px = Offset address of PFC_P_mn - 0x20 */ +#define RZV2H_P0 0 +#define RZV2H_P1 1 +#define RZV2H_P2 2 +#define RZV2H_P3 3 +#define RZV2H_P4 4 +#define RZV2H_P5 5 +#define RZV2H_P6 6 +#define RZV2H_P7 7 +#define RZV2H_P8 8 +#define RZV2H_P9 9 +#define RZV2H_PA 10 +#define RZV2H_PB 11 + +#define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2H_P##b, p, f) +#define RZV2H_GPIO(port, pin) RZG2L_GPIO(RZV2H_P##port, pin) + +#endif /* __DT_BINDINGS_RZV2H_PINCTRL_H */ From patchwork Mon Dec 16 19:53:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910269 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3797920C48E; Mon, 16 Dec 2024 19:53:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378832; cv=none; b=SVP9t6xqF1PsQeMiUVYRmEJX2PYzwcrrgm0eX4yxdmYIBy8HHSXEA+fyvRdF811zZUqJ8D+9NN294nw5g2Ls2Qj4jqGb8Qt/E7yf7Br6dsMwPiHcWhxfgXlbV7KfNrgDlHXTTl0ZYyZTkC0F3kes6dw3gpyKjxcmioaW6cONAH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378832; c=relaxed/simple; bh=IBmblwPuoL0vvjltFdrHvH4ub1EGDEoc2g7FtC0d+xA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A5Rz2BPAsvgKCTzi2WllKxH1C/twapW6astpvvNWy2RBSS2yPlJSWMZwxaU25vanblVF82fl1dtEciFc3JdNL9VWp/dO0odIUsxCW8x7jGet0huYjWW09DkKo21iwyUohKivWI4ko/ha0iVwD1MtCQNc/cK2iYQAGgg9fbEUJfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: J3FiKQ5gSPyuBdd+GSkSaw== X-CSE-MsgGUID: Gnyd55mRTFGw+eUZISuiOA== X-IronPort-AV: E=Sophos;i="6.12,239,1728918000"; d="scan'208";a="231992156" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:48 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5CE1B40638CF; Tue, 17 Dec 2024 04:53:35 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v4 2/7] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC Date: Mon, 16 Dec 2024 19:53:12 +0000 Message-ID: <20241216195325.164212-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add documentation for the pin controller found on the Renesas RZ/G3E (R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more pins(P00-PS3). Acked-by: Conor Dooley Signed-off-by: Biju Das --- v3->v4: * Dropped ack tag from Conor as there is separate file for RZG3E_P* definitions v2->v3: * Updated the macros with hardware indices in the hardware manual. * The changes are trivial, so retained ack tag from Conor. v1->v2: * Fixed the warnings reported by bot. --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 7 +++- .../pinctrl/renesas,r9a09g047-pinctrl.h | 41 +++++++++++++++++++ 2 files changed, 46 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index a1805b6e3f63..768bb3c2b456 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g057-pinctrl # RZ/V2H(P) - items: @@ -125,7 +126,7 @@ additionalProperties: drive-push-pull: true renesas,output-impedance: description: - Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this + Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this property corresponds to register bit values that can be set in the PFC_IOLH_mn register, which adjusts the drive strength value and is pin-dependent. $ref: /schemas/types.yaml#/definitions/uint32 @@ -142,7 +143,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g057-pinctrl + enum: + - renesas,r9a09g047-pinctrl + - renesas,r9a09g057-pinctrl then: properties: resets: diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h new file mode 100644 index 000000000000..b2cda1a44b0a --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3E family pinctrl bindings. + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZG3E_PINCTRL_H +#define __DT_BINDINGS_RZG3E_PINCTRL_H + +#include + +/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */ +#define RZG3E_P0 0 +#define RZG3E_P1 1 +#define RZG3E_P2 2 +#define RZG3E_P3 3 +#define RZG3E_P4 4 +#define RZG3E_P5 5 +#define RZG3E_P6 6 +#define RZG3E_P7 7 +#define RZG3E_P8 8 +#define RZG3E_PA 10 +#define RZG3E_PB 11 +#define RZG3E_PC 12 +#define RZG3E_PD 13 +#define RZG3E_PE 14 +#define RZG3E_PF 15 +#define RZG3E_PG 16 +#define RZG3E_PH 17 +#define RZG3E_PJ 19 +#define RZG3E_PK 20 +#define RZG3E_PL 21 +#define RZG3E_PM 22 +#define RZG3E_PS 28 + +#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f) +#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin) + +#endif /* __DT_BINDINGS_RZG3E_PINCTRL_H */ From patchwork Mon Dec 16 19:53:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910268 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2B4DD20765F; Mon, 16 Dec 2024 19:53:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378831; cv=none; b=a2m1KSqAgqf0PfZUnqm0pcw8Lwj03EHNsuRg4Ih7Ga/B8weMTpguaqpj3lLNVn5AnZnkhyKQgEtxtB3/xX+Oc+YuvR1TmFChFgaZmG7a829aOmX5NoxFiKFQHo9WPGubKTRBuFCGdj2JXKGEABoRb/PClDKUkUtcz/HTb20iFAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378831; c=relaxed/simple; bh=/d5Hz7MZ25rEoSZPJMN/gZrUxbL4u37m3x35qURLbnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R3aZTwkfO4SjPj/FEt2NolNwD4t+kG3MdslFKOEGEtxFbE3n+FQzyVMwwIBUYdekquRFyS8cZyv2NFjp0Xcb6PxCPI1NWru+Vbd5EAjWBr4+Wmg+lvhCQYpnFm55m6Rk2oDO23acK9PBh2CIewGTpT4N3A1kG8TUpxngc4M0tJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ZqEcFmsdRaKRWKfB8RNm4w== X-CSE-MsgGUID: MO5/WkEbSyu/31u6oc6L4A== X-IronPort-AV: E=Sophos;i="6.12,239,1728918000"; d="scan'208";a="228014624" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:48 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8E73840638D0; Tue, 17 Dec 2024 04:53:39 +0900 (JST) From: Biju Das To: Linus Walleij Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 3/7] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table Date: Mon, 16 Dec 2024 19:53:13 +0000 Message-ID: <20241216195325.164212-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently r9a09g057_variable_pin_cfg table uses port 11 instead of port PB as mentioned in the hardware manual. Update the r9a09g057_variable_pin_cfg table with alpha-numeric port names to match with the hardware manual. Signed-off-by: Biju Das --- v3->v4: * Included header file renesas,r9a09g057-pinctrl.h * Updated r9a09g057_variable_pin_cfg table replacing PORT_PB->RZV2H_PB macro. v3: * New patch. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 1a7be7d7b520..b5af69af937a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -26,6 +26,7 @@ #include #include +#include #include #include "../core.h" @@ -382,12 +383,12 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, } static const u64 r9a09g057_variable_pin_cfg[] = { - RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), }; #ifdef CONFIG_RISCV From patchwork Mon Dec 16 19:53:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910271 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A6D4820CCC5; Mon, 16 Dec 2024 19:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378837; cv=none; b=dXGbdMxTd8+y3sRTmyqETEJhQy8LBlDkHhXtEg7jk1rzt2Q9Zx6Z/8DAklbZtrXqCRXcIxDcg2ReAuCYjSrAN0Mm3iaqLGMoPCjmYwcY+UQ6GZeYlJtjdufZ+R1dgxg5bD9vXL0kaOf3HVEgRGywP+kV+IUz1E/BgANjRxLArSs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378837; c=relaxed/simple; bh=Gcfk+cRTipbikvpFtkvWpr354Yk+xRTivvj5dh11cRE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WulOyr3ftQLYimLzDRCNXcstL1zLQSsi7XltopySnSJHZHuWuT2DRXPoHC1n454x3sZ6+E5xqxdR1NY8HlgICfze0TWmJeuMG5zOCr8Tv338jwJqJlwNrY5/m+2W1ruVUzbU8zfDAKjBdZSfybOW9mtp9arHLQ63ebm89QCqtGQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: qgLGwRAyQy2pz1EY/iNQoQ== X-CSE-MsgGUID: Dl5wko/9RluTy0RSIc6xIw== X-IronPort-AV: E=Sophos;i="6.12,239,1728918000"; d="scan'208";a="231992160" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:54 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 331FF40638D1; Tue, 17 Dec 2024 04:53:41 +0900 (JST) From: Biju Das To: Linus Walleij Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 4/7] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC Date: Mon, 16 Dec 2024 19:53:14 +0000 Message-ID: <20241216195325.164212-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pinctrl driver support for RZ/G3E SoC. Signed-off-by: Biju Das --- v4->v4: * Included header file renesas,r9a09g047-pinctrl.h * Replaced macros PORT_P*->RZG3E_P* * Updated rzg3e_gpio_names table with NULL port names for ports corresponding to unsupported hardware indices. * Updated r9a09g047_gpio_configs table with NULL value for ports corresponding to unsupported hardware indices. v2->v3: * Replaced RZG3E_* macro with generic PORT_* macro. * Added ports based on hardware indices. * Replaced macros WDTUDF_CA->WDTUDFCA and WDTUDF_CM->WDTUDFCM. * Replaced macro QSD0_*->SD0*. v1->v2: * No change. --- drivers/pinctrl/renesas/Kconfig | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 173 ++++++++++++++++++++++++ 2 files changed, 174 insertions(+) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 7f3f41c7fe54..3c18d908b21e 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -41,6 +41,7 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0 select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_RZV2M if ARCH_R9A09G011 + select PINCTRL_RZG2L if ARCH_R9A09G047 select PINCTRL_RZG2L if ARCH_R9A09G057 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b5af69af937a..4fae24453c11 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -382,6 +383,44 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +static const u64 r9a09g047_variable_pin_cfg[] = { + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), +}; + static const u64 r9a09g057_variable_pin_cfg[] = { RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), @@ -1963,6 +2002,73 @@ static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ }; +static const char * const rzg3e_gpio_names[] = { + "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", + "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "", "", "", "", "", "", "", "", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", + "", "", "", "", "", "", "", "", + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", +}; + +static const u64 r9a09g047_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ + RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS | + PIN_CFG_ELC), /* P1 */ + RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | + PIN_CFG_NOD), /* P2 */ + RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ + RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ + RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ + RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS | + PIN_CFG_ELC), /* P7 */ + RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ + RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */ + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ + RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */ + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ + RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ + RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */ + RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ +}; + static const char * const rzv2h_gpio_names[] = { "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", @@ -2253,6 +2359,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = { { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, }; +static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { + { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, + { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, + { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, + { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, + (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; @@ -2763,6 +2906,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg3e_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzv2h_gpio_names)); @@ -3161,6 +3307,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; +static struct rzg2l_pinctrl_data r9a09g047_data = { + .port_pins = rzg3e_gpio_names, + .port_pin_configs = r9a09g047_gpio_configs, + .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs), + .dedicated_pins = rzg3e_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins), + .hwcfg = &rzv2h_hwcfg, + .variable_pin_cfg = r9a09g047_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg), + .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), + .custom_params = renesas_rzv2h_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = renesas_rzv2h_conf_items, +#endif + .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, + .pmc_writeb = &rzv2h_pmc_writeb, + .oen_read = &rzv2h_oen_read, + .oen_write = &rzv2h_oen_write, + .hw_to_bias_param = &rzv2h_hw_to_bias_param, + .bias_param_to_hw = &rzv2h_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g057_data = { .port_pins = rzv2h_gpio_names, .port_pin_configs = r9a09g057_gpio_configs, @@ -3197,6 +3366,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a08g045-pinctrl", .data = &r9a08g045_data, }, + { + .compatible = "renesas,r9a09g047-pinctrl", + .data = &r9a09g047_data, + }, { .compatible = "renesas,r9a09g057-pinctrl", .data = &r9a09g057_data, From patchwork Mon Dec 16 19:53:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910273 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 58E6720CCC5; Mon, 16 Dec 2024 19:53:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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d="scan'208";a="231992163" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:57 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1B11D406320F; Tue, 17 Dec 2024 04:53:44 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 5/7] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Replace RZG2L macros Date: Mon, 16 Dec 2024 19:53:15 +0000 Message-ID: <20241216195325.164212-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace RZG2L_* macros with RZV2H_* macros, so that we can define port names in alpha-numeric. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Replaced rzg2l-pinctrl.h->renesas,r9a09g057-pinctrl.h header file. * Added Rb tag from Geert. v3: * New patch. --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 4703da8e9cff..0b705c987b6c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include #include "r9a09g057.dtsi" @@ -56,7 +56,7 @@ reg_3p3v: regulator1 { vqmmc_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; regulator-name = "SDHI1 VccQ"; - gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; + gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; gpios-states = <0>; @@ -158,38 +158,38 @@ &ostm7 { &pinctrl { i2c0_pins: i2c0 { - pinmux = , /* I2C0_SDA */ - ; /* I2C0_SCL */ + pinmux = , /* I2C0_SDA */ + ; /* I2C0_SCL */ }; i2c1_pins: i2c1 { - pinmux = , /* I2C1_SDA */ - ; /* I2C1_SCL */ + pinmux = , /* I2C1_SDA */ + ; /* I2C1_SCL */ }; i2c2_pins: i2c2 { - pinmux = , /* I2C2_SDA */ - ; /* I2C2_SCL */ + pinmux = , /* I2C2_SDA */ + ; /* I2C2_SCL */ }; i2c3_pins: i2c3 { - pinmux = , /* I2C3_SDA */ - ; /* I2C3_SCL */ + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ }; i2c6_pins: i2c6 { - pinmux = , /* I2C6_SDA */ - ; /* I2C6_SCL */ + pinmux = , /* I2C6_SDA */ + ; /* I2C6_SCL */ }; i2c7_pins: i2c7 { - pinmux = , /* I2C7_SDA */ - ; /* I2C7_SCL */ + pinmux = , /* I2C7_SDA */ + ; /* I2C7_SCL */ }; i2c8_pins: i2c8 { - pinmux = , /* I2C8_SDA */ - ; /* I2C8_SCL */ + pinmux = , /* I2C8_SDA */ + ; /* I2C8_SCL */ }; scif_pins: scif { @@ -199,7 +199,7 @@ scif_pins: scif { sd1-pwr-en-hog { gpio-hog; - gpios = ; + gpios = ; output-high; line-name = "sd1_pwr_en"; }; @@ -219,7 +219,7 @@ sd1_clk { }; sd1_cd { - pinmux = ; /* SD1_CD */ + pinmux = ; /* SD1_CD */ }; }; }; From patchwork Mon Dec 16 19:53:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910272 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD3AA20C48E; Mon, 16 Dec 2024 19:53:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378839; cv=none; b=mNJQo1JcWlPcCjT4VMJLgxqEnuZS0kZD8lGSrEX0PRqCcq/rdAqkduB9RRTnBFuKVMsbeZCYkpIQeVpcxZJ6CCNMk/ZZVRI5ci79OVX/f32COlLEzDT/IoESCXVJo9+qfHdat7/HfPeodFK7lER1HXIq2t7xFByrkJw4vYkk3iY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378839; c=relaxed/simple; bh=l3SKUf0RRPZ3LhobSN4pIoLTWc57kHCXHqkdAciGug0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PDkSjiT98IEiVqaR6nlmVJwdK2HfzTsodnIAwLkPY4eawg6UNUIls37d12+eEU5VIc1jiIB4ZMOFmwqgrzVPMgMPbfgx2kOi0VNH0lMbgdWiREXEd3HeyAcU1CMy/65ZPBodrDT9bNyFeTTiW859nudxp6MDhCQqQvu3D3UwFcM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: UCZ1kcWWR52Q22Q6W/MqFQ== X-CSE-MsgGUID: qy/dkMH6TYeRF/G5Srz5Eg== X-IronPort-AV: E=Sophos;i="6.12,239,1728918000"; d="scan'208";a="228014632" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:57 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 830A140638D2; Tue, 17 Dec 2024 04:53:48 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 6/7] arm64: dts: renesas: r9a09g047: Add pincontrol node Date: Mon, 16 Dec 2024 19:53:16 +0000 Message-ID: <20241216195325.164212-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * No Change. v2->v3: * Updated gpio range from 176->232 to match the port number based on harware indices. * Added Rb tag from Geert. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 39a7cfb3095b..15711f9b6038 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -131,6 +131,19 @@ soc: soc { #size-cells = <2>; ranges; + pinctrl: pinctrl@10410000 { + compatible = "renesas,r9a09g047-pinctrl"; + reg = <0 0x10410000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 232>; + #interrupt-cells = <2>; + interrupt-controller; + power-domains = <&cpg>; + resets = <&cpg 0xa5>, <&cpg 0xa6>; + }; + cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>; From patchwork Mon Dec 16 19:53:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13910270 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 29C7720CCDA; Mon, 16 Dec 2024 19:53:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378837; cv=none; b=SuhD8SwiWUh257MKtyCeM9mJ6qHlGKbzOlhp+tlyVXPRXQ9Zmh/Gjpuoh64tm0ADalrQRsNFg9bJ4w21SM9JArDcBpidELNf4Chl+FPPruEQeMELHuAwcKIXdjFVHEQE6Hli7U5VZwG4SqeB5ps4WkrXfBtrF49LON3nO2sKjB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734378837; c=relaxed/simple; bh=pHeIEhZAHw7VKa55xxkHFt9tcdb7RAb0E4BBWmx2CPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hZJAPgfZeD50myZC/cnUynr2qVZ+5w43J2DF7d/nuIFuhEsQVUrOtp/1TDH8re9/5ue+mkvxUcts8tLnX06hKMPZFZq9aRyPql8VSaKCNwyQC0FhOR342jwx+4FQWK3CwnE8r99QTWmXgh+fHO4Rm9OfVqwIKaSv/1rVrQZcZgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: HbUEFUjxRAuSpREfU8r66w== X-CSE-MsgGUID: tOFAO9RwTliMoeIRQTUpOQ== X-IronPort-AV: E=Sophos;i="6.12,239,1728918000"; d="scan'208";a="228014628" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 17 Dec 2024 04:53:54 +0900 Received: from localhost.localdomain (unknown [10.226.93.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id EF80240638D0; Tue, 17 Dec 2024 04:53:51 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v4 7/7] arm64: dts: renesas: r9a09g047: Add scif pincontrol Date: Mon, 16 Dec 2024 19:53:17 +0000 Message-ID: <20241216195325.164212-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> References: <20241216195325.164212-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add device node for scif pincontrol. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v3->v4: * Replaced rzg2l-pinctrl.h->renesas,r9a09g047-pinctrl.h header file. * Retained Rb tag. v2->v3: * Added Rb tag from Geert. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index d4d61bd03969..c063d47e2952 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include "r9a09g047e57.dtsi" #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" @@ -16,3 +17,15 @@ / { compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; }; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance = <1>; + }; +}; + +&scif0 { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; +};