From patchwork Tue Dec 17 06:48:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE0F4E7716A for ; Tue, 17 Dec 2024 07:01:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Tue, 17 Dec 2024 06:49:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 43h33kx8y4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:00 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4BH6n0Yb014877; Tue, 17 Dec 2024 06:49:00 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-wasimn-hyd.qualcomm.com [10.147.246.180]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4BH6mx2E014866 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:00 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3944840) id EE1124D9; Tue, 17 Dec 2024 12:18:58 +0530 (+0530) From: Wasim Nazir To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@quicinc.com, Wasim Nazir Subject: [PATCH v4 1/7] dt-bindings: arm: qcom,ids: add SoC ID for QCS9075 Date: Tue, 17 Dec 2024 12:18:50 +0530 Message-ID: <20241217064856.2772305-2-quic_wasimn@quicinc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241217064856.2772305-1-quic_wasimn@quicinc.com> References: <20241217064856.2772305-1-quic_wasimn@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YoS6X7iIYxFi0ijNobwelX9gXXUQjlNg X-Proofpoint-ORIG-GUID: YoS6X7iIYxFi0ijNobwelX9gXXUQjlNg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 impostorscore=0 spamscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 clxscore=1011 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170054 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241216_224911_465424_EEAD6A14 X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the unique ID for Qualcomm QCS9075 SoC. This value is used to differentiate the SoC across qcom targets. Acked-by: Rob Herring (Arm) Signed-off-by: Wasim Nazir --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) -- 2.47.0 diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index e850dc3a1ad3..1b3e0176dcb7 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -284,6 +284,7 @@ #define QCOM_ID_QCS9100 667 #define QCOM_ID_QCS8300 674 #define QCOM_ID_QCS8275 675 +#define QCOM_ID_QCS9075 676 #define QCOM_ID_QCS615 680 /* From patchwork Tue Dec 17 06:48:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0633DE7716A for ; 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Tue, 17 Dec 2024 06:49:03 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4BH6n0oq014906; Tue, 17 Dec 2024 06:49:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 43h33kx8y0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:00 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4BH6n025014873; Tue, 17 Dec 2024 06:49:00 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-wasimn-hyd.qualcomm.com [10.147.246.180]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4BH6mxUt014867 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:00 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3944840) id F20185AB; Tue, 17 Dec 2024 12:18:58 +0530 (+0530) From: Wasim Nazir To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@quicinc.com, Wasim Nazir , Dmitry Baryshkov Subject: [PATCH v4 2/7] soc: qcom: socinfo: add QCS9075 SoC ID Date: Tue, 17 Dec 2024 12:18:51 +0530 Message-ID: <20241217064856.2772305-3-quic_wasimn@quicinc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241217064856.2772305-1-quic_wasimn@quicinc.com> References: <20241217064856.2772305-1-quic_wasimn@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kVO4_xVpEukHpjaCZBqlKPg5nk_9pZM6 X-Proofpoint-ORIG-GUID: kVO4_xVpEukHpjaCZBqlKPg5nk_9pZM6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 impostorscore=0 spamscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 clxscore=1011 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170054 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_064919_672856_749B4170 X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update soc_id table for the Qualcomm QCS9075 SoC to represent qcs9075 machine. Reviewed-by: Dmitry Baryshkov Signed-off-by: Wasim Nazir --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) -- 2.47.0 diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 62fadfe44a09..174210f3467b 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -451,6 +451,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QCS9100) }, { qcom_board_id(QCS8300) }, { qcom_board_id(QCS8275) }, + { qcom_board_id(QCS9075) }, { qcom_board_id(QCS615) }, }; From patchwork Tue Dec 17 06:48:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0AF1E7717F for ; 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QCS9075 is compatible IoT-industrial grade variant of SA8775p SoC. Unlike QCS9100, it doesn't have safety monitoring feature of Safety-Island(SAIL) subsystem, which affects thermal management. Acked-by: Rob Herring (Arm) Signed-off-by: Wasim Nazir --- Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.47.0 diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d394dffe3fba..8cee92a804c4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -57,6 +57,7 @@ description: | qcs8550 qcm2290 qcm6490 + qcs9075 qcs9100 qdu1000 qrb2210 @@ -950,6 +951,14 @@ properties: - qcom,sa8775p-ride-r3 - const: qcom,sa8775p + - items: + - enum: + - qcom,qcs9075-rb8 + - qcom,qcs9075-ride + - qcom,qcs9075-ride-r3 + - const: qcom,qcs9075 + - const: qcom,sa8775p + - items: - enum: - qcom,qcs9100-ride From patchwork Tue Dec 17 06:48:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF947E7716A for ; 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Tue, 17 Dec 2024 06:49:04 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4BH6n0Gu014908; Tue, 17 Dec 2024 06:49:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 43h33kx8y5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:00 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4BH6n07R014875; Tue, 17 Dec 2024 06:49:00 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-wasimn-hyd.qualcomm.com [10.147.246.180]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4BH6mxeq014864 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:00 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3944840) id 064CE5AD; Tue, 17 Dec 2024 12:18:59 +0530 (+0530) From: Wasim Nazir To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@quicinc.com, Wasim Nazir , Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v4 4/7] arm64: dts: qcom: Add support for QCS9075 RB8 Date: Tue, 17 Dec 2024 12:18:53 +0530 Message-ID: <20241217064856.2772305-5-quic_wasimn@quicinc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241217064856.2772305-1-quic_wasimn@quicinc.com> References: <20241217064856.2772305-1-quic_wasimn@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LPG7SYgwlcL-K20SqRrht-gJh1gel9oJ X-Proofpoint-ORIG-GUID: LPG7SYgwlcL-K20SqRrht-gJh1gel9oJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 mlxscore=0 clxscore=1015 suspectscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170054 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_064919_176738_B8C1D8C5 X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add initial device tree support for the RB8 board based on Qualcomm's QCS9075 SoC. Basic changes are supported for boot to shell. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs9075-rb8.dts | 281 +++++++++++++++++++++++ 2 files changed, 282 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-rb8.dts -- 2.47.0 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4686f2a8ddd8..78613a1bd34a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs9075-rb8.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts new file mode 100644 index 000000000000..ecaa383b6508 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include +#include + +#include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Robotics RB8"; + compatible = "qcom,qcs9075-rb8", "qcom,qcs9075", "qcom,sa8775p"; + + aliases { + serial0 = &uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = ; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting an over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = ; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = ; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&tlmm { + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; From patchwork Tue Dec 17 06:48:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE657E7717F for ; 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Tue, 17 Dec 2024 06:49:04 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4BH6n0tv014924; Tue, 17 Dec 2024 06:49:01 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 43h33kx8ys-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:01 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4BH6n0bL014876; Tue, 17 Dec 2024 06:49:01 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-wasimn-hyd.qualcomm.com [10.147.246.180]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4BH6n1Q5014928 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:01 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3944840) id 0A3795AE; Tue, 17 Dec 2024 12:18:59 +0530 (+0530) From: Wasim Nazir To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@quicinc.com, Wasim Nazir Subject: [PATCH v4 5/7] arm64: dts: qcom: Add support for QCS9075 Ride & Ride-r3 Date: Tue, 17 Dec 2024 12:18:54 +0530 Message-ID: <20241217064856.2772305-6-quic_wasimn@quicinc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241217064856.2772305-1-quic_wasimn@quicinc.com> References: <20241217064856.2772305-1-quic_wasimn@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MeMfxgGqj3xJGo61ObBnNAYjBn6vtl8V X-Proofpoint-ORIG-GUID: MeMfxgGqj3xJGo61ObBnNAYjBn6vtl8V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170054 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_064919_986820_9E70A457 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device tree support for QCS9075 Ride & Ride-r3 boards. QCS9075 lacks the safety monitoring features of Safety-Island (SAIL) subsystem which is available in QCS9100, and it affects thermal management. Also, between ride and ride-r3 ethernet phy is different. Ride uses 1G ethernet phy while ride-r3 uses 2.5G ethernet phy. Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts | 46 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs9075-ride.dts | 46 ++++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-ride.dts -- 2.47.0 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 78613a1bd34a..41cb2bbd3472 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -118,6 +118,8 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9075-rb8.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs9075-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs9075-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts new file mode 100644 index 000000000000..d9a8956d3a76 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "sa8775p-ride.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS9075 Ride Rev3"; + compatible = "qcom,qcs9075-ride-r3", "qcom,qcs9075", "qcom,sa8775p"; +}; + +ðernet0 { + phy-mode = "2500base-x"; +}; + +ðernet1 { + phy-mode = "2500base-x"; +}; + +&mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@0 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x0>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts new file mode 100644 index 000000000000..3b524359a72d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; + +#include "sa8775p-ride.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS9075 Ride"; + compatible = "qcom,qcs9075-ride", "qcom,qcs9075", "qcom,sa8775p"; +}; + +ðernet0 { + phy-mode = "sgmii"; +}; + +ðernet1 { + phy-mode = "sgmii"; +}; + +&mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; +}; From patchwork Tue Dec 17 06:48:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94D0BE7716A for ; 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Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) -- 2.47.0 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 76bd7424985a..32911e57e761 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -693,6 +693,7 @@ CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y +CONFIG_CPU_IDLE_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_IMX_SC_THERMAL=m @@ -1595,6 +1596,8 @@ CONFIG_HISI_PMU=y CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m CONFIG_MESON_DDR_PMU=m +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y CONFIG_NVMEM_LAYOUT_SL28_VPD=m CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_ELE=m From patchwork Tue Dec 17 06:48:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wasim Nazir X-Patchwork-Id: 13911309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 793D0E7717F for ; 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Tue, 17 Dec 2024 06:49:05 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4BH6n0Jf014904; Tue, 17 Dec 2024 06:49:01 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 43h33kx8yu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:01 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4BH6n1oR014949; Tue, 17 Dec 2024 06:49:01 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-wasimn-hyd.qualcomm.com [10.147.246.180]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4BH6n1Yr014926 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Dec 2024 06:49:01 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3944840) id 1292E5B0; Tue, 17 Dec 2024 12:18:59 +0530 (+0530) From: Wasim Nazir To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@quicinc.com, Manaf Meethalavalappu Pallikunhi Subject: [PATCH v4 7/7] arm64: dts: qcom: Enable cpu cooling devices for QCS9075 platforms Date: Tue, 17 Dec 2024 12:18:56 +0530 Message-ID: <20241217064856.2772305-8-quic_wasimn@quicinc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241217064856.2772305-1-quic_wasimn@quicinc.com> References: <20241217064856.2772305-1-quic_wasimn@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dSHkelXadJpWJJ5GJ8BhFYwoLPGczhge X-Proofpoint-ORIG-GUID: dSHkelXadJpWJJ5GJ8BhFYwoLPGczhge X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=1 priorityscore=1501 spamscore=0 malwarescore=0 mlxscore=0 clxscore=1015 suspectscore=0 mlxlogscore=840 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412170054 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_064919_971382_7AF350E6 X-CRM114-Status: GOOD ( 17.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manaf Meethalavalappu Pallikunhi In QCS9100 SoC, the safety subsystem monitors all thermal sensors and does corrective action for each subsystem based on sensor violation to comply safety standards. But as QCS9075 is non-safe SoC it requires conventional thermal mitigation to control thermal for different subsystems. The cpu frequency throttling for different cpu tsens is enabled in hardware as first defense for cpu thermal control. But QCS9075 SoC has higher ambient specification. During high ambient condition, even lowest frequency with multi cores can slowly build heat over the time and it can lead to thermal run-away situations. This patch restrict cpu cores during this scenario helps further thermal control and avoids thermal critical violation. Add cpu idle injection cooling bindings for cpu tsens thermal zones as a mitigation for cpu subsystem prior to thermal shutdown. Add cpu frequency cooling devices that will be used by userspace thermal governor to mitigate skin thermal management. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/qcs9075-rb8.dts | 1 + arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts | 1 + arch/arm64/boot/dts/qcom/qcs9075-ride.dts | 1 + arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi | 287 ++++++++++++++++++ 4 files changed, 290 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi -- 2.47.0 diff --git a/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts index ecaa383b6508..3ab6deeaacf1 100644 --- a/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts +++ b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts @@ -9,6 +9,7 @@ #include "sa8775p.dtsi" #include "sa8775p-pmics.dtsi" +#include "qcs9075-thermal.dtsi" / { model = "Qualcomm Technologies, Inc. Robotics RB8"; diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts index d9a8956d3a76..5f2d9f416617 100644 --- a/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "sa8775p-ride.dtsi" +#include "qcs9075-thermal.dtsi" / { model = "Qualcomm Technologies, Inc. QCS9075 Ride Rev3"; diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts index 3b524359a72d..10ce48e7ba2f 100644 --- a/arch/arm64/boot/dts/qcom/qcs9075-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; #include "sa8775p-ride.dtsi" +#include "qcs9075-thermal.dtsi" / { model = "Qualcomm Technologies, Inc. QCS9075 Ride"; diff --git a/arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi b/arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi new file mode 100644 index 000000000000..40544c8582c4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&cpu0 { + #cooling-cells = <2>; +}; + +&cpu1 { + #cooling-cells = <2>; + cpu1_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +&cpu2 { + #cooling-cells = <2>; + cpu2_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +&cpu3 { + #cooling-cells = <2>; + cpu3_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +&cpu4 { + #cooling-cells = <2>; + cpu4_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +&cpu5 { + #cooling-cells = <2>; + cpu5_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +&cpu6 { + #cooling-cells = <2>; + cpu6_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +&cpu7 { + #cooling-cells = <2>; + cpu7_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <800000>; + exit-latency-us = <10000>; + }; +}; + +/ { + thermal-zones { + cpu-0-1-0-thermal { + trips { + cpu_0_1_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_0_1_0_passive>; + cooling-device = <&cpu1_idle 100 100>; + }; + }; + }; + + cpu-0-2-0-thermal { + trips { + cpu_0_2_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_0_2_0_passive>; + cooling-device = <&cpu2_idle 100 100>; + }; + }; + }; + + cpu-0-3-0-thermal { + trips { + cpu_0_3_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_0_3_0_passive>; + cooling-device = <&cpu3_idle 100 100>; + }; + }; + }; + + cpu-0-1-1-thermal { + trips { + cpu_0_1_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_0_1_1_passive>; + cooling-device = <&cpu1_idle 100 100>; + }; + }; + }; + + cpu-0-2-1-thermal { + trips { + cpu_0_2_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_0_2_1_passive>; + cooling-device = <&cpu2_idle 100 100>; + }; + }; + }; + + cpu-0-3-1-thermal { + trips { + cpu_0_3_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_0_3_1_passive>; + cooling-device = <&cpu3_idle 100 100>; + }; + }; + }; + + cpu-1-0-0-thermal { + trips { + cpu_1_0_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_0_0_passive>; + cooling-device = <&cpu4_idle 100 100>; + }; + }; + }; + + cpu-1-1-0-thermal { + trips { + cpu_1_1_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_1_0_passive>; + cooling-device = <&cpu5_idle 100 100>; + }; + }; + }; + + cpu-1-2-0-thermal { + trips { + cpu_1_2_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_2_0_passive>; + cooling-device = <&cpu6_idle 100 100>; + }; + }; + }; + + cpu-1-3-0-thermal { + trips { + cpu_1_3_0_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_3_0_passive>; + cooling-device = <&cpu7_idle 100 100>; + }; + }; + }; + + cpu-1-0-1-thermal { + trips { + cpu_1_0_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_0_1_passive>; + cooling-device = <&cpu4_idle 100 100>; + }; + }; + }; + + cpu-1-1-1-thermal { + trips { + cpu_1_1_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_1_1_passive>; + cooling-device = <&cpu5_idle 100 100>; + }; + }; + }; + + cpu-1-2-1-thermal { + trips { + cpu_1_2_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_2_1_passive>; + cooling-device = <&cpu6_idle 100 100>; + }; + }; + }; + + cpu-1-3-1-thermal { + trips { + cpu_1_3_1_passive: trip-point1 { + temperature = <116000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_1_3_1_passive>; + cooling-device = <&cpu7_idle 100 100>; + }; + }; + }; + }; +};