From patchwork Tue Dec 17 08:42:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13911382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11B87E77184 for ; Tue, 17 Dec 2024 08:43:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2D3C10E885; Tue, 17 Dec 2024 08:43:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kti74dr3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B5E210E87F; Tue, 17 Dec 2024 08:43:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734424997; x=1765960997; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6HuH8m53Oed5iG6uEP1upukBxI178/zU7kfo8CAz7GA=; b=kti74dr3bI1MO+dDCzJjacvBkG69wvn+1KxMrlQW4hUMOfl22AcnWXrQ /nXFS6eHcOkqv84I0C5bAwmHloKA8L/R7M4twPkXitBPXaEwMMLo+eAJ/ Mg4kqqDzmBx/UVOMxiFG+ynCHlOnJgJeEoN7WjDtfo18yNy0JR1RdCYCx B016EaaDJxFpCVFtTAaWePB5NvwXNeUIaDOvNSNRtjgQze6gZgA3OlSm9 Q8HPkl+maOsl+eNEJyDRzmZDF8yjMtOaXd7aeBLDaYRXuybcyVC2YgAw5 sWnPmyIYWqksHV9XMY9IJWo69iGCn2xW/xqY7GHI8T4SmSTBBN1AaNQqn Q==; X-CSE-ConnectionGUID: JM9sjCr1SC++/evz7zhkYA== X-CSE-MsgGUID: zKbzpInmSsCiB4W4ri5KfQ== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="38614958" X-IronPort-AV: E=Sophos;i="6.12,241,1728975600"; d="scan'208";a="38614958" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 00:43:17 -0800 X-CSE-ConnectionGUID: oMz+nZn4SxyUzrbvdjk8Mg== X-CSE-MsgGUID: dyglYSLDRl2ZKqUeKdHoCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,241,1728975600"; d="scan'208";a="97703942" Received: from ettammin-desk.ger.corp.intel.com (HELO vgovind2-mobl3..) ([10.245.245.122]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 00:43:15 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v2 1/3] drm/i915/xe: add register definitions for fbc dirty rect support Date: Tue, 17 Dec 2024 10:42:43 +0200 Message-Id: <20241217084245.246218-2-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217084245.246218-1-vinod.govindapillai@intel.com> References: <20241217084245.246218-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Register definitions for FBC dirty rect support Bspec: 71675, 73424 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h index ae0699c3c2fe..b1d0161a3196 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -100,6 +100,15 @@ #define FBC_STRIDE_MASK REG_GENMASK(14, 0) #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) +#define XE3_FBC_DIRTY_RECT(fbc_id) _MMIO_PIPE((fbc_id), 0x43230, 0x43270) +#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, 16) +#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val)) +#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0) +#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val)) + +#define XE3_FBC_DIRTY_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x43234, 0x43274) +#define FBC_DIRTY_RECT_EN REG_BIT(31) + #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID REG_BIT(0) #define SNB_FBC_FRONT_BUFFER REG_BIT(1) From patchwork Tue Dec 17 08:42:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13911383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2E96E7717F for ; Tue, 17 Dec 2024 08:43:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8880810E887; Tue, 17 Dec 2024 08:43:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KSezDWui"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id B90AC10E887; Tue, 17 Dec 2024 08:43:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734425000; x=1765961000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SkKGERynx+IqsmwlwFpX9xctqqb/4S1nBBuS6/VDpI0=; b=KSezDWui/rSnBaQNqtaa7LqbYZYtD0GByW2e/2lAlHy2Xe3yetK9kZcS +Q9rKNSg8xgtkhaZ6P1sncDP06qQM1ITqw7NQzw4pzlvmZRsY9BMST0JL Frv4Ac31dRdFFun4ApIPee3GeqFkE4TOt8UJs/KBGBnkTPViAM+JVNxui wCeRnGG65U04PCbC+7FyInTOxzTqN9/jQHLT1DPIf/51+ixGnc3HCytyh 1P+1l6AGFnZdkH2Yqsk+OFvgSFlIrXfOMvs+91VY4gSGjlqIaEGp1PRSp /AChInPlaQHPFFyI2Q6dzyObOUuhitOw7hDrB6xeol9uaTeaWuDSizO05 g==; X-CSE-ConnectionGUID: 5vWg5M9PRrGMJMDN9Xv/Pg== X-CSE-MsgGUID: VUsavVjnQWS2GKaEYK4VNw== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="38614959" X-IronPort-AV: E=Sophos;i="6.12,241,1728975600"; d="scan'208";a="38614959" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 00:43:20 -0800 X-CSE-ConnectionGUID: m01cYGReSyiTPKMFoJJQdQ== X-CSE-MsgGUID: cAn1IvGZQcalyv0P1YqfnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,241,1728975600"; d="scan'208";a="97703947" Received: from ettammin-desk.ger.corp.intel.com (HELO vgovind2-mobl3..) ([10.245.245.122]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 00:43:18 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v2 2/3] drm/i915/xe3: add dirty rect support for FBC Date: Tue, 17 Dec 2024 10:42:44 +0200 Message-Id: <20241217084245.246218-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217084245.246218-1-vinod.govindapillai@intel.com> References: <20241217084245.246218-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Dirty rectangle feature allows FBC to recompress a subsection of a frame. When this feature is enabled, display will read the scan lines between dirty rectangle start line and dirty rectangle end line in subsequent frames. v2: Move dirty rect handling to fbc state (Ville) Bspec: 71675, 73424 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_display.c | 4 + drivers/gpu/drm/i915/display/intel_fbc.c | 96 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_fbc.h | 4 + 3 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4271da219b41..d381dce04755 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7209,6 +7209,8 @@ static void intel_update_crtc(struct intel_atomic_state *state, commit_pipe_pre_planes(state, crtc); + intel_fbc_program_dirty_rect(NULL, state, crtc); + intel_crtc_planes_update_arm(NULL, state, crtc); commit_pipe_post_planes(state, crtc); @@ -7678,6 +7680,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state); bdw_set_pipe_misc(new_crtc_state->dsb_commit, new_crtc_state); + intel_fbc_program_dirty_rect(new_crtc_state->dsb_commit, + state, crtc); intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index df05904bac8a..637b8d21ed1d 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -42,6 +42,7 @@ #include #include +#include #include #include "gem/i915_gem_stolen.h" @@ -58,6 +59,7 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_display_wa.h" +#include "intel_dsb.h" #include "intel_fbc.h" #include "intel_fbc_regs.h" #include "intel_frontbuffer.h" @@ -88,6 +90,7 @@ struct intel_fbc_state { u16 override_cfb_stride; u16 interval; s8 fence_id; + struct drm_rect dirty_rect; }; struct intel_fbc { @@ -527,6 +530,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) struct intel_display *display = fbc->display; u32 dpfc_ctl; + if (DISPLAY_VER(display) >= 30) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); + /* Disable compression */ dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); if (dpfc_ctl & DPFC_CTL_EN) { @@ -670,6 +676,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (DISPLAY_VER(display) >= 20) intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + if (DISPLAY_VER(display) >= 30) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), + FBC_DIRTY_RECT_EN); + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), DPFC_CTL_EN | dpfc_ctl); } @@ -1203,6 +1213,85 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) return i8xx_fbc_tiling_valid(plane_state); } +static void +__intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_plane *plane) +{ + struct intel_display *display = to_intel_display(plane); + struct intel_fbc *fbc = plane->fbc; + struct intel_fbc_state *fbc_state = &fbc->state; + + if (fbc_state->plane != plane) + return; + + intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), + FBC_DIRTY_RECT_START_LINE(fbc_state->dirty_rect.y1) | + FBC_DIRTY_RECT_END_LINE(fbc_state->dirty_rect.y2)); +} + +void +intel_fbc_program_dirty_rect(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_plane_state __maybe_unused *plane_state; + struct intel_plane *plane; + int i; + + if (DISPLAY_VER(display) < 30) + return; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_fbc *fbc = plane->fbc; + + if (!fbc || plane->pipe != crtc->pipe) + continue; + + __intel_fbc_program_dirty_rect(dsb, plane); + } +} + + +static void +update_dirty_rect_to_full_region(struct intel_plane_state *plane_state, + struct drm_rect *dirty_rect) +{ + int y_offset = plane_state->view.color_plane[0].y; + int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16; + + dirty_rect->y1 = y_offset; + dirty_rect->y2 = y_offset + plane_height - 1; +} + +static void +validate_and_clip_dirty_rect(struct intel_plane_state *plane_state, + struct drm_rect *dirty_rect) +{ + int y_offset = plane_state->view.color_plane[0].y; + int plane_height = drm_rect_height(&plane_state->uapi.src) >> 16; + int max_endline = y_offset + plane_height; + + dirty_rect->y1 = clamp(dirty_rect->y1, y_offset, max_endline); + dirty_rect->y2 = clamp(dirty_rect->y2, dirty_rect->y1, max_endline); +} + +static void +intel_fbc_compute_dirty_rect(struct intel_plane *plane, + struct intel_plane_state *old_plane_state, + struct intel_plane_state *new_plane_state) +{ + struct intel_fbc *fbc = plane->fbc; + struct intel_fbc_state *fbc_state = &fbc->state; + struct drm_rect *fbc_dirty_rect = &fbc_state->dirty_rect; + + if (drm_atomic_helper_damage_merged(&old_plane_state->uapi, + &new_plane_state->uapi, + fbc_dirty_rect)) + validate_and_clip_dirty_rect(new_plane_state, fbc_dirty_rect); + else + update_dirty_rect_to_full_region(new_plane_state, fbc_dirty_rect); +} + static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) @@ -1210,8 +1299,10 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state->base.dev); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - const struct intel_plane_state *plane_state = + struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); + struct intel_plane_state *old_plane_state = + intel_atomic_get_old_plane_state(state, plane); struct intel_fbc *fbc = plane->fbc; struct intel_fbc_state *fbc_state = &fbc->state; @@ -1236,6 +1327,9 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); + + if (DISPLAY_VER(display) >= 30) + intel_fbc_compute_dirty_rect(plane, old_plane_state, plane_state); } static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index ceae55458e14..acaebe15f312 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -14,6 +14,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_display; +struct intel_dsb; struct intel_fbc; struct intel_plane; struct intel_plane_state; @@ -48,5 +49,8 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); void intel_fbc_reset_underrun(struct intel_display *display); void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); void intel_fbc_debugfs_register(struct intel_display *display); +void intel_fbc_program_dirty_rect(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc); #endif /* __INTEL_FBC_H__ */ From patchwork Tue Dec 17 08:42:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13911384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DA2DE7717F for ; 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([10.245.245.122]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Dec 2024 00:43:21 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com, santhosh.reddy.guddati@intel.com, jani.saarinen@intel.com Subject: [PATCH v2 3/3] drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled Date: Tue, 17 Dec 2024 10:42:45 +0200 Message-Id: <20241217084245.246218-4-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241217084245.246218-1-vinod.govindapillai@intel.com> References: <20241217084245.246218-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It is not recommended to have both FBC and PSR2 selective fetch be enabled at the same time in a plane. If PSR2 selective fetch or panel replay is on, mark FBC as not possible in that plane. v2: fix the condition to disable FBC if PSR2 enabled (Jani) Bspec: 68881 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 637b8d21ed1d..23e1f7c35d42 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1432,9 +1432,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || DISPLAY_VER(display) >= 30) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; }