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[34.38.134.32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4362559ec46sm167475755e9.20.2024.12.17.01.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 01:40:46 -0800 (PST) From: Tudor Ambarus Date: Tue, 17 Dec 2024 09:40:20 +0000 Subject: [PATCH v5 1/3] dt-bindings: mailbox: add google,gs101-mbox MIME-Version: 1.0 Message-Id: <20241217-acpm-v4-upstream-mbox-v5-1-cd1d3951fe84@linaro.org> References: <20241217-acpm-v4-upstream-mbox-v5-0-cd1d3951fe84@linaro.org> In-Reply-To: <20241217-acpm-v4-upstream-mbox-v5-0-cd1d3951fe84@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734428445; l=3405; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=oGbadS/EXFOmnPlUbzd78fQ8Sa6oboYVtVmK/tk9ZNU=; b=o39r/a65k4kXSV5QfRaDOokAx5BK2B4HFYrhAv0oPz7TlgqFXptplibdlk3n/NcgfUf68gxSi 1BS6mafZikSDarVm9MLWDNTdW21MMS5QWgqUCvz37F8c5DiFzt9IgE/ X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_014048_334214_4D1D4BE3 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add bindings for the Samsung Exynos Mailbox Controller. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski --- .../bindings/mailbox/google,gs101-mbox.yaml | 79 ++++++++++++++++++++++ include/dt-bindings/mailbox/google,gs101.h | 14 ++++ 2 files changed, 93 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml new file mode 100644 index 000000000000..bc7288923795 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Mailbox Controller + +maintainers: + - Tudor Ambarus + +description: | + The samsung exynos mailbox controller has 16 flag bits for hardware interrupt + generation and a shared register for passing mailbox messages. When the + controller is used by the ACPM protocol the shared register is ignored and + the mailbox controller acts as a doorbell. The controller just raises the + interrupt to the firmware after the ACPM protocol has written the message to + SRAM. + +properties: + compatible: + const: google,gs101-mbox + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + interrupts: + description: IRQ line for the RX mailbox. + maxItems: 1 + + '#mbox-cells': + description: | + <&phandle type channel> + phandle : label name of controller. + type : channel type, doorbell or data-transfer. + channel : channel number. + + Here is how a client can reference them: + mboxes = <&ap2apm_mailbox DOORBELL 2>; + mboxes = <&ap2apm_mailbox DATA 3>; + const: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + # Doorbell mode. + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + ap2apm_mailbox: mailbox@17610000 { + compatible = "google,gs101-mbox"; + reg = <0x17610000 0x1000>; + clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; + clock-names = "pclk"; + interrupts = ; + #mbox-cells = <2>; + }; + }; diff --git a/include/dt-bindings/mailbox/google,gs101.h b/include/dt-bindings/mailbox/google,gs101.h new file mode 100644 index 000000000000..7ff4fe669f9e --- /dev/null +++ b/include/dt-bindings/mailbox/google,gs101.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024 Linaro Ltd. + * + * This header provides constants for the defined mailbox channel types. + */ + +#ifndef _DT_BINDINGS_MAILBOX_GOOGLE_GS101_H +#define _DT_BINDINGS_MAILBOX_GOOGLE_GS101_H + +#define DOORBELL 0 +#define DATA 1 + +#endif /* _DT_BINDINGS_MAILBOX_GOOGLE_GS101_H */ From patchwork Tue Dec 17 09:40:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13911553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2C2DE7716A for ; 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[34.38.134.32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4362559ec46sm167475755e9.20.2024.12.17.01.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 01:40:47 -0800 (PST) From: Tudor Ambarus Date: Tue, 17 Dec 2024 09:40:21 +0000 Subject: [PATCH v5 2/3] mailbox: add Samsung Exynos driver MIME-Version: 1.0 Message-Id: <20241217-acpm-v4-upstream-mbox-v5-2-cd1d3951fe84@linaro.org> References: <20241217-acpm-v4-upstream-mbox-v5-0-cd1d3951fe84@linaro.org> In-Reply-To: <20241217-acpm-v4-upstream-mbox-v5-0-cd1d3951fe84@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734428445; l=7613; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ch9bLEDAwuuM6wIBFS8dUZsQMo2a87ncAz/QuVGegyA=; b=HWP8gwFS9ptfi3AaIeb3AKQ+iprpG9u2wio+GD624E3JpOIVeTIIaXaABprepkLT1aF8Rh93H q2JPx5KG9vxCho8aFuENRfcLF0k2Zb0bFQT7EFy2timfM1nk31d5rbQ X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_014049_205750_C25A3F4F X-CRM114-Status: GOOD ( 25.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Samsung Exynos mailbox controller has 16 flag bits for hardware interrupt generation and a shared register for passing mailbox messages. When the controller is used by the ACPM protocol the shared register is ignored and the mailbox controller acts as a doorbell. The controller just raises the interrupt to APM after the ACPM protocol has written the message to SRAM. Add support for the Samsung Exynos mailbox controller. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski --- drivers/mailbox/Kconfig | 11 +++ drivers/mailbox/Makefile | 2 + drivers/mailbox/exynos-mailbox.c | 184 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 197 insertions(+) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 8ecba7fb999e..44b808c4d97f 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -36,6 +36,17 @@ config ARM_MHU_V3 that provides different means of transports: supported extensions will be discovered and possibly managed at probe-time. +config EXYNOS_MBOX + tristate "Exynos Mailbox" + depends on ARCH_EXYNOS || COMPILE_TEST + help + Say Y here if you want to build the Samsung Exynos Mailbox controller + driver. The controller has 16 flag bits for hardware interrupt + generation and a shared register for passing mailbox messages. + When the controller is used by the ACPM protocol the shared register + is ignored and the mailbox controller acts as a doorbell that raises + the interrupt to the ACPM firmware. + config IMX_MBOX tristate "i.MX Mailbox" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 5f4f5b0ce2cc..86192b5c7c32 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o obj-$(CONFIG_ARM_MHU_V3) += arm_mhuv3.o +obj-$(CONFIG_EXYNOS_MBOX) += exynos-mailbox.o + obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mailbox.c new file mode 100644 index 000000000000..9d875806d0f9 --- /dev/null +++ b/drivers/mailbox/exynos-mailbox.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2024 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EXYNOS_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */ +#define EXYNOS_MBOX_INTCR0 0x24 /* Interrupt Clear Register 0 */ +#define EXYNOS_MBOX_INTMR0 0x28 /* Interrupt Mask Register 0 */ +#define EXYNOS_MBOX_INTSR0 0x2c /* Interrupt Status Register 0 */ +#define EXYNOS_MBOX_INTMSR0 0x30 /* Interrupt Mask Status Register 0 */ +#define EXYNOS_MBOX_INTGR1 0x40 /* Interrupt Generation Register 1 */ +#define EXYNOS_MBOX_INTMR1 0x48 /* Interrupt Mask Register 1 */ +#define EXYNOS_MBOX_INTSR1 0x4c /* Interrupt Status Register 1 */ +#define EXYNOS_MBOX_INTMSR1 0x50 /* Interrupt Mask Status Register 1 */ + +#define EXYNOS_MBOX_INTMR0_MASK GENMASK(15, 0) +#define EXYNOS_MBOX_INTGR1_MASK GENMASK(15, 0) + +#define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK) + +enum { + EXYNOS_MBOX_CELL_TYPE, + EXYNOS_MBOX_CELL_ID, + EXYNOS_MBOX_CELLS +}; + +#define EXYNOS_MBOX_CELL_TYPE_COUNT 2 + +/** + * struct exynos_mbox - driver's private data. + * @regs: mailbox registers base address. + * @mbox: pointer to the mailbox controller. + * @dev: pointer to the mailbox device. + * @pclk: pointer to the mailbox peripheral clock. + */ +struct exynos_mbox { + void __iomem *regs; + struct mbox_controller *mbox; + struct device *dev; + struct clk *pclk; +}; + +static int exynos_mbox_chan_index(struct mbox_chan *chan) +{ + struct mbox_controller *mbox = chan->mbox; + int i; + + for (i = 0; i < mbox->num_chans; i++) + if (chan == &mbox->chans[i]) + return i; + return -EINVAL; +} + +static int exynos_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct exynos_mbox *exynos_mbox = dev_get_drvdata(chan->mbox->dev); + int index; + + index = exynos_mbox_chan_index(chan); + if (index < 0) + return index; + + writel(BIT(index), exynos_mbox->regs + EXYNOS_MBOX_INTGR1); + + return 0; +} + +static const struct mbox_chan_ops exynos_mbox_chan_ops = { + .send_data = exynos_mbox_send_data, +}; + +static struct mbox_chan *exynos_mbox_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + u32 type, id; + + if (sp->args_count != EXYNOS_MBOX_CELLS) { + dev_err(mbox->dev, "Invalid argument count %d\n", + sp->args_count); + return ERR_PTR(-EINVAL); + } + + type = sp->args[EXYNOS_MBOX_CELL_TYPE]; + if (type >= EXYNOS_MBOX_CELL_TYPE_COUNT) { + dev_err(mbox->dev, "Invalid channel type %d\n", type); + return ERR_PTR(-EINVAL); + } + + if (type == DATA) { + dev_err(mbox->dev, "DATA channel type [%d] not supported\n", + type); + return ERR_PTR(-EINVAL); + }; + + id = sp->args[EXYNOS_MBOX_CELL_ID]; + if (id >= mbox->num_chans) { + dev_err(mbox->dev, "Invalid channel ID %d\n", id); + return ERR_PTR(-EINVAL); + } + + return &mbox->chans[id]; +} + +static const struct of_device_id exynos_mbox_match[] = { + { .compatible = "google,gs101-mbox" }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos_mbox_match); + +static int exynos_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos_mbox *exynos_mbox; + struct mbox_controller *mbox; + struct mbox_chan *chans; + int i; + + exynos_mbox = devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL); + if (!exynos_mbox) + return -ENOMEM; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + chans = devm_kcalloc(dev, EXYNOS_MBOX_CHAN_COUNT, sizeof(*chans), + GFP_KERNEL); + if (!chans) + return -ENOMEM; + + exynos_mbox->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(exynos_mbox->regs)) + return PTR_ERR(exynos_mbox->regs); + + exynos_mbox->pclk = devm_clk_get_enabled(dev, "pclk"); + if (IS_ERR(exynos_mbox->pclk)) + return dev_err_probe(dev, PTR_ERR(exynos_mbox->pclk), + "Failed to enable clock.\n"); + + mbox->num_chans = EXYNOS_MBOX_CHAN_COUNT; + mbox->chans = chans; + mbox->dev = dev; + mbox->ops = &exynos_mbox_chan_ops; + mbox->of_xlate = exynos_mbox_of_xlate; + + for (i = 0; i < EXYNOS_MBOX_CHAN_COUNT; i++) + chans[i].mbox = mbox; + + exynos_mbox->dev = dev; + exynos_mbox->mbox = mbox; + + platform_set_drvdata(pdev, exynos_mbox); + + /* Mask out all interrupts. We support just polling channels for now. */ + writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0); + + return devm_mbox_controller_register(dev, mbox); +} + +static struct platform_driver exynos_mbox_driver = { + .probe = exynos_mbox_probe, + .driver = { + .name = "exynos-acpm-mbox", + .of_match_table = exynos_mbox_match, + }, +}; +module_platform_driver(exynos_mbox_driver); + +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Samsung Exynos mailbox driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Dec 17 09:40:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13911554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4A07E7716A for ; Tue, 17 Dec 2024 10:04:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1rzC8vvycH/Cp0hUw6Wfj4qRoaSuoHKIpGfYrmHMjP8=; b=fPPkyqE0HoAmBbX4pYHYA61m7I aaiESVuOz3s/kjEfuKnbFeLUbtRdwaNjDZKQnUPg1at8BuBl3X/64D/dEgbX8TXPsFWHTxhUY7RYp ObOFT7HHe6o/0QLOFjPtXibecRSyYKVD14m+nkCTdrAUfkrxf6pQmCCmqfUkMRFVluR23dVF45xB9 Hv8kuU/Kw6LHMsoUftlqu9u3c4eJm2uPkPhZofP0dp8LEmM8W82MmTouaBOHGdf6+hGAgQULXVsN8 Un/m7aLXHJHT/ePaRm9vCmqPEMtm9g9Xnq5nDvL8Szcm8w0TChV2jOx7Yy9RpivdkJao59UbAYaKj VFCDc5yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tNUQe-0000000D2Y4-2z10; Tue, 17 Dec 2024 10:03:48 +0000 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tNU4P-0000000Cxay-3WJV for linux-arm-kernel@lists.infradead.org; Tue, 17 Dec 2024 09:40:50 +0000 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-435f8f29f8aso36411895e9.2 for ; Tue, 17 Dec 2024 01:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1734428448; x=1735033248; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1rzC8vvycH/Cp0hUw6Wfj4qRoaSuoHKIpGfYrmHMjP8=; b=PmAl5SQlSb6dD9gjW9jGuLMyBk6KFVnjC1Vd5WzWG8MBza7JeLshojYfTZo30NLfAk Z1to8Y9/VaoVUcFBI7Wfx75BR4yFnInIk/6dJMzZw03Td9I3QZXVK9UI3jYNMTX22pPC jaP6iVsfzLyyDK2Nsve1ASQzl1GA1yGdhVIKapEikTa7zaER2QnGBd6QOXIiB6YWdudQ FQoC/UC5dPsZU9VMfkavDyV7S4T5GRBRiS041yXr7OFbk5rkF/6HICSkLz8WBAo5/UzQ CCpEFoywSfj0ymJBfkeNadrU5zk+ULl9uv9Nw33gl8AvZuQHZ0LKrgZfAsf/QdzP3FZH E9yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1734428448; x=1735033248; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1rzC8vvycH/Cp0hUw6Wfj4qRoaSuoHKIpGfYrmHMjP8=; b=CA9AQ7OKl+/iHoLlbSgwFDhGO5K9J9550Afe7RuM4Vp+hXHVjRQFFt+F1cEooYll54 RzG0fIZ/HghxBAjqhXMr7YQjfaF1vAc/gLj2IDcmw0yaRo32oc6L0/e0msWBrlwGBXLZ JGhicG4MGwU66Iei3IpuRDeLM913Sb8fOr7sQ/ZUbQ/4Ulg7m76dxOVg/XncLYbhw/YC fAtcb3HtNC8PU3KSRD4Bwc0YAwUzGxm/1HLFFMu1VEO1RrK64UgLMHd44t119PWww+Ld 3TDJo+eEscOqU57Fg/PGD3uhAEq3Vw8xrR8S6f0rSRhYXb0OqUQzwRkM+w7mkBlEjhKN TuJw== X-Forwarded-Encrypted: i=1; AJvYcCWG1+xOzCCpknGnEADiILxeiY5kyAMV3tSUNlkDGYvO2hop+1CsWC0sRP6ddejCb5HAfI8vAKDwao152klr+f8l@lists.infradead.org X-Gm-Message-State: AOJu0YyATgDLy2+hjG97Y329YJXhMfH2zGfylMmbMmtuXdGvqHuugFb1 Bfx/9JpCYIyFMBXM7lXw/jMeLtn8OyvqjqEOyfn/wmGPBV8C1NkooRo2YcK2WIY= X-Gm-Gg: ASbGncsBTfg6ei0iGkiFErqU+uz5duFaQIU6cBxpQhZQI+O05unl22iyeVLFuAbHqmO Eos7SRyvMlsZi0yD3gmqHmayR7D7vtl7fUHEVC7Eq3u3SJoTFpDddxt4l5YD7Ek/mtcw325P8gD 103TFyh9wlA5f6euoPCA6ZcxqARClNmfxDZjcMEBJ9larCOZAOTIwWZrnCiECKwVrzySVLc8f3x V2vp8urPPsqrK8QqjWxqX6zt6ZaWTDzv7xQ1bU8Rcs0LS3HgyAcK50Xm9WuwOjj+HeyyYa84jaA sMIOMIGPRxh86rR6ekwxIeOJcldo53NXqg== X-Google-Smtp-Source: AGHT+IGdL77URRUUDel/620o0E15cA6VUq4GPfffaHhqeuBMk65coFdHp1nDn5rm38NPj5m5jvSG6g== X-Received: by 2002:a05:600c:1d1f:b0:434:f0df:9f6 with SMTP id 5b1f17b1804b1-4364767f087mr28742535e9.3.1734428448580; Tue, 17 Dec 2024 01:40:48 -0800 (PST) Received: from ta2.c.googlers.com (32.134.38.34.bc.googleusercontent.com. [34.38.134.32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4362559ec46sm167475755e9.20.2024.12.17.01.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 01:40:48 -0800 (PST) From: Tudor Ambarus Date: Tue, 17 Dec 2024 09:40:22 +0000 Subject: [PATCH v5 3/3] MAINTAINERS: add entry for Samsung Exynos mailbox driver MIME-Version: 1.0 Message-Id: <20241217-acpm-v4-upstream-mbox-v5-3-cd1d3951fe84@linaro.org> References: <20241217-acpm-v4-upstream-mbox-v5-0-cd1d3951fe84@linaro.org> In-Reply-To: <20241217-acpm-v4-upstream-mbox-v5-0-cd1d3951fe84@linaro.org> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, daniel.lezcano@linaro.org, vincent.guittot@linaro.org, ulf.hansson@linaro.org, arnd@arndb.de, Tudor Ambarus X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734428445; l=1216; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=9mXBYawofpPepE2BF91P/arRig7nezklsaAdla8ShbI=; b=Z0AXVvEDLX3dGQQUU6S7FG2YiVuEm8f4RKNyhHzyRa5O41uaawalfgmZW9iW5t8kzyPwvDlhN g3py0lZDyAoDARc+CygZuhG7TGX1DhEtmkfDDEsBIZmbJzbmsW3NitI X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241217_014049_878827_30BAD3DB X-CRM114-Status: UNSURE ( 9.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add entry for the Samsung Exynos mailbox driver. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index baf0eeb9a355..6bef5fc5e4ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3023,6 +3023,7 @@ F: drivers/*/*s3c24* F: drivers/*/*s3c64xx* F: drivers/*/*s5pv210* F: drivers/clocksource/samsung_pwm_timer.c +F: drivers/mailbox/exynos-mailbox.c F: drivers/memory/samsung/ F: drivers/pwm/pwm-samsung.c F: drivers/soc/samsung/ @@ -20717,6 +20718,15 @@ F: arch/arm64/boot/dts/exynos/exynos850* F: drivers/clk/samsung/clk-exynos850.c F: include/dt-bindings/clock/exynos850.h +SAMSUNG EXYNOS MAILBOX DRIVER +M: Tudor Ambarus +L: linux-kernel@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml +F: drivers/mailbox/exynos-mailbox.c +F: include/dt-bindings/mailbox/google,gs101.h + SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER M: Krzysztof Kozlowski L: linux-crypto@vger.kernel.org