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Signed-off-by: Wei Fang --- arch/arm64/boot/dts/freescale/imx95.dtsi | 93 ++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index e9c7a8265d71..86f9fed9998c 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1702,5 +1702,98 @@ ddr-pmu@4e090dc0 { reg = <0x0 0x4e090dc0 0x0 0x200>; interrupts = ; }; + + netc_blk_ctrl: system-controller@4cde0000 { + compatible = "nxp,imx95-netc-blk-ctrl"; + reg = <0x0 0x4cde0000 0x0 0x10000>, + <0x0 0x4cdf0000 0x0 0x10000>, + <0x0 0x4c81000c 0x0 0x18>; + reg-names = "ierb", "prb", "netcmix"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&scmi_devpd IMX95_PD_NETC>; + assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, + <&scmi_clk IMX95_CLK_ENETREF>; + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; + assigned-clock-rates = <666666666>, <250000000>; + clocks = <&scmi_clk IMX95_CLK_ENET>; + clock-names = "ipg"; + status = "disabled"; + + netc_bus0: pcie@4ca00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4ca00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0x0>; + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0x90 &its 0x65 0x1>, //ENETC2 VF0 + <0xa0 &its 0x66 0x1>, //ENETC2 VF1 + <0xc0 &its 0x67 0x1>; //NETC Timer + /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ + ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 + /* Timer BAR2 - prefetchable memory */ + 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 + /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ + 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 + /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ + 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; + + enetc_port0: ethernet@0,0 { + compatible = "pci1131,e101"; + reg = <0x000000 0 0 0 0>; + clocks = <&scmi_clk IMX95_CLK_ENETREF>; + clock-names = "ref"; + status = "disabled"; + }; + + enetc_port1: ethernet@8,0 { + compatible = "pci1131,e101"; + reg = <0x004000 0 0 0 0>; + clocks = <&scmi_clk IMX95_CLK_ENETREF>; + clock-names = "ref"; + status = "disabled"; + }; + + enetc_port2: ethernet@10,0 { + compatible = "pci1131,e101"; + reg = <0x008000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer: ethernet@18,0 { + reg = <0x00c000 0 0 0 0>; + status = "disabled"; + }; + }; + + netc_bus1: pcie@4cb00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4cb00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x1 0x1>; + /* EMDIO BAR0 - non-prefetchable memory */ + ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 + /* EMDIO BAR2 - prefetchable memory */ + 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; + + netc_emdio: mdio@0,0 { + compatible = "pci1131,ee00"; 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In addition, because all ENETC instances share MDIO bus, so enable EMDIO at the same time. Signed-off-by: Wei Fang --- .../boot/dts/freescale/imx95-19x19-evk.dts | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 6086cb7fa5a0..e838234c8317 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -38,6 +38,7 @@ aliases { mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + ethernet0 = &enetc_port0; }; bt_sco_codec: audio-codec-bt-sco { @@ -428,6 +429,33 @@ &wdog3 { status = "okay"; }; +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + realtek,clkout-disable; + }; +}; + &scmi_iomuxc { pinctrl_flexspi1: flexspi1grp { fsl,pins = < @@ -665,6 +693,30 @@ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_emdio: emdiogrp{ + fsl,pins = < + IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; }; &thermal_zones {