From patchwork Tue Dec 17 11:36:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LECOINTRE Philippe X-Patchwork-Id: 13913167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3AB47E77183 for ; Wed, 18 Dec 2024 08:18:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B038310EAE1; Wed, 18 Dec 2024 08:18:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; secure) header.d=thalesgroup.com header.i=@thalesgroup.com header.b="GUpTgMck"; dkim-atps=neutral Received: from esa.hc1631-21.eu.iphmx.com (esa.hc1631-21.eu.iphmx.com [23.90.123.40]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E16A10E211; Tue, 17 Dec 2024 11:36:15 +0000 (UTC) X-CSE-ConnectionGUID: SJ/OOKH7Qpmpn++a6GiS8A== X-CSE-MsgGUID: gQ6vE3HJS2e002ayTYNp1A== Authentication-Results: ob1.hc1631-21.eu.iphmx.com; dkim=pass (signature verified) header.i=@thalesgroup.com X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="25129903" X-IronPort-AV: E=Sophos;i="6.12,241,1728943200"; d="scan'208";a="25129903" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thalesgroup.com; i=@thalesgroup.com; s=bbmfo20230504; t=1734435373; h=from:to:cc:subject:date:message-id: content-transfer-encoding:mime-version; bh=TD5JtJ2CP9uixpsc/oDUrpMauClPo34I9Wrt3XUOczw=; b=GUpTgMckTYH4IazAUpRsiPtjvDwwgGVK2wIf9qo1OlGc+7xq1lEb4hxl MAklz1hjXi8iZcAdd7MrIw/aUsjedGmGuNotQ1VoPHlYSk3Hd4acMj9/M JLVWFs19pAZ/Awn79lzJySw5fyC+pl+TNfODhxndlhM8DQjMH5s7pUuLr u4v8WAhufV6iuLI6JAUX1HSOlbYTJI1BAtpE5QlKdP0MKkdSlruEyn2Fc 6la+kCw7gQ9eTBYZ9KtPIY1o6JaFm59xwnSTq4M62WDGcsHGv5Opq1hUE HP0X8o+rSNZ9bbBIRA8T0a3wQzbYY1wd421u4hUrTeNQva7t2b4QZP917 A==; X-CSE-ConnectionGUID: 8E5OR/n3Tim3T20hqXeytw== X-CSE-MsgGUID: M5qaJL3sS52hnV0qp6Gszg== X-CSE-ConnectionGUID: /bhLdXNKTBG1cwQzZZTApg== X-CSE-MsgGUID: gGjcmQmfQiWgACfXvEJgMA== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="37641209" X-IronPort-AV: E=Sophos;i="6.12,241,1728943200"; d="scan'208";a="37641209" From: LECOINTRE Philippe To: Lucas Stach , Russell King , Christian Gmeiner CC: David Airlie , Simona Vetter , "etnaviv@lists.freedesktop.org" , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , LENAIN Simon , BARBEAU Etienne , LEJEUNE Sebastien Subject: [PATCH v4] drm/etnaviv: add optional reset support Thread-Topic: [PATCH v4] drm/etnaviv: add optional reset support Thread-Index: AdtQdTRCCPdja+p8TdeGkYsfNshIoA== Date: Tue, 17 Dec 2024 11:36:11 +0000 Message-ID: Accept-Language: fr-FR, en-US Content-Language: fr-FR X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-nodisclaimer: 0 MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 18 Dec 2024 08:18:11 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add optional reset support which is mentioned in vivante,gc.yaml to allow the driver to work on SoCs whose reset signal is asserted by default Signed-off-by: Philippe Lecointre Acked-by: Simon Lenain --- v4: - Rework to match feedback --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 41 +++++++++++++++++++++++++++ drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 2 ++ 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 2d4c112ce033..cf0d9049bcf1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "etnaviv_cmdbuf.h" @@ -172,6 +173,29 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) return 0; } +static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu) +{ + int ret; + + /* + * 32 core clock cycles (slowest clock) required before deassertion + * 1 microsecond might match all implementations without computation + */ + usleep_range(1, 2); + + ret = reset_control_deassert(gpu->rst); + if (ret) + return ret; + + /* + * 128 core clock cycles (slowest clock) required before any activity on AHB + * 1 microsecond might match all implementations without computation + */ + usleep_range(1, 2); + + return 0; +} + static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision) { return gpu->identity.model == model && @@ -799,6 +823,12 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) goto pm_put; } + ret = etnaviv_gpu_reset_deassert(gpu); + if (ret) { + dev_err(gpu->dev, "GPU reset deassert failed\n"); + goto fail; + } + etnaviv_hw_identify(gpu); if (gpu->identity.model == 0) { @@ -1860,6 +1890,17 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) if (IS_ERR(gpu->mmio)) return PTR_ERR(gpu->mmio); + + /* Get Reset: */ + gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + if (IS_ERR(gpu->rst)) + return dev_err_probe(dev, PTR_ERR(gpu->rst), + "failed to get reset\n"); + + err = reset_control_assert(gpu->rst); + if (err) + return dev_err_probe(dev, err, "failed to assert reset\n"); + /* Get Interrupt: */ gpu->irq = platform_get_irq(pdev, 0); if (gpu->irq < 0) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index 4d8a7d48ade3..5cb46c84e03a 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -93,6 +93,7 @@ struct etnaviv_event { struct etnaviv_cmdbuf_suballoc; struct regulator; struct clk; +struct reset_control; #define ETNA_NR_EVENTS 30 @@ -158,6 +159,7 @@ struct etnaviv_gpu { struct clk *clk_reg; struct clk *clk_core; struct clk *clk_shader; + struct reset_control *rst; unsigned int freq_scale; unsigned int fe_waitcycles;