From patchwork Mon Dec 23 02:55:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24546E77188 for ; Mon, 23 Dec 2024 03:06:10 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A91CC6B0088; Sun, 22 Dec 2024 22:06:09 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id A41A16B0089; Sun, 22 Dec 2024 22:06:09 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 90A266B0093; Sun, 22 Dec 2024 22:06:09 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 756956B0088 for ; Sun, 22 Dec 2024 22:06:09 -0500 (EST) Received: from smtpin12.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 26B391C8773 for ; Mon, 23 Dec 2024 03:06:09 +0000 (UTC) X-FDA: 82924733766.12.E5712FC Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf30.hostedemail.com (Postfix) with ESMTP id D329D80007 for ; Mon, 23 Dec 2024 03:04:55 +0000 (UTC) Authentication-Results: imf30.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf30.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1734923132; a=rsa-sha256; cv=none; b=zBT+9Q8Hk6ZyyVGAtqnelSqQvdtQ293cR2WnWp79k9fkdVlfrRrDedKEBl0rxfh/r3umqe RVZtoYguD6yCoFWHoovVLO5poTzY1bbMVqxrVdNv7Su4AjENR6pAnLGcFklptbPg8YfVuM +4U7OpMKmO7fPCv+oKksQpz5foZ6C6E= ARC-Authentication-Results: i=1; imf30.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf30.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1734923132; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yNOxEDig2CZaZYYg6AjMWiyWxe7yKdbBFR9wTrF96Hw=; b=mhJy46H3oCkVNmehuGgwUQ6DI8tl4Va9RUvm2KLeEbz8/t27Aa1xLCYxv+5ov4yhsxVut/ 57rST3hJod9xPh7zYOiHstCwePbdKga52k04c/1nH/8q2jETIsCOx97U1EogzTI/aFHQ9r zU7nD3g5lIMrrJepgwWkOXisjH7xTWk= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdo-000000001Ih-2gNN; Sun, 22 Dec 2024 21:57:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 01/11] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Date: Sun, 22 Dec 2024 21:55:07 -0500 Message-ID: <20241223025751.3268975-2-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Stat-Signature: uyw4bp7t7okzkwayrnhajde45jexpq8f X-Rspam-User: X-Rspamd-Queue-Id: D329D80007 X-Rspamd-Server: rspam08 X-HE-Tag: 1734923095-439568 X-HE-Meta: U2FsdGVkX199JxlqwiEm69xadaXAYI6Z4//IYH8ujurGa8S+fudQdXvbSPdw09wjLAcAXqw5sY2w2Z8LcqAhAhrg3X3/OILT2+KCL25FXgetDnUYDvukIYP1gz/aTNSsg0xbQ3/2kaJhCL9I8kijcH/J+yL3GSNtaDkbMbwcDdhxJVZfr6aN7Q0XpncUyx6WKedHERv4tMb1xuhDvj8YK30H5SQJNmp4zYQNtrIL8rKm049O1SgBVZ8cu9qUrOm2LaXHPSs5XcNZacj4F5zffSOj8OPoJaNxPIxoNgHUSRX8ih7q5osydQ9xyQoHwV1Ks4YXnsDUBhtHLdT117g7+IB8yxj29xqx6XMjKbAhR7pGN9+Aj7alGQVsSKKZG2UkGunSoc1UdklTl6A3EgmVLwywHcpAoyU7e1ws312Wms1v8rmiwzSPFbshuU/Jy7dJpwmTgZD2udsNUXjZLBpyuTL5PJwU7XVJz0SJ46joDkfIhgvFsVOiKB3wAmHI9ueV+LreK+FFiAej2xfn1I5dieUyXXWY9YefbG6MBWgeY+QVh8m+qSmSOvNRN7TCJ7s2+zaSiOklS9c7qHzVCwkptKU9kec+bGNwNTupQi7NOiFa4ovchAnfWi/Vxx5zMuOvJMaMM+ljktXk3PXrQj9/tQyF8gWtH1srFzxaLPl9VaXWMFixelRIiAndD1UeMhObRqeuBjXd3oZ1bSp63cxH0V1b43pFpMOP3lSU7HGR+qzl4x0Ac5cZiZ01XqyWHDtTmZXVEQKCmAZxHAlZRu04t9WTRX66hWxXJZNfhqFMyES/YGnOzdBHF/qyX+FW4XyQrxVSb+4NOD1/jm33BmYgWwBUTYIAjqpAf79szsL/B4GQFrsfKo9h8aRyMGS7o9q3LppfXIY4IIiT6dZ4xBZTnOMT7ghKEOQwRQSuziHv9yrerEPQKQ/6ilTT5Kb49zbSWz10BWXsKZ5jSRuhIpa YEHkssTs 0Ebg/wil8QPBzbd6v8Ea7lfXIHCzd2MNGPtrxOoig5Amft9bdl+SNAPFGpgYl8/0zNyNMiBGGe7FZH1WBOvsqaF2JaOzFi1p/2Ycx8Ifnzr+9o2HBJ7ka6998o7TbCDO+qw/ASrsVLdbvoFCc2NdIPr7L6ftYbQynHeU79GdJyi3h+0brHBuIo3YXnewmAs6pqDBI0SbDnycvK1czjuTGmf5CnN7lF1d7cftcMWURkSiOVnkH8ys6dXMwP76YbEse60U8OrfYN55zSS5GsyPRRurfpfHDpXEEh8YaeJD/2foXk48Bw5RTaD6VCi/gWS1c0tSuyOYxOJbdC2UMAU3xzulKYFzVkWyRU8V6VQTMD2AGqJe0jSAEl/bZBLbJa1W+w719abKABiqkqkkatgQ898dqbccyXLUKpdzMzZ8usI+gG/c= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Currently x86 usse CONFIG_MMU_GATHER_TABLE_FREE when using paravirt, and not when running on bare metal. There is no real good reason to do things differently for each setup. Make them all the same. Signed-off-by: Rik van Riel Suggested-by: Peter Zijlstra --- arch/x86/Kconfig | 2 +- arch/x86/kernel/paravirt.c | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9d7bd0ae48c4..e8743f8c9fd0 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -274,7 +274,7 @@ config X86 select HAVE_PCI select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP - select MMU_GATHER_RCU_TABLE_FREE if PARAVIRT + select MMU_GATHER_RCU_TABLE_FREE select MMU_GATHER_MERGE_VMAS select HAVE_POSIX_CPU_TIMERS_TASK_WORK select HAVE_REGS_AND_STACK_ACCESS_API diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index fec381533555..2b78a6b466ed 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -59,11 +59,6 @@ void __init native_pv_lock_init(void) static_branch_enable(&virt_spin_lock_key); } -static void native_tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - tlb_remove_page(tlb, table); -} - struct static_key paravirt_steal_enabled; struct static_key paravirt_steal_rq_enabled; @@ -191,7 +186,7 @@ struct paravirt_patch_template pv_ops = { .mmu.flush_tlb_kernel = native_flush_tlb_global, .mmu.flush_tlb_one_user = native_flush_tlb_one_user, .mmu.flush_tlb_multi = native_flush_tlb_multi, - .mmu.tlb_remove_table = native_tlb_remove_table, + .mmu.tlb_remove_table = tlb_remove_table, .mmu.exit_mmap = paravirt_nop, .mmu.notify_page_enc_status_changed = paravirt_nop, From patchwork Mon Dec 23 02:55:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1611E77188 for ; Mon, 23 Dec 2024 03:02:20 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 3DACF6B007B; Sun, 22 Dec 2024 22:02:20 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 362EF6B0083; Sun, 22 Dec 2024 22:02:20 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 203986B0088; Sun, 22 Dec 2024 22:02:20 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0011.hostedemail.com [216.40.44.11]) by kanga.kvack.org (Postfix) with ESMTP id 011DC6B007B for ; Sun, 22 Dec 2024 22:02:19 -0500 (EST) Received: from smtpin09.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay05.hostedemail.com (Postfix) with ESMTP id C294C4614E for ; Mon, 23 Dec 2024 03:02:19 +0000 (UTC) X-FDA: 82924723014.09.DA5C261 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf02.hostedemail.com (Postfix) with ESMTP id 7F8FC80018 for ; Mon, 23 Dec 2024 03:01:06 +0000 (UTC) Authentication-Results: imf02.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf02.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1734922921; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vu+np97BEOhzxibTxU5s+5i0frH+GWBwAeJ+kY0b4kg=; b=q5b4tBcQpdq9HP9gxV857NfpFEsqGwhCsxA+Y/slRha+lsGYEEkDXXe8054kfphOqHWIiG K1R30DWRHD0+v0zASeGwwB0PDOy477QCD9RXeQ+mY7GihUD7cfRPGoY7ApfXo+lpci5rXR MAJXVtS/shWV9fPwShfLoZQKVwcVa8o= ARC-Authentication-Results: i=1; imf02.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf02.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1734922921; a=rsa-sha256; cv=none; b=EbgOD/6bLpL8PL6HqlANjSgaNBnVlFiWIXr0PTddrQHW42XKi8EaxctvANvHUKQ8RKanLn mYjLtkwMeZm4mrLvCpPAhUi/UjrSAGU3Y5WAezllCsSNSPbGlAeDYeF766c1hFW8a6wwEO GvAy8yI+domKogXGzCOPfC4K5Weit0k= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdo-000000001Ih-3IcY; Sun, 22 Dec 2024 21:57:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 02/11] x86/mm: add X86_FEATURE_INVLPGB definition. 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Signed-off-by: Rik van Riel --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..b7209d6c3a5f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* "invlpgb" INVLPGB instruction */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ From patchwork Mon Dec 23 02:55:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F3E7E7718D for ; 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bh=XkfGOJSqy4hVcRMB7cZA7dAORYByX/Np69HzIE+fTbc=; b=Il4OErN3oAltItEGiCF/aMfs6AnEB08MyfMe6GQmF8rMkelMyB8Y/tCXU06oyjqRvPDGl0 Kb9OUhOInqhoF0+AIpAKFisXT20MrV3joz0CoHPtygSLHhfK0gwDFdjjgCnXb2Nx2COnN2 fUaCwxN7PjnMPHjX+uJ7fo1f2cU19HI= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdo-000000001Ih-3jUV; Sun, 22 Dec 2024 21:57:56 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 03/11] x86/mm: get INVLPGB count max from CPUID Date: Sun, 22 Dec 2024 21:55:09 -0500 Message-ID: <20241223025751.3268975-4-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 6CDD240005 X-Stat-Signature: kriki8tgmxu9n9os6ng5wm6umrujabyz X-Rspam-User: X-HE-Tag: 1734922889-717194 X-HE-Meta: U2FsdGVkX1+xNCEzNCyrB/2gSM4jL/KptWThL0873t1LoqKcIg/bwwK5GqOm9EwAE3pxYnj+ujJ3godoYETCb5jGiT7eUbNd8omIzAYSKtGgdY+1+28QznoeXsEm6Q/bpM0FhOgFicausWOkhyiQ7mOK4Ow6wDJd7eV778nq+L7ZQZVMNPCQgXl7LMnoGWCR1QRR3usxipIgypIue21BN6eoJhcqJN5AsHlHh//3lLRjASYQ1GeoqB7A6krrn0aqyzCYQx1irjorDYHbAhH5heotCxoIKbhcuBxx8edfFIRbx7gyqx617B5FvKQlyk0MiNK6kA1HtpZSoGjoikwEUFBZkH5ZcDExU0N1DaPmDIgqontbdS02J131dwHFtPxCgvo6od2WR0jQcWfZXXJkxHA72vdo9IP/DAwWXwfFZI43EcO50eDhTDMuqQ/yMFzJyugvKucJxqqkNphJhaHEm3oZXMXK2VAmB72nupTTcbbwUoeKIW7tYUD1hH4/VZSCZ6H8gijTLLW5uxhmVnaKSJ4TRTrTMeYXjiHN25GcHSJ5mu8l8x5U/kvLriOQnkXvwdgQLIzYk5NMxZ6/G6K8yVkEd6PKEyUVKQaRqhK68c7aCmg/4NYcdsEzzS0pogseJIMD91j7ql0F8wnUXyXMoS6ez2WXaVOJ/fgG8NC0nRyk9eeODcpZXU0m0nZN3bYFbzACtGKk/zGJmoNJCpB2IzNZ2RqF4tSzU8jetvWpHdsUARtNof17hhB72NrgFXlYwhA+O7ldUOZnTDyD8aBvjrtUe16G8RYX5R5ZbMUpjC4yeq1nA96lZiwcA2oMl3XeDYd7wmrSf9B7sjjSg0lAg6yNYGlFCwSwtmai0dhfbT+1zp8NaVnaylWrdHls8FGNIVn5gzssrS9uW+vl2PL0qkHBZ562jsBw1jvQPKepEfZAJzY1pktEvt3sHG1mks45aDtwpT1XELuMhH3wGZg vqNA+aq7 HmWKg+Q0lrbYJe2ePWEaHGYcb0OOpdoR9Ao5jgU9uCG3pF8wfU/8Nw/ea3ZNeQ5ipyQ9fUJ1TbTM0by1O/71lkwLUHURU/0lyybBQKvZ/aEat5Dk7+2XFujX5LOwkKiOvzuC+IHO5NnpRBjwUgjhqoGFo/elNGkSlrNJaXpm9PVcS9ERcD17mzzDyUmIi5KvzhR3YKr9siSWsTtOtJy2Ivq6wKQNGcXaof3lmbesHLQNzWmchLkp3IDxjMG168iz0XogXgvcLY6cdoN/Zz6PJnUkXoVUsH1F519O0Opq8SKUaU5J5ty53SiqlOXsSBE8VwZqQ X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbflush.h | 1 + arch/x86/kernel/cpu/amd.c | 8 ++++++++ arch/x86/kernel/setup.c | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..7d1468a3967b 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -182,6 +182,7 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +extern u16 invlpgb_count_max; extern void initialize_tlbstate_and_flush(void); diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..226b8fc64bfc 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1135,6 +1135,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + if (c->extended_cpuid_level < 0x80000008) + return; + + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + + /* Max number of pages INVLPGB can invalidate in one shot */ + invlpgb_count_max = (edx & 0xffff) + 1; } static const struct cpu_dev amd_cpu_dev = { diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index f1fea506e20f..ef2b49edca25 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -138,6 +138,10 @@ __visible unsigned long mmu_cr4_features __ro_after_init; __visible unsigned long mmu_cr4_features __ro_after_init = X86_CR4_PAE; #endif +#ifdef CONFIG_CPU_SUP_AMD +u16 invlpgb_count_max; +#endif + #ifdef CONFIG_IMA static phys_addr_t ima_kexec_buffer_phys; static size_t ima_kexec_buffer_size; From patchwork Mon Dec 23 02:55:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AC4FE7718D for ; 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bh=yRu48wDyQbjXodzZ0IQCHNm8zDJ9Qrsyu2zd3npGVTA=; b=jtaDcNDO0ttwMomAlUhi3xk3pQHrs1OAT8N/JkaJ6EtMHhPHtA9NIJs7jTDt+ajc3LlOfK skT7u6xmIfTHmkFUjHu3G7ZR1qVavBtVCto4fxKobxHzFArzleeqHbd6dSsLl5QgSKhUFB 7o3S/RYkkWKWCPgNZkLtL7mwnAxqCKE= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdp-000000001Ih-079E; Sun, 22 Dec 2024 21:57:57 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 04/11] x86/mm: add INVLPGB support code Date: Sun, 22 Dec 2024 21:55:10 -0500 Message-ID: <20241223025751.3268975-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 9D8A9180005 X-Stat-Signature: u77ehgc7r8o7eu51o6cfcyhbbpxc1hm4 X-HE-Tag: 1734923015-385042 X-HE-Meta: U2FsdGVkX19WByLthZ7VViBtTAyhVk6UlgjgTfJIBCKMfgGON3JxMRMSiUOKbhOTIM72jCTAlszuSIzsP+ymnvZZqOgW5WPryHbiaCM6D1KU1wbz92RTPE9+ULVua9qJX3cxoNkoqqr8zXN4IEDlb5zoyw9vhu1UMoN6xIu658L+P8WQVhorw4OTGKRCpqXujjE8xO83M0BcYa41e6c/gybcXn2age+RI6Y+8ArtnYSl5IOlGQhcAlZw8duZtuznMITbV/JEGfKuRz2iUniJyGVg7kVdAiQa/o+GNtdg9nIaZgTBF7j05hLNFSnxXrDNehifKriXJPvSJjhZAbp5V1KV8Yohrf+A/Fb1a2NX2aPe/JJyy+wPs1GtXbfXRuBTnyGYTqpzDGaM2puzSG5kPk6edab1HislmuxRBkudOIhhSzl2m5CS4lrvutzbaj30nxjcxIR6aveZZ0EnosNFm+1lYMYuPJASBPLfyUcbRw2eWR+PzjVyySCi8L4yOhFSeCQEjQuPWPhh4KCH/Th9+MAoc0b8F1DLssABnGUpXNhAZQ/Y/yLtBupwJaGDQlF7Gu5zq7BedhdWZdmzvGUmvxqcOA2jX+JzHGw3VRphFW94jDxYFKZzrOOx3Clxg519IpoI0e90v1AcYkBCSKjQXHxvhbHQk74MhoztBQ0SOZ/EotShc9HJQRp6LMnGX+kqEi/aTv9Y4lUAkSK+oZTb3BQLL/Wp9xgCKwGYx4kWvdhFK/CW6ZyUicPRFHQhRZfQY0/OsQHTJLMjqcSHpo/iVPbrVP67moNX8byicvv9OH0ea6NGhBQXXhT4kPJl1HzndCIyupirkN+fU8U2GyiYVyuCrkgzpoWEJBIGNGXjomeb3fO9iHrb4GLt8JboGjmQenFyAR7WTCuZozg7fr0kMhtqfT/wfRMfvgN5g5ZwMGlPXIAD68ZCwRgA7aB9qFS1gYF34VaR1y06kZq0SB5 uFs7xqzO Bx5/tpkhJBwuiP52Na73Bfs7x0E5BzZrUxOV907UGk/Sf7tqE5Z4OPOfGCCtZ0ByzqghfLqTC3YXJ6Kuzh7zS5+4K1IO2d952n8P0i6q1sMwQFbpU0V+YuIbRryI0garjE480oGbluCNnQve1PkALCdmJSm6ROfHargw2RMr18+D7S1Oyuygo1XmbDnfnKxAZLeX3y/d1ORtws7t6JdaifsAWGIkZN6Zm6LlmxqW9Lhcnshlf6NRHJ9S4s9NfNxK9VNivSAkhDUA/6ZgV2Ah9Y8u7w7iRhugzAVA/K+SqPtLl3knWnigVl2l2kJM9QSLaxxQ4 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 93 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 94 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..862775897a54 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, unsigned long addr, + int extra_count, bool pmd_stride, unsigned long flags) +{ + u64 rax = addr | flags; + u32 ecx = (pmd_stride << 31) | extra_count; + u32 edx = (pcid << 16) | asid; + + asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); +} + +static inline void invlpgb_flush_user_nr(unsigned long pcid, unsigned long addr, + int nr, bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given ASID, not including globals. */ +static inline void invlpgb_flush_single_asid(unsigned long asid) +{ + __invlpgb(asid, 0, 0, 0, 0, INVLPGB_ASID); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr(unsigned long addr, int nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + asm volatile("tlbsync"); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 7d1468a3967b..20074f17fbcd 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include From patchwork Mon Dec 23 02:55:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2986E7718D for ; Mon, 23 Dec 2024 03:04:36 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 8BC476B0092; Sun, 22 Dec 2024 22:04:36 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 86CA76B0093; Sun, 22 Dec 2024 22:04:36 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 75AF86B0095; Sun, 22 Dec 2024 22:04:36 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id 4BE9D6B0092 for ; Sun, 22 Dec 2024 22:04:36 -0500 (EST) Received: from smtpin19.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id 14981AF96F for ; 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imf16.hostedemail.com; dkim=none; spf=pass (imf16.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1734923049; a=rsa-sha256; cv=none; b=JsDypIXqbc/EjhCJ1w7Lxlg/0YbgFN3qY/7YLMEPbb4dz+18eovglNBwjsnhvEKDaF8wFx O3vEADOxMs9oDaA1dME6/Xhz+Mb2Ox5DmLGIzahNU09xkKgcP83JTkwGJzH77rQ6o0zDnj wOMh/rG5I/535PTTFZZ74Y7rGD47Zis= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdp-000000001Ih-10Ae; Sun, 22 Dec 2024 21:57:57 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 05/11] x86/mm: use INVLPGB for kernel TLB flushes Date: Sun, 22 Dec 2024 21:55:11 -0500 Message-ID: <20241223025751.3268975-6-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam05 X-Stat-Signature: 4r8xdq5cje6ke988agnug5f1amm7mopd X-Rspamd-Queue-Id: 51EE4180006 X-Rspam-User: X-HE-Tag: 1734923036-588664 X-HE-Meta: U2FsdGVkX19oa4TGx5lD1ekfZIJ037tIaZK7/8NXwqf1jYWfonej5Kk/xvF/XAK36SG+W1o0RljJUnNdZa5i+tUzbKSrCkWZ97l4YKMKGWi6BprSbEG46EtrCemAghaH8bhML2gm/tGKiTlvVL0z75tW1PPg6q1IeN9BL1IW1s5pQ9KubKh+nA+B6tiw2eqF/KKvdIhCi+Fvu1za/sauhW28FptbuCyMp4KAeFx8LbRjZZUxtmiIBAk+eUpLQtJgnM8ROI5SFhvjivrhuS5iski2fpxtv5HtICz3C/vOz8BeWaPVobyFXa+2zVDnsU7krGHWwWXVQoc6raWseS6NEVs/lIzbPEcCcl6rp0t4SMqglJaIqkJzOd1cHLrJYllwcsxZ/OV7RG50ZYJ1zRysCvw9y3tNzsh/vd72MGtGw9XIKvjPydlDaVBnaLl+GzuhuINqUj0un/ojNGuJbfn9eJmkBhTTq6xh3ap5u8sftAOIhkZ5hq7sIy1PpWpneI+lATMbNYJcmJyZL/5rhbw8kA2e2pQ+VoVkwIIrSmb4xi/LyxUBcWZePXG+U2MxcRancWRZIEvDom5jLggfQApjPh+6qtZvQ6ooIsnVf2Wd2drw9DMf5t+sfvb7UP0j2X9OLUk9q7gsXidSFZLrZ+1O9VNyt47FBNmX0bvOLUONQU4CWw86UoAlXI4A7DTLv9dayQLvezhwhMM0gEKg1OxIy0SdfL5IXJRvUDIAaYWtwqjeQ3IooJCytte3QL0V8Y6B496Rh6+W2ciHCJZoVboWEfdFOptK6T1IXmhWQfWqbM5lJ8jH1fzgKbdNASSFf+tlvthFdGrCwruGsr9A6ib1l4QRV2TSY8dKpYba4nyneewzKcD9G4z9TlAftdzGyldRO6i+aCqC8mYzUbB8ahcjLvY4WTS9r8e4zSusKRgCDKuHtfAxDAhhLaWY1ft+DUDuequ2WbU5lGFigtkxxna 6aSo/VSd 5aAp9M758Tj27m+r5qYXi/iD3ALjCa/eX2JiX0aQpD0OX07S42cqexK934vYiFhErOYsrJPHp52qE0h72xAsIdvLr1B3aQx/I8Con0nE7DY4m6+PjSMLCLpz/q1EwdbfE4bJqvrZhi6WjjhziiN7sUCQx+9oaXyufDukndeuhY0pu3BRlVVZ2hx6LJjiyqIeCKasqfc6foPSX4keh76jfybGVy+X6ZPksHz+7PbkuyGKQD/79yRugH5KmVl5qUgYKmcg0N0bH+cZxvtiQeKanIxJxHw20lHG4TeA9wxxeDOI/ywXvLAgReesBaId8zO8X7DuE X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Use broadcast TLB invalidation for kernel addresses when available. This stops us from having to send IPIs for kernel TLB flushes. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 6cf881a942bb..29207dc5b807 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1077,6 +1077,32 @@ void flush_tlb_all(void) on_each_cpu(do_flush_tlb_all, NULL, 1); } +static void broadcast_kernel_range_flush(unsigned long start, unsigned long end) +{ + unsigned long addr; + unsigned long maxnr = invlpgb_count_max; + unsigned long threshold = tlb_single_page_flush_ceiling * maxnr; + + /* + * TLBSYNC only waits for flushes originating on the same CPU. + * Disabling migration allows us to wait on all flushes. + */ + guard(preempt)(); + + if (end == TLB_FLUSH_ALL || + (end - start) > threshold << PAGE_SHIFT) { + invlpgb_flush_all(); + } else { + unsigned long nr; + for (addr = start; addr < end; addr += nr << PAGE_SHIFT) { + nr = min((end - addr) >> PAGE_SHIFT, maxnr); + invlpgb_flush_addr(addr, nr); + } + } + + tlbsync(); +} + static void do_kernel_range_flush(void *info) { struct flush_tlb_info *f = info; @@ -1089,6 +1115,11 @@ static void do_kernel_range_flush(void *info) void flush_tlb_kernel_range(unsigned long start, unsigned long end) { + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + broadcast_kernel_range_flush(start, end); + return; + } + /* Balance as user space task's flush, a bit conservative */ if (end == TLB_FLUSH_ALL || (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) { From patchwork Mon Dec 23 02:55:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19781E77188 for ; Mon, 23 Dec 2024 03:05:09 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9CE666B008C; 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Sun, 22 Dec 2024 21:57:57 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 06/11] x86/tlb: use INVLPGB in flush_tlb_all Date: Sun, 22 Dec 2024 21:55:12 -0500 Message-ID: <20241223025751.3268975-7-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Stat-Signature: tmxrsd71x57xhy6nqgr6fg7aa749qxog X-Rspam-User: X-Rspamd-Queue-Id: D62D4A0007 X-Rspamd-Server: rspam08 X-HE-Tag: 1734923045-716676 X-HE-Meta: U2FsdGVkX1+zqQ84hLyhzv568rT+KLOJvx1tddGk6ub8lq8bnGNVV/gtJUdNszYo6JP5BDQjgsi7RFIUEOcSHCSb/Q/m2Craq7BsZcIqKctefE6GcL5CA7rzLqpjlJ4ukoG0dat98ZkeBAW36/tW7BHKxAfzP6yMDQGJUH4VcP5Es9ogz+vSEGTA6cMj+X4gmo+iAtRK0sF6WVLpZ5W8JQanAJfLHHbTr0QqDJ/McMaxQ/8sCBnLPcAg8uFrFys5JWB8T1f0Vfh18BgZBJZZX5KEpOhnqaOX0z+dEkTLxNG3omD2lstfo15QCo4hYKXb0R+8dN7TjsHV5eSQu4AXdoThwQAKZnXUTs53REG50nAMRuFCpro1/qMOkuwB0IgJrEV3wuMPDk/bv0ERaJlk1uTUAUOZMIzv4NYvNcBHGaMaH7wFDCHZzep20o6BM0D5joB89LUH7spwTGHjDpL6WGb92ZiOLspq6e3SMVI6+zi3C1FxZzr7s7CKEA52b7xGuBasQs5I+TcZqwkNBDfhKVZoRe8Bjn/WM5R5I7GxDJSrEtA7fnz18ffTpFV0GFmO2puXvK2qlIW/vxLSHON1lOCZEBVjPQ9P7BkX6VpbW5HTBkydqZ4IhB4NWjIfxNkB8GeRaJrs6IqKyREHPf5hGMSexVsC0+fAHDhBx88YD5dK+4562P8c/7R57Cm14kuiMaeZ+lCbw88pyZ+bQ++t91/xgv5LEWez86xRU2u3YIiIBmQyL9+6WOK06ta6l6oD8Sfp3CRiiQnTZ3vcMhlffjybNCn99MrSbIm5Um/chdusdbiOF0B6iwsMe7R2FaEIWQxI6Z//ayYNDm2MObKpRxv+M5YZ/pu9blE1Yay4A1GPIFxLx4N4hmYe7hkiKYhm6C4ketViluptc88nU6H4bNHmepkQpZi5FopPNPix7nbqguKMYVpnecsWtgEQVr5c6cNvsCAyxEsxwgPOGJN DycZVEQP kANhRWUA7Ts1vzVNiPVKB8vx9tHb5nkead83HD/rCSrrPfv+3oABbeFyW1QKS4BgOFktzfQqd59D24hSuapxV2fV0FiigxcwmouhlxeDbQavF8E7T7nC5+MmcyR8jJVkJT7rCE5C5/oY8DkL2YFER2WbRcmwCly3up8cuH47v5kMOZdXhnejKvOHvnygxmfX3R5ntrf3Y9yjXUwkRUSDy59aLRT8bz9Nv7Jj4LuNKR0VZReSApkAZ06j1GWD7uL4ycqWtwNmUZ+Eof+KODO0FfwY4L3MNXho9ppHkuTseYt+1LEEBI9srnVnwOsp8q3y/nSr8kdEdl4pNjKCfFKU7jByakXsV+FDkSSRS86fKhymEa/Y= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The flush_tlb_all() function is not used a whole lot, but we might as well use broadcast TLB flushing there, too. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 29207dc5b807..266d5174fc7b 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1074,6 +1074,12 @@ static void do_flush_tlb_all(void *info) void flush_tlb_all(void) { count_vm_tlb_event(NR_TLB_REMOTE_FLUSH); + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + guard(preempt)(); + invlpgb_flush_all(); + tlbsync(); + return; + } on_each_cpu(do_flush_tlb_all, NULL, 1); } From patchwork Mon Dec 23 02:55:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D69BE77188 for ; Mon, 23 Dec 2024 03:03:40 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id B06BE6B0088; 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Sun, 22 Dec 2024 21:57:57 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 07/11] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Date: Sun, 22 Dec 2024 21:55:13 -0500 Message-ID: <20241223025751.3268975-8-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 432C2180009 X-Stat-Signature: wqgam7nmb9pd47rp7m6iqkffqhsa4rmt X-Rspam-User: X-Rspamd-Server: rspam09 X-HE-Tag: 1734922991-745915 X-HE-Meta: U2FsdGVkX18mSKbnKNsbtBe4SFOq94Ffr+S0skUW0kRhjZ89KYnGetNuiGB92ndjl2ZRzuhQPtPuLgFV533E+8r805/X+3yzGtn+sFL5XlQlnxSxA6inDQh+YSbH8uhpxlnBFcXW8eaxj3nkB4WFav870hqLhyFwGuFYX6nYtdeJ8LLioL32zxS8rZuMVBcohnfzjqfEzAbNmhqTdtXuqLNvnqKEjCsoTgTJYPvFAdIL4TNAZ/cIGMTUY8AOp0HxUY/KINSQ1UG5MQ96qCB9j36QLI+d18isLCpr7hvqhmwDE7cDmyi4YHX5yP8BrpC1gFC3vC87DssBSb6Kw4xm9/nEZiu+mClTeO+wV4OG5oeoFFTQSOlmS6721cM9TwhJ+PP8Vax1sg9W8uWzCCC1n4DrBzrrz+Cl0oq0oepqSruFXj1lDVEWjUsfuH5PQqHdmCeYmbVkHdeHWkSNL3CBKm8D71ZGqD8f/fhC1w0JZk/xMSf4rx/zTAkue90n2gnB2OQ7QE8GsqKc7A7v3Z/V/G6fdWCFt3FycR/YWr6YMVex6ieDhicf90gH18qhNTXIZ2eSE0SorAC/r7iWUZxYtVwvbiyyM9U9vGz9OlXp5/IzBwskkbyMmGmr+xexYILHvK7sBRylgSTHONMN1OechbdaGp/s0ShKl+k9GBvCGFEoZgo4UBfbCGnGWdwGWB3MmG6EmddwAmyxzrpxwWVIUfm4BhmoeamibrdSMp9xMadMA7xNcoxLKtBnGA5VQUY8WJKIYOg7x8bAzJqDZaKq8c8EodTv8D/oR8WXUpGHbU2H4L1QHg0wBUbE11jTZecmjQm/ikDHvsrIJewPo3fAJydumrzw8amMaPwaOwcM4XpzEZEEPpXNb+nd1UOSr2IPTFE6GBV06rC+BAFwgVJdrWlAghhaIjIKTANK+0b2hqpQzeKnsAg8ILkikPkoQkPAqLCkrV8RcRRdL+2x9SD YZ/5wtsp kBoT/xQ5U50t1zaN5u5winv7A+JTp5rS0tsfEZZEWhgCHQsMmrD5YzNunSlPdk9mWQusM0qIeeXDkbW4naH3MrGXCU+URS2mmic8fISXVwC+d3XtNFodpN8u9VbImLjnxbyfsz1n8hyRafh3NQRS6X5DIYDZGe62nb4l5BRsScFl7xmhP6Z0jMTc3n6N+Hk4j/zx18wLLKIXWcK8pnqnk4IHnNdrYG94Ji9N8xi/T3ZxqmCyIEJzEiZxmyxK7SSmDH1B2ceT3ftJRAX21R0PX66x6eeR1tSnuh3kWY4rqmt742prfpEhnVjRoLOLHh8CJRm9A X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: In the page reclaim code, we only track the CPU(s) where the TLB needs to be flushed, rather than all the individual mappings that may be getting invalidated. Use broadcast TLB flushing when that is available. Signed-off-by: Rik van Riel --- arch/x86/mm/tlb.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 266d5174fc7b..64f1679c37e1 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1310,8 +1310,16 @@ EXPORT_SYMBOL_GPL(__flush_tlb_all); void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { struct flush_tlb_info *info; + int cpu; + + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { + guard(preempt)(); + invlpgb_flush_all_nonglobals(); + tlbsync(); + return; + } - int cpu = get_cpu(); + cpu = get_cpu(); info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, TLB_GENERATION_INVALID); From patchwork Mon Dec 23 02:55:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 105A4E7718D for ; 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imf24.hostedemail.com; dkim=none; spf=pass (imf24.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdp-000000001Ih-3H0e; Sun, 22 Dec 2024 21:57:57 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 08/11] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Date: Sun, 22 Dec 2024 21:55:14 -0500 Message-ID: <20241223025751.3268975-9-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 54D1A18000D X-Stat-Signature: 44nek6u695dpgjgdu1rd88ru6wf6fp33 X-Rspam-User: X-HE-Tag: 1734923167-824009 X-HE-Meta: U2FsdGVkX1/g8RoE8w9xDPFezfYpD1oTIJuHG6eawesUk0LSWet9KPBr0+EyPEBF8Nfy1Nm4IV0WCdjxdhScYQq22D9UC+DrxiatB/g7KsH699HhPbizkMfYhhMDO8z0TQ/Dzm8vINmEkpVqWQR8f1ok3wgfxfXgPT2YapVOOqY68DdAsHcyzl5RdnBDTuHy9iYg6rsNNUCtCyr2GiYvBsM7cc/CjXtBCzH2xmnaML6zFheLoBu7aemTVo2Vr552jNfq0UDfR+QCRzKUojawL59fZaAbOfwrN9TybbHggDwlK+gF1IU0jR/nb4EUc9IwzIztdNEjv6093kh8H+267n8WWJpng9SzBBIOX+7PUfzf/CJCSgGFTwJhXpB/Ve8cm/bxbOFCsgkBn5M5K+cmQx2TdHurREfafwKYNd1RT2gv9ffZo4xyR81JMkORKVy345w8BY+KXRlxVRfnBN6qpa0vwPVnRTPWP7Cg5LpSOVKPBRyKzO+Fqp4LofFtzDYPWAR15PYndIu5PJC64jt85IdhxGEMBU57oVvGozL7YVtIsyJEzgYAbRXfCurt36MmWp71oWsMDI0o/hv5I229hD6EMjZI7z1QyDNULffJUkTW02ZMFF7/eFg8Bvyv8/lHXbIF4P8A8nDYNto7E1vi2Hy+whEOf23qDtrCeKw3bSO6Kt9OJjMoltA0egi1j1L3OWmwr9dhq9X0PZsGlSXQEtwcsGTBMtSVhoXe3izCAPDxL5iKSn0AIAQoYzilaZMBlmOgQFdezuM0abwCu1t9+xFJjyCbyRlq6zY8gp90b1VNeU5aj1AeGMSg4deDlWGEFKeQHgjGfprgOCShO/Rgo7N0/aKxK1DiU6TuOWRkiV+fYRvqBucvNferfafp4hVyA5YZeZDyntEn2A9xz44hf8aEm6x9U9Gt4bwM8Yk2YFwzP0Q84Klczwkl+XZoyXGvZVZxl97plabUAME6FiJ CJzqGUXF z2QCMj2y69PIZbn22Bm/fZHzLi8r64OxNrSqBrZe1qsAxjLmyKAmquui7QjIkcBU+3IAVbK/VSL3dJRIudhJZlHXK9ApP8ktSRC4jRD9vaL0OicHfSTNlf68bqiJTw5S04Ksd9OsDeJ9do7sLh6h3wEGpm9jgwUr9aZ5ypsRjVabvTR/8lu5Igg5NElS4BqLTeQ1fEr1txoRBBiHtj1g3uvG64lIQAfmj13yYdXqa0kIuExskfvcNSAZG5lE8OEpIhh2pqq1E43nDn+VOMU+gF96mLb+qP8BoSnw6ynZtQu53agJtWLjXohkKvZ2xEWa0rhT4 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Use broadcast TLB invalidation, using the INVPLGB instruction, on AMD EPYC 3 and newer CPUs. In order to not exhaust PCID space, and keep TLB flushes local for single threaded processes, we only hand out broadcast ASIDs to processes active on 3 or more CPUs, and gradually increase the threshold as broadcast ASID space is depleted. Signed-off-by: Rik van Riel --- arch/x86/include/asm/mmu.h | 6 + arch/x86/include/asm/mmu_context.h | 12 ++ arch/x86/include/asm/tlbflush.h | 15 ++ arch/x86/mm/tlb.c | 313 ++++++++++++++++++++++++++++- 4 files changed, 337 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 3b496cdcb74b..a8e8dfa5a520 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -48,6 +48,12 @@ typedef struct { unsigned long flags; #endif +#ifdef CONFIG_CPU_SUP_AMD + struct list_head broadcast_asid_list; + u16 broadcast_asid; + bool asid_transition; +#endif + #ifdef CONFIG_ADDRESS_MASKING /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index 795fdd53bd0a..0dc446c427d2 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -139,6 +139,8 @@ static inline void mm_reset_untag_mask(struct mm_struct *mm) #define enter_lazy_tlb enter_lazy_tlb extern void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk); +extern void destroy_context_free_broadcast_asid(struct mm_struct *mm); + /* * Init a new mm. Used on mm copies, like at fork() * and on mm's that are brand-new, like at execve(). @@ -161,6 +163,13 @@ static inline int init_new_context(struct task_struct *tsk, mm->context.execute_only_pkey = -1; } #endif + +#ifdef CONFIG_CPU_SUP_AMD + INIT_LIST_HEAD(&mm->context.broadcast_asid_list); + mm->context.broadcast_asid = 0; + mm->context.asid_transition = false; +#endif + mm_reset_untag_mask(mm); init_new_context_ldt(mm); return 0; @@ -170,6 +179,9 @@ static inline int init_new_context(struct task_struct *tsk, static inline void destroy_context(struct mm_struct *mm) { destroy_context_ldt(mm); +#ifdef CONFIG_CPU_SUP_AMD + destroy_context_free_broadcast_asid(mm); +#endif } extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 20074f17fbcd..074f46b74b92 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -65,6 +65,21 @@ static inline void cr4_clear_bits(unsigned long mask) */ #define TLB_NR_DYN_ASIDS 6 +#ifdef CONFIG_CPU_SUP_AMD +#define is_dyn_asid(asid) (asid) < TLB_NR_DYN_ASIDS +#define is_broadcast_asid(asid) (asid) >= TLB_NR_DYN_ASIDS +#define in_asid_transition(info) (info->mm && info->mm->context.asid_transition) +#else +#define is_dyn_asid(asid) true +#define is_broadcast_asid(asid) false +#define in_asid_transition(info) false + +inline bool needs_broadcast_asid_reload(struct mm_struct *next, u16 prev_asid) +{ + return false; +} +#endif + struct tlb_context { u64 ctx_id; u64 tlb_gen; diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 64f1679c37e1..29a64f8c4c94 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -74,13 +74,15 @@ * use different names for each of them: * * ASID - [0, TLB_NR_DYN_ASIDS-1] - * the canonical identifier for an mm + * the canonical identifier for an mm, dynamically allocated on each CPU + * [TLB_NR_DYN_ASIDS, MAX_ASID_AVAILABLE-1] + * the canonical, global identifier for an mm, identical across all CPUs * - * kPCID - [1, TLB_NR_DYN_ASIDS] + * kPCID - [1, MAX_ASID_AVAILABLE] * the value we write into the PCID part of CR3; corresponds to the * ASID+1, because PCID 0 is special. * - * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS] + * uPCID - [2048 + 1, 2048 + MAX_ASID_AVAILABLE] * for KPTI each mm has two address spaces and thus needs two * PCID values, but we can still do with a single ASID denomination * for each mm. Corresponds to kPCID + 2048. @@ -225,6 +227,18 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, return; } + /* + * TLB consistency for this ASID is maintained with INVLPGB; + * TLB flushes happen even while the process isn't running. + */ +#ifdef CONFIG_CPU_SUP_AMD + if (static_cpu_has(X86_FEATURE_INVLPGB) && next->context.broadcast_asid) { + *new_asid = next->context.broadcast_asid; + *need_flush = false; + return; + } +#endif + if (this_cpu_read(cpu_tlbstate.invalidate_other)) clear_asid_other(); @@ -251,6 +265,248 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, *need_flush = true; } +#ifdef CONFIG_CPU_SUP_AMD +/* + * Logic for AMD INVLPGB support. + */ +static DEFINE_RAW_SPINLOCK(broadcast_asid_lock); +static u16 last_broadcast_asid = TLB_NR_DYN_ASIDS; +static DECLARE_BITMAP(broadcast_asid_used, MAX_ASID_AVAILABLE) = { 0 }; +static LIST_HEAD(broadcast_asid_list); +static int broadcast_asid_available = MAX_ASID_AVAILABLE - TLB_NR_DYN_ASIDS - 1; + +static void reset_broadcast_asid_space(void) +{ + mm_context_t *context; + + lockdep_assert_held(&broadcast_asid_lock); + + /* + * Flush once when we wrap around the ASID space, so we won't need + * to flush every time we allocate an ASID for boradcast flushing. + */ + invlpgb_flush_all_nonglobals(); + tlbsync(); + + /* + * Leave the currently used broadcast ASIDs set in the bitmap, since + * those cannot be reused before the next wraparound and flush.. + */ + bitmap_clear(broadcast_asid_used, 0, MAX_ASID_AVAILABLE); + list_for_each_entry(context, &broadcast_asid_list, broadcast_asid_list) + __set_bit(context->broadcast_asid, broadcast_asid_used); + + last_broadcast_asid = TLB_NR_DYN_ASIDS; +} + +static u16 get_broadcast_asid(void) +{ + lockdep_assert_held(&broadcast_asid_lock); + + do { + u16 start = last_broadcast_asid; + u16 asid = find_next_zero_bit(broadcast_asid_used, MAX_ASID_AVAILABLE, start); + + if (asid >= MAX_ASID_AVAILABLE) { + reset_broadcast_asid_space(); + continue; + } + + /* Try claiming this broadcast ASID. */ + if (!test_and_set_bit(asid, broadcast_asid_used)) { + last_broadcast_asid = asid; + return asid; + } + } while (1); +} + +/* + * Returns true if the mm is transitioning from a CPU-local ASID to a broadcast + * (INVLPGB) ASID, or the other way around. + */ +static bool needs_broadcast_asid_reload(struct mm_struct *next, u16 prev_asid) +{ + u16 broadcast_asid = next->context.broadcast_asid; + + if (broadcast_asid && prev_asid != broadcast_asid) + return true; + + if (!broadcast_asid && is_broadcast_asid(prev_asid)) + return true; + + return false; +} + +void destroy_context_free_broadcast_asid(struct mm_struct *mm) +{ + if (!mm->context.broadcast_asid) + return; + + guard(raw_spinlock_irqsave)(&broadcast_asid_lock); + mm->context.broadcast_asid = 0; + list_del(&mm->context.broadcast_asid_list); + broadcast_asid_available++; +} + +static int mm_active_cpus(struct mm_struct *mm) +{ + int count = 0; + int cpu; + + for_each_cpu(cpu, mm_cpumask(mm)) { + /* Skip the CPUs that aren't really running this process. */ + if (per_cpu(cpu_tlbstate.loaded_mm, cpu) != mm) + continue; + + if (per_cpu(cpu_tlbstate_shared.is_lazy, cpu)) + continue; + + count++; + } + return count; +} + +/* + * Assign a broadcast ASID to the current process, protecting against + * races between multiple threads in the process. + */ +static void use_broadcast_asid(struct mm_struct *mm) +{ + guard(raw_spinlock_irqsave)(&broadcast_asid_lock); + + /* This process is already using broadcast TLB invalidation. */ + if (mm->context.broadcast_asid) + return; + + mm->context.broadcast_asid = get_broadcast_asid(); + mm->context.asid_transition = true; + list_add(&mm->context.broadcast_asid_list, &broadcast_asid_list); + broadcast_asid_available--; +} + +/* + * Figure out whether to assign a broadcast (global) ASID to a process. + * We vary the threshold by how empty or full broadcast ASID space is. + * 1/4 full: >= 4 active threads + * 1/2 full: >= 8 active threads + * 3/4 full: >= 16 active threads + * 7/8 full: >= 32 active threads + * etc + * + * This way we should never exhaust the broadcast ASID space, even on very + * large systems, and the processes with the largest number of active + * threads should be able to use broadcast TLB invalidation. + */ +#define HALFFULL_THRESHOLD 8 +static bool meets_broadcast_asid_threshold(struct mm_struct *mm) +{ + int avail = broadcast_asid_available; + int threshold = HALFFULL_THRESHOLD; + int mm_active_threads; + + if (!avail) + return false; + + mm_active_threads = mm_active_cpus(mm); + + /* Small processes can just use IPI TLB flushing. */ + if (mm_active_threads < 3) + return false; + + if (avail > MAX_ASID_AVAILABLE * 3 / 4) { + threshold = HALFFULL_THRESHOLD / 4; + } else if (avail > MAX_ASID_AVAILABLE / 2) { + threshold = HALFFULL_THRESHOLD / 2; + } else if (avail < MAX_ASID_AVAILABLE / 3) { + do { + avail *= 2; + threshold *= 2; + } while ((avail + threshold ) < MAX_ASID_AVAILABLE / 2); + } + + return mm_active_threads > threshold; +} + +static void count_tlb_flush(struct mm_struct *mm) +{ + if (!static_cpu_has(X86_FEATURE_INVLPGB)) + return; + + /* Check every once in a while. */ + if ((current->pid & 0x1f) != (jiffies & 0x1f)) + return; + + if (meets_broadcast_asid_threshold(mm)) + use_broadcast_asid(mm); +} + +static void finish_asid_transition(struct flush_tlb_info *info) +{ + struct mm_struct *mm = info->mm; + int bc_asid = mm->context.broadcast_asid; + int cpu; + + if (!mm->context.asid_transition) + return; + + for_each_cpu(cpu, mm_cpumask(mm)) { + if (READ_ONCE(per_cpu(cpu_tlbstate.loaded_mm, cpu)) != mm) + continue; + + /* + * If at least one CPU is not using the broadcast ASID yet, + * send a TLB flush IPI. The IPI should cause stragglers + * to transition soon. + */ + if (per_cpu(cpu_tlbstate.loaded_mm_asid, cpu) != bc_asid) { + flush_tlb_multi(mm_cpumask(info->mm), info); + return; + } + } + + /* All the CPUs running this process are using the broadcast ASID. */ + mm->context.asid_transition = 0; +} + +static void broadcast_tlb_flush(struct flush_tlb_info *info) +{ + bool pmd = info->stride_shift == PMD_SHIFT; + unsigned long maxnr = invlpgb_count_max; + unsigned long asid = info->mm->context.broadcast_asid; + unsigned long addr = info->start; + unsigned long nr; + + /* Flushing multiple pages at once is not supported with 1GB pages. */ + if (info->stride_shift > PMD_SHIFT) + maxnr = 1; + + if (info->end == TLB_FLUSH_ALL) { + invlpgb_flush_single_pcid(kern_pcid(asid)); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_single_pcid(user_pcid(asid)); + } else do { + /* + * Calculate how many pages can be flushed at once; if the + * remainder of the range is less than one page, flush one. + */ + nr = min(maxnr, (info->end - addr) >> info->stride_shift); + nr = max(nr, 1); + + invlpgb_flush_user_nr(kern_pcid(asid), addr, nr, pmd); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr(user_pcid(asid), addr, nr, pmd); + addr += nr << info->stride_shift; + } while (addr < info->end); + + finish_asid_transition(info); + + /* Wait for the INVLPGBs kicked off above to finish. */ + tlbsync(); +} +#endif /* CONFIG_CPU_SUP_AMD */ + /* * Given an ASID, flush the corresponding user ASID. We can delay this * until the next time we switch to it. @@ -556,8 +812,9 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ if (prev == next) { /* Not actually switching mm's */ - VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != - next->context.ctx_id); + if (is_dyn_asid(prev_asid)) + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != + next->context.ctx_id); /* * If this races with another thread that enables lam, 'new_lam' @@ -573,6 +830,23 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); + /* + * Check if the current mm is transitioning to a new ASID. + */ + if (needs_broadcast_asid_reload(next, prev_asid)) { + next_tlb_gen = atomic64_read(&next->context.tlb_gen); + + choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); + goto reload_tlb; + } + + /* + * Broadcast TLB invalidation keeps this PCID up to date + * all the time. + */ + if (is_broadcast_asid(prev_asid)) + return; + /* * If the CPU is not in lazy TLB mode, we are just switching * from one thread in a process to another thread in the same @@ -626,8 +900,10 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, barrier(); } +reload_tlb: new_lam = mm_lam_cr3_mask(next); if (need_flush) { + VM_BUG_ON(is_broadcast_asid(new_asid)); this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); load_new_mm_cr3(next->pgd, new_asid, new_lam, true); @@ -746,7 +1022,7 @@ static void flush_tlb_func(void *info) const struct flush_tlb_info *f = info; struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); - u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + u64 local_tlb_gen; bool local = smp_processor_id() == f->initiating_cpu; unsigned long nr_invalidate = 0; u64 mm_tlb_gen; @@ -769,6 +1045,16 @@ static void flush_tlb_func(void *info) if (unlikely(loaded_mm == &init_mm)) return; + /* Reload the ASID if transitioning into or out of a broadcast ASID */ + if (needs_broadcast_asid_reload(loaded_mm, loaded_mm_asid)) { + switch_mm_irqs_off(NULL, loaded_mm, NULL); + loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); + } + + /* Broadcast ASIDs are always kept up to date with INVLPGB. */ + if (is_broadcast_asid(loaded_mm_asid)) + return; + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) != loaded_mm->context.ctx_id); @@ -786,6 +1072,8 @@ static void flush_tlb_func(void *info) return; } + local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID && f->new_tlb_gen <= local_tlb_gen)) { /* @@ -953,7 +1241,7 @@ STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask, * up on the new contents of what used to be page tables, while * doing a speculative memory access. */ - if (info->freed_tables) + if (info->freed_tables || in_asid_transition(info)) on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true); else on_each_cpu_cond_mask(should_flush_tlb, flush_tlb_func, @@ -1026,14 +1314,18 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, bool freed_tables) { struct flush_tlb_info *info; + unsigned long threshold = tlb_single_page_flush_ceiling; u64 new_tlb_gen; int cpu; + if (static_cpu_has(X86_FEATURE_INVLPGB)) + threshold *= invlpgb_count_max; + cpu = get_cpu(); /* Should we flush just the requested range? */ if ((end == TLB_FLUSH_ALL) || - ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) { + ((end - start) >> stride_shift) > threshold) { start = 0; end = TLB_FLUSH_ALL; } @@ -1049,9 +1341,12 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start, * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { + if (IS_ENABLED(CONFIG_CPU_SUP_AMD) && mm->context.broadcast_asid) { + broadcast_tlb_flush(info); + } else if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids) { info->trim_cpumask = should_trim_cpumask(mm); flush_tlb_multi(mm_cpumask(mm), info); + count_tlb_flush(mm); } else if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) { lockdep_assert_irqs_enabled(); local_irq_disable(); From patchwork Mon Dec 23 02:55:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB0E8E77188 for ; Mon, 23 Dec 2024 03:06:40 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 49E756B008A; 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Sun, 22 Dec 2024 21:57:58 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 09/11] x86,tlb: do targeted broadcast flushing from tlbbatch code Date: Sun, 22 Dec 2024 21:55:15 -0500 Message-ID: <20241223025751.3268975-10-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam06 X-Rspamd-Queue-Id: 3E8E81A0008 X-Rspam-User: X-Stat-Signature: sywu95nsg1bo4dpafrx1ntfzmomtckr1 X-HE-Tag: 1734923159-857383 X-HE-Meta: U2FsdGVkX1/ZFpgM2A4aPnzIlV2CQlUjIK3r8/HgQEhFAwE4LPbxVFwAzVOEv86+Ii2YlYNoy8gEZf67f5ztiiiHdNLYP9xgYIi8iUWFvhrl5bBvGbgGJc/GOCCt7T9d4vWAkMinfxf3ormUxxld2OTatsJNF9uQwo27cPDZ1pXdAP9/zB/y3UPqdM9+xHGSfeznAeDJUaSIIkJ1vMG74WSgG/F8BI61uELj2gmh8J6hepv4tRzDa3WTLzvxYm8sCYm5cXyXF6+DiMhRm+LSjAdGX2UTg0NMz4BdXTBmgjVOCKDh52dr6niIOEudQEPry3aygY/Flbw9yH30Fry08AoAXCIyZZdEGR2r1MYkKuBYDITiIqoWrsIj2YcDIX7d0CJFql0CgAxPau9xbjCmSs8Zrr46sXsfsGqqVMFYl1cW4dcsf6QHc8oq846z4aCnaQJ++Q8tWsTBV+u2OJStXJJ9SBAUtwZIYKVTnCe/jJ1dxV44aAo9a/HvYt+5dzs7YvhjY1h5zNwoZswV+VRPgt9xhOPGIl4yzi215EDnVk5Of+aFLXCHy8BY9X1XqsUR5rmfpYnWlzuD2c+SAOAU4li0roR9Ir96X+ExPUdVyVWhnn8QcIgp4VJkMZNU0OseFl36P8+gD5LRwuXYdx5OfqD6KS/g52H2tRzVDIRqhsJlds+DCBtgyjnDqOeULuIWDNkiwlMfdKAEFjO+KaNXBu3m19dkzIdt3qtkFdlT93gzYuajD5NSyTXQ8/mZ/IMTOxz3ynQ+Yh1cOdDjw9uhoXYBeAMsyr7lGsQ1jPKB6enMzmIOn3mczoViyxuMkcGC2savdYjXZawU2DpQKkQWBaVIa4j9E6K19ssUNUFvDfLM+K3I6sDtABr+OHgqIxoBtsoFDg15H3GbKrDhc/L/dvLIT2etcSX7J1oqM76bKhgPA3vsSj6S1RGA6N6NlhWVPbLBFSjJINg/NTGalOP IqYZxl7z l9QMKSc789s8tsvmWsqAf3mfUkNoTpvOImduQ9Xm768S0fm/MMgimUXRKsyoyXKu2eSZvVUQHxX8++caxbDN6xssMkL9mVh6Wa/QD9QYw29wCEYlNDC6T5kLheucWhPko8SDKE9BVmNdN2pAIOKVlF9gpbQzJuhmRjLvGsqHpJR55eieNdkef0Y2BYNbFlfASY70Yxq8bwkQvWRN+CbSncBC4O8bO2o2k82XdVJ/nwIlN92IJBxmp88M0DCDfPZqjQRcOH3rYYFl76kyTPUCz2AMZnAosadPCT7eJqts3qGz7TXQwniGkrYHsPJjfJ8QYDaHY X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbbatch.h | 1 + arch/x86/include/asm/tlbflush.h | 12 +++------ arch/x86/mm/tlb.c | 48 ++++++++++++++++++++++++++------- 3 files changed, 42 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/tlbbatch.h b/arch/x86/include/asm/tlbbatch.h index 1ad56eb3e8a8..f9a17edf63ad 100644 --- a/arch/x86/include/asm/tlbbatch.h +++ b/arch/x86/include/asm/tlbbatch.h @@ -10,6 +10,7 @@ struct arch_tlbflush_unmap_batch { * the PFNs being flushed.. */ struct cpumask cpumask; + bool used_invlpgb; }; #endif /* _ARCH_X86_TLBBATCH_H */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 074f46b74b92..71d094841356 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -295,21 +295,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 29a64f8c4c94..c5459516a72e 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1605,16 +1605,7 @@ EXPORT_SYMBOL_GPL(__flush_tlb_all); void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) { struct flush_tlb_info *info; - int cpu; - - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - guard(preempt)(); - invlpgb_flush_all_nonglobals(); - tlbsync(); - return; - } - - cpu = get_cpu(); + int cpu = get_cpu(); info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, TLB_GENERATION_INVALID); @@ -1632,12 +1623,49 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB) && batch->used_invlpgb) { + tlbsync(); + migrate_enable(); + batch->used_invlpgb = false; + } + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm->context.broadcast_asid) { + u16 asid = mm->context.broadcast_asid; + /* + * Queue up an asynchronous invalidation. The corresponding + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done + * on the same CPU. + */ + if (!batch->used_invlpgb) { + batch->used_invlpgb = true; + migrate_disable(); + } + invlpgb_flush_user_nr(kern_pcid(asid), uaddr, 1, 0); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr(user_pcid(asid), uaddr, 1, 0); + } else { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or From patchwork Mon Dec 23 02:55:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EBFEE7718D for ; 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imf22.hostedemail.com; dkim=none; spf=pass (imf22.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdq-000000001Ih-0scS; Sun, 22 Dec 2024 21:57:58 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 10/11] x86/mm: enable AMD translation cache extensions Date: Sun, 22 Dec 2024 21:55:16 -0500 Message-ID: <20241223025751.3268975-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 58AD7C0003 X-Stat-Signature: r48dxqk633crdxspxodpgm5jyztercyd X-Rspam-User: X-HE-Tag: 1734922953-558361 X-HE-Meta: U2FsdGVkX1/D/EgZcV0ah9+SGy8wB7XJVGYpfe0Lw7iAUc39KB4JyewZseuYHLxrqRZc/sHeiAXBMx/ssGMDfhvv0jnbRwF+oGwFF5XQ+pwEECL36MMSy0T4rfLmCAns1mETtLvm8KtK1CZfutH0hCUwflFX3AucDB2mjssCGo8XZhMFvk3WO3aAzZCz9zg9Dwf0bEeq5MSbmJBBCNk1w8AT3e7UmC8iofm4PPiaMukJuzYTCYH5ErnaDj4PxUe3UEODltZyx8wW5QEDucIqKTgqXsjvdHe7UTv8EFFHgNZ27F63/0w2unTU1F3Y575ubfaworGpF0j2pBlJDN98O4/TCqF5rEMPmzrAvzKTmnQYgq8lmbPtRl6dUOuZA02cUg5ogmsWfugG05HkeA2WZOfcPvmFmFZpLrlfyFZ9e9BoeHGPj48sb90VRudaoZqN2w9wCliRBp9iW7/ZTYsYfpOWSU6BXTXS83Q2bqarGDBBKo3VKzJnYfzhUbGugCIztFjQ18ZKJuU8T6KKoZJgEnhFlEJjGUOCUHsVUJuPuBNyH7yOtX/mP7e9S6zBVST7UtO6YThph2BkOr2dpJL6P+HtE/E5YERHu9VoPF02EslERDsu1SoIwErsu1B7oYW4yhZTxlv+1BhH65PxAOLVmqquzjIkTQN9VtyDZP1/IpWUZuG9AQ2srfGwbQsjrjQerlFig5H7AOOD+0mASHDb7mP/Zfb2kjzwdIqHglu54eEAnE1w1ph5MTcOkkcZoSi7E9sGxMzp6/hWdy9Na8Qy90M9YxZpkj8hORvck5Kjv2Az1updinP2DhVPyM30Y8/PvLsHpgwdsSqnC1QbDzQU9vFZYzEucDDeGX4qOhikDGii9SbFe6KTxpo84DIeXAonrIM1hs9v+KuQUiBe/R6wQw9WLehMRZHWm9WW1gGLCNBTMzSLDQRZRIwWKZCpQX6KbN1/bVhQBuxBpQI8Jgi 8jM/esr/ QmPMJEqmZ3re1fJcyzaUSKeRsbMvoRPEAGxiA78j2+Hj6hNl7iW/u/FS463xeI1kaHW055BIr0Y4BpOumo9hIwQMcZwILnyFWIDoHvYAobBKJMjfj+oGxZQNVnpXlz/fZZeIfEqwvZw/PN4dCq2wwHqu4W+OCs5MbfMv4i+BNMQaEiimBPuPDYHCWJZ8lTqdwjIonSCwbYXRb9g1V+gKx2x+lDCvM21+dnZKVUJsEsTUPA9ysJqZFTelretgMBDhqjWNTaF3ZbKMBFBrdIrkUW48sFaslYmioR5bdpCowNqgfpOYPCQpVKXG/whtHeT12dkXG X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidation. This can help reduce the TLB miss rate, by keeping more intermediate mappings in the cache. From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. Signed-off-by: Rik van Riel --- arch/x86/kernel/cpu/amd.c | 8 ++++++++ arch/x86/mm/tlb.c | 10 +++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 226b8fc64bfc..4dc42705aaca 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) /* Max number of pages INVLPGB can invalidate in one shot */ invlpgb_count_max = (edx & 0xffff) + 1; + + /* If supported, enable translation cache extensions (TCE) */ + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + if (ecx & BIT(17)) { + u64 msr = native_read_msr(MSR_EFER);; + msr |= BIT(15); + wrmsrl(MSR_EFER, msr); + } } static const struct cpu_dev amd_cpu_dev = { diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index c5459516a72e..f1e2358616e5 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -480,7 +480,7 @@ static void broadcast_tlb_flush(struct flush_tlb_info *info) if (info->stride_shift > PMD_SHIFT) maxnr = 1; - if (info->end == TLB_FLUSH_ALL) { + if (info->end == TLB_FLUSH_ALL || info->freed_tables) { invlpgb_flush_single_pcid(kern_pcid(asid)); /* Do any CPUs supporting INVLPGB need PTI? */ if (static_cpu_has(X86_FEATURE_PTI)) @@ -1113,7 +1113,7 @@ static void flush_tlb_func(void *info) * * The only question is whether to do a full or partial flush. * - * We do a partial flush if requested and two extra conditions + * We do a partial flush if requested and three extra conditions * are met: * * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that @@ -1140,10 +1140,14 @@ static void flush_tlb_func(void *info) * date. By doing a full flush instead, we can increase * local_tlb_gen all the way to mm_tlb_gen and we can probably * avoid another flush in the very near future. + * + * 3. No page tables were freed. If page tables were freed, a full + * flush ensures intermediate translations in the TLB get flushed. */ if (f->end != TLB_FLUSH_ALL && f->new_tlb_gen == local_tlb_gen + 1 && - f->new_tlb_gen == mm_tlb_gen) { + f->new_tlb_gen == mm_tlb_gen && + !f->freed_tables) { /* Partial flush */ unsigned long addr = f->start; From patchwork Mon Dec 23 02:55:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E426E77188 for ; Mon, 23 Dec 2024 03:02:49 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id C66956B0082; Sun, 22 Dec 2024 22:02:48 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id C15186B0083; Sun, 22 Dec 2024 22:02:48 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id ADD436B0088; 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bh=SXXuSMpFNCfzTFZ81LFvoO369pHVUEu6XId56aIoa+E=; b=gR30CdsNYQnLoVIFizu94RvZYgRHLcHVZW/N/vUhgzoBQO+jU9yNnBElr/zgnjiXXd/2y3 YlY4A4/zL4W7mcERd9GWyEC/NCeFjScAJAj+Po+jtip2ETWQ4Ba7+IYEmqC17L4IvDTOjn /Hh2T/iC1bOq/QxK+WuviuCRrkZopVs= ARC-Authentication-Results: i=1; imf30.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf30.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1734922949; a=rsa-sha256; cv=none; b=U1e8d7ASBRIwhVKHyYU6VSryYT0XPW3l5qu/IGdOa6YKNh/m6xm3iXajeFE6Y2gFxvxSdy S4bZ9IHJFrxijhG6z3ubrYPFBMQX+TeHxPIAa8KihuK9/q5YsuloR8Faozo91XfsVH1QG5 V7p8rMs2e+OGc5spWZNvuAaS0bHvuCE= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdq-000000001Ih-1jeK; Sun, 22 Dec 2024 21:57:58 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 11/11] x86/mm: only invalidate final translations with INVLPGB Date: Sun, 22 Dec 2024 21:55:17 -0500 Message-ID: <20241223025751.3268975-12-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: CE3DA80007 X-Stat-Signature: akw1o9gfnbjinnrrkae3w3okooe11zwa X-Rspam-User: X-Rspamd-Server: rspam11 X-HE-Tag: 1734922894-679612 X-HE-Meta: U2FsdGVkX18I4XBGrl4dfnBDtLjex33mKEp8IkdP24V9ePZDv8Ir5dZIeonvNCGn+tTm7Bc7wNrqdns0BgkqjWiCHmA2C4UCfI+/RgP85ab68zVxuyzeRqCVu+niaiMNH3tDXocLjgkiCoSvCnCVoChiLPmb44C9S40BB6ltQwDRFxx4T1sv9Qml1PW/5lH7Q6tsTjMfjuN/tG1XYQOgjVJkifIrB0BfkWWsFIZB26pIlQTbxWOPVTEd96FtFEQAk5bOLBVHlk09Ujy+eC6VvbynoHg/1WUOm7k8ydwYT9Z+RSYR258QNgdfJsSBwCrgMS1lcmm4jd8catjfPPhIdW5IQlJApwNFkEvjE9unM80928fmVE6EsyKuAilI9x8JCzDGgDJ2b/I0CJ1SlEkToEfCHc0ou6iX5UbNMEnUo8LQr0KU+9WBM5Bi9TEKfzywVab93JhDGXx/FGeEyBFkBbRvPaJtaG4RzJr0qeIHU4AFJ8vIvQo5uauZU3h/+vby1FEOWVohdRphDT8zUfcm74o1EMLcyoUc87uXgWn7p/EkpPwvZzHM5/6d74npbkAYOVFH2+8gNYJU39HTSN/bvoP5yzFiHwVjCJErlj830/2d3YIx0P7HPMdMtN+jl1kCwMY17I8QSDYLT0pEVQZZFd+YCbH6gDjzyuoGg+WEQmbjvyDrMUCCoodcGtrVp2v7WNeEoDKe20/ov0wqefAMWQq1r5IzKQRqrIHoJmH9FJcJ0mZQijVui1xqMgtW4D1Ko3OjOudN41xXdwqhrTEMcPKmnAloohmmUyuwrGqF5sfdy2UZFRhEaXTs7mPYivMhrfpvlCWII0NDaC2ooNT0P7H8KUUY4emm2bDdg44GAePsLyHR6OAD+qjqHEr+soWPw6kp7/G3jfID2Ka3Cexw2JLK+0v4MGv6A8MEmiAXZQPQnQMUwFG+A5UDfTvP7u0faWJiJzq4pIk1+GFWFqY QTrLqJRc TS//1Bk2Ub0a3gcI4hT0RjH5Pj2tH7N3AQVH4PO99pmFxvs9W2467yU7gmz6AwyPTDOTubfaTxtl6erMv6tw2RsBUWxfAurZbq6vd/id7pjfJhdv4mX7uUE9qbffxItzj/UkYc1oW3FOKUBp1oFvHA34gtbIwQnrbOw+e7bCtymCR+rlq1Cwz9oAjDsK7DUZbupT5Wmeg4VDoXdcWXRLLta3pAgq323nb2De9gZncw34/v8osjBPBRO1YmzAKJ98ES0DuYCysOzefAG7mgmY/rdjnLSx/HEheiExAusETryNLW45/Fv65GWrSR/eLIDLAFoQr X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Use the INVLPGB_FINAL_ONLY flag when invalidating mappings with INVPLGB. This way only leaf mappings get removed from the TLB, leaving intermediate translations cached. On the (rare) occasions where we free page tables we do a full flush, ensuring intermediate translations get flushed from the TLB. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h index 862775897a54..2669ebfffe81 100644 --- a/arch/x86/include/asm/invlpgb.h +++ b/arch/x86/include/asm/invlpgb.h @@ -51,7 +51,7 @@ static inline void invlpgb_flush_user(unsigned long pcid, static inline void invlpgb_flush_user_nr(unsigned long pcid, unsigned long addr, int nr, bool pmd_stride) { - __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA | INVLPGB_FINAL_ONLY); } /* Flush all mappings for a given ASID, not including globals. */