From patchwork Tue Dec 24 14:10:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13920158 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79D7E1D79B6 for ; Tue, 24 Dec 2024 14:10:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049449; cv=none; b=CATydI8xeCejf8R7ZxlcpCxqGPTg+hjEcAXbdqiyBa/1x28Lx/dlPgle3NiK5l58zSrsfShEPV1QmU7fSUYpOjH6qh39d59Z8zN0dAerMGsacFPF5qoJt8H9Nj5Uftbjn+2UKNG82j+BNl2VzTinuDPAUMQP5BtZr6cJVvWNxCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049449; c=relaxed/simple; bh=Xw5xh82M6lqdr/nghSYHfW5cBYo0ON32Tui2FZ35TfA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nTV53OUneXhwe+23SyVqNdoroWoGqgkQTySSTmlcHwvGYCmUQ21sKHRmXQ7juTetLgkZptyuptpuoKVLQRdw5npGDEpEoor71iIqvZirE9+TNh0A7Ur3La/2Z/LQlZWWg5RA4yVd3XHLcJZj0n1nkUHE3HLfdDGbBbCeuaqiGss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=CKGOS2bU; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="CKGOS2bU" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BOBNdQ7015541 for ; Tue, 24 Dec 2024 14:10:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= btH923ahnbPdwp6dWib9PdG9Wrn7QfWHcRe4kSFbGB4=; b=CKGOS2bUm1Q6NdwX AvhVhlR574EJazVDZ+795oeCrarSR2l3bruLuamdkM/MvjW2eeS1EZGLFBhZCALN YWjw/RVsAh31JBzJHDyvf0A2gQiDB9BuoNHcPYq4dOLkMwmeDwddQi/PcKPBj1po JkkUW+bzfLWqCroSNaXH/YJsiz58KePh0b29frN86YOGL0jgfMNJh70ynAZYwKWS NIO2VTALN132Byr4EqISgWQssswlYIkT3WsrZkOef4UJEqcTNN+BHHYu1I2upHyq 8ZljqK6Yy7F7D7icUJ6AWov7/Occ1xARaiyVxm1LPooCNJasauKivk4fvg4BeCw/ 2ame3w== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43qv1g0q9t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Dec 2024 14:10:46 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-21631cbf87dso47128115ad.3 for ; Tue, 24 Dec 2024 06:10:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735049446; x=1735654246; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=btH923ahnbPdwp6dWib9PdG9Wrn7QfWHcRe4kSFbGB4=; b=dxwfEFwro3XaMT7VBip/YAw9aBD5FIzeA+ODUB2WE5bidB3DvfPXul8fu9ZkDnA1ig BLAIB5SOtqWl1xIW0cCXlePPsBEX163eioJ3rZT0TyXun/AArqlDgiLoFy+JzBifPe40 e8YE1gdVX2cGx1rS5O8feP5j70gSTti8ysXrOjgoGeSKfe2JwKcxYxqhdExU7qdiMUTS LCRuUhtlq18dMo/saPMfBo7Jw9/UBbmElFtE2Yo/8dr5tAI2lezzVN0R9GMr5DttAE+Z AmHFg+tDoN+M/fCpKpXdyvP0MWVsYZ8qSK7c+HC/OXtv0EIfSVYVDb8yxSJfNxtwsUT5 EjrQ== X-Gm-Message-State: AOJu0YxPO2/PT8+KNqm+Bl5E90wcmFbM4g5ZRxXeCV1LoyrTj+cAE1wd u+fIiI0bqmfTI+CBFgAL8Q5KiD6RGir74ZP2jmu6MZBsJwDmJblG7WW1SQpz7+LeioTOsadvqPh XUz4QObsvlHT2v9GQBB+IM7n+0H4R70xKpJYUT4hSdUUVDBdLJ1Cwo6mE4Me78eVJ X-Gm-Gg: ASbGncscqI1HHUEkXmVxVxrdd0eUXZr9x4GVtaRY3+hDraMwFBy1xyGO0sEP66WWXUJ XJKCcX++obsej0pMUxXdHyRM9OCnfpjBf5L/+629Vnz+9QH3Q4DNHBfoIUXXptmUT45wlZyzP1s qFup4zzOn4MGCMERrXX3BL84eb5+PK4JPUB4M626L50T/Vdgg/+lhhvilh0e4s7hnidMiw3j+oz W7sK8rNVLpl2KAVS/Z5LsDQsbdSNGTN5bpmjCa8PvSrVDszMbohlKrEnf4E3xaCGl/GnU3DMHEB Xknygy32OmajETMa X-Received: by 2002:a05:6a00:4487:b0:71e:744a:3fbc with SMTP id d2e1a72fcca58-72abe0957d8mr24589159b3a.21.1735049445846; Tue, 24 Dec 2024 06:10:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEDqis4LkXy5VHJ0HegLCjeJKr7+Mw7vi/WgX+RX9zCBHdvxftli3uQAVEKHL28nGypxkG9PA== X-Received: by 2002:a05:6a00:4487:b0:71e:744a:3fbc with SMTP id d2e1a72fcca58-72abe0957d8mr24589110b3a.21.1735049445432; Tue, 24 Dec 2024 06:10:45 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad90b8f5sm9691216b3a.194.2024.12.24.06.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 06:10:45 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 24 Dec 2024 19:40:15 +0530 Subject: [PATCH v2 1/4] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-enable_ecam-v2-1-43daef68a901@oss.qualcomm.com> References: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> In-Reply-To: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, mmareddy@quicinc.com, Krishna chaitanya chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735049433; l=1616; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=MfhniBxtocnuTilX1vl9/3VUiJ5IIq5lqt/LvaduY3Q=; b=/vxSocfEw7wTbjMJRMiQJH6JoPvSAAPGA4gzAeueswEJpneKJCePMZbPk5yOko/MuSmnrMpQO +3r3ZdGGa0KATFu/D+cadzRY/o0e5m1eKIBVS/dEMG41EuzHAcsomOx X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: by8ZPBp7-FkAJQOccadnhCKygBZsn35m X-Proofpoint-ORIG-GUID: by8ZPBp7-FkAJQOccadnhCKygBZsn35m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 mlxscore=0 mlxlogscore=903 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412240122 From: Krishna chaitanya chundru Increase the configuration size to 256MB as required by the ECAM feature. And also move config space, DBI, ELBI, iATU to upper PCIe region and use lower PCIe region entierly for BAR region. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 55db1c83ef55..bece859aee31 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2201,10 +2201,10 @@ wifi: wifi@17a10040 { pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + <4 0x00000000 0 0xf1d>, + <4 0x00000f20 0 0xa8>, + <4 0x10000000 0 0x1000>, + <4 0x00000000 0 0x10000000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; @@ -2215,8 +2215,8 @@ pcie1: pcie@1c08000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40000000 0x0 0x100000>, + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>; interrupts = , , From patchwork Tue Dec 24 14:10:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13920159 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E21AA1D90C9 for ; Tue, 24 Dec 2024 14:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049455; cv=none; b=esnn1sQzP2Ljxj0x+E20FGg/L8xVDWDRupzwgavuLJdGXcGmk8nKkq23DK+PMSOFky3U7pv8kufjf9Y++yQNr++QRV6qEKpzD5DWdP4C2szmIl6QjOznIsQVWWnqjafiAX1D++neTUsrsMyONnag09HyLARL1yqxYy0Kv0QSdFs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049455; c=relaxed/simple; bh=yKG9hzN6ljtAxROuJ1414Bv70zPHZWOeRMaB2J0/llo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hWEIZ6G43ebSHs29Xw0qSk+JXZcrD8yMkKCEFe4XgkeQQM7gekd6PYn1HxLLiEaQlbfbgugQC/MRmsrS+waQOSG2myfm8IKylpBBhTcdJDOoJzlbTtMEQc25utZ/mP+1t/NNEqQYTYcx7e3QpfKads6JCMo4UD+v3ktLHQCqqcA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=E5kdtHCC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="E5kdtHCC" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BODt0sO024977 for ; Tue, 24 Dec 2024 14:10:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QycD27NzJnz9NoB4Y7CaVJAP4MZXFSK/RUmrRiXblnk=; b=E5kdtHCC05WqNni0 4kh5qE6x8S4uOVWFkJERnDIi9W4anR+JIu+WvmRXO+CalUwgYVIICSiE0VpN3j4h kqriasRI56f7h97w6dzti/lhSHi8dhPmTvzBpkc6k2gwmUtk2ufcPaCslw8hvyNC EM82xqSgqCJfjfdjoPNiqCPHTYNdva3TCfYkUKBQV47FhC3lbG4Q7h09NIExjt6Q cumXDr3EnGtf7tJ6RsadXPgY+ylim93pycYCNSCTuIs2aGyTr47PEfPzen9dZn9D jS78arNB4RnmZ2GSUCWm3mueqx8RVyRlfgW+RXxntN3ehNB/tQ7rK8TozqjdtN4D ZW6NLQ== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43qwm189a0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Dec 2024 14:10:52 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-2ef80d30df1so5315579a91.1 for ; Tue, 24 Dec 2024 06:10:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735049452; x=1735654252; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QycD27NzJnz9NoB4Y7CaVJAP4MZXFSK/RUmrRiXblnk=; b=tFUQMYR9hzdjk0SvBHo8gfIiSsOMjIft1zYv2W5+1kk+dGHVEHlq/GfI/0mA/caRVB CRH1uPEgk427nDzBMWimve+6dsBhTAG/9yak/hAM8tJpc4LzcilItiZB1sRxRAwp6rEJ qSDKqIEbxF1I3632NcRwFTiscvOXDeRjcwIdoWL2mluASRdFoac7/fTkM7LQBjb5C+fM P0kW2ey4zdqaeiEpowCXG0rzFVqI9aGF59AlW0Iw0NOOTvq+asXqMd/svwzTmYMgNm1p Bu8wu9IIqFcrTPTulqdCISSu5sMAnqk4LJZx8fpz1I8KbPppb6UTzEqHi5Vuh4pDCaUH uiHw== X-Gm-Message-State: AOJu0Yy4Mr1aqwLM1qIwfVRBR6yupd+K8W1enET44olLLqKIUKskNc5p tcqqZZDysr4quT3O4xM5PNsdgViZYQiTB9NlJmje3yYCswyP1PzCEDmp+ba+mq7NZgnlC+GpRk3 EPU+/1mSFyGtzgJOAuyFgo98zIsc5VkKBvpOxcOeC0J4MA/mEnr+B0ciN9327Ai9W X-Gm-Gg: ASbGncsvG+YJEqDFIlsxfUR+HG4Oz949QFbz3Gk9UtrEo1zOUod8NKzrwfjRF8wJ2d7 WwyFPfYh+k1XIq7qLUK1ZCSxrDT1iTnnfU+ZFaVsqdyyDfUjLhIX9IoNCy7ZwOMV5IYC9HNT+/q gwsFXvOmnIuR8EOLYsSLfcrkindSaPa0ioqUSQS8xr51sSNSrrSeUVLyVDz6VXgOS9pVct8BQMu tJAJ7UaML46kFvOqf+UDlQ+1Z4U9/A1lnVQamSybxPGc+Uyr69bJq4iLocc772CyN+dIw55tScH JBZUNy2CkeBUe08q X-Received: by 2002:a05:6a00:3c81:b0:72a:bc6a:3a88 with SMTP id d2e1a72fcca58-72abdecc754mr20811923b3a.22.1735049451952; Tue, 24 Dec 2024 06:10:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IFUs6eDLT0Y8q+LfDf3tn03yV6shUplRzfYQEs3T2gACVG4Xjia+yfflcreEQzwyFLHc4L4qA== X-Received: by 2002:a05:6a00:3c81:b0:72a:bc6a:3a88 with SMTP id d2e1a72fcca58-72abdecc754mr20811894b3a.22.1735049451489; Tue, 24 Dec 2024 06:10:51 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad90b8f5sm9691216b3a.194.2024.12.24.06.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 06:10:50 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 24 Dec 2024 19:40:16 +0530 Subject: [PATCH v2 2/4] PCI: dwc: Add ECAM support with iATU configuration Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-enable_ecam-v2-2-43daef68a901@oss.qualcomm.com> References: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> In-Reply-To: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, mmareddy@quicinc.com, Krishna chaitanya chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735049433; l=10125; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=QO9aP4hVIT8X9Xt9RaVwKvgucRLV13hNyD+uG8KkdzA=; b=8BrNuV2sRRDAvqgIhFAaIEDj9AZEJ/8moENmJC7bf+qg1A1g25S+X5WUR+yJaQUe/rUTgQxJv prxVVBzfKQYD5ZNpYyMkh/i4lS5n3kv66uvtxkFaLDeJ+mFC9UrSG7G X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 8O4LyYcpYMM7fIbMS7GKh8wNSoGrDd9U X-Proofpoint-ORIG-GUID: 8O4LyYcpYMM7fIbMS7GKh8wNSoGrDd9U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412240122 From: Krishna chaitanya chundru The current implementation requires iATU for every configuration space access which increases latency & cpu utilization. Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, which shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12]of the translated address. Configuring iATU in config shift feature enables ECAM feature to access the config space, which avoids iATU configuration for every config access. Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. As DBI comes under config space, this avoids remapping of DBI space separately. Instead, it uses the mapped config space address returned from ECAM initialization. Change the order of dw_pcie_get_resources() execution to achieve this. Enable the ECAM feature if the config space size is equal to size required to represent number of buses in the bus range property, add a function which checks this. The DWC glue drivers uses this function and decide to enable ECAM mode or not. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 136 +++++++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 11 ++ 4 files changed, 130 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..73c3aed6b60a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -9,6 +9,7 @@ config PCIE_DW config PCIE_DW_HOST bool select PCIE_DW + select PCI_HOST_COMMON config PCIE_DW_EP bool diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d2291c3ceb8b..4e07fefe12e1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,61 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) } } +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = {0}; + struct resource_entry *bus; + int ret, bus_range_max; + + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + + /* + * Root bus under the root port doesn't require any iATU configuration + * as DBI space will represent Root bus configuration space. + * Immediate bus under Root Bus, needs type 0 iATU configuration and + * remaining buses need type 1 iATU configuration. + */ + atu.index = 0; + atu.type = PCIE_ATU_TYPE_CFG0; + atu.cpu_addr = pp->cfg0_base + SZ_1M; + atu.size = SZ_1M; + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + ret = dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + bus_range_max = resource_size(bus->res); + + /* Configure remaining buses in type 1 iATU configuration */ + atu.index = 1; + atu.type = PCIE_ATU_TYPE_CFG1; + atu.cpu_addr = pp->cfg0_base + SZ_2M; + atu.size = (SZ_1M * (bus_range_max - 2)); + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + return dw_pcie_prog_outbound_atu(pci, &atu); +} + +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resource *res) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct resource_entry *bus; + + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pp->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pp->cfg)) + return PTR_ERR(pp->cfg); + + pci->dbi_base = pp->cfg->win; + pci->dbi_phys_addr = res->start; + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -431,19 +486,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) raw_spin_lock_init(&pp->lock); - ret = dw_pcie_get_resources(pci); - if (ret) - return ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); - if (res) { - pp->cfg0_size = resource_size(res); - pp->cfg0_base = res->start; - - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); - } else { + if (!res) { dev_err(dev, "Missing *config* reg space\n"); return -ENODEV; } @@ -454,6 +498,31 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->bridge = bridge; + pp->cfg0_size = resource_size(res); + pp->cfg0_base = res->start; + + if (pp->ecam_mode) { + ret = dw_pcie_create_ecam_window(pp, res); + if (ret) + return ret; + bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->sysdata = pp->cfg; + pp->cfg->priv = pp; + } else { + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; + bridge->sysdata = pp; + } + + ret = dw_pcie_get_resources(pci); + if (ret) + goto err_free_ecam; + /* Get the I/O range from DT */ win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); if (win) { @@ -462,14 +531,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base = pci_pio_to_address(win->res->start); } - /* Set default bus ops */ - bridge->ops = &dw_pcie_ops; - bridge->child_ops = &dw_child_pcie_ops; - if (pp->ops->init) { ret = pp->ops->init(pp); if (ret) - return ret; + goto err_free_ecam; } if (pci_msi_enabled()) { @@ -504,6 +569,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pp->ecam_mode) { + ret = dw_pcie_config_ecam_iatu(pp); + if (ret) + goto err_free_msi; + } + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -533,8 +604,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); - bridge->sysdata = pp; - ret = pci_host_probe(bridge); if (ret) goto err_stop_link; @@ -558,6 +627,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); +err_free_ecam: + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_host_init); @@ -578,6 +651,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); + + if (pp->cfg) + pci_ecam_free(pp->cfg); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); @@ -985,3 +1061,25 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci) return ret; } EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); + +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct platform_device *pdev = to_platform_device(pci->dev); + struct resource *config_res, *bus_range; + u64 bus_config_space_count; + + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; + if (!bus_range) + return false; + + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + if (!config_res) + return false; + + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; + if (resource_size(bus_range) > bus_config_space_count) + return false; + + return true; +} diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..63d36676f858 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -509,7 +509,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - val = PCIE_ATU_ENABLE; + val = PCIE_ATU_ENABLE | atu->ctrl2; if (atu->type == PCIE_ATU_TYPE_MSG) { /* The data-less messages only for now */ val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..41022f06572e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -171,6 +172,7 @@ #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 @@ -342,6 +344,7 @@ struct dw_pcie_ob_atu_cfg { u8 func_no; u8 code; u8 routing; + u32 ctrl2; u64 cpu_addr; u64 pci_addr; u64 size; @@ -379,6 +382,8 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool ecam_mode; + struct pci_config_window *cfg; }; struct dw_pcie_ep_ops { @@ -685,6 +690,7 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp); int dw_pcie_allocate_domains(struct dw_pcie_rp *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) { @@ -715,6 +721,11 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static inline bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) +{ + return 0; +} #endif #ifdef CONFIG_PCIE_DW_EP From patchwork Tue Dec 24 14:10:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13920160 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B801D6DBB for ; Tue, 24 Dec 2024 14:11:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049464; cv=none; b=U5dJzDrAqwRdKHXpnrbV3RI9mv6TSYjXKEa4y9lGuDy6XP9JkysdHsO6eJ/CMJnSYhwqsVSHAbV0WLa3qHcBHGjF8KOyEWWH4ypMI5DPkpXFAaz+Eg3/Qchwu03FmqJl7MEdrjvzuHaYpJeza9fV32L6/VQGPCgJbfGERzDbXBQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049464; c=relaxed/simple; bh=0Xx6GMsAw+JWlDoTPToHHqQOG07yIdiQ1yAV7t7FJ5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ngUyzdDe5xmS5YPd8wKkAChENy9Yxo+RvurIDhNY6amUEXR7oOFOoVqvxa4btuEjhhtvmrXKZp48+cL7a65uqABCU7bFI4boAJYTqWrrcOlwyYZUHNIHipWaI7fa+pOkzNbOMkBVL8TCbhXERHHePajpkVfuWF+vguEU6f3vKTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Kw4xKlcd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Kw4xKlcd" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BOD3gPr021056 for ; Tue, 24 Dec 2024 14:11:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 1HEWmjXS5JJuGEVhkOT6pTbnHC1543u6z3ZHIx/4YjI=; b=Kw4xKlcdv0q6shJr 8wbDHZ4JxAhK8qDD89fkkmCAoW0eiB288/ND7iBJJUcyS6wgpvZb43pqBb4x1sV+ x0ewTCdNGSqhr6tTv3AbKUzz5XWv0BoNmL9upGavoWT0Cld2FWh5rixMIL/A4S8U rZy0hnMifucNyFLXX6uPqGE0vgHg/2GM8njHpqqWm33+EKvI6mbvm8MjVDpKwkeV wHX9OXYVUQ5SQf9HCXkPiyRmWwM1GHCrOV12AOs7+KAXbOODE464jSCue9vI4WpI d6Qc+c68jK7AvxMm0GPwdVlENCQmWBoBwjxUKsDRaQF0xoP82UHDskzUqeo3Kkkv uyg7pw== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43qwgt8b38-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Dec 2024 14:11:01 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2166464e236so90465525ad.1 for ; Tue, 24 Dec 2024 06:11:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735049460; x=1735654260; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1HEWmjXS5JJuGEVhkOT6pTbnHC1543u6z3ZHIx/4YjI=; b=IaNfG48p1HCmFR9GIyBDQanpnziGd0EOrK/6dmHEiNqzZBF8DOt9DbBLt1SbCLhKpp UUyiP4LnUfWjBEfv7WogF34csB/5hGzJ+aKZ325ljKpOnXalBR/UCtoaDskKNW5dbUHt B34qnk11K3UsbTJR9F5C5Rd2nzc33xDygFO4XXYOPsMuwAvDaz5hikgETTI0xxGxq6KJ OWOEEpZCypzJmAX1VJzzGMwjKhkcLxgU/Q36UdtlqME2yI6K5DBmpVOCRADrkXhYZyfI cxh921MMP+Hdat6LTGrKWVrkR0Md1SZplH7lZzRIHE6UDLDNu+FV4jaxSNZHQlo8RUIy p8Qg== X-Gm-Message-State: AOJu0YwPgIT2BD7fSJNESt9gYUg0SwnpTButxvdnoKFy0N/TMn9HyhOH /j4Bgo4FDSNVL2WVxkKZBd0EdObdVBimvlB7/jNNyn4ODUqF2JFkFhFdLASevYKumrY7WqMRsTg 2o72obYR98nbTYnWPjmKLQnNLwtVOte7ptKpVobzlRP4evy7cIWkugQG4fPq0O+eR X-Gm-Gg: ASbGncvGQrVTQMQF61KJfvUVPItaV1i30BfiCNWN6jFYlDzbRuKj/S40La85R7vMye3 NCGe2TfMyrs/IljSdOpbyuBljhY5mJ6cyhjoYXIirKFCtOfAAfjp2kEOIaAwfwij9h5bWLK6E1i EQI24IHKnKDFi56aPHq9HjxZTAmKr0MUfG+kd2jrVxC2k87lb62ri8YUxla+VwI7mAqPY9zK5m7 HMunN9nwAs4LDU6h488imJPKtnhcwCIbp3JaNpT/z8GvLs958awI5vvUnEBDdjtzKFjwoEvm8b0 P/wjlQG2jeAiatOD X-Received: by 2002:a05:6a20:c907:b0:1e0:e07f:2f01 with SMTP id adf61e73a8af0-1e5df939d84mr24516979637.0.1735049459528; Tue, 24 Dec 2024 06:10:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IFGxQd/3dtpr+emjaEkW2pVkPDwgEoBoiqsutuMOLha1DB7CG6CsiB1HWQkUaeJk6s/Y1o24Q== X-Received: by 2002:a05:6a20:c907:b0:1e0:e07f:2f01 with SMTP id adf61e73a8af0-1e5df939d84mr24516828637.0.1735049457329; Tue, 24 Dec 2024 06:10:57 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad90b8f5sm9691216b3a.194.2024.12.24.06.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 06:10:57 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 24 Dec 2024 19:40:17 +0530 Subject: [PATCH v2 3/4] PCI: dwc: Reduce DT reads by allocating host bridge via DWC glue driver Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-enable_ecam-v2-3-43daef68a901@oss.qualcomm.com> References: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> In-Reply-To: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, mmareddy@quicinc.com, Krishna chaitanya chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735049433; l=1397; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=0Xx6GMsAw+JWlDoTPToHHqQOG07yIdiQ1yAV7t7FJ5Q=; b=7URn+oI+BDdjhibv3tPY1iSYtX0PuA28lSzDe0WICKdg6iuIrn2WCFUaD3YHsFVZ92oGowk1M 0p7lFy9UkSiAZ77yj2PuzkIh0E0M25WXzVf5qzR5qpsJD8rfbc48KZP X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 2RvQp6mrbO8aO2uvAEY6fMZ53AVPJXqG X-Proofpoint-ORIG-GUID: 2RvQp6mrbO8aO2uvAEY6fMZ53AVPJXqG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 mlxlogscore=889 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412240122 Allow DWC glue drivers to allocate the host bridge, avoiding redundant device tree reads primarily in dw_pcie_ecam_supported(). Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 4e07fefe12e1..c3f464f128f0 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -479,8 +479,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct device *dev = pci->dev; struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); + struct pci_host_bridge *bridge = pp->bridge; struct resource_entry *win; - struct pci_host_bridge *bridge; struct resource *res; int ret; @@ -492,11 +492,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) return -ENODEV; } - bridge = devm_pci_alloc_host_bridge(dev, 0); - if (!bridge) - return -ENOMEM; - - pp->bridge = bridge; + if (!pp->bridge) { + bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return -ENOMEM; + pp->bridge = bridge; + } pp->cfg0_size = resource_size(res); pp->cfg0_base = res->start; From patchwork Tue Dec 24 14:10:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13920161 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDB151BCA19 for ; Tue, 24 Dec 2024 14:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049478; cv=none; b=nLjSekNavYZVj358kLPGqt0bT3neLQM+52N4L3uZOHzrbA4wKQNGj5tRc3TqzAPBdAZBUjJLjXwuCu8xdrDI4lz+XjlMBYxIINKIhtTJSlYF9dwr3LLAyEVVIC9caIOotLyrPQluLO1Y/2QXa2oshnL2Fh6euZoYbxcX0t3vHL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735049478; c=relaxed/simple; bh=wUYvHZAm3A/KcGP43qeUWycLI5gU56sEXnr/Lx8vtfw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SpMQIUcaEyG+08vXXzbcrXLOeK6owk3WLrUaBaqybdJmLQn28dkN/59Sb8staZs46WSrSIwnAhxoGTigKBXsR2xFT0PTjIagFpVKmdxcU8EUM6jTj3sLhhVLxLfv48q8ZlwLZL2EZegWuNLvgROaInMLCRXxmMnY7/fMT8ZaDa0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=il/TPmrg; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="il/TPmrg" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BOC5Oag009740 for ; Tue, 24 Dec 2024 14:11:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vPQy9s4x824wAEkt8ywhd2HnwSF0tV7LCRg9PNd+bLc=; b=il/TPmrgxXzjYejR KrH1oV6naHe4APpK9pgQLFyET7/4BTk9nU8tLz1AKQt3mi4OIxkJmg3biyX6fLUo CvPlMqNmM5lLSCH8mpwmqoXcw23UxuZXZbxA1Sk4jyx8JqkZvvuxW7tPpOTsxjSy D8W1MFPD82ENQsZewb/xAIPWZckZCZQDlee1ty3BhKHtSwUnD9ToA7EWlnzCQrOB CLVHRUFzAjqtLpPFYeIw6rFv3u8qzhbzBuU3QGLl2MNdt8D68wLdvcRA1PImQOpK P1DX8c9wI5EsaM7FsKEZQTsgzM0WMLIUz9Q9sX3BzgwwjyegbYaj81lri1VvVK0E oHNN/w== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43qvnggjvv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 24 Dec 2024 14:11:16 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-2efa0eb9cfeso5070298a91.0 for ; Tue, 24 Dec 2024 06:11:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1735049464; x=1735654264; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vPQy9s4x824wAEkt8ywhd2HnwSF0tV7LCRg9PNd+bLc=; b=MyOZLWkjdAr45zvn4vWhLg9LZV+ZIThWbKhaMrz/1I8O6sLyWYazXdfm6PYa47kBWT y0vX/sTsQbutrLVcDSkH0jXjTvr2KJCOzSJbjgGa2py70tQc+duilIGGS8G4ehgaW3Jj s+U5aGhqMLCyhenn8Rpu5yvg+jj2xAgTaAwZkmFpOkPjjR3MDmEVabUrKqYf3VXqkRvo 72UpjV+14pT6z81N3RpsgUTooYJHCQzvXzbUMklxZ12danGHNBqAq2Ujex/ovz2lq1RF 2wp8PHrRej9Lb9hvroE4AUCZ/dS0+62u/HTPmz8DoQJKYyS95IHiSUll5/UgbGV88k0/ ++9w== X-Gm-Message-State: AOJu0Yy1BIBgz7jcjjSyE4kkEuMAkb0vTSm9HdONx3vkn+kNoAy2fSmC hSDmhs0SFQjzwpq2VtFH+noWFa77pjaZMnuVdbQ4CkHFneFX8eIz179MeflNfwsiVQIe4ta65Kq dlZNYwFdqPNf2fyLzVT4PfhFOXosuNfsmbeX5J+Fr6dFs17jxjUDGi4IPWJBycV1K X-Gm-Gg: ASbGncvtRh+GtWOfjOcve/4eOgBiN1QLzs2Wolu3A5LUi5atuQUZLza21GLBV2cPXbe r0Fn34F+GbrZnjPNzW+OZ9PK1ZnzUBX8Zft6iWU8GhlqhhNx4lcTytyFRcxe9DAq5Xl5Lr6gBhJ ZWRcM2E/uxnaLAKCnPHqGoyWOJNrnwOELVeSf0/jMsKdkMtRaDpFPV38zj+L/Um+qSP8OEGrioj HKEVeKlSchQEMtNeTCGEn3JUh70KpjImK3v9yDj5bdwdTR8C5keFXA3vncHbIWeRDKPzxGDSZdC XKB7lFmqepc2YQYs X-Received: by 2002:a05:6a00:7428:b0:725:4a1b:38ec with SMTP id d2e1a72fcca58-72aa9a10440mr28763237b3a.3.1735049463620; Tue, 24 Dec 2024 06:11:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IErff/FA1vKquEFtYhlg+zdGdF4K7JzJ02E1k3WXm+tdcOzvFvSCIJeGGmW9knAoOWGJCCAyw== X-Received: by 2002:a05:6a00:7428:b0:725:4a1b:38ec with SMTP id d2e1a72fcca58-72aa9a10440mr28763175b3a.3.1735049463166; Tue, 24 Dec 2024 06:11:03 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad90b8f5sm9691216b3a.194.2024.12.24.06.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 06:11:02 -0800 (PST) From: Krishna Chaitanya Chundru Date: Tue, 24 Dec 2024 19:40:18 +0530 Subject: [PATCH v2 4/4] PCI: qcom: Enable ECAM feature Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241224-enable_ecam-v2-4-43daef68a901@oss.qualcomm.com> References: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> In-Reply-To: <20241224-enable_ecam-v2-0-43daef68a901@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, mmareddy@quicinc.com, Krishna chaitanya chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1735049433; l=6085; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=SYsZuISEFecO0dItPGcTh+FGUKWuxe8fmZZ5miNptNM=; b=dLBEFEgy1I5Gl1ZJAKGNY0qz6PpU7YGeC8ekRh7iiq6BJwbg6v31pm9WdBv1yxGgCqiFpqTsM zKTdDCvesKEAwi0z29XkkxKSQXAIBO5IzcBlW9NEbOn1SUMfYkE6DFX X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: avHUvBT032O7We8oFn7czLeKQwRtsSZG X-Proofpoint-ORIG-GUID: avHUvBT032O7We8oFn7czLeKQwRtsSZG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412240123 From: Krishna chaitanya chundru The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register gives us the offset from which ELBI starts. so use this offset and cfg win to map these regions instead of doing the ioremap again. On root bus, we have only the root port. Any access other than that should not go out of the link and should return all F's. Since the iATU is configured for the buses which starts after root bus, block the transactions starting from function 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going outside the link through ECAM blocker through PARF registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++++++++-- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index dc102d8bd58c..cf94718d3059 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -52,6 +52,7 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_SLV_DBI_ELBI 0x1b4 #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c @@ -61,6 +62,17 @@ #define PARF_DBI_BASE_ADDR_V2_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c +#define PARF_ECAM_BASE 0x380 +#define PARF_ECAM_BASE_HI 0x384 + #define PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 @@ -84,6 +96,7 @@ /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define PCIE_ECAM_BLOCKER_EN BIT(26) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -294,15 +307,60 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } +static int qcom_pci_config_ecam(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u64 addr, addr_end; + u32 val; + + /* Set the ECAM base */ + writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); + writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); + + /* + * The only device on root bus is the Root Port. Any access other than that + * should not go out of the link and should return all F's. Since the iATU + * is configured for the buses which starts after root bus, block the transactions + * starting from function 1 of the root bus to the end of the root bus (i.e from + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. + */ + addr = pci->dbi_phys_addr + SZ_4K; + writel(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); + writel(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); + + writel(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); + writel(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); + + addr_end = pci->dbi_phys_addr + SZ_1M - 1; + + writel(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); + writel(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); + + writel(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); + writel(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); + + val = readl(pcie->parf + PARF_SYS_CTRL); + val |= PCIE_ECAM_BLOCKER_EN; + writel(val, pcie->parf + PARF_SYS_CTRL); + return 0; +} + static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); + int ret; if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) { qcom_pcie_common_set_16gt_equalization(pci); qcom_pcie_common_set_16gt_lane_margining(pci); } + if (pci->pp.ecam_mode) { + ret = qcom_pci_config_ecam(&pci->pp); + if (ret) + return ret; + } /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) pcie->cfg->ops->ltssm_enable(pcie); @@ -1233,6 +1291,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie = to_qcom_pcie(pci); + u16 offset; int ret; qcom_ep_reset_assert(pcie); @@ -1241,6 +1300,11 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; + if (pp->ecam_mode) { + offset = readl(pcie->parf + PARF_SLV_DBI_ELBI); + pcie->elbi = pci->dbi_base + offset; + } + ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); if (ret) goto err_deinit; @@ -1613,6 +1677,13 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; pp = &pci->pp; + pp->bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!pp->bridge) { + ret = -ENOMEM; + goto err_pm_runtime_put; + } + + pci->pp.ecam_mode = dw_pcie_ecam_supported(pp); pcie->pci = pci; pcie->cfg = pcie_cfg; @@ -1629,10 +1700,12 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); - if (IS_ERR(pcie->elbi)) { - ret = PTR_ERR(pcie->elbi); - goto err_pm_runtime_put; + if (!pp->ecam_mode) { + pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(pcie->elbi)) { + ret = PTR_ERR(pcie->elbi); + goto err_pm_runtime_put; + } } /* MHI region is optional */