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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The CPU-to-SDHC interconnect path for the SDHC_2 needs to have the active-only tags. The tags are missing entirely on for the SDHC_4 controller interconnect paths. Fix all tags for both controllers. Fixes: ffb21c1e19b1 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers") Signed-off-by: Abel Vesa --- Please note that the commit that this patch fixes hasn't made it beyond Bjorn's tree yet. So fixes tag points to that. Also this is based on Bjorn's arm64-for-6.14 to make sure it applies without conflicts. --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) --- base-commit: 1caf6149c3bf41a2ee07869449c4ea1ec8bbc2f8 change-id: 20241227-b4-x1e80100-qcp-sdhc-fixes-686b7cfdf064 Best regards, diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 0e30029bfc1948d8412d62095a0c9b9274ebb9a2..9d31cb55b055d0726c73f726d6467edaf4607dbe 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4315,8 +4315,10 @@ sdhc_2: mmc@8804000 { power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; - interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; dma-coherent; @@ -4366,8 +4368,10 @@ sdhc_4: mmc@8844000 { power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc4_opp_table>; - interconnects = <&aggre2_noc MASTER_SDCC_4 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_4 0>; + interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; dma-coherent;