From patchwork Sat Jan 4 20:54:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Belwon X-Patchwork-Id: 13926367 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 080EF25760 for ; Sat, 4 Jan 2025 20:54:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736024075; cv=none; b=HyS6u7l2jNCWyrJ+miQDJqKMzv98I8DY3eB3DA5lMGqgQ4XpoLOKhmKH11FKWwp6KMCb71Il4AcYAMegRilRZM+utCNF1SDoEsfOU+xhxivxRus0aZHr8+36You8T0DAyONU/eojMJ2Scg3rhgyljycWgcdfVGnaM8QiHevtzqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736024075; c=relaxed/simple; bh=u277CPLBGNkpYhIE1Rr/ra64g8X2BqQPgiL87IDzy5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hJ081M6PkF2Joln0KbP5DQ7W8VnQ1Duq2vELeHqaCmUNcTRNnAePF6208D9OD2/QNHt+S4O8wrzaJCLjZtEOCD3nRFFFLbubcAV9ucBdL5XwyCpZXipmgLorHAHVH3mXuOqI9pKyY/e+4UzEjC1vW3Tf1L5yBu7N1kSSWX1tiNc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org; spf=pass smtp.mailfrom=mentallysanemainliners.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b=FEXNIqLb; arc=none smtp.client-ip=34.202.193.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b="FEXNIqLb" Authentication-Results: purelymail.com; auth=pass DKIM-Signature: a=rsa-sha256; b=FEXNIqLbA2dho6TkleojVJU/mNabeFXI+ZNE1ovlYhYWGv6w+dSDF7Ao+DJsC9IkhHH6czuTO/nXxpeJEbpsalZgHGURIbCDWTaRBMcNSP3S1OBR3QcwpZ7OBcGljJ25BX41BlvQ6Hz6Puacv/fvUFxtI7TjpqGElO8AkcbU43BcyiGjPQlOdfCY4ckyvFCVmDwgCTiYPjKltJhEbwkJJojdVcjLB9j/ZRk1WDcBd9ZMQ8E9yiI1/5oyyQ2VmovZpW/ioM1tjdTfsqcTmWjj9URkPiTX/Fcvfw/rSckDX8F8GNuxk7S4WtNyTxwT9RcFYuk8bsNZLV/Z45zKmI7lqA==; s=purelymail3; d=purelymail.com; v=1; bh=u277CPLBGNkpYhIE1Rr/ra64g8X2BqQPgiL87IDzy5Q=; h=Feedback-ID:Received:From:Date:Subject:To; Feedback-ID: 68247:10037:null:purelymail X-Pm-Original-To: linux-samsung-soc@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id 166263896; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Sat, 04 Jan 2025 20:54:30 +0000 (UTC) From: Igor Belwon Date: Sat, 04 Jan 2025 21:54:16 +0100 Subject: [PATCH 1/2] dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250104-cmu-nodes-v1-1-ae8af253bc25@mentallysanemainliners.org> References: <20250104-cmu-nodes-v1-0-ae8af253bc25@mentallysanemainliners.org> In-Reply-To: <20250104-cmu-nodes-v1-0-ae8af253bc25@mentallysanemainliners.org> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Krzysztof Kozlowski , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Igor Belwon X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736024066; l=1238; i=igor.belwon@mentallysanemainliners.org; s=20241206; h=from:subject:message-id; bh=u277CPLBGNkpYhIE1Rr/ra64g8X2BqQPgiL87IDzy5Q=; b=LmjPRu8Mc9V1XnLhYRXEnZgszVTkWv+64u5dFvrbNqNXJzVqL6r4jRSD41n4kiRqffrzMcZUN ClRoiJQmxEGD67zArdb9WO7RM52IToo79RzKP82xSBa4TBPXaN5Wcc2 X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=qKAuSTWKTaGQM0vwBxV0p6hPKMN4vh0CwZ+bozrG5lY= Add a dedicated compatible for the MCT of the Exynos 990 SoC. The design for the timer is reused from previous SoCs. Signed-off-by: Igor Belwon Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 02d1c355808e4eadd77b98247cd70e76aea72b21..12ff972bfefcc5dcef2a38582e963ea49a567d18 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos5433-mct - samsung,exynos850-mct - samsung,exynos8895-mct + - samsung,exynos990-mct - tesla,fsd-mct - const: samsung,exynos4210-mct @@ -135,6 +136,7 @@ allOf: - samsung,exynos5433-mct - samsung,exynos850-mct - samsung,exynos8895-mct + - samsung,exynos990-mct then: properties: interrupts: From patchwork Sat Jan 4 20:54:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Belwon X-Patchwork-Id: 13926369 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D69C1D5176 for ; Sat, 4 Jan 2025 20:54:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736024077; cv=none; b=kcaRCmNqmRppW/5fBKuBc/wqayjFQ0T3z6OqNAhrn6/H//kkkJfLMg8wuoMw9jtgiOTwNaOY2kspIvK7PIUrhi4dDMtQwF6AByYyVE1SLNpDoMgll1yfGC0GvaKDrWApre73zfEZgD1vCkbJ9PHhcfgEadBtyNHAO7v7B4GNMaA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736024077; c=relaxed/simple; bh=y7XGmitoB/d2FvK9oMBRHq/8yp1wqAV+TBRDnbZB5hI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A8k0Y0JI96gMIYtc01TnqtjzoDHt01XdT3EqGC965stqwRhG7TWxYtgEED3R4czOQ8RWE2NBG/xnye+Qku/v0Rbfy/MlZzf0CD55Saab5UZNpoFdO31oSe6RoARXcG4U4uXeLP4znp+8Rm/WjSCo2VQx+2nGKgEraYx+U/OEp/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org; spf=pass smtp.mailfrom=mentallysanemainliners.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b=KCWzH/Nr; arc=none smtp.client-ip=34.202.193.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b="KCWzH/Nr" Authentication-Results: purelymail.com; auth=pass DKIM-Signature: a=rsa-sha256; b=KCWzH/NrfDRl0+2n/iVUM9pAtbsVro7gQCLC6SIXHPJjvIZEHSlFkzuolfgmZnZlg7X5vUeVgP5rYh73jHH3ZdiNTZErHhLFc9GF/6FPRvNsySLgbWZLHfW7dQL4mhEOzeP90mQWc3E4sR1CCuXJiTFxNubCVS57VbkMJb9wWSbYnqLbzYZLsucESY/WiCryLYZLoxk5Fz1K3oYO4GZcl8g2jF08d4quoB06nxkng9vf6tUU5A70rNMGYTchNWBIY29UwVWfiWv09DiKpfG7NbZMkDaNWLBRnUu2cQzC4fjTW4IAyjoRVkR2aMf5sKzXFd+vPfWo0k/Vdf+p5QoICw==; s=purelymail3; d=purelymail.com; v=1; bh=y7XGmitoB/d2FvK9oMBRHq/8yp1wqAV+TBRDnbZB5hI=; h=Feedback-ID:Received:From:Date:Subject:To; Feedback-ID: 68247:10037:null:purelymail X-Pm-Original-To: linux-samsung-soc@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id 166263896; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Sat, 04 Jan 2025 20:54:32 +0000 (UTC) From: Igor Belwon Date: Sat, 04 Jan 2025 21:54:17 +0100 Subject: [PATCH 2/2] arm64: dts: exynos990: Add CMU_PERIS and MCT nodes Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250104-cmu-nodes-v1-2-ae8af253bc25@mentallysanemainliners.org> References: <20250104-cmu-nodes-v1-0-ae8af253bc25@mentallysanemainliners.org> In-Reply-To: <20250104-cmu-nodes-v1-0-ae8af253bc25@mentallysanemainliners.org> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Krzysztof Kozlowski , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Igor Belwon X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1736024066; l=2006; i=igor.belwon@mentallysanemainliners.org; s=20241206; h=from:subject:message-id; bh=y7XGmitoB/d2FvK9oMBRHq/8yp1wqAV+TBRDnbZB5hI=; b=wp2LiSqexkr9nlHacMJNjzsq1rbdxz2rqG+owfiMvUU9d/JnivDj75Gj+YL+MCUHbOd/T6a4R ISu+kItYJrcDs1YSZ0vQDqHEwKNs6b49ulHYnfWXL7UGuSX/+cCpHzK X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=qKAuSTWKTaGQM0vwBxV0p6hPKMN4vh0CwZ+bozrG5lY= CMU_PERIS is a new clock controller that clocks the MCT. The MCT has 9 timers (1x count-up global timer, 8x count-down CPU local). The global timer generates 4 interrupts, and each local timer generates one interrupt. So, in total 12 interrupts. Signed-off-by: Igor Belwon --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index 9d017dbed9523e874891f13258d331c3e829ca03..0e18711cbdc98a65cbd2d709cdd53a7680b833f2 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -181,6 +181,36 @@ chipid@10000000 { reg = <0x10000000 0x100>; }; + cmu_peris: clock-controller@10020000 { + compatible = "samsung,exynos990-cmu-peris"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names = "oscclk", "bus"; + }; + + timer@10040000 { + compatible = "samsung,exynos990-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; reg = <0x10101000 0x1000>,