From patchwork Mon Jan 6 05:43:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 13926964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D73FE77198 for ; Mon, 6 Jan 2025 05:45:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tUfu1-0003hg-7Z; Mon, 06 Jan 2025 00:43:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tUfu0-0003hR-Ai for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:48 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tUfty-0004Hm-UE for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:48 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2f43d17b0e3so20477573a91.0 for ; Sun, 05 Jan 2025 21:43:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1736142225; x=1736747025; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H/EMwbW9ao32OaXwASoWqvLNsXxITTvHnX2/S/pK7bk=; b=DD7VN7iZXDPBixbxaoPfg1GvzXm8toK/m3NQHNHhjYFt2wBIMM+faRM3kHlOOAiKPL mXbFAXf4jingnrG5wBPcsfAjDkAVLI1vv7OTxEe3Z5yWKOheow/KlwcSsRia3r4zUG50 4xzYbDGdKd/sHyl6r/KTun6gAQtuRFnbv1V7GpsDni9p0+AYswwDSwgeqnCiLoE63b3W VS8fJuqoMl+YWHLiA+8m2rl5Tt1OfA9U2TjBdBuIAQYdRcnq+R7NB8x/JyhNE0nXp6tg 1KDkpt+LUii+S4ziCf5VY3Ax17lD/VD/FI1Y0HHOEi/oHaotCL26gheJBuK0LqwsC8UG FVhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736142225; x=1736747025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H/EMwbW9ao32OaXwASoWqvLNsXxITTvHnX2/S/pK7bk=; b=pBatcOodFNv3eaYAMX4pjpvyB+cpUWIBe1+q0lf8NiridQOWCFAueei3E+4U9JJEmj I2CWR2Lb6LoYGbrAYEXaUSFQDUjWE+ZhtItwKtWzVPYJikb+J22fDfr1PmkgoicNf1MA T1UqsvK4EjThBExi2+gTbU/mv1B1a4C1RsVqVjrxbnOpttVmOxhXvRCndvPR6OSrBZvX wFEkjfTlzW0AUkq4ENrrVOij2AIgEQ7sWyGWEELg8jAzHIsZ7GzP84SIBlL20b/1fYIE b/sDaK4OsB00oTCJnDkGTOcaxZS6RP27jDkRtUbAAURYMtlooDVpX6ibBWpZy8WI+CqP auPQ== X-Gm-Message-State: AOJu0YylZP1z1jBuQtzTWgsz9i6v3pxhFJWUQM4dH6/kJsRnUldqnXqH hW+1CuWNku83K1O75pgIvfa+NRhH5VSp2Wk6PdE4AUGkWkW9EDcY0hW08rFAwGg/ZSfN5FUi9+9 T9Npe/n27Hj7ALd8/ZQCjHmVhoP4UVaxrdIXBcdjsDgdjqhBQGb1AIIwzP7PCiYDOAEUJz26/sn Lf0eWBTXDVcu11yfhoBieWkYB85SgpKeVc/RpfQ6UUPg== X-Gm-Gg: ASbGncsawkuymdJiwiilVwM8od3/FPj/LTXOfH5tBQ5vVKzN9wPfmit5luSTGSDD+dW vZcAGp6i0rlDFYz5Mqnv0uK0n+qarWXJsXeEq23qvndTZESlTp7RsYiJezrNiR4L8Xjc6zYEWz/ iagcu+5g26d+e9xDUYCjtzM35WFuDAiOM2g3rZJwtghSZvAeuPeufEBkgTUW+++aZ7UxIHD+DNO gk5QbFC2jnDFhGlz+csRCm+N2aQ4NTSBAkig0n6ItM8Jlw3+6cYubk8wF9c+DxN51iAMLwzXN3D Dnt1Dq7RynA= X-Google-Smtp-Source: AGHT+IEtvkda5k/jHKPGaQepjhqIYd2Hl+ttgBCcPenIceaQwpNr3fumalfhX7c3zDEYdmYSaNHjRA== X-Received: by 2002:a17:90b:1f92:b0:2f5:63a:44f9 with SMTP id 98e67ed59e1d1-2f5063a47b8mr17635688a91.23.1736142224491; Sun, 05 Jan 2025 21:43:44 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc96eac6sm285722215ad.80.2025.01.05.21.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 21:43:44 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tommy Wu , Frank Chang Subject: [PATCH v12 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig Date: Mon, 6 Jan 2025 13:43:31 +0800 Message-Id: <20250106054336.1878291-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106054336.1878291-1-frank.chang@sifive.com> References: <20250106054336.1878291-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu The boolean variable 'ext_smrnmi' is used to determine whether the Smrnmi extension exists. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fe0c4173d2..28b43932db 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -129,6 +129,7 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_smrnmi; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl; From patchwork Mon Jan 6 05:43:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 13926961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2267FE77188 for ; Mon, 6 Jan 2025 05:44:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tUfuB-0003kC-5h; Mon, 06 Jan 2025 00:43:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tUfu8-0003j5-3A for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:56 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tUfu1-0004IF-DK for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:55 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-21644aca3a0so14655225ad.3 for ; Sun, 05 Jan 2025 21:43:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1736142227; x=1736747027; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z8LsyuACSdwiN3QycgR2G1Ajx+zirWJN8wOULR7lYME=; b=Q8jT2oMkP7Z5H1DuwWKorjw+8D2G//gYtox6lEetLCsHElImbtso/fX8En5oThShX4 MiO+dvxzVohyABnFLGd5BgctZUIX//DLL+g1fVE7bmLnKaaGypv814TlAifr1ao2TB1B nuFQ1Bp2quX0MmPwYyxAZfOKflhRkHpfRHfEJW9pwS0QdwP4mES8cjR7FWaKQ8QB+/TY +oyaZWZHGIs7+SwnKbIsBWe27czdour6Cw/aRbSIIbA3I1vS0hKWVX948HVOqhqy2mxk gswZOd17Zt3xQ99GOUBPQfi5YOmZzUQZaksBNKATjCzHMstVFZFdrEXZRI63o4a60zDX ElcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736142227; x=1736747027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z8LsyuACSdwiN3QycgR2G1Ajx+zirWJN8wOULR7lYME=; b=mTo5eXVBdl0H31Z6WS96nekXGz4mDrYRWcOPtoB+5J9EFCcWdJSNGNjN9DYyVzvb/I RvCJvTom2mb3hpiw1Q7NhWcrG1s3wObFRLcRsNbGdeOXkyl66iUsCRcuiH4Wzf48Iokn wbyfRdK6JabzDKmvxa4x58TDxfN+4fG1ao+Mp8kg+b9nAjcepQLLZbOtMbZwW/fElyN4 81vEWCW2mC+3Giyj3bTnAOHeiYa4NmRZ7qGe2FpPnWyx8a/9on7ppZgpvCjUmxSkcgMZ c80ejNa6x/OiHQbFJmpjPTekM1dst5gQb/CgR1kIoQnMDbVu5d4hY3NeKKpFGb6jt5kJ S42Q== X-Gm-Message-State: AOJu0YyTY0Tyq81YpaYAp1D4CG+5yYcHgeO5sK9/SWsi8QTzkl/JnR5n MKwk7ET6AkiJT+hCjVtd0+S3ul3DzXvOt/4BnClfdC0mcPmlpiZZ3AoXcbOUzkgfAOFFfdvbDbn HVtpFA9zAjS/QZhhd+pUQkpHCqLYdkxcvasGTnGweY7kNEr6r0BAuDrLoN3K0BAqXDj1N2LacF1 +FUWkd9VvFsv/d5aTvY5A6zqS4/9rv1Ocp4F0EFil8WA== X-Gm-Gg: ASbGncvyZSxQFSVOrg+S/V6AEFF06wp3OXEs6Ui/MgOrD2fFmv7fUFmsRze5LSU4Lqn ueDE1hewTt9XmG+vQ6YZ1FpYDhtzb4+TuBBZ/fpTjnhk4+EZWxa6d2DDIfwxBl/wN+lzSQYEpfB 1x1I7aVIRbv8VUQtCsEv98l4wixoykj3D3g/MHnBYC+TprhMHae/4didNfosf1NMyl8iu48+5Br kk/I+VyzG15CIgKUd5Y84N53sbsjCEbZxYyIg8jtUta1N/1a2qQtk/amIfEhdmRXLW+2QSoi9rw blBnAocNVEs= X-Google-Smtp-Source: AGHT+IGpkfpqcJ422VPzvGxmOocPMDyJbrbt60c37ldrNFkHp8G9QGvYmih9ucBZLDSfXITxtgcNug== X-Received: by 2002:a17:903:22c3:b0:216:6769:9eea with SMTP id d9443c01a7336-219e6f133ccmr839763165ad.37.1736142227270; Sun, 05 Jan 2025 21:43:47 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc96eac6sm285722215ad.80.2025.01.05.21.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 21:43:46 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tommy Wu , Frank Chang Subject: [PATCH v12 2/6] target/riscv: Add Smrnmi CSRs Date: Mon, 6 Jan 2025 13:43:32 +0800 Message-Id: <20250106054336.1878291-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106054336.1878291-1-frank.chang@sifive.com> References: <20250106054336.1878291-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 7 ++++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 954425081d..2ae9a8a895 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1134,6 +1134,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) riscv_trigger_reset_hold(env); } + if (cpu->cfg.ext_smrnmi) { + env->rnmip = 0; + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 252fdb8672..0079c640f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -486,6 +486,13 @@ struct CPUArchState { uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; #endif /* CONFIG_KVM */ + + /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; + target_ulong rnmip; }; /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fe4e34c64a..9e9637263d 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -353,6 +353,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -634,6 +640,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 381cda81f8..f35b8f4c21 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -597,6 +597,17 @@ static RISCVException debug(CPURISCVState *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif static RISCVException seed(CPURISCVState *env, int csrno) @@ -4654,6 +4665,67 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch = val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc = val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause = val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask = (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |= MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus = (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif /* Crypto Extension */ @@ -5161,6 +5233,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_sstateen_1_3, .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* RNMI */ + [CSR_MNSCRATCH] = { "mnscratch", rnmi, read_mnscratch, write_mnscratch, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNEPC] = { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNCAUSE] = { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MNSTATUS] = { "mnstatus", rnmi, read_mnstatus, write_mnstatus, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, From patchwork Mon Jan 6 05:43:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 13926966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09053E77188 for ; Mon, 6 Jan 2025 05:46:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tUfuA-0003jd-4C; Mon, 06 Jan 2025 00:43:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tUfu6-0003iu-RZ for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:55 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tUfu4-0004If-Bq for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:54 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2163dc5155fso194934435ad.0 for ; Sun, 05 Jan 2025 21:43:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1736142230; x=1736747030; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DntsfFBjwCA5RYsDFTsuywnSc4lKU2VsGQNjqTvtrY0=; b=HHEMZWdiOsi9J0J+9Jo2fuWPPP+EnLbzPfK8ITb/gRxnARvxpLtkrg6hyq6PDXBC8l hfZzha2Lds/Bngm3sPl4wT5yE6ReLmQTndgSYqSluyn7W3xkiBdQDB7k5xH1yzwS9n1Z mWA1FimT4wuODoHn3lY4xKbm8KzzgRt5mCu0HutbBjHbuk0TEObQLGm6zYVcsm4X8jUm 64F2rt7h100IbNL9yX1JEOwnoqXJZaUY5jQWorW3uOr21al3G5DoxLzus5ZXfLUoVssW LVpL0g9hHyKVSeD2qhjBYbnnxhsgVz7SlD5y0+iqSgfUSH9zlGrQP4VF10mQi6tV2GCZ 7EGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736142230; x=1736747030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DntsfFBjwCA5RYsDFTsuywnSc4lKU2VsGQNjqTvtrY0=; b=pWX398eVoyz2HrvL3mKeanLtjAhpVA/JdqwUcJL3X7JHpmolTFBGk8dpStoQn29XGq JIa3BOi4gQlQ2x5Kf3IPLPr5jkuf9TUpDVo3xtTTM+wYTsbNcrmQv6sPKP0T5vDqCAKG XHy684Bp0Q2vdOH9v711qMOii8m4ouG/fRMmzDKb67dK5CMJ4yAYqLpdMK43recZYxul rIhp2NJ9p7lzsUh22qEMaXQ1c0a8w4Hztru3bqDdOEXHEYkuUZWQd8SYTVVQjHiLDtKh U3Z6d/g/ObYggZfp9nFYmug2zmjIDnBzazzoqJPD+ItUQF+04moJ0qOUEkq2B3Vy+tZB yWBw== X-Gm-Message-State: AOJu0YyHoV+qhQ4aY1WZTkkcwwUBT6QwpZlQS7ZcIwL9PYBdGBMu7m5e 37CsX/kNSKUh3ZWoYvYnWJlI7aVBtrmCFOF/WkTH5Zm08QwmxJqDUyClCUMAhgApqDQ9TvQjpAW S9BFMZEdC8ihIL+8wiXKPh20h3D1Rr9hKI8qOBQq2ejq6ccf6PB/18W0RO3OWQ5/Fe2aRquRDoY gVvtCkdVD21eQrJ9X4770/IX5q5XzoynX0zgW8IBrdGA== X-Gm-Gg: ASbGnctGtBuY9EvtT7OZrwidp0MgWCjR8Rbl144EUtgG9FX3Qp5iqKXyzEv6BueaSHQ J/HnksSWh4L8DEWpZhKiixb5t1DnrChl6Qxj5OeJhR0lNr6CRMVeK2+MY9xsxEN0gfR8UDRVN8t AiXE2m6X6Rnc7F0vhe9d0MBhGZRf4u95r6O5mcWjCtkDCu8nRkyN2g+7SiiZlbUUEZZZDQVECoD D0qrMPTB566rHBSnsKvj8AAOkv01d27B44jnDs/+GubNA08u2HSk0QntBnPrB5dk98+E9wb4rmJ YhgNohVgckU= X-Google-Smtp-Source: AGHT+IFXh5lAPkoTO7Q8rwrJebnYfNjWOTFXozz2ra+By2e3gSJpjGiUQzswqXXxEgTzdWyw3IodPw== X-Received: by 2002:a17:902:d48a:b0:215:b8b6:d2ea with SMTP id d9443c01a7336-219e6ea1cc6mr748732875ad.15.1736142229963; Sun, 05 Jan 2025 21:43:49 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc96eac6sm285722215ad.80.2025.01.05.21.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 21:43:49 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tommy Wu , Frank Chang Subject: [PATCH v12 3/6] target/riscv: Handle Smrnmi interrupt and exception Date: Mon, 6 Jan 2025 13:43:33 +0800 Message-Id: <20250106054336.1878291-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106054336.1878291-1-frank.chang@sifive.com> References: <20250106054336.1878291-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to handle the RNMI signals. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/riscv_hart.c | 41 ++++++++++++++++ include/hw/riscv/riscv_hart.h | 4 ++ target/riscv/cpu.c | 11 +++++ target/riscv/cpu.h | 3 ++ target/riscv/cpu_bits.h | 12 +++++ target/riscv/cpu_helper.c | 88 ++++++++++++++++++++++++++++++++--- 6 files changed, 152 insertions(+), 7 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index bc9ffdd2d4..62b7c44350 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -26,6 +26,7 @@ #include "target/riscv/cpu.h" #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" +#include "qemu/error-report.h" static const Property riscv_harts_props[] = { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), @@ -33,6 +34,23 @@ static const Property riscv_harts_props[] = { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), + + /* + * Smrnmi implementation-defined interrupt and exception trap handlers. + * + * When an RNMI interrupt is detected, the hart then enters M-mode and + * jumps to the address defined by "rnmi-interrupt-vector". + * + * When the hart encounters an exception while executing in M-mode with + * the mnstatus.NMIE bit clear, the hart then jumps to the address + * defined by "rnmi-exception-vector". + */ + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, + uint64_t), + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, + uint64_t), }; static void riscv_harts_cpu_reset(void *opaque) @@ -46,6 +64,29 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); + + if (s->harts[idx].cfg.ext_smrnmi) { + if (idx < s->num_rnmi_irqvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-interrupt-vector", s->rnmi_irqvec[idx]); + } + + if (idx < s->num_rnmi_excpvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-exception-vector", s->rnmi_excpvec[idx]); + } + } else { + if (s->num_rnmi_irqvec > 0) { + warn_report_once("rnmi-interrupt-vector property is ignored " + "because Smrnmi extension is not enabled."); + } + + if (s->num_rnmi_excpvec > 0) { + warn_report_once("rnmi-exception-vector property is ignored " + "because Smrnmi extension is not enabled."); + } + } + s->harts[idx].env.mhartid = s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 912b4a2682..a6ed73a195 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,10 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint32_t num_rnmi_irqvec; + uint64_t *rnmi_irqvec; + uint32_t num_rnmi_excpvec; + uint64_t *rnmi_excpvec; RISCVCPU *harts; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ae9a8a895..29d530ad85 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1419,6 +1419,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level) g_assert_not_reached(); } } + +static void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level); +} #endif /* CONFIG_USER_ONLY */ static bool riscv_cpu_is_dynamic(Object *cpu_obj) @@ -1442,6 +1447,8 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ general_user_opts = g_hash_table_new(g_str_hash, g_str_equal); @@ -2798,6 +2805,10 @@ static const Property riscv_cpu_properties[] = { #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), #endif DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0079c640f7..2c4f12e1e1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -493,6 +493,8 @@ struct CPUArchState { target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ target_ulong mnstatus; target_ulong rnmip; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; }; /* @@ -591,6 +593,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9e9637263d..17787fd693 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -680,6 +680,12 @@ typedef enum { /* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 +/* Default RNMI Interrupt Vector address */ +#define DEFAULT_RNMI_IRQVEC 0x0 + +/* Default RNMI Exception Vector address */ +#define DEFAULT_RNMI_EXCPVEC 0x0 + /* Exception causes */ typedef enum RISCVException { RISCV_EXCP_NONE = -1, /* sentinel value */ @@ -734,6 +740,9 @@ typedef enum RISCVException { /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) +/* RNMI causes */ +#define RNMI_MAX 16 + /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) @@ -972,6 +981,9 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 +/* RISC-V-specific interrupt pending bits. */ +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 + /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f62b21e182..e90b85f2cd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -505,6 +505,18 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) uint64_t vsbits, irq_delegated; int virq; + /* Priority: RNMI > Other interrupt. */ + if (riscv_cpu_cfg(env)->ext_smrnmi) { + /* If mnstatus.NMIE == 0, all interrupts are disabled. */ + if (!get_field(env->mnstatus, MNSTATUS_NMIE)) { + return RISCV_EXCP_NONE; + } + + if (env->rnmip) { + return ctz64(env->rnmip); /* since non-zero */ + } + } + /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { mie = 1; @@ -567,7 +579,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - if (interrupt_request & CPU_INTERRUPT_HARD) { + uint32_t mask = CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI; + + if (interrupt_request & mask) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; int interruptno = riscv_cpu_local_irq_pending(env); @@ -699,6 +713,30 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) env->geilen = geilen; } +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) +{ + CPURISCVState *env = &cpu->env; + CPUState *cs = CPU(cpu); + bool release_lock = false; + + if (!bql_locked()) { + release_lock = true; + bql_lock(); + } + + if (level) { + env->rnmip |= 1 << irq; + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); + } else { + env->rnmip &= ~(1 << irq); + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); + } + + if (release_lock) { + bql_unlock(); + } +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env = &cpu->env; @@ -1849,6 +1887,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool write_gva = false; bool always_storeamo = (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); uint64_t s; + int mode; /* * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -1866,7 +1905,24 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; int sxlen = 0; - int mxlen = 0; + int mxlen = 16 << riscv_cpu_mxl(env); + bool nnmi_excep = false; + + if (cpu->cfg.ext_smrnmi && env->rnmip && async) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPV, + env->virt_enabled); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPP, + env->priv); + env->mncause = cause | ((target_ulong)1U << (mxlen - 1)); + env->mnepc = env->pc; + env->pc = env->rnmi_irqvec; + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_mode(env, PRV_M, false); + + return; + } if (!async) { /* set tval to badaddr for traps with address information */ @@ -1960,8 +2016,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); - if (env->priv <= PRV_S && cause < 64 && - (((deleg >> cause) & 1) || s_injected || vs_injected)) { + mode = env->priv <= PRV_S && cause < 64 && + (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M; + + if (mode == PRV_S) { /* handle the trap in S-mode */ /* save elp status */ if (cpu_get_fcfien(env)) { @@ -2016,6 +2074,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) ((async && (env->stvec & 3) == 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S, virt); } else { + /* + * If the hart encounters an exception while executing in M-mode + * with the mnstatus.NMIE bit clear, the exception is an RNMI exception. + */ + nnmi_excep = cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; + /* handle the trap in M-mode */ /* save elp status */ if (cpu_get_fcfien(env)) { @@ -2043,14 +2109,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MPP, env->priv); s = set_field(s, MSTATUS_MIE, 0); env->mstatus = s; - mxlen = 16 << riscv_cpu_mxl(env); env->mcause = cause | ((target_ulong)async << (mxlen - 1)); env->mepc = env->pc; env->mtval = tval; env->mtval2 = mtval2; env->mtinst = tinst; - env->pc = (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); + + /* + * For RNMI exception, program counter is set to the RNMI exception + * trap handler address. + */ + if (nnmi_excep) { + env->pc = env->rnmi_excpvec; + } else { + env->pc = (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); + } riscv_cpu_set_mode(env, PRV_M, virt); } From patchwork Mon Jan 6 05:43:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 13926967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A073E77199 for ; Mon, 6 Jan 2025 05:46:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tUfuE-0003lZ-3s; Mon, 06 Jan 2025 00:44:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tUfu9-0003jc-Ob for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:58 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tUfu7-0004J5-V7 for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:57 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2156e078563so172625975ad.2 for ; Sun, 05 Jan 2025 21:43:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1736142233; x=1736747033; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DMWiwVoFUO9CgNCJuVDY2YJrtySv3drqiXkHUeaBqX8=; b=CHRjJsut+ogbOScYqtkgw04fIa6NiS9hYF2nEtbFk7VeGvLNVK4R7pcNhg7cKvoY3y w1rZ/yRZLRWxJGqMHa+aiLLDu+oF3D6Sio5y/FoQjZGzyU/0iKzPVIF+LBxKQKweABvb DiVmcEb8oVdra3TN2bLb0A8i6HUxm3PQGaxPIDz3KQpQ4QWIMykwhAycxZCTD8yrx6yk aPWzC+kfLHyO4ZLWc40ghusoNf39lryUPVLu9tWczE0Ub4tUHvFm8LHYF1bcOG1oJVf0 fCjzoVQuXh1efAkdlCAJlHxDYDFmyHLY7WAxudjhYWSr76BZ1rmQ6YBysm2y9wuT3WFe cHaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736142233; x=1736747033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DMWiwVoFUO9CgNCJuVDY2YJrtySv3drqiXkHUeaBqX8=; b=jf3uqbLthdwOWE0TAKQAwz5BeEOo4+Nc9hgvgMqJULpj5OQk56gn6gHO5U1qbGYjRm b9Yo2pfac2U8wbGtG5b6jMfsBV+qeplWd8fY3MVMsFWVGdT5QSa3SmRNF26GC3pLMRwl tYoMcnEwA0Z3PkNnxijCb1c1h1uN35fEbBYBIZAKDaZdhRhAdHWqSR2YC4fJMuSVdu8K Mqti7CLURlQ1NRmll9RO2SEP7ch6B9QnuWe1LFP6u3MQA3u8ozEDxubiJFKxuuQii9Vt vv4HQOu+DvKj11HEiS1Fj6ixR+IudnFJdfIW0XVxXB1wIJzKCam2trqC/IF1lagfs1BR KGqg== X-Gm-Message-State: AOJu0Yx1hTBwYBUo+5pBKhrTawjGxyQjMJkQ4bK4JKv2JLsmg1S85Zrc 3YhcF0CgejBTEVSevog3bzY4ozNkDmw2NVOoli6hyAX2ntfd4IPhgfBe1HR2RDnchgSSh0MPSXC RKPz8mokedKF30M84u1sE6oWtw4egQLLdfZ+s9w9YEItKrOJ8l1htayq5ydZS9pxile0N/N0DVt sKDNR+nQrNluvqgCCP7tnLvnP3J5UZzHhAjxqkvhGw2Q== X-Gm-Gg: ASbGnctd59NRW++yKzEzybeU54eJO1mAeUXNrZFQDbMMhOMe//jbMWYd69j5C1E+9ps lRN/zXGcjiakkv2IxsUzx2Pb7GOAECrB5e1xthWPcK1i/4Uy6W4NE75CE3GkrPuM2GJJnqfphfA WaTjvG61ZSXpButMpzgQor5KjSp2+SW9fGMGLpZXwNA5tplV8td6R3vdkSoX+DEVgC8IZeqHtjE ks5WDOsz65t1ZI2vQ32AUg7l4i9EZczWTRjN2msIl/KMa2Wsh1YXFnQ2PxyR3Z5xS3D4sbMsTqM 7UJZaMqp2K8= X-Google-Smtp-Source: AGHT+IFhpduUXhDNV5ApBzk6FHaLHzbZUkW07f75JmI1oWdcVEvjHQkXKvAByG9o+zSrKVUl4dBZGQ== X-Received: by 2002:a17:902:e84b:b0:216:6f1a:1c77 with SMTP id d9443c01a7336-219e6f105d3mr774972755ad.43.1736142233140; Sun, 05 Jan 2025 21:43:53 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc96eac6sm285722215ad.80.2025.01.05.21.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 21:43:52 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tommy Wu , Frank Chang Subject: [PATCH v12 4/6] target/riscv: Add Smrnmi mnret instruction Date: Mon, 6 Jan 2025 13:43:34 +0800 Message-Id: <20250106054336.1878291-5-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106054336.1878291-1-frank.chang@sifive.com> References: <20250106054336.1878291-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 20 +++++++++ target/riscv/op_helper.c | 45 ++++++++++++++++--- 4 files changed, 64 insertions(+), 5 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 451261ce5a..16ea240d26 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(wrs_nto, void, env) DEF_HELPER_1(tlb_flush, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e9139ec1b9..942c434c6e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -121,6 +121,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u { diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index ecd3b8b2c9..73f940d406 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -18,6 +18,12 @@ * this program. If not, see . */ +#define REQUIRE_SMRNMI(ctx) do { \ + if (!ctx->cfg_ptr->ext_smrnmi) { \ + return false; \ + } \ +} while (0) + static bool trans_ecall(DisasContext *ctx, arg_ecall *a) { /* always generates U-level ECALL, fixed in do_interrupt handler */ @@ -106,6 +112,20 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + REQUIRE_SMRNMI(ctx); + decode_save_opc(ctx, 0); + gen_helper_mnret(cpu_pc, tcg_env); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b..63ec53e992 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -321,24 +321,30 @@ target_ulong helper_sret(CPURISCVState *env) return retpc; } -target_ulong helper_mret(CPURISCVState *env) +static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, + target_ulong prev_priv) { if (!(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } - target_ulong retpc = env->mepc; if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } - uint64_t mstatus = env->mstatus; - target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); - if (riscv_cpu_cfg(env)->pmp && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } +} + +target_ulong helper_mret(CPURISCVState *env) +{ + target_ulong retpc = env->mepc; + uint64_t mstatus = env->mstatus; + target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); + + check_ret_from_m_mode(env, retpc, prev_priv); target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) && (prev_priv != PRV_M); @@ -370,6 +376,35 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } +target_ulong helper_mnret(CPURISCVState *env) +{ + target_ulong retpc = env->mnepc; + target_ulong prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP); + target_ulong prev_virt; + + check_ret_from_m_mode(env, retpc, prev_priv); + + prev_virt = get_field(env->mnstatus, MNSTATUS_MNPV) && + (prev_priv != PRV_M); + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, true); + + /* + * If MNRET changes the privilege mode to a mode + * less privileged than M, it also sets mstatus.MPRV to 0. + */ + if (prev_priv < PRV_M) { + env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false); + } + + if (riscv_has_ext(env, RVH) && prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_mode(env, prev_priv, prev_virt); + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs = env_cpu(env); From patchwork Mon Jan 6 05:43:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 13926965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE5FDE77198 for ; Mon, 6 Jan 2025 05:45:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tUfuE-0003mF-MF; Mon, 06 Jan 2025 00:44:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tUfuB-0003kG-BK for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:59 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tUfu9-0004JV-Ot for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:43:59 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-21636268e43so14402465ad.2 for ; Sun, 05 Jan 2025 21:43:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1736142236; x=1736747036; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lo+Qbn3A7nMoxmaDM+Be00oVtg6NcANgPSVAsqKGf7E=; b=ftXFen5IkYPY1kBbq04QjW+HC2BfNKqMBXykkqs39vJZDsAMTg5vg/YwfwS4HgK6X/ uq/Lz6xcvTJID1sdLGaP04+icXrhgmvB+TnO1cORZVw4MGQYNEBcJmPHP1QcEfILGacA oHUAdwJm7BcBJfW18okvWOcSmFMwzPjaeFEtP4nZH6G/3kjAMsQ1COWwhs4w8wPnb3+U fY5cWfEAI6hCOPUwUS7Kwo8SzsTr0siv5nH8aLSTp6DaW3eQMFoxbSqKmockvI3/Uhld 1kG5CSjUEEkSvNmLGVkWYbP1QIm1kxrHvc+zuQ7GhjPzN/mUQRbiPvEYVb15jy52/TIt zLdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736142236; x=1736747036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lo+Qbn3A7nMoxmaDM+Be00oVtg6NcANgPSVAsqKGf7E=; b=GijqiXvF8Ve4YDuH1/zxffo4/P5FwDZej3UbkqB11Xi/Y3yCoHylKJX4h9bQOIpecs BfjXGfDjvwgI8AadsEGnldM9z1JY+jgPnaN0KUHmWuJgsO60jTAOh1QV4hxxuQwU+vnV WCGtnUy8jbacWz42qNqS3tPSsU1aR7qBqW6aYwXmGHHoz++SzU3bWRieQFu6t709z1Rs EMU8x/IyLCkhoMwPs9FaJiZzgJZH0/fwZedQoVDu/p1zXewMdBP5k34L5+wKjW96NWQ2 8hqjEH2QNNNsHyY6oySU7QVQqi2DqabnrIufMEjmWjDYTdBQX4eud454/coa2NGvL+MP ME0w== X-Gm-Message-State: AOJu0Yw0cMPdGXw0n4rBwq8D1PJGGngUsOuUBjZNMNKsdW1N/VNctrdV VRAUm38WqOxBVM/VWCsy28X/T8tJSwe4KAlEFjfaMA3zK7Zu9+qS7UOBrgBuht9468wo30VJWeM LRMTlyMrvCEnrA7R7p46ZBb0iZlbO5rXh11Mp+L4PP4jkvxv5gZcJuKtVyzxe+xers9Gz2/wyDz 0B7Vk/tWSg8gqAPIxmz3BF1qd2kVO6mpQ0lqaSrVCulA== X-Gm-Gg: ASbGncvBE3gfFW0F4mksmZ/Uh1Vh1wvXB4OvK7HLDKrfVo2Sy5phAFXnDkoKx2JLZmk JffK/HqjC2nDv1sNOfQgK5OIL0QsygL2BXmTQQeMulXvacMcIOF47fZSFKvcQHeGAGDON/BF/a8 prQ8gKqUUHlYQKeSgqqLcQkidu3WyHzjyz7E1RHbGSPiicCExasxnCxgrzjFmZPHNzIjTIRy82j XMp4sdkCtHMMcVfQB089SxsorDr9bA4jkb2ev5e5YetAmWw4/0L1ijiy+MjvlHt5pga/zekQCr7 QyG+JrLtKc8= X-Google-Smtp-Source: AGHT+IHWU++NW0+tcazJZn6R+qRAOGkTkpbSd0uEs/QRr0TocMp7y+iFfioTubbETH7rRfffIXg79Q== X-Received: by 2002:a17:902:c40e:b0:215:853d:38 with SMTP id d9443c01a7336-219e6ebb75bmr790968905ad.25.1736142235769; Sun, 05 Jan 2025 21:43:55 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc96eac6sm285722215ad.80.2025.01.05.21.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 21:43:55 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tommy Wu , Frank Chang Subject: [PATCH v12 5/6] target/riscv: Add Smrnmi cpu extension Date: Mon, 6 Jan 2025 13:43:35 +0800 Message-Id: <20250106054336.1878291-6-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106054336.1878291-1-frank.chang@sifive.com> References: <20250106054336.1878291-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Tommy Wu This adds the properties for ISA extension Smrnmi. Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all interrupts will be disabled. Since our current OpenSBI does not support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for now. We can re-enable it once OpenSBI includes proper support for it. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Signed-off-by: Daniel Henrique Barboza Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 29d530ad85..d9bc0d124e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), @@ -1621,6 +1622,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e03b409248..9cfdd68fdc 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1431,6 +1431,15 @@ static void riscv_init_max_cpu_extensions(Object *obj) if (env->misa_mxl != MXL_RV32) { isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } + + /* + * ext_smrnmi requires OpenSBI changes that our current + * image does not have. Disable it for now. + */ + if (cpu->cfg.ext_smrnmi) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); + qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); + } } static bool riscv_cpu_has_max_extensions(Object *cpu_obj) From patchwork Mon Jan 6 05:43:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 13926962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFDDDE77188 for ; Mon, 6 Jan 2025 05:45:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tUfuG-0003mi-LP; Mon, 06 Jan 2025 00:44:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tUfuE-0003lu-Dm for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:44:02 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tUfuC-0004KO-Pp for qemu-devel@nongnu.org; Mon, 06 Jan 2025 00:44:02 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-218c8aca5f1so254013375ad.0 for ; Sun, 05 Jan 2025 21:44:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1736142238; x=1736747038; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t8m78Xl46ptOhKZOofTQdhh1EfKppuOWG2YufccK/Go=; b=W7CEnJuLZ7cGPPKoyWRvdWRIrPA6Oi8kOkCnUByQ3HuAc7+pBhw5He7qq3A+vFxUVY lIx72Dfa44DqJDUNw+ob2F9uuhtmP3SGhbHHPnkv7pKfKUW6QKL46HrCFiHFkvquxq9w Lj/33M41eym1KMRBkhM1gzfFcY1nrgx2D55YJcmqL8lTSJgP/bkI3rIQVf62lW9wSS53 3Ec59t52vN8UxMn7snASlialy73tde/GesDXrJFsW9PNCYFCrIzfQT+fNRDcrJRcoJXr H35d9NH7zxQb0gb2jhwOxZrggEl1V3G0d9tfvcYy1MPpPYJ0ECm0LCVWZ4hexQy6l90N Zyag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736142238; x=1736747038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t8m78Xl46ptOhKZOofTQdhh1EfKppuOWG2YufccK/Go=; b=SjXrI7AyQJOguz8fk15j339PTog4J8srPiIiC+940yPPJ622wt53l26P68h+2ryxfz IRWH8ORc4KzyL5Tm/kjaMONPNClfN0mtuxsb2Vo/HJ/Q0vCiscQJq5gk9W58cluWa3Ky WP02/UuHfUBLRqIcyGSHJfOjzxWtveP8FtHm89o8NJQdO9NkzVGQ29cESjIWZGBEYAlm Mpbn+GJTyT2TyO4PtKFUVTHm7Uh/63hulzs2dh9zlvuwU4mW/e2KIMQ1jVPXeQeoPveL eajW95QOhZQUvkN2uo5YDKWxguaDPHuVpFxsnP1uZHhmWSvnW6nmi/zi8W+xNJezm0sf wxdQ== X-Gm-Message-State: AOJu0YwEubSDlnRKZAm8JSRiZRLptcrhqYDaFTJME0vpESQ6GZhHZWcL VUf4YqkR1GCGkgkj2R2kGcjOnt7s4fnxyAv5FMWLNabU7CqIv2Q9SFGrovwNVMWnfglISVP09gZ JnoNKXjNlqeO1yDNn/6Z37nx/Zm/3PLiZ9XGe1HDPHNvEw4/Vvo7gudFLlTPC+xmdWV5QnjFglW lRMWSbWmIrnfLriSOuwdNqlcuz7WqAdHat5KffMaiR0g== X-Gm-Gg: ASbGncuWCZWVBPeGX4yAK+LSoz54b4nfKtuGj7r8pRrtfGkmq7vPJjG/L5OfNXDc/eY ZdTioFn9Uat3HYNNTcpdS3ITj12RxIIOIuAiyYNX9lxxnWxBRnNo39QfEHcInTtus9+TZ68OjG9 GVkhxZ7yv2zRMw13q5ispLXpOeqgwgSovycY0XdJzCvaXruOnYkjn+3bv5kqfxCKPs6Q6jyH+OE PfQ1tO+7ZFaQa5JDKMzSG9zcEs0vKBzXNPwXDuD/k5K3qylEZGHRfX5wyBvMcbx6EeGWMVxzIPV JCXZC2D9Md8= X-Google-Smtp-Source: AGHT+IGdsUM0by9JB8swIeXcXINa9alfU+PpMt1KUpX4njEQWM3cyOwD6Y0UtVVurjuq7zAvIknuZA== X-Received: by 2002:a17:902:ea11:b0:216:4016:5aea with SMTP id d9443c01a7336-219e6ebaf1amr850553345ad.29.1736142238328; Sun, 05 Jan 2025 21:43:58 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([210.176.154.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc96eac6sm285722215ad.80.2025.01.05.21.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 21:43:57 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Frank Chang Subject: [PATCH v12 6/6] target/riscv: Add Zicfilp support for Smrnmi Date: Mon, 6 Jan 2025 13:43:36 +0800 Message-Id: <20250106054336.1878291-7-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250106054336.1878291-1-frank.chang@sifive.com> References: <20250106054336.1878291-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frank Chang Zicfilp extension introduces the MNPELP (bit 9) in mnstatus. The MNPELP field holds the previous ELP. When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the value y, then ELP is set to the value of MNPELP if yLPE is 1; otherwise, it is set to NO_LP_EXPECTED. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 11 ++++++++++- target/riscv/op_helper.c | 9 +++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 17787fd693..be9d0f5c05 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -643,6 +643,7 @@ typedef enum { /* RNMI mnstatus CSR mask */ #define MNSTATUS_NMIE 0x00000008 #define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPELP 0x00000200 #define MNSTATUS_MNPP 0x00001800 /* VM modes (satp.mode) privileged ISA 1.10 */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e90b85f2cd..8a31b9fe7b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1918,6 +1918,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mnepc = env->pc; env->pc = env->rnmi_irqvec; + if (cpu_get_fcfien(env)) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, env->elp); + } + /* Trapping to M mode, virt is disabled */ riscv_cpu_set_mode(env, PRV_M, false); @@ -2085,7 +2089,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in M-mode */ /* save elp status */ if (cpu_get_fcfien(env)) { - env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, env->elp); + if (nnmi_excep) { + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, + env->elp); + } else { + env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, env->elp); + } } if (riscv_has_ext(env, RVH)) { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 63ec53e992..a4b625fcd9 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -402,6 +402,15 @@ target_ulong helper_mnret(CPURISCVState *env) riscv_cpu_set_mode(env, prev_priv, prev_virt); + /* + * If forward cfi enabled for new priv, restore elp status + * and clear mnpelp in mnstatus + */ + if (cpu_get_fcfien(env)) { + env->elp = get_field(env->mnstatus, MNSTATUS_MNPELP); + } + env->mnstatus = set_field(env->mnstatus, MNSTATUS_MNPELP, 0); + return retpc; }