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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e384054sm4880929f8f.36.2025.01.10.08.02.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/9] hw/arm/stellaris: Link each board schematic Date: Fri, 10 Jan 2025 17:01:56 +0100 Message-ID: <20250110160204.74997-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Board schematic is useful to corroborate GPIOs/IRQs wiring. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 1bba96df14e..9b414ff9069 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1379,6 +1379,10 @@ static void lm3s6965evb_init(MachineState *machine) stellaris_init(machine, &stellaris_boards[1]); } +/* + * Stellaris LM3S811 Evaluation Board Schematics: + * http://www.ti.com/lit/ug/symlink/spmu030.pdf + */ static void lm3s811evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1395,6 +1399,10 @@ static const TypeInfo lm3s811evb_type = { .class_init = lm3s811evb_class_init, }; +/* + * Stellaris: LM3S6965 Evaluation Board Schematics: + * http://www.ti.com/lit/ug/symlink/spmu029.pdf + */ static void lm3s6965evb_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); From patchwork Fri Jan 10 16:01:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13935108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E054E7719C for ; Fri, 10 Jan 2025 16:05:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWHTo-0007gi-DQ; Fri, 10 Jan 2025 11:03:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWHSq-0007GB-3W for qemu-devel@nongnu.org; Fri, 10 Jan 2025 11:02:26 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWHSl-0004C9-5L for qemu-devel@nongnu.org; Fri, 10 Jan 2025 11:02:21 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-436345cc17bso17025165e9.0 for ; Fri, 10 Jan 2025 08:02:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736524935; x=1737129735; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+1SHV4ouwmWCxa4hls/VEliYDrrRoOnyygtn8mgw1kM=; b=YCW5VyiDAxjhZbB1P6jmdgoxRqXchg1SqeLkZLeiikLr9RIxth2PgjYd3Nqi+6skwn pUS6ZA9WZD06I1Ku3+actb+fwPPZep+b5mBC5QYR9kOmGUGSIvmJF4Dh8fIOt2710Cbd u1Z57J2694spJhLJnXwyvth7Tm0GSSb8QpgFNz63agok4JOqpynyZHLGoMxfEqfWVqYC 5+rLOjNCV9i6h+GqgdKxumRwKHYO5y+Hu2Gi6/JgEkzPAxCPIHkbyRaoIzSmLJLqKwgT bLSGNMPzT/bz4zokIkfYmMOmJwwAhpDlftvdN/sizW3L7KmVPA0yMi/2wPaEBZyLoXdD /4qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736524935; x=1737129735; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+1SHV4ouwmWCxa4hls/VEliYDrrRoOnyygtn8mgw1kM=; b=KB8ESEzDYAalAr8B6wwlYOo8eoKOIqOKnTmOeH9Z1hJOnabmpPKhGbZPT3ZxpahgtK iKJYe1iA1/OCRs0M8vnfJOruBNzF/vSG7eS63WAjw1y4HRCSmQKC3nHbELnjyBRpeWYf dd6mEHPtm/JmWfW2CaesKBqE4wCoYJdlR76dzv/AVuYfYG/Qn7sfEMo5oaCOHKDJ0h85 V23UQXj3I9AbVo386sJQqaCvNLFTgNPZjH6GE4guSgvOH0LInNqSkzb9SYDM8/7iqxxD zfkMmPBteQv2wuq6KceqMnjALb76BEuZrpXsPmWjcqsJzuiUY6W4ogy+wYJ5K6zbDsjK Dp9A== X-Gm-Message-State: AOJu0Yzo32gyASCXJqFPSbl1nRt1tTSWP4UFtW5f054NKsYZF/BMdxQS 4dGjTmwoAXgarsMUn+XMC2QmTk84LkhM4BSHHNTuyfnkBAI7jp+v922O/ccmq64DWjkf/Nga+p+ oFCs= X-Gm-Gg: ASbGncvhBH9lxRq5QFltYHhe+qyf5Xpw/9k4veWthY5nqAXMrWWsMsy3mmAJIYcxBgx 955133eGKRTzsJ/VUztx76o8SmigBz3/sWqVXIpC/58Q4uqcaql5kpAXWjdywMkMhilCeVhjnkz euI+SFn+2MoaopEd8FXYRWl8TMzv6wVIeNHBaApuBYvjgFEJxsUIHszS4Nc7gIjJysYaQlYrASh cYmwBD7ZY6y17qimwVHRzo02pvG5Qz3B1Fab58LISy7uQht3LwfD3B6KQtTJ6bH4p4Sqazbra08 Au/u983c1ZsjaBIUqRxFfBLbkU2KcXM= X-Google-Smtp-Source: AGHT+IETBxk9KKLClJ71WnVoUuEQGWiXXoZtd+FAn7yhk7Yw5zxx/Y/+I57SN8/XWwTMBQdcLIPgig== X-Received: by 2002:a05:600c:3b0c:b0:434:fbda:1f36 with SMTP id 5b1f17b1804b1-436e26e51a0mr99968965e9.20.1736524935062; Fri, 10 Jan 2025 08:02:15 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e9e37d69sm55675815e9.30.2025.01.10.08.02.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/9] hw/arm/stellaris: Constify read-only arrays Date: Fri, 10 Jan 2025 17:01:57 +0100 Message-ID: <20250110160204.74997-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 9b414ff9069..7c9e7e6c15b 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -101,7 +101,7 @@ static void ssys_update(ssys_state *s) qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); } -static uint32_t pllcfg_sandstorm[16] = { +static const uint32_t pllcfg_sandstorm[16] = { 0x31c0, /* 1 Mhz */ 0x1ae0, /* 1.8432 Mhz */ 0x18c0, /* 2 Mhz */ @@ -120,7 +120,7 @@ static uint32_t pllcfg_sandstorm[16] = { 0x585b /* 8.192 Mhz */ }; -static uint32_t pllcfg_fury[16] = { +static const uint32_t pllcfg_fury[16] = { 0x3200, /* 1 Mhz */ 0x1b20, /* 1.8432 Mhz */ 0x1900, /* 2 Mhz */ @@ -964,7 +964,7 @@ static void stellaris_adc_init(Object *obj) } /* Board init. */ -static stellaris_board_info stellaris_boards[] = { +static const stellaris_board_info stellaris_boards[] = { { "LM3S811EVB", 0, 0x0032000e, From patchwork Fri Jan 10 16:01:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13935112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 043CAE7719C for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2da63eesm90389005e9.3.2025.01.10.08.02.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 3/9] hw/arm/stellaris: Remove incorrect unimplemented i2c-0 at 0x40002000 Date: Fri, 10 Jan 2025 17:01:58 +0100 Message-ID: <20250110160204.74997-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is nothing mapped at 0x40002000. I2C#0 is already mapped at 0x40021000. Remove the invalid mapping added in commits aecfbbc97a2 & 394c8bbfb7a. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 7c9e7e6c15b..254f7a234bf 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1001,7 +1001,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf * * 40000000 wdtimer - * 40002000 i2c (unimplemented) * 40004000 GPIO * 40005000 GPIO * 40006000 GPIO @@ -1356,7 +1355,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) /* Add dummy regions for the devices we don't implement yet, * so guest accesses don't cause unlogged crashes. */ - create_unimplemented_device("i2c-0", 0x40002000, 0x1000); create_unimplemented_device("i2c-2", 0x40021000, 0x1000); create_unimplemented_device("PWM", 0x40028000, 0x1000); create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); From patchwork Fri Jan 10 16:01:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13935110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7F19E77188 for ; Fri, 10 Jan 2025 16:05:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWHTq-0007js-H5; Fri, 10 Jan 2025 11:03:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tWHSx-0007HV-92 for qemu-devel@nongnu.org; Fri, 10 Jan 2025 11:02:32 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tWHSt-0004FE-Ni for qemu-devel@nongnu.org; Fri, 10 Jan 2025 11:02:29 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4368a293339so25797995e9.3 for ; Fri, 10 Jan 2025 08:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736524945; x=1737129745; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jNnZwPGg9I7cmBuNCb0r/kiY7/oGOFV7SpkVL4fmHdY=; b=YVGt4BFVhvuYPrg9itQb0GUOvcULsk9PmsRaoo0JpjhYCmFyqFTRKKJSadbof25nHI ecxHx5RiQHY3Imu7hBXDRi2Lbr9TUY7NKgX9+ZHf2Y3M682STr9g6KBSwhEMUXeI6qUW vJ8/KNtXsDSxkcp/WBT7ZpD6iJh1Pt5r6fqnHNeUP9D8yBwbLgm3OmAbJq2F1rqT+iYr ywLNfbqz6K1tD4ry6zGTdnIJ+AgDK+eJoDNYXaXzlDdGRxAPrPuRhxXLhXEYpOrgxlHL kT3z37Tsqdx1r/RYH2jDn5xJrIb/f6d//r8++ebFUrJGWWECoQeUunZo58hqCDJ9KuRW buRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736524945; x=1737129745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jNnZwPGg9I7cmBuNCb0r/kiY7/oGOFV7SpkVL4fmHdY=; b=kPK/i0JQhvpbsLAJzDHWo+aSTsSbQYn0jfzQtNNSVZyLnOWoB3ibjbFsSrjWDVRYYb H/F2NdEqUzPK5s2xqjwVLY+7vbPmtLqk4H11COe9/Sj74hpRuJboBBj5MRVttNmpfURX QK4xU7ebdbvFD1GNEKWRRpTKtVcu/6VzrT1HsxU34F09nfx7JpmcOIL3FIHNO9Q7k9qZ 7J70mGN3XxYkzNqygKCQG/gfL6cOvpxF0Sg6lKhIdnc4xPPX3AVe4Tx0sDBQ4XgNospl H1h4a+eK4gBFR4GANWCmwnsSAc+ovYNZOZDRtvCWS2K+QpsU9JIx+PwndVIVnMvkj2Ix C1Zg== X-Gm-Message-State: AOJu0YyX10O130xwtYZ68K/cqV0gcvn93fHbpD1RpfgVFVSAidVpQ2N6 4gLfG4gle7wI8MBuT8j7hUyYwYp5MXcAc9q+l7bk5xFOGKFMOMsBJ12vjllNpL2MO2xm647W2Uv Qjuk= X-Gm-Gg: ASbGnctTQhcARQawaRqbkscbgtufsMARN6ldQyw+oexc8dC6QEPe0oFUMfK2bap/NJe rsucZMAFX9RH5L3iqFsahi+pNi1UvwG/BwhJ0yEUt/Nsxzqaq3EV6YVgIZVQP+S4tpRTqhClTPp ZLeKmRWmJiRf6Tl8KrtNM6kVUCG/z89MdsNmufHWEgJ8H9Pi/r+HzPnSLjrpnfu86YbSMBCFv/T TpY/SYU79OGSd+tIUtBUzEdt7nB9nILWY3hruWqZ8f3xXi+Kpdlj0PiPKEqMEAVw03rXNCyOIwe tiBGIwjozN+bvUQk7CIZHQAH4BefS7o= X-Google-Smtp-Source: AGHT+IFujjUMtRkidsiSlAZX8v29R9gn+9Snc3FHaN4CxP0BTy2RcMlSIkI5GtMo/C7iNWm4yNy9tg== X-Received: by 2002:a05:600c:1d0c:b0:434:ff25:19a0 with SMTP id 5b1f17b1804b1-436e2706f7emr92076505e9.21.1736524944309; Fri, 10 Jan 2025 08:02:24 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 254f7a234bf..b4c3412c490 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -49,6 +49,11 @@ #define NUM_IRQ_LINES 64 #define NUM_PRIO_BITS 3 +#define NUM_GPIO 7 +#define NUM_UART 4 +#define NUM_GPTM 4 +#define NUM_I2C 2 + typedef const struct { const char *name; uint32_t did0; @@ -989,12 +994,12 @@ static const stellaris_board_info stellaris_boards[] = { static void stellaris_init(MachineState *ms, stellaris_board_info *board) { - static const int uart_irq[] = {5, 6, 33, 34}; - static const int timer_irq[] = {19, 21, 23, 35}; - static const uint32_t gpio_addr[7] = + static const int uart_irq[NUM_UART] = {5, 6, 33, 34}; + static const int timer_irq[NUM_GPTM] = {19, 21, 23, 35}; + static const uint32_t gpio_addr[NUM_GPIO] = { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 0x40024000, 0x40025000, 0x40026000}; - static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; + static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31}; /* Memory map of SoC devices, from * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) @@ -1030,9 +1035,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) */ Object *soc_container; - DeviceState *gpio_dev[7], *nvic; - qemu_irq gpio_in[7][8]; - qemu_irq gpio_out[7][8]; + DeviceState *gpio_dev[NUM_GPIO], *nvic; + qemu_irq gpio_in[NUM_GPIO][8]; + qemu_irq gpio_out[NUM_GPIO][8]; qemu_irq adc; int sram_size; int flash_size; @@ -1123,7 +1128,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } else { adc = NULL; } - for (i = 0; i < 4; i++) { + for (i = 0; i < NUM_GPTM; i++) { if (board->dc2 & (0x10000 << i)) { SysBusDevice *sbd; @@ -1157,7 +1162,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } - for (i = 0; i < 7; i++) { + for (i = 0; i < NUM_GPIO; i++) { if (board->dc4 & (1 << i)) { gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], qdev_get_gpio_in(nvic, @@ -1178,7 +1183,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - for (i = 0; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2da66e6sm91520325e9.4.2025.01.10.08.02.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:28 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 5/9] hw/arm/stellaris: Use DEVCAP macro to access DeviceCapability registers Date: Fri, 10 Jan 2025 17:02:00 +0100 Message-ID: <20250110160204.74997-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add definitions (DCx_periph) for the DeviceCapability bits, replace direct bitmask checks with the DEV_CAP() macro, which use the extract/deposit API. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index b4c3412c490..64e6797553a 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -8,6 +8,7 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "qapi/error.h" #include "hw/core/split-irq.h" #include "hw/sysbus.h" @@ -54,6 +55,26 @@ #define NUM_GPTM 4 #define NUM_I2C 2 +/* + * See Stellaris Data Sheet chapter 5.2.5 "System Control", + * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4). + */ +#define DC1_WDT 3 +#define DC1_HIB 6 +#define DC1_MPU 7 +#define DC1_ADC 16 +#define DC1_PWM 20 +#define DC2_UART(n) (n) +#define DC2_SSI 4 +#define DC2_QEI(n) (8 + n) +#define DC2_I2C(n) (12 + 2 * n) +#define DC2_GPTM(n) (16 + n) +#define DC2_COMP(n) (24 + n) +#define DC4_GPIO(n) (n) +#define DC4_EMAC 28 + +#define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1) + typedef const struct { const char *name; uint32_t did0; @@ -1117,7 +1138,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000); sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); - if (board->dc1 & (1 << 16)) { + if (DEV_CAP(1, ADC)) { dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), qdev_get_gpio_in(nvic, 15), @@ -1129,7 +1150,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) adc = NULL; } for (i = 0; i < NUM_GPTM; i++) { - if (board->dc2 & (0x10000 << i)) { + if (DEV_CAP(2, GPTM(i))) { SysBusDevice *sbd; dev = qdev_new(TYPE_STELLARIS_GPTM); @@ -1146,7 +1167,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - if (board->dc1 & (1 << 3)) { /* watchdog present */ + if (DEV_CAP(1, WDT)) { dev = qdev_new(TYPE_LUMINARY_WATCHDOG); object_property_add_child(soc_container, "wdg", OBJECT(dev)); qdev_connect_clock_in(dev, "WDOGCLK", @@ -1163,7 +1184,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) for (i = 0; i < NUM_GPIO; i++) { - if (board->dc4 & (1 << i)) { + if (DEV_CAP(4, GPIO(i))) { gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], qdev_get_gpio_in(nvic, gpio_irq[i])); @@ -1174,7 +1195,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - if (board->dc2 & (1 << 12)) { + if (DEV_CAP(2, I2C(0))) { dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, qdev_get_gpio_in(nvic, 8)); i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); @@ -1184,7 +1205,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } for (i = 0; i < NUM_UART; i++) { - if (board->dc2 & (1 << i)) { + if (DEV_CAP(2, UART(i))) { SysBusDevice *sbd; dev = qdev_new("pl011_luminary"); @@ -1196,7 +1217,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); } } - if (board->dc2 & (1 << 4)) { + if (DEV_CAP(2, SSI)) { dev = sysbus_create_simple("pl022", 0x40008000, qdev_get_gpio_in(nvic, 7)); if (board->peripherals & BP_OLED_SSI) { @@ -1305,7 +1326,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) qemu_irq_raise(gpio_out[GPIO_D][0]); } } - if (board->dc4 & (1 << 28)) { + if (DEV_CAP(4, EMAC)) { DeviceState *enet; enet = qdev_new("stellaris_enet"); From patchwork Fri Jan 10 16:02:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13935106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80B40E7719C for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e4c1967sm4765917f8f.86.2025.01.10.08.02.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 6/9] hw/arm/stellaris: Map both I2C controllers Date: Fri, 10 Jan 2025 17:02:01 +0100 Message-ID: <20250110160204.74997-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There are 2 I2C controllers, map them both, removing the unimplemented one. Keep the OLED controller on the first I2C bus. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 64e6797553a..655bf85e89e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1021,6 +1021,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) { 0x40004000, 0x40005000, 0x40006000, 0x40007000, 0x40024000, 0x40025000, 0x40026000}; static const int gpio_irq[NUM_GPIO] = {0, 1, 2, 3, 4, 30, 31}; + static const uint32_t i2c_addr[NUM_I2C] = {0x40020000, 0x40021000}; + static const int i2c_irq[NUM_I2C] = {8, 37}; /* Memory map of SoC devices, from * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) @@ -1062,7 +1064,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) qemu_irq adc; int sram_size; int flash_size; - I2CBus *i2c; + DeviceState *i2c_dev[NUM_I2C]; DeviceState *dev; DeviceState *ssys_dev; int i; @@ -1195,14 +1197,18 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) } } - if (DEV_CAP(2, I2C(0))) { - dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, - qdev_get_gpio_in(nvic, 8)); - i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); - if (board->peripherals & BP_OLED_I2C) { - i2c_slave_create_simple(i2c, "ssd0303", 0x3d); + for (i = 0; i < NUM_I2C; i++) { + if (DEV_CAP(2, I2C(i))) { + i2c_dev[i] = sysbus_create_simple(TYPE_STELLARIS_I2C, i2c_addr[i], + qdev_get_gpio_in(nvic, + i2c_irq[i])); } } + if (board->peripherals & BP_OLED_I2C) { + I2CBus *bus = (I2CBus *)qdev_get_child_bus(i2c_dev[0], "i2c"); + + i2c_slave_create_simple(bus, "ssd0303", 0x3d); + } for (i = 0; i < NUM_UART; i++) { if (DEV_CAP(2, UART(i))) { @@ -1381,7 +1387,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) /* Add dummy regions for the devices we don't implement yet, * so guest accesses don't cause unlogged crashes. */ - create_unimplemented_device("i2c-2", 0x40021000, 0x1000); create_unimplemented_device("PWM", 0x40028000, 0x1000); create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); From patchwork Fri Jan 10 16:02:02 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc08bbsm89879665e9.12.2025.01.10.08.02.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 7/9] hw/arm/stellaris: Only create MPU when available Date: Fri, 10 Jan 2025 17:02:02 +0100 Message-ID: <20250110160204.74997-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 655bf85e89e..d87587225c2 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1128,6 +1128,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); qdev_prop_set_bit(nvic, "enable-bitband", true); + if (!DEV_CAP(1, MPU)) { + qdev_prop_set_uint32(nvic, "mpu-ns-regions", 0); /* Disable MPU */ + } qdev_connect_clock_in(nvic, "cpuclk", qdev_get_clock_out(ssys_dev, "SYSCLK")); /* This SoC does not connect the systick reference clock */ From patchwork Fri Jan 10 16:02:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13935111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A82EE7719D for ; Fri, 10 Jan 2025 16:06:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tWHTr-0007m1-UI; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e38397csm4794123f8f.24.2025.01.10.08.02.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 8/9] hw/arm/stellaris: Only map existing devices as unimplemented Date: Fri, 10 Jan 2025 17:02:03 +0100 Message-ID: <20250110160204.74997-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index d87587225c2..c89522332e2 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1390,11 +1390,21 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) /* Add dummy regions for the devices we don't implement yet, * so guest accesses don't cause unlogged crashes. */ - create_unimplemented_device("PWM", 0x40028000, 0x1000); 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436e2dc0babsm90587775e9.14.2025.01.10.08.02.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Jan 2025 08:02:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 9/9] hw/arm/stellaris: Wire GPTM[#n] output to ADC input #n Date: Fri, 10 Jan 2025 17:02:04 +0100 Message-ID: <20250110160204.74997-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250110160204.74997-1-philmd@linaro.org> References: <20250110160204.74997-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The ADC model is very simple, and only consider the 4 GPTM IRQs as trigger. Currently they are all wired to the same input IRQ. This is a QDev design mistake. We could use a OR_IRQ, but the ADC actually really has one input for each GPTM, so have the ADC create 4 inputs and wire each GPTM output to them. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/stellaris.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index c89522332e2..446d6595a6d 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -701,8 +701,16 @@ static void stellaris_i2c_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -/* Analogue to Digital Converter. This is only partially implemented, - enough for applications that use a combined ADC and timer tick. */ +/* + * Analogue to Digital Converter. + * + * Each of the 4 trigger inputs has a MUX for 5 inputs + * (see Stellaris Data Sheet Figure 11-1: "ADC Module Block Diagram"). + * + * This model only consider the GPTM inputs, thus MUX is not implemented. + */ + +#define STELLARIS_ADC_TRIGGERS 4 #define STELLARIS_ADC_EM_CONTROLLER 0 #define STELLARIS_ADC_EM_COMP 1 @@ -986,7 +994,7 @@ static void stellaris_adc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, "adc", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); + qdev_init_gpio_in(dev, stellaris_adc_trigger, STELLARIS_ADC_TRIGGERS); } /* Board init. */ @@ -1061,7 +1069,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) DeviceState *gpio_dev[NUM_GPIO], *nvic; qemu_irq gpio_in[NUM_GPIO][8]; qemu_irq gpio_out[NUM_GPIO][8]; - qemu_irq adc; + DeviceState *adc; int sram_size; int flash_size; DeviceState *i2c_dev[NUM_I2C]; @@ -1144,15 +1152,12 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28)); if (DEV_CAP(1, ADC)) { - dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, + adc = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, qdev_get_gpio_in(nvic, 14), qdev_get_gpio_in(nvic, 15), qdev_get_gpio_in(nvic, 16), qdev_get_gpio_in(nvic, 17), NULL); - adc = qdev_get_gpio_in(dev, 0); - } else { - adc = NULL; } for (i = 0; i < NUM_GPTM; i++) { if (DEV_CAP(2, GPTM(i))) { @@ -1166,9 +1171,12 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i])); + /* TODO: This is incorrect, but we get away with it because the ADC output is only ever pulsed. */ - qdev_connect_gpio_out(dev, 0, adc); + if (adc) { + qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(adc, i)); + } } }