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Sat, 11 Jan 2025 16:56:01 -0800 (PST) Message-ID: <19bb108e93bb58eecc6a53d78ff4e75fc380f072.camel@gmail.com> Subject: [PATCH RFC] arm64: dts: sophgo: Add initial SG2000 SoC device tree From: Alexander Sverdlin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Date: Sun, 12 Jan 2025 01:55:05 +0100 User-Agent: Evolution 3.54.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250111_165604_276177_32B2EBF6 X-CRM114-Status: GOOD ( 17.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). --- Dear ARM, RISCV, DT maintainers, I'd like to ask your opinion on the below patch, which I plan as a base for ARM64 BSP for dual-arch (RISCV or ARM64) Cvitek SoC SG2000. The main motivation for ARM64 support is the ARCH support in the upstream gcc, which is not that mature for RISCV. I believe it's the first time we already have quite some base in the tree for a SoC, so it would be advantageous to re-use it and not duplicate the same SoC structures in two places, especially having in mind that Cvitek/Sophgo are still working on upstreaming and by far not all HW blocks are populated in the SoC DTs. They focus primarely on RISCV, so ARM64 would be dragging behind in this case if it would be forked. On the other hand, including SoC dtsi from RISCV into ARM64 poses some technical challenges by itself, obviously CPU cores have to be deleted, same is true for interrupt controller. And the interrupt numbers are of course difference for ARM GIC, so they have to be overwritten. Alternatively I can split existing .dtsi included below into their RISCV-specific and generic parts, so that both ARM64 and RISCV would include generic part and their corresponding ARCH-specific parts bringing CPU cores + interrupt controller + IRQ numbers for each and every device separately. The below example isactually booting (being included into board-level DT), so it's a real example I'd be ready to submit if there will be no objections of the cross-ARCH include approach in general. What are your thoughts?  arch/arm64/boot/dts/sophgo/sg2000.dtsi | 164 +++++++++++++++++++++++++  1 file changed, 164 insertions(+)  create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 000000000000..96afd342bde5 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include +#include "../../../../riscv/boot/dts/sophgo/cv18xx.dtsi" +#include "../../../../riscv/boot/dts/sophgo/cv181x.dtsi" + +/delete-node/ &cpu0; +/delete-node/ &plic; +/delete-node/ &clint; + +/ { + compatible = "sophgo,sg2000"; + interrupt-parent = <&gic>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MiB */ + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , +      ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , +      , +      , +      ; + always-on; + clock-frequency = <25000000>; + }; + + gic: interrupt-controller@1f01000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f01000 0x1000>, +       <0x01f02000 0x2000>; + }; + + soc { + /delete-property/ interrupt-parent; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, +       <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; +}; + +&cpus { + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; +}; + +&clk { + compatible = "sophgo,sg2000-clk"; +}; + +&saradc { + interrupts = ; +}; + +&dmac { + interrupts = ; +}; + +&spi0 { + interrupts = ; +}; + +&spi1 { + interrupts = ; +}; + +&spi2 { + interrupts = ; +}; + +&spi3 { + interrupts = ; +}; + +&uart0 { + interrupts = ; +}; + +&uart1 { + interrupts = ; +}; + +&uart2 { + interrupts = ; +}; + +&uart3 { + interrupts = ; +}; + +&uart4 { + interrupts = ; +}; + +&porta { + interrupts = ; +}; + +&portb { + interrupts = ; +}; + +&portc { + interrupts = ; +}; + +&portd { + interrupts = ; +}; + +&i2c0 { + interrupts = ; +}; + +&i2c1 { + interrupts = ; +}; + +&i2c2 { + interrupts = ; +}; + +&i2c3 { + interrupts = ; +}; + +&i2c4 { + interrupts = ; +}; + +&emmc { + interrupts = ; +}; + +&sdhci0 { + interrupts = ; +}; + +&sdhci1 { + interrupts = ; +};