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Mon, 13 Jan 2025 07:09:46 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 1/5] irqchip/riscv-intc: Balance priority and fairness during irq handling Date: Mon, 13 Jan 2025 23:09:29 +0800 Message-Id: <20250113150933.65121-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_070947_745089_2B2E8426 X-CRM114-Status: GOOD ( 12.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Both csr cause and csr topi record the pending bit with the highest priority. If interrupts with high priority arrive frequently within a certain period of time, the interrupts with low priority won't get a chance to be handled. For example, if external interrupts and software interrupts arrive very frequently, the timer interrupts will never be handled. Then buddy watchdog on a buddy CPU will report a hardlockup on the current CPU while current CPU actually can receive irq. This commit solves this problem by handling all pending irqs in a round. During each round, this commit handles pending irqs by their priority. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-intc.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f653c13de62b..bc2ec26aa9e9 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -26,20 +26,40 @@ static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG; static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG; static unsigned int riscv_intc_custom_nr_irqs __ro_after_init; +static unsigned int riscv_prio_irqs[] = { +#ifdef CONFIG_RISCV_M_MODE + IRQ_M_EXT, IRQ_M_SOFT, IRQ_M_TIMER, +#endif + IRQ_S_EXT, IRQ_S_SOFT, IRQ_S_TIMER, IRQ_S_GEXT, + IRQ_VS_EXT, IRQ_VS_SOFT, IRQ_VS_TIMER, + IRQ_PMU_OVF, +}; + static void riscv_intc_irq(struct pt_regs *regs) { - unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; - - if (generic_handle_domain_irq(intc_domain, cause)) - pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause); 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Mon, 13 Jan 2025 07:09:50 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:09:50 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 2/5] irqchip/riscv-imsic: Add a threshold to ext irq handling times Date: Mon, 13 Jan 2025 23:09:30 +0800 Message-Id: <20250113150933.65121-3-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_070951_831949_3B577AC8 X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V's external irq has higher priority than software irq, timer irq and pmu overflow irq. In existing implementation of IMSIC driver, If external irqs keep arriving within a certain period of time, no other interrupt will get a chance to be handled. This commit solves this problem by introducing a threshold to the number of times imsic interrupts can be processed in each round. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-imsic-early.c | 31 ++++++++++++++----------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index c5c2e6929a2f..63097f2bbadf 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -20,6 +20,8 @@ #include "irq-riscv-imsic-state.h" +#define IMSIC_HANDLE_THRESHOLD 20 + static int imsic_parent_irq; #ifdef CONFIG_SMP @@ -76,6 +78,7 @@ static void imsic_handle_irq(struct irq_desc *desc) int err, cpu = smp_processor_id(); struct imsic_vector *vec; unsigned long local_id; + unsigned int handled = 0; chained_irq_enter(chip, desc); @@ -85,21 +88,23 @@ static void imsic_handle_irq(struct irq_desc *desc) if (local_id == IMSIC_IPI_ID) { if (IS_ENABLED(CONFIG_SMP)) ipi_mux_process(); - continue; - } - - if (unlikely(!imsic->base_domain)) - continue; - - vec = imsic_vector_from_local_id(cpu, local_id); - if (!vec) { - pr_warn_ratelimited("vector not found for local ID 0x%lx\n", local_id); - continue; + } else if (likely(imsic->base_domain)) { + vec = imsic_vector_from_local_id(cpu, local_id); + + if (unlikely(!vec)) + pr_warn_ratelimited("vector not found for local ID 0x%lx\n", + local_id); + else { + err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq); + + if (unlikely(err)) + pr_warn_ratelimited("hwirq 0x%x mapping not found\n", + vec->hwirq); + } } - err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq); - if (unlikely(err)) - pr_warn_ratelimited("hwirq 0x%x mapping not found\n", vec->hwirq); + if (handled++ >= IMSIC_HANDLE_THRESHOLD) + break; } chained_irq_exit(chip, desc); From patchwork Mon Jan 13 15:09:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 13937709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99175C02180 for ; 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Mon, 13 Jan 2025 07:09:54 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:09:54 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes Date: Mon, 13 Jan 2025 23:09:31 +0800 Message-Id: <20250113150933.65121-4-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_070955_854185_AF25BB29 X-CRM114-Status: UNSURE ( 8.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as IMSIC issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-imsic-early.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index 63097f2bbadf..c6317cb557fb 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -29,6 +29,12 @@ static void imsic_ipi_send(unsigned int cpu) { struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel_relaxed(IMSIC_IPI_ID, local->msi_va); } From patchwork Mon Jan 13 15:09:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 13937712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8193C0218A for ; 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Mon, 13 Jan 2025 07:09:58 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:09:58 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 4/5] irqchip/timer-clint: Use wmb() to order normal writes and IPI writes Date: Mon, 13 Jan 2025 23:09:32 +0800 Message-Id: <20250113150933.65121-5-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_070959_708784_74963C55 X-CRM114-Status: UNSURE ( 7.70 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as CLINT issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/clocksource/timer-clint.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 0bdd9d7ec545..8d73b45f9966 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -48,6 +48,12 @@ EXPORT_SYMBOL(clint_time_val); #ifdef CONFIG_SMP static void clint_send_ipi(unsigned int cpu) { + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); } From patchwork Mon Jan 13 15:09:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 13937711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 744ADC02184 for ; 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Mon, 13 Jan 2025 07:10:03 -0800 (PST) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f54a26ae2fsm10193120a91.9.2025.01.13.07.09.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Jan 2025 07:10:02 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 5/5] irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes Date: Mon, 13 Jan 2025 23:09:33 +0800 Message-Id: <20250113150933.65121-6-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_071003_710456_096FDBD9 X-CRM114-Status: UNSURE ( 7.68 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as ACLINT SSWI issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/irqchip/irq-thead-c900-aclint-sswi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip/irq-thead-c900-aclint-sswi.c index b0e366ade427..7246a008a0f0 100644 --- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c @@ -31,6 +31,12 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); static void thead_aclint_sswi_ipi_send(unsigned int cpu) { + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu)); }