From patchwork Thu Jan 23 11:01:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13948143 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4BAE20E021; Thu, 23 Jan 2025 11:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630129; cv=none; b=YeelTWXAqpaglkeu81Jkmcizmoj67UFM7c62jPdjiMUrPCe0lnNZf8RTkM8TvT7JnghnxrRUAkHFqewpBuHCPbU5ArD68S3Wv4WyyNXZIgNfkfJhyb4RblRO8+UuME5bCTLLmPcXTv+KvcQ4ysEvbaDCsq/MUxlRdZ0gvyDoeAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630129; c=relaxed/simple; bh=bCeIqKozA0uCUswQ7QSh5THPEiib/UKBFfZYY9bJ968=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ifE2jbdN65PNG202AI+FdR3aWBEYByhmymzOsYKQnLOaLaihy8jF2fy2H9zNLqxiZ0o6ek+AGMMwD+4sbWAK+ytmWFir2gVRbmy5kYyvl/UtxWHRY8lpGF+7iIGNarPbjLcCwc1CcDRIN956QbXoGzGlKFmsTCDInEKTZlWZkZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=G6OsRrAX; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="G6OsRrAX" Received: by mail.gandi.net (Postfix) with ESMTPSA id 6A54360006; Thu, 23 Jan 2025 11:02:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1737630125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J4te1nDJuia8tlkOq1rs3PPQ64j4O7/bep+hWYRRNyI=; b=G6OsRrAXjbtf8NhXBpatCBrOs9jUHknyyCarwyWA8V98JCTy08cgwM8BsHwGBSSBqN8b15 JuQNNTV/+6RT1KcqgPFO/LmHVmK/epyQkFtAI+c2oqZWzNqgMLgh+yOmuNQm6HWgRv7BjD 3diWnBo+zo0JOaUr5pLy8JhqfVbz94lPhx5dYTSR2gLJt5P0KWTqqkhqix2ieurE9NLzgn Wim4CtrZRDH2eKzJZ2m0eRWlb6WPOoNdbdenN2w10DC3P48Jdw/rOhWufVONXDHVNYa5sZ /9peoqNCweQuLHiaoSWawQlo6iCy9rF4ZWTZbc65PcE6iyPxa4X+UD8NN9+/fQ== From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:54 +0100 Subject: [PATCH v3 1/5] dt-bindings: mips: Document mti,mips-cm Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250123-cluster-hci-broken-v3-1-8a7ec57cbf68@bootlin.com> References: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> In-Reply-To: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> To: Aleksandar Rikalo , Thomas Bogendoerfer , Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vladimir Kondratiev , =?utf-8?q?Th?= =?utf-8?q?=C3=A9o_Lebrun?= , Tawfik Bayouk , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.2 X-GND-Sasl: gregory.clement@bootlin.com Add device tree binding documentation for MIPS Coherence Manager. This component enables support for SMP by providing each processor in the system with a uniform view of memory. The Coherence Manager is responsible for establishing the global ordering of requests from all elements of the system and sending the correct data back to the requester. Based on the work of Jiaxun Yang Signed-off-by: Gregory CLEMENT Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/mips/mti,mips-cm.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4324b2306535f1bf66c44b1f96be9094ee282041 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Coherence Manager + +description: + The Coherence Manager (CM) is responsible for establishing the + global ordering of requests from all elements of the system and + sending the correct data back to the requester. It supports Cache + to Cache transfers. + https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf + https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf + +maintainers: + - Jiaxun Yang + +properties: + compatible: + const: mti,mips-cm + + reg: + description: + Base address and size of the Global Configuration Registers + referred to as CMGCR.They are the system programmer's interface + to the Coherency Manager. Their location in the memory map is + determined at core build time. In a functional system, the base + address is provided by the Coprocessor 0, but some + System-on-Chip (SoC) designs may not provide an accurate address + that needs to be described statically. + + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + coherency-manager@1fbf8000 { + compatible = "mti,mips-cm"; + reg = <0x1bde8000 0x8000>; + }; +... From patchwork Thu Jan 23 11:01:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13948144 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF07E20E028; Thu, 23 Jan 2025 11:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630130; cv=none; b=AjkV3RnJ87wuLTcjoq3djw0nMizIh75igky5KKKgABp5tLdzhaaRgJb47eqojsU6BVZ9iJ2WYvx1sQdQiulROx/S1KDOaYAymIMVCKU+TZg285SaZJlRyqMIf1YvUBfvId9/Dq9RvOzmr8zBGKwW2q/BSWuJaufg9bHAOeQy2aU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630130; c=relaxed/simple; bh=eCZcvNDqgRHWn+DEZZL59YOltlZjMrfu5yAU2RkOUHM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qggRfq7YE0S1IZdJzbhpCH3DNw7Vivc2ocFD6C8G3gPBvWmppjlY7+3rEzsVBKWqtFz8E+kcN7phFOG7zBcQlJrlPOcps0t5b8AtO52YaX2Tun+4TwsQeznGST/bzj+LnFkAheC3v9Hesp/dTBTUs3r3zpkvkoztp+HZ6ViAMV4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=NByx9zpL; arc=none smtp.client-ip=217.70.183.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NByx9zpL" Received: by mail.gandi.net (Postfix) with ESMTPSA id 632CA240003; Thu, 23 Jan 2025 11:02:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1737630125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Agaud90VoME8ZewXzuNqT14dIsUTegKa0Q3Nwf0CwVc=; b=NByx9zpLp8b3fVUc/6pKNAMD9hFS9sIEKZeMnbjjNXLuRzSqbvXHON8m0BImYG3+wSgK/k 1fSnxBOLgopAqc4Svp1gtSCcrKN5E1YI8Y7/g0cvgGz0IrNDocwWVBgeqMgKZBnKkOuQQd jSOKVpaxY9ecCx1JVJ1Wcxmcq5U0xIev1VeZ7yKZzD48O46xp7UZFJ4iir9JvpK8XMVCHt efAruvrbIHW1gXNYI3K5UpxDofR3iJQYXwYVzHzcsR9voz3bSVcGj1Y21go7AVtwsBE7t8 P17Xsm3VgaKM1qyk7JR999XCHmPcde49i8JYYAzkyNpT24UJjhvEFOQxDt/q4A== From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:55 +0100 Subject: [PATCH v3 2/5] dt-bindings: mips: mips-cm: Add a new compatible string for EyeQ6 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250123-cluster-hci-broken-v3-2-8a7ec57cbf68@bootlin.com> References: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> In-Reply-To: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> To: Aleksandar Rikalo , Thomas Bogendoerfer , Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vladimir Kondratiev , =?utf-8?q?Th?= =?utf-8?q?=C3=A9o_Lebrun?= , Tawfik Bayouk , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.2 X-GND-Sasl: gregory.clement@bootlin.com The CM3.5 used on EyeQ6 reports that Hardware Cache Initialization is complete, but in reality it's not the case. It also incorrectly indicates that Hardware Cache Initialization is supported. This new compatible string allows warning about this broken feature that cannot be detected at runtime. Signed-off-by: Gregory CLEMENT Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mips/mti,mips-cm.yaml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml index 4324b2306535f1bf66c44b1f96be9094ee282041..d129d6382847768dc026336d8d2c7328b6b81f9b 100644 --- a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml @@ -19,7 +19,12 @@ maintainers: properties: compatible: - const: mti,mips-cm + oneOf: + - const: mti,mips-cm + - const: mobileye,eyeq6-cm + description: + On EyeQ6 the HCI (Hardware Cache Initialization) information for + the L2 cache in multi-cluster configuration is broken. reg: description: @@ -44,4 +49,9 @@ examples: compatible = "mti,mips-cm"; reg = <0x1bde8000 0x8000>; }; + + - | + coherency-manager { + compatible = "mobileye,eyeq6-cm"; + }; ... From patchwork Thu Jan 23 11:01:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13948147 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57E2120F09E; Thu, 23 Jan 2025 11:02:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630135; cv=none; b=o3bF9V2EOxfMcJMi345UjBYvE8XQTs5FAdGXe5SEZj6KvQ0+5rY75WES97zhFB8YN3y6Ea1htBCnFrdw5vCpci2rnxPh6Ig7Exy/l5L8iQmG5xCSiu+BB9ZFjEgFgkeAszkVp0QbxLauubQY9aa5K0rGsO/7xeJjG/mhs4TDxgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630135; c=relaxed/simple; bh=CmfB10dbxbE66zWa8LaXXp2eyVUqKez9VZ+PExKYGD8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tIlMPg6RuydZmo/yV2QpB6rjjMGGHuwllt+VKshseBuKczoTQ2EU79SwyEqyOmlAMtjkw7jCiIfQGizUiLmamk8mz38h8An54ZBypkRp7qI7D9ot1vNqiEmmq3vfVQj5UmZ5eG7KRV5Eh2rCOCxuMZRpi2qTNObGVoeuOf62FGA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=H3xk4Roq; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="H3xk4Roq" Received: by mail.gandi.net (Postfix) with ESMTPSA id 35D0BFF80D; Thu, 23 Jan 2025 11:02:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1737630126; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q33NT071U8WlcsIRWPJA76qWRECyC9SSqhmwTcM83HQ=; b=H3xk4RoqdOCShLvE4QE9lY3+gFMU3UvoWvucvLp7hoRmz9h7aGekHtXoCsim3AeRq8eyyB lhD8MiNG+OiIkekNst4pHgp8XNd+wEaFuQPbgrmcqLuUpCxrP7YfdeFqHF7rBWG1IWyHA1 Km3Oef4cX3xZRQlXFh8C6rDsnjjlhUvpGkfIWqyCTt5VoJkW4CUHkDakh9rlahyC97Zi+Y 7V2yOpMPKVVpQjYuh8DAOKmoCjv0fAswnUpZUFp3NuvUtgOx3y2QLR/7a8VxQIpJNR4sJ9 AgoByQRTznMnJPVQidca2gjiwnWKYrVOSEWJd3E0OlPSuNKnSkjv+5NIg0v4Jw== From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:56 +0100 Subject: [PATCH v3 3/5] MIPS: cm: Detect CM quirks from device tree Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250123-cluster-hci-broken-v3-3-8a7ec57cbf68@bootlin.com> References: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> In-Reply-To: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> To: Aleksandar Rikalo , Thomas Bogendoerfer , Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vladimir Kondratiev , =?utf-8?q?Th?= =?utf-8?q?=C3=A9o_Lebrun?= , Tawfik Bayouk , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.2 X-GND-Sasl: gregory.clement@bootlin.com Some information that should be retrieved at runtime for the Coherence Manager can be either absent or wrong. This patch allows checking if some of this information is available from the device tree and updates the internal variable accordingly. For now, only the compatible string associated with the broken HCI is being retrieved. Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/mips-cm.h | 22 ++++++++++++++++++++++ arch/mips/kernel/mips-cm.c | 14 ++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 1afa85db1fb37d1017fbe7d6b7a2b7d2470e8257..3bfe0633b57639bfb05b7692e4bb83ba7c0b2523 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -59,6 +59,16 @@ extern phys_addr_t mips_cm_l2sync_phys_base(void); */ extern int mips_cm_is64; +/* + * mips_cm_is_l2_hci_broken - determine if HCI is broken + * + * Some CM reports show that Hardware Cache Initialization is + * complete, but in reality it's not the case. They also incorrectly + * indicate that Hardware Cache Initialization is supported. This + * flags allows warning about this broken feature. + */ +extern bool mips_cm_is_l2_hci_broken; + /** * mips_cm_error_report - Report CM cache errors */ @@ -97,6 +107,18 @@ static inline bool mips_cm_present(void) #endif } +/** + * mips_cm_update_property - update property from the device tree + * + * Retrieve the properties from the device tree if a CM node exist and + * update the internal variable based on this. + */ +#ifdef CONFIG_MIPS_CM +extern void mips_cm_update_property(void); +#else +static void mips_cm_update_property(void) {} +#endif + /** * mips_cm_has_l2sync - determine whether an L2-only sync region is present * diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 9854bc2b6895d4db67d216586f65e4810661d29b..43cb1e20baed3648ff83bb5d3bbe6a726072e063 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -14,6 +15,7 @@ void __iomem *mips_gcr_base; void __iomem *mips_cm_l2sync_base; int mips_cm_is64; +bool mips_cm_is_l2_hci_broken; static char *cm2_tr[8] = { "mem", "gcr", "gic", "mmio", @@ -237,6 +239,18 @@ static void mips_cm_probe_l2sync(void) mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE); } +void mips_cm_update_property(void) +{ + struct device_node *cm_node; + + cm_node = of_find_compatible_node(of_root, NULL, "mobileye,eyeq6-cm"); + if (!cm_node) + return; + pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken"); + mips_cm_is_l2_hci_broken = true; + of_node_put(cm_node); +} + int mips_cm_probe(void) { phys_addr_t addr; From patchwork Thu Jan 23 11:01:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13948145 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6700320E312; 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arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="AtvC1NNH" Received: by mail.gandi.net (Postfix) with ESMTPSA id 122A0C0005; Thu, 23 Jan 2025 11:02:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1737630127; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BSEqBmSqmyvDs47D4eD55kQ405suvhvrk4+/jN9RG4w=; b=AtvC1NNHDsmnuNkreBztRc/o3xLGLTrouKh/l+MfxhFUB+vYCa8PfySP4ANvopUjnHzeiw rwdukG9eawxvf2VrKIF0TRpq8jGV2ib4cwCrnWTiq8PrLLUh4rvKOTCw/u77zI0Wq1W5dJ yZKNX6ZOqP/43gTk4yrBLmyQN06gghdfj7jKTPVXEeZ7rpGMvKwBg0+1wTnopQ9ZgJJAb5 uj1usJoXKaqniGBj4J5w4/QqnsUvvAXRpSUhOD0r1s2H8exmQKbHqY6BTXKVGiwhjkyX5L c1KHw8m6tP6+prL9fbYPQovmBKR1+EKADpCaZYJo2hMrx6G32xSD/DRO+0sO9A== From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:57 +0100 Subject: [PATCH v3 4/5] MIPS: CPS: Support broken HCI for multicluster Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250123-cluster-hci-broken-v3-4-8a7ec57cbf68@bootlin.com> References: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> In-Reply-To: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> To: Aleksandar Rikalo , Thomas Bogendoerfer , Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vladimir Kondratiev , =?utf-8?q?Th?= =?utf-8?q?=C3=A9o_Lebrun?= , Tawfik Bayouk , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.2 X-GND-Sasl: gregory.clement@bootlin.com Some CM3.5 devices incorrectly report that hardware cache initialization has completed, and also claim to support hardware cache initialization when they don't actually do so. This commit fixes this issue by retrieving the correct information from the device tree and allowing the system to bypass the hardware cache initialization step. Instead, it relies on manual operation. As a result, multi-user support is now possible for these CPUs. Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/smp-cps.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index b20ea4048429e1aab2bffbada793ee594bee1e05..e85bd087467e8caf0640ad247ee5f8eb65107591 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -333,6 +333,9 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) sizeof(*mips_cps_cluster_bootcfg), GFP_KERNEL); + if (nclusters > 1) + mips_cm_update_property(); + for (cl = 0; cl < nclusters; cl++) { /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(cl); @@ -394,7 +397,7 @@ static void init_cluster_l2(void) { u32 l2_cfg, l2sm_cop, result; - while (1) { + while (!mips_cm_is_l2_hci_broken) { l2_cfg = read_gcr_redir_l2_ram_config(); /* If HCI is not supported, use the state machine below */ From patchwork Thu Jan 23 11:01:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13948146 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B89C720E6E5; Thu, 23 Jan 2025 11:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630131; cv=none; b=bjO2Jpx7NFVlBJ+mdMzV8vBC8AE9J29TorMm9TUHnNb8BbWnaE7wlqpizck7BcQOuWEygJFWfe86l2Kb4/QbO0ZeSGMPqDyF18kKfb8IGG2syHKjO02IJEcWANkRUvYHjMyOy+s2Ny8DD24EtZByxxbChYpqXaqSEyCeHJxgewQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737630131; c=relaxed/simple; bh=nyoBjJeplMqsP6hiHUlqfIT5u31Sy7DAgdVBnnvQX4Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WDfdA9CcXkGZtXE6YgxP5jeHrmNp56+9aTp3OJLNyabMzWYeVIK/RF740lw7X6G9IElze451tHONyaWaMLrFFEzIjFwXP5viPIbkUbuNsEEcPz+P1gduA5HhArPkeXjG1/Nqva8TRiDRoZL2ZfSw1QzTc+paC/QuyOuK7z/MbTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=NeQmVH94; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NeQmVH94" Received: by mail.gandi.net (Postfix) with ESMTPSA id C2790C000B; Thu, 23 Jan 2025 11:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1737630128; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=z+xrqkHkD3Qz7CE8k+Ni75tjNz0Jjog+QmgQtGZGrmk=; b=NeQmVH94j1VwlXNf7q6BUMpHMqPqZ0A2CT7zkp+dnSTi79v4atNIi5fqZM2tCs5HTCrnox p50/3rp4TU0iWubfwfNUFukL/lF98sasoVmdLY7k/pNpWp4qk7FopG/cmF2IjULM8jv22L bb6WZhLeY+2rLf/EsZcKTlFxHiu9UmhTM0JZazTfw1au3RXMHpRSKwp+B/m7BL179PKfWy Jh+OzO66iH/NkRIwXxCT8WlV+2+KnQudzP0rNW1CvLcpRXcNGvCf+QiCU/Al1qq300Mmca Ss0R69NESEFTyqYJ4Dt2p8xOvIW6B1JIzHqjhkOYLceoJwG+6fKqW3pqnjTCpw== From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:58 +0100 Subject: [PATCH v3 5/5] MIPS: mobileye: dts: eyeq6h: Enable cluster support Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250123-cluster-hci-broken-v3-5-8a7ec57cbf68@bootlin.com> References: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> In-Reply-To: <20250123-cluster-hci-broken-v3-0-8a7ec57cbf68@bootlin.com> To: Aleksandar Rikalo , Thomas Bogendoerfer , Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vladimir Kondratiev , =?utf-8?q?Th?= =?utf-8?q?=C3=A9o_Lebrun?= , Tawfik Bayouk , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.2 X-GND-Sasl: gregory.clement@bootlin.com The CM3.5 device used in EyeQ6H SoCs incorrectly reports the status for Hardware Cache Initialization (HCI). This commit adds the compatible string for the CM to acknowledge this issue, which enables the use of the second CPU cluster. Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi index 4a1a43f351d39625b520a16d035cacd2e29d157c..dabd5ed778b739b62f5c6e7348f1837a207dbb6c 100644 --- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi @@ -32,6 +32,10 @@ cpu_intc: interrupt-controller { #interrupt-cells = <1>; }; + coherency-manager { + compatible = "mobileye,eyeq6-cm"; + }; + xtal: clock-30000000 { compatible = "fixed-clock"; #clock-cells = <0>;