From patchwork Mon Jan 27 11:36:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951250 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B2FCA1FE454; Mon, 27 Jan 2025 11:37:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977876; cv=none; b=sqE00s4B2qTWGnIAGcSNCR2uvzmur4VBCmgqn3MKRjQHqZNP8205YNGdq0zzXBpErhU2YvPAR11OBZlP1+aQjDScfdDAIhk+jBqf241ZUz2bgFwwzeoZRUc/H6MmWfDUMLpUGYDx7WmSUu7/MACbETGQR3geu7JW39yM1hWkeTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977876; c=relaxed/simple; bh=BcQAyPKRI2tbhKrM5eOFfbzlwubMHtM3V5xgEu5a/s0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F3gEUF7NA2AklzLOCdw37oo/MSXXrqnjLnasxwpib1/ZxiZwM8q7TRhlpwe5EanPVQxVb6ZnLBtHX8DkDRm0Mgqea0T5yCq8HUl0oRtolVAdSajJCuwkJSOfDdn+5nexF+8uEKXJFh9jZeTna6UsLjGpVdR2NoZmAUN6OQlM9jY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: VngSgHpbTfycGyDWMwHGvA== X-CSE-MsgGUID: uLmnWbL/R6mPfNxcwWEtYg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:48 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id AF78241F25B5; Mon, 27 Jan 2025 20:37:29 +0900 (JST) From: Biju Das To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Fabrizio Castro , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v2 01/12] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC Date: Mon, 27 Jan 2025 11:36:56 +0000 Message-ID: <20250127113723.24479-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register offset is 0x830 compared to 0x30 on RZ/V2H. - The number of supported GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 15 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E SoC. Acked-by: Rob Herring (Arm) Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- .../bindings/interrupt-controller/renesas,rzv2h-icu.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a7..3f99c8645767 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the From patchwork Mon Jan 27 11:36:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951246 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4D55A1FECC3; Mon, 27 Jan 2025 11:37:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977872; cv=none; b=laXWlfvoezpRdowp6K614YNZgTwfUF9penN3zBNBquxKNkae3q6I0uoa6BZVpV1d1vG4rCJYtHzInBQYv5IpTIFnC8eUY8mcMkrVd3ay8pyI4pML2tIvzI+MmLm6eDvwqy3fUXyePavgae4gMSWUjq9hNEbtsHqPyGKGdMn1esw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977872; c=relaxed/simple; bh=mAn+2FCOMP1AT2RkiSpT2aTw+e4/P0GLysBlTQ3/PiU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZbJrAwV9HSZV7XhYb8h32uKs5rQHTegbeG0Ad4gnLn+EsZ4nM2ARiHR8jOQBPhEpKICncF7R7keP0muyEYiaeztx74la48IgfxrukrGqgDr0kn/qVedriauHBkraeHzEx4edxSvdNfyigM/VVpkDQDR5BVJteA92B+z/KzI/jtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: /fNWoL4uQUidvr35ORumlQ== X-CSE-MsgGUID: GU5CWnjLTZKaOQ86/LQHIw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:48 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 12C0441F25BF; Mon, 27 Jan 2025 20:37:33 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 02/12] clk: renesas: r9a09g047: Add ICU clock/reset Date: Mon, 27 Jan 2025 11:36:57 +0000 Message-ID: <20250127113723.24479-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add ICU clock and reset entries. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- drivers/clk/renesas/r9a09g047-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 1886eab9ef9e..1181e7b605e8 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -90,6 +90,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, BUS_MSTOP(3, BIT(5))), DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, @@ -128,6 +130,7 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ From patchwork Mon Jan 27 11:36:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951245 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 10D451FCFEF for ; Mon, 27 Jan 2025 11:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977871; cv=none; b=KMe70mZ7fGuFahvae2T067lxyEBh81V3MT5u49diZUPUbw6XYZ4QgQ8du/o/pODqT1uCma031TbiPX+C6WgnjS2I+EDJwxGEGlGKEAAJVksNLZ6gxOrAxaLO2A/TNaJsCJ4BG3PeLhWjGu9QGM1Jjle5Q3IzF/Muaj8oa9d3I3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977871; c=relaxed/simple; bh=rnwdeobL2zFoVrzsZDPM1BQr0dEzL9t4W25HyqB1zXM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kg6z1jJdXGmxxBvJBpBVjkoMBsJzOq18avQ0TMkdF4J8FgAPjoXRLkC02fI6Cuauc5SsK3awQb57GIxfGJ4rmZGoRQ8zUDzPehHcRygfe+eEfJSq2E+xdd+JhKdde+MCXUuohuKufrEL/7GhEo9mVn9T4qHbc475LGn90GNQIt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: kKF17PTETwK1Dswo8NObjw== X-CSE-MsgGUID: SI/pq8IdT9ixUF6jxwz9Pw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:48 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9AE6841F278E; Mon, 27 Jan 2025 20:37:37 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 03/12] irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv Date: Mon, 27 Jan 2025 11:36:58 +0000 Message-ID: <20250127113723.24479-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use rzv2h_icu_chip directly on irq_domain_set_hwirq_and_chip() and drop the global variable irqchip from struct rzv2h_icu_priv. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- drivers/irqchip/irq-renesas-rzv2h.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fe2d29e91026..fd432b43506b 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -83,13 +83,11 @@ /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure. * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers */ struct rzv2h_icu_priv { void __iomem *base; - const struct irq_chip *irqchip; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; }; @@ -390,7 +388,7 @@ static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne if (hwirq > (ICU_NUM_IRQ - 1)) return -EINVAL; - ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip, (void *)(uintptr_t)tint); if (ret) return ret; @@ -446,8 +444,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto put_dev; } - rzv2h_icu_data->irqchip = &rzv2h_icu_chip; - rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) { ret = PTR_ERR(rzv2h_icu_data->base); From patchwork Mon Jan 27 11:36:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951249 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 93A791FECC3 for ; Mon, 27 Jan 2025 11:37:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977874; cv=none; b=raFF5uLzC2QwggaQhJmufzQUFLU5cysPRHFAVwzMr61AZFEf5kudWcjLtx2a2vu2v5XaYo5vC/ia1yCJsFY4k55b4fEAGQoTZEySovNGrwdZjQ9rR7a30Jy9JWl8s7oOhTBDh6PpGJvO72BRMLiose1Rm47esDKphLCTTfQ2e1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977874; c=relaxed/simple; bh=JlNWG9SE5RxFmBANlQUrR8SUcn8OcPtFIyX1WlO3EhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Il9nrgD5lM3fGI3PNuemSq1D9YXusSHySu8OAqAjoyDwh/PVN80FEEZb/63AwrRVFT+Ksekx7r/Y8saBWJSvCr2nCTD9qcV+mjhysKBJXMOvNLbIC0WYX4v/NRQSXbihe22aH0pjUjHK7XC7gXbHj3u7msNQpM6MwGzM6Le0sdA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: pXwEBHqOSlGPfutcqZ/40g== X-CSE-MsgGUID: QV1XSH12SA+cPMFmmxzNxQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:48 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9F79A41F2797; Mon, 27 Jan 2025 20:37:40 +0900 (JST) From: Biju Das To: Thomas Gleixner , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 04/12] irqchip/renesas-rzv2h: Use devm_reset_control_get_exclusive_deasserted() Date: Mon, 27 Jan 2025 11:36:59 +0000 Message-ID: <20250127113723.24479-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use devm_reset_control_get_exclusive_deasserted() to simplify rzv2h_icu_init(). Signed-off-by: Biju Das --- v1->v2: * Split the simplification patch into two. * Updated commit header and description. * Replaced devm_reset_control_get_optional_exclusive_deasserted()-> devm_reset_control_get_exclusive_deasserted(). * Moved simplification using devm_pm_runtime_enable() to next patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index fd432b43506b..5c5d2e015a88 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -456,15 +456,10 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto put_dev; } - resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); + resetn = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); if (IS_ERR(resetn)) { ret = PTR_ERR(resetn); - goto put_dev; - } - - ret = reset_control_deassert(resetn); - if (ret) { - dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); + dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret); goto put_dev; } @@ -495,7 +490,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) pm_runtime_put(&pdev->dev); pm_disable: pm_runtime_disable(&pdev->dev); - reset_control_assert(resetn); put_dev: put_device(&pdev->dev); From patchwork Mon Jan 27 11:37:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951247 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5E6AB1FECCD for ; Mon, 27 Jan 2025 11:37:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977873; cv=none; b=f5VzLzhT3HdkLbGwXhDCfbpGKLPTudLnol+v+3z+CCBSt5u4rnzuA1W2HxgBE3dcRAoK+7YJ6E9M15JA9vncPmIsaZnQMeX8P6ChHUtA3pYD4B5/5qEv6UjIREKxCIs0cOd7ZzVRof6zp4gYkjwyAe9CvAhfRjBhMkhFQ7ciEnE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977873; c=relaxed/simple; bh=vvhhNmJ7JnncN3IH8Bfe+4DKsW9/AtiaICDXAvgNApo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Wvl6AR09ekZJp95WyqRFDSHyiLG2DL4hgF1NQR3zJ+SYUmQ9y3LiMg/iiS+uhF1b/CYxUTYFxaFSh6oOjTtaBjuoD1Z31ewcJ4dCInlzzIlluZV0hPki7sSVi5e9u7RlRkFDWof9K0g2hYHcYJAYXZkyxLVgl1DyHjEFNIah9/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 65QK8hO6RSqH0Dv7Y1T6rA== X-CSE-MsgGUID: fgsWO7PSQAu36FGINmujgA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:48 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5B1A341F25A5; Mon, 27 Jan 2025 20:37:43 +0900 (JST) From: Biju Das To: Thomas Gleixner , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 05/12] irqchip/renesas-rzv2h: Simplify rzv2h_icu_init() Date: Mon, 27 Jan 2025 11:37:00 +0000 Message-ID: <20250127113723.24479-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Simplify rzv2h_icu_init() by using devm_pm_runtime_enable(). Signed-off-by: Biju Das --- v2: * New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 5c5d2e015a88..f90652013082 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -463,11 +463,16 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto put_dev; } - pm_runtime_enable(&pdev->dev); + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret); + goto put_dev; + } + ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); - goto pm_disable; + goto put_dev; } raw_spin_lock_init(&rzv2h_icu_data->lock); @@ -488,8 +493,6 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) pm_put: pm_runtime_put(&pdev->dev); -pm_disable: - pm_runtime_disable(&pdev->dev); put_dev: put_device(&pdev->dev); From patchwork Mon Jan 27 11:37:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951248 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8D6BF1FECBF for ; Mon, 27 Jan 2025 11:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977873; cv=none; b=m7G9d/e/6Lkk6RbcvR9BKfhseC4DbaQpZbtJQJ9idVUMLmfpEuv07d3I1gMR6n9WV6RK3ByubuoNUii7ubcptis8y87b0GtDeS1RrJnXT42fp4r2XBVKWWTEdg4pBkQzCnBsx1V6/wFm2BiKy6OWdDJTXz4bcWPA6UvYF2eszpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977873; c=relaxed/simple; bh=OT0bh4toV/mYEs7J/nXQPmM1s4vdHhfX4tEQ7UOGGY8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KndDkCvYiPS2ZeS3XE/a/1lWtwYhb1qkZs8NKu/sUgm1w/YV4SCxzVBd4N77X1bNy0v2qkERdzwMG8jdM74+PVBM9UXphqDjp2xTxZ6Wqt1JRod4C7fhW3pTcytP91cNHn+A0nV8HzgDhqTY7zudfqdDHcgCfOWvsxNueYXekAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: FdFN44J0TC2KZ7QA2Jpwsw== X-CSE-MsgGUID: 5uOI2lD+TyyNG+SF9erhKQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:48 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1782941F25B2; Mon, 27 Jan 2025 20:37:45 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 06/12] irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable Date: Mon, 27 Jan 2025 11:37:01 +0000 Message-ID: <20250127113723.24479-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences:  - The TINT register offset starts at 0x830 instead of 0x30.  - The number of GPIO interrupts for TINT selection is 141 instead of 86.  - The pin index and TINT selection index are not in the 1:1 map  - The number of TSSR registers is 15 instead of 8  - Each TSSR register can program 2 TINTs instead of 4 TINTs Introduce struct rzv2h_hw_info to handle these differences and add t_offs variable to take care of the TINT register offset difference between RZ/G3E and RZ/V2H. Refactor the code by moving rzv2h_icu_init() into rzv2h_icu_init_common() and pass the varable containing hw difference to support both these SoCs. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags * Started aligning kernel doc, struct members and struct initializers in a tabular fashion. --- drivers/irqchip/irq-renesas-rzv2h.c | 46 +++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index f90652013082..663f8a69c916 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -80,16 +80,26 @@ #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) #define ICU_PB5_TINT 0x55 +/** + * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. + * @t_offs: TINT offset + */ +struct rzv2h_hw_info { + u16 t_offs; +}; + /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure. * @base: Controller's base address * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Pointer to struct rzv2h_hw_info */ struct rzv2h_icu_priv { void __iomem *base; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; + const struct rzv2h_hw_info *info; }; static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data) @@ -109,7 +119,7 @@ static void rzv2h_icu_eoi(struct irq_data *d) tintirq_nr = hw_irq - ICU_TINT_START; bit = BIT(tintirq_nr); if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + ICU_TSCLR); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); } else if (hw_irq >= ICU_IRQ_START) { tintirq_nr = hw_irq - ICU_IRQ_START; bit = BIT(tintirq_nr); @@ -137,12 +147,12 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) tssel_n = ICU_TSSR_TSSEL_N(tint_nr); guard(raw_spinlock)(&priv->lock); - tssr = readl_relaxed(priv->base + ICU_TSSR(k)); + tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) tssr |= ICU_TSSR_TIEN(tssel_n); else tssr &= ~ICU_TSSR_TIEN(tssel_n); - writel_relaxed(tssr, priv->base + ICU_TSSR(k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } static void rzv2h_icu_irq_disable(struct irq_data *d) @@ -245,8 +255,8 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq u32 bit = BIT(tint_nr); int k = tint_nr / 16; - tsctr = readl_relaxed(priv->base + ICU_TSCTR); - titsr = readl_relaxed(priv->base + ICU_TITSR(k)); + tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR); + titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k)); titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n); /* @@ -255,7 +265,7 @@ static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq */ if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) || (titsel == ICU_TINT_EDGE_FALLING))) - writel_relaxed(bit, priv->base + ICU_TSCLR); + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); } static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) @@ -306,21 +316,21 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); - tssr = readl_relaxed(priv->base + ICU_TSSR(tssr_k)); + tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); - writel_relaxed(tssr, priv->base + ICU_TSSR(tssr_k)); + writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - titsr = readl_relaxed(priv->base + ICU_TITSR(titsr_k)); + titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k)); titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n); titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n); - writel_relaxed(titsr, priv->base + ICU_TITSR(titsr_k)); + writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k)); rzv2h_clear_tint_int(priv, hwirq); - writel_relaxed(tssr | tien, priv->base + ICU_TSSR(tssr_k)); + writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); return 0; } @@ -419,7 +429,8 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device return 0; } -static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) +static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent, + const struct rzv2h_hw_info *hw_info) { struct irq_domain *irq_domain, *parent_domain; struct rzv2h_icu_priv *rzv2h_icu_data; @@ -485,6 +496,8 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) goto pm_put; } + rzv2h_icu_data->info = hw_info; + /* * coccicheck complains about a missing put_device call before returning, but it's a false * positive. We still need &pdev->dev after successfully returning from this function. @@ -499,6 +512,15 @@ static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) return ret; } +static const struct rzv2h_hw_info rzv2h_hw_params = { + .t_offs = 0, +}; + +static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) +{ + return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params); +} + IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) From patchwork Mon Jan 27 11:37:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951251 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C72AB1FE454 for ; Mon, 27 Jan 2025 11:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977880; cv=none; b=MIQoKNFO342iqJ5nAnqP2X3baqIMZxxjfXI/+5C2IahoygSpMZ03WkVCRoprYyyeINCkI9DizYyMceiCrXFPew1xR8Iu8KZtimnA9FnM74nQkX0yOjHMxaZbgCKvu6fdqfw7ocymgTct3TtKtG5AXnv16LAb11oC3noDk+6XhUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977880; c=relaxed/simple; bh=/WDBBTcM0f79wtJckESvuJoZSoHrr0/1K7SpCR58i+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ETNdKRUma8hy85SDxhIYCx4Y8Gaurv8p8LBOymG/3HiGikeGejms2oSJ3W6fPuSpfCWmqmozi1eSMzLqzwbq6tkL0fUyvo8LE0G6eh/88rVf/ZOfLBcl/mq/NrY84QJnFMC8og9WlHPdlEFoJTYnAVmgc4IJ5sKthX1+0GJecjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: GhBrGZ/MQ5KG8BdutO/Geg== X-CSE-MsgGUID: 14AyIV8iT/CUtSSNtom+zQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jan 2025 20:37:57 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1A99341F25AC; Mon, 27 Jan 2025 20:37:48 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 07/12] irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info Date: Mon, 27 Jan 2025 11:37:02 +0000 Message-ID: <20250127113723.24479-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The number of GPIO interrupts on RZ/G3E for TINT selection is 141 compared to 86 on RZ/V2H. Rename the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL to hold this difference for RZ/V2H. Add max_tssel variable to struct rzv2h_hw_info to handle this difference. Signed-off-by: Biju Das --- v1->v2: * Renamed the macro ICU_PB5_TINT->ICU_RZV2H_TSSEL_MAX_VAL. * Replaced hexa decimal constant with ICU_RZV2H_TSSEL_MAX_VAL in struct rzv2h_hw_params. --- drivers/irqchip/irq-renesas-rzv2h.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 663f8a69c916..211da5ab0d7f 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -78,14 +78,16 @@ #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) -#define ICU_PB5_TINT 0x55 +#define ICU_RZV2H_TSSEL_MAX_VAL 0x55 /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @max_tssel: TSSEL max value */ struct rzv2h_hw_info { u16 t_offs; + u8 max_tssel; }; /** @@ -298,13 +300,12 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) return -EINVAL; } + priv = irq_data_to_priv(d); tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); - if (tint > ICU_PB5_TINT) + if (tint > priv->info->max_tssel) return -EINVAL; - priv = irq_data_to_priv(d); hwirq = irqd_to_hwirq(d); - tint_nr = hwirq - ICU_TINT_START; tssr_k = ICU_TSSR_K(tint_nr); @@ -514,6 +515,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, + .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) From patchwork Mon Jan 27 11:37:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951252 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1AF501FE454 for ; Mon, 27 Jan 2025 11:38:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977882; cv=none; b=Cu/+13bNTzPYkjyK7CRDOq4EooelqTpmR/yyeUf4O2/WYiCLECF5hZb4t0ZjUzP0RKGPiGl8ygskk8qaU1xZRNHAUL2cI9rDZnJ9qAXWKzExq2utrbOYVlKtYHMaaRvWXuzpGkz0MW8iGy4R9anGKnbYLn4xUpYYxvHqBFN+6CM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977882; c=relaxed/simple; bh=BoWbW++eLM7qVqV9gMMcltVUC1RT2QUqVhm/UpZCY6w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z+lG6mmJ3eIv1ZVFfoSllVmLmHky8YmPEvTB0qZf4DETxg+lNK3RY2cdbzKgmGL7byqiKjXJd913CN2aKjpAeWCa3Zh58KdRbXK3SY0rt8UqQpOWFIA35v7dwaH9czhkbEuIKRfNU6r7FOhonjRF4N4I1jjLbeOrdgO2RQwtZGg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ilAIkYwkTXqyXNqDuXlV1A== X-CSE-MsgGUID: r3tNEC89QRGEywy4m5oHpw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jan 2025 20:38:00 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8E14941F25B2; Mon, 27 Jan 2025 20:37:51 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 08/12] irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info Date: Mon, 27 Jan 2025 11:37:03 +0000 Message-ID: <20250127113723.24479-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E the number of TSSR registers is 15 compared to 8 on RZ/V2H and each TSSR register can program 2 TINTs compared to 4 on RZ/V2H. Add tssr_k variable to struct rzv2h_hw_info to handle this difference and drop the macros ICU_TSSR_K and ICU_TSSR_TSSEL_N. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- drivers/irqchip/irq-renesas-rzv2h.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 211da5ab0d7f..cfc1ff6307cb 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_K(tint_nr) ((tint_nr) / 4) -#define ICU_TSSR_TSSEL_N(tint_nr) ((tint_nr) % 4) #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) @@ -84,10 +82,12 @@ * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset * @max_tssel: TSSEL max value + * @tssr_k: TSSR index k */ struct rzv2h_hw_info { u16 t_offs; u8 max_tssel; + u8 tssr_k; }; /** @@ -145,8 +145,8 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) return; tint_nr = hw_irq - ICU_TINT_START; - k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + k = tint_nr / priv->info->tssr_k; + tssel_n = tint_nr % priv->info->tssr_k; guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); @@ -308,8 +308,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; - tssr_k = ICU_TSSR_K(tint_nr); - tssel_n = ICU_TSSR_TSSEL_N(tint_nr); + tssr_k = tint_nr / priv->info->tssr_k; + tssel_n = tint_nr % priv->info->tssr_k; titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); @@ -516,6 +516,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, + .tssr_k = 4, }; static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) From patchwork Mon Jan 27 11:37:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951253 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 954E01FECBF for ; Mon, 27 Jan 2025 11:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977884; cv=none; b=LkjljjUv47ghG8ODaA/Wphdy1es8oe6GjqhsxbhOJeU1fg62ft6F+ai/XmUuI1kyWs2hhN9A6ocRGHEwso9+HZ8gjgLq26ZKkUIxiEOiX9sYr0OpQaoxqLQzmak88MB9h2/BQJGzjAquiQlBK4tODtAOnIlizYxkzW3Hvqax+EY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977884; c=relaxed/simple; bh=DI5VZjEpYnsGLIbTCtzKqxfCMEZFjr20wm4kcJBF0ws=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D0K2EITEgE4OW9uhHo9PNMncwKIASsFfVo4Ux6A7micCwI38gkuNNDOApInh3Ciz0hpINbPayCKlwHH30KNmJJSd67aE5fZQEe/brTyBGURkby9oO2L4JtbZb15zjn8MwEHMfTU6Sj6+U9LxRkYfN0353mLstzn8dlCzmcWRCBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: dEWKIgURT2KYUSrQjXPFBQ== X-CSE-MsgGUID: 2jj3lG1uSFq4OnH7U4R/cQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jan 2025 20:38:01 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 930F641F25B5; Mon, 27 Jan 2025 20:37:54 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 09/12] irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info Date: Mon, 27 Jan 2025 11:37:04 +0000 Message-ID: <20250127113723.24479-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G3E each TSSR register can program 2 TINTs compared to 4 TINTs on RZ/V2H. Add tssel_mask and tssel_shift variables to struct rzv2h_hw_info to simplify the calculations when we add support for RZ/G3E and drop the macros ICU_TSSR_TSSEL_PREP and ICU_TSSR_TSSEL_MASK. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- drivers/irqchip/irq-renesas-rzv2h.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index cfc1ff6307cb..cff1f49bb130 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) -#define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) #define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) @@ -81,11 +79,15 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @tssel_mask: TSSEL mask + * @tssel_shift: TSSEL shift * @max_tssel: TSSEL max value * @tssr_k: TSSR index k */ struct rzv2h_hw_info { u16 t_offs; + u16 tssel_mask; + u8 tssel_shift; u8 max_tssel; u8 tssr_k; }; @@ -318,8 +320,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); + tssr &= ~((priv->info->tssel_mask << (tssel_n * priv->info->tssel_shift)) | tien); + tssr |= (tint << (tssel_n * priv->info->tssel_shift)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); @@ -515,6 +517,8 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, + .tssel_mask = GENMASK(6, 0), + .tssel_shift = 8, .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, .tssr_k = 4, }; From patchwork Mon Jan 27 11:37:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951254 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D6C011FE454 for ; Mon, 27 Jan 2025 11:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977884; cv=none; b=Qwj/RVRnDgjS2IQLt7+y7oCZDpBtH0ZPUOyw3iV1kzyYLM9ktW/p2fEADzS0co9KXGmJXAZm/skFNZ/8JkW+6MavAcxWdTkbJd3P94BWzoKysYjQZzqoCmAKRxUjm7rLwkmG+wi1pg0pNYNaz1/wujUkgUG7Rxhe7Di6FrnOHrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977884; c=relaxed/simple; bh=9m/TaQ3llUz8V6pygoH/iP/Tj3bei8o7OltSxLjA3ag=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HZUOFk14aDdgMHr6y43Jv/9D27GraBaIrlUcNRE38Fdq0LrDrKbSUdGFQKgHjrJrgs+blZnpYUaf4dpMdPD7Nu+/0tuQvTywOAWcZb8Lh21Nnjm4eu/4VhtHPwlmou1ElJ8iekGWGoyvVShKTk62LHrJ7X+36wpyAOrS4abXnvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: eNHimjqzSuu29p4NkYagyw== X-CSE-MsgGUID: Beo4FSywRdKZYYGEEg5fFg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 27 Jan 2025 20:38:01 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9347A41F278B; Mon, 27 Jan 2025 20:37:57 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org, Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 10/12] irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info Date: Mon, 27 Jan 2025 11:37:05 +0000 Message-ID: <20250127113723.24479-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The TINT enable position on RZ/G3E is BIT 15 compared to BIT 8 on RZ/V2H. Add tien variable to struct rzv2h_hw_info to simplify the calculations when we add support for RZ/G3E and drop the macro ICU_TSSR_TIEN. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- drivers/irqchip/irq-renesas-rzv2h.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index cff1f49bb130..70293a7822e7 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -64,8 +64,6 @@ #define ICU_TINT_LEVEL_HIGH 2 #define ICU_TINT_LEVEL_LOW 3 -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) - #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n) @@ -79,6 +77,7 @@ /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. * @t_offs: TINT offset + * @tien: TIEN mask * @tssel_mask: TSSEL mask * @tssel_shift: TSSEL shift * @max_tssel: TSSEL max value @@ -86,6 +85,7 @@ */ struct rzv2h_hw_info { u16 t_offs; + u16 tien; u16 tssel_mask; u8 tssel_shift; u8 max_tssel; @@ -153,9 +153,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) guard(raw_spinlock)(&priv->lock); tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); if (enable) - tssr |= ICU_TSSR_TIEN(tssel_n); + tssr |= priv->info->tien << (tssel_n * priv->info->tssel_shift); else - tssr &= ~ICU_TSSR_TIEN(tssel_n); + tssr &= ~(priv->info->tien << (tssel_n * priv->info->tssel_shift)); writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } @@ -315,7 +315,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) titsr_k = ICU_TITSR_K(tint_nr); titsel_n = ICU_TITSR_TITSEL_N(tint_nr); - tien = ICU_TSSR_TIEN(titsel_n); + tien = priv->info->tien << (titsel_n * priv->info->tssel_shift); guard(raw_spinlock)(&priv->lock); @@ -517,6 +517,7 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, + .tien = BIT(7), .tssel_mask = GENMASK(6, 0), .tssel_shift = 8, .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL, From patchwork Mon Jan 27 11:37:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951255 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 845BE1FE454 for ; Mon, 27 Jan 2025 11:38:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977894; cv=none; b=JeziQ1J75uuc5y2ptHyL3HEiTUb1jLi8vG9WheWv/AxgSbTh5abkzVi5kxCjzezw002M/wGfTb1r4uwHFP9rceO8uThZMnXR16iC7guAGGBPqCM7KhX8m9CsYMTQUHaVA+1MqRMfum582xvQp5CzGyaPCk5dfsIiOvpKhPs2QF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977894; c=relaxed/simple; bh=xtCQXUz07204z660BejHL8pQ+g1JL+EeFTBz0+aLaVg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LX9D84oc23oO8bsjKqH4p5dWyfn95c0FDmRQAbiQVjqNBqakQgdqeNfEWri2GNsS2GqJlHUBDPbhHaXQwh8B3jvRDOsbZLjTMRTgtAvUmGU4xLrLDPs3/h6oG1HTc+cLApcVwaCVjT6G3ijtohbWR+snBMKWPrFhPGE2o3yogCE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: tNFm5x50QKuZWeVLtzyYhg== X-CSE-MsgGUID: DGD5gb/KQ6qoPTiERG+HPg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jan 2025 20:38:11 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 99FEA41F25AC; Mon, 27 Jan 2025 20:38:00 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 11/12] irqchip/renesas-rzv2h: Add RZ/G3E support Date: Mon, 27 Jan 2025 11:37:06 +0000 Message-ID: <20250127113723.24479-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ICU block on the RZ/G3E SoC is almost identical to the one found on the RZ/V2H SoC, with the following differences: - The TINT register offset starts at 0x830 instead of 0x30. - The number of GPIO interrupts for TINT selection is 141 instead of 86. - The pin index and TINT selection index are not in the 1:1 map - The number of TSSR registers is 15 instead of 8 - Each TSSR register can program 2 TINTs instead of 4 TINTs Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and adding LUT for mapping between pin index and TINT selection index. Signed-off-by: Biju Das --- v1->v2: * Introduced ICU_RZG3E_{TSSEL_MAX_VAL,TINT_OFFSET} macros and used these macros in struct rzv2h_hw_params rather than using the hex constants. --- drivers/irqchip/irq-renesas-rzv2h.c | 49 +++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c index 70293a7822e7..12f5ee09af22 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -72,10 +72,13 @@ #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define ICU_RZG3E_TINT_OFFSET 0x800 +#define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure. + * @tssel_lut: TINT lookup table * @t_offs: TINT offset * @tien: TIEN mask * @tssel_mask: TSSEL mask @@ -84,6 +87,7 @@ * @tssr_k: TSSR index k */ struct rzv2h_hw_info { + const u8 *tssel_lut; u16 t_offs; u16 tien; u16 tssel_mask; @@ -307,6 +311,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) if (tint > priv->info->max_tssel) return -EINVAL; + if (priv->info->tssel_lut) + tint = priv->info->tssel_lut[tint & 0xff]; + hwirq = irqd_to_hwirq(d); tint_nr = hwirq - ICU_TINT_START; @@ -515,6 +522,42 @@ static int rzv2h_icu_init_common(struct device_node *node, struct device_node *p return ret; } +/* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */ +static const u8 rzg3e_tssel_lut[] = { + 81, 82, 83, 84, 85, 86, 87, 88, /* P00-P07 */ + 89, 90, 91, 92, 93, 94, 95, 96, /* P10-P17 */ + 111, 112, /* P20-P21 */ + 97, 98, 99, 100, 101, 102, 103, 104, /* P30-P37 */ + 105, 106, 107, 108, 109, 110, /* P40-P45 */ + 113, 114, 115, 116, 117, 118, 119, /* P50-P56 */ + 120, 121, 122, 123, 124, 125, 126, /* P60-P66 */ + 127, 128, 129, 130, 131, 132, 133, 134, /* P70-P77 */ + 135, 136, 137, 138, 139, 140, /* P80-P85 */ + 43, 44, 45, 46, 47, 48, 49, 50, /* PA0-PA7 */ + 51, 52, 53, 54, 55, 56, 57, 58, /* PB0-PB7 */ + 59, 60, 61, /* PC0-PC2 */ + 62, 63, 64, 65, 66, 67, 68, 69, /* PD0-PD7 */ + 70, 71, 72, 73, 74, 75, 76, 77, /* PE0-PE7 */ + 78, 79, 80, /* PF0-PF2 */ + 25, 26, 27, 28, 29, 30, 31, 32, /* PG0-PG7 */ + 33, 34, 35, 36, 37, 38, /* PH0-PH5 */ + 4, 5, 6, 7, 8, /* PJ0-PJ4 */ + 39, 40, 41, 42, /* PK0-PK3 */ + 9, 10, 11, 12, 21, 22, 23, 24, /* PL0-PL7 */ + 13, 14, 15, 16, 17, 18, 19, 20, /* PM0-PM7 */ + 0, 1, 2, 3 /* PS0-PS3 */ +}; + +static const struct rzv2h_hw_info rzg3e_hw_params = { + .tssel_lut = rzg3e_tssel_lut, + .t_offs = ICU_RZG3E_TINT_OFFSET, + .tien = BIT(15), + .tssel_mask = GENMASK(7, 0), + .tssel_shift = 16, + .max_tssel = ICU_RZG3E_TSSEL_MAX_VAL, + .tssr_k = 2, +}; + static const struct rzv2h_hw_info rzv2h_hw_params = { .t_offs = 0, .tien = BIT(7), @@ -524,12 +567,18 @@ static const struct rzv2h_hw_info rzv2h_hw_params = { .tssr_k = 4, }; +static int rzg3e_icu_init(struct device_node *node, struct device_node *parent) +{ + return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params); +} + static int rzv2h_icu_init(struct device_node *node, struct device_node *parent) { return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params); } IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) +IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro "); From patchwork Mon Jan 27 11:37:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13951256 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6CD9F1FE454; Mon, 27 Jan 2025 11:38:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977896; cv=none; b=iOcLS0OTlqMETqTYzu+sRc6RdBZqEOf659+vJYmt2erKOABnyp4zYi1lm1OFT75onBW1SJ9Ih24eBvrxDvdAKewaey/bFOeXYFFRBjXB8GH8/kEPbigf0hWtbWSappa/5RozHC9c1QmDWpo3xDABRJSAQUTT4OV0JNOp0uEehOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737977896; c=relaxed/simple; bh=TApvh36DkBBlaRJePE7XfxZgmL9uLkFPABlIgS8xvQI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Tu99lza4VlPGk+NsJFTC9sZEYMhq91HmtQY5kJTlwssjQA5brd4HyRi07O4U6Clpd3E0feWSWSUccX0EejWO5gX5TlIXRLZGLPHDS+WCh3SZDm5XmwjyOndoaQHrrim/Dz2rg7nB701WTIfxEUuYJutRiJezf+3yqAUytHDuRUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: blLG3KaFR7WlkhoI01LmtA== X-CSE-MsgGUID: i/QWf4NJQOmsuNqJATcv4Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jan 2025 20:38:14 +0900 Received: from localhost.localdomain (unknown [10.226.94.28]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1CAB641F2788; Mon, 27 Jan 2025 20:38:02 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Fabrizio Castro , Tommaso Merciai Subject: [PATCH v2 12/12] arm64: dts: renesas: r9a09g047: Add icu node Date: Mon, 27 Jan 2025 11:37:07 +0000 Message-ID: <20250127113723.24479-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> References: <20250127113723.24479-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add interrupt control node to RZ/G3E ("R9A09G047") SoC DTSI and add icu as interrupt-parent of pincontrol. Also, define the ICU IRQs for board DT users. Reviewed-by: Fabrizio Castro Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 108 +++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index c93aa16d0a6e..2023f70d3329 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -8,6 +8,24 @@ #include #include +#define RZG3E_NMI 0 +#define RZG3E_IRQ0 1 +#define RZG3E_IRQ1 2 +#define RZG3E_IRQ2 3 +#define RZG3E_IRQ3 4 +#define RZG3E_IRQ4 5 +#define RZG3E_IRQ5 6 +#define RZG3E_IRQ6 7 +#define RZG3E_IRQ7 8 +#define RZG3E_IRQ8 9 +#define RZG3E_IRQ9 10 +#define RZG3E_IRQ10 11 +#define RZG3E_IRQ11 12 +#define RZG3E_IRQ12 13 +#define RZG3E_IRQ13 14 +#define RZG3E_IRQ14 15 +#define RZG3E_IRQ15 16 + / { compatible = "renesas,r9a09g047"; #address-cells = <2>; @@ -131,6 +149,95 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g047-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g047-pinctrl"; reg = <0 0x10410000 0 0x10000>; @@ -140,6 +247,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 232>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; };