From patchwork Mon Jan 27 15:11:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13951526 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5549213959D; Mon, 27 Jan 2025 15:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737990697; cv=none; b=oYsuVMkE3RvcXscF5MLGY3ZnV/drxDu77XOiNuTQxgf3afJoeAhlWsBsbenPiitnQufLKYPAbp7NLi8K9nraqlexJAqYLEN+wlXOIoTcTYRiwydj2XPAeP9z7gM85sLT1s1Xbfyg8b/lUW3rd7dX7H7IhRumGIs47l+ZBi25XFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737990697; c=relaxed/simple; bh=qOYcTGQB9wTnJxpMb02AAig2CDcgutp1313sBJKzN8w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I7yfwU3gmx4IPj6iDa+iAR871ZGh7cKhneaUafKBW2X+PHzwRUlXcuObHm4iUMlUCHfnO0aQ0RDNPWhdCa6ATkRcEYT1+q36qkddpIUUmTNp2n0O6Rt7i1CpgMKl20OBt0R+vWD9ljxJv3hZWe7oAHRAYN4nH1bPEue6944L+Ww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=D3XWmDNu; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="D3XWmDNu" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50RDWCXb005707; Mon, 27 Jan 2025 10:11:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=n35zO GD7GuLNZpWxs0SR7wJS1RQieHw/nDhVhHgJtLw=; b=D3XWmDNu3R85l6TRYn4OA coMNMciHs5aKEHsHJ3dJWuT4Xsc/UuQUV6hT87dVpxhHVM+AK/gBEKsDohnHWb32 M+TQFg9s/VB3cdb1IDy3vp7x4KIO57XntbuU/vEDOYaZAie8rZxLvz5AqobovhGz gSBirYHSt4gh5k43jUKRU6Eg1S42YpnZzVOb1gMlRsqoKsuMX/p+oFwt0v0ziVvq CNLrxD3oggHuhEZIm+l+az48uVRURu7XM+K4RwwCRefgkuJTujNk1lrY1pzkHaIq TjdMBZ2+u8v80Pp0j7iJ/vA5DLepCwlsul6Cx6+mQWhDF/FWtv55CqaEN4/YBgEV Q== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 44eb44gdbp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 Jan 2025 10:11:19 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 50RFBI5h038378 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Jan 2025 10:11:18 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:11:17 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:11:17 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFB1YI008230; Mon, 27 Jan 2025 10:11:04 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , , , , David Lechner Subject: [PATCH v2 01/16] iio: adc: ad7768-1: Fix conversion result sign Date: Mon, 27 Jan 2025 12:11:01 -0300 Message-ID: <64e32c0ac7357ca7ddea813ba932bf957cbbeca2.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: Jwbk1u7J0A78YqJB3PX5SIinIc5GXktY X-Proofpoint-GUID: Jwbk1u7J0A78YqJB3PX5SIinIc5GXktY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1011 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 From: Sergiu Cuciurean The ad7768-1 ADC output code is two's complement, meaning that the voltage conversion result is a signed value.. Since the value is a 24 bit one, stored in a 32 bit variable, the sign should be extended in order to get the correct representation. Also the channel description has been updated to signed representation, to match the ADC specifications. Fixes: a5f8c7da3dbe ("iio: adc: Add AD7768-1 ADC basic support") Reviewed-by: David Lechner Reviewed-by: Marcelo Schmitt Signed-off-by: Sergiu Cuciurean --- v2 Changes: * Patch moved to the start of the patch series. --- drivers/iio/adc/ad7768-1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 113703fb7245..c3cf04311c40 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -142,7 +142,7 @@ static const struct iio_chan_spec ad7768_channels[] = { .channel = 0, .scan_index = 0, .scan_type = { - .sign = 'u', + .sign = 's', .realbits = 24, .storagebits = 32, .shift = 8, @@ -371,7 +371,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, ret = ad7768_scan_direct(indio_dev); if (ret >= 0) - *val = ret; + *val = sign_extend32(ret, chan->scan_type.realbits - 1); iio_device_release_direct_mode(indio_dev); if (ret < 0) From patchwork Mon Jan 27 15:11:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13951527 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A02D9130A54; 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Mon, 27 Jan 2025 10:11:44 -0500 (EST) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 50RFBhDm038426 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Jan 2025 10:11:43 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:11:43 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:11:43 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFBWV0008377; Mon, 27 Jan 2025 10:11:34 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 02/16] dt-bindings: iio: adc: ad7768-1: add trigger-sources property Date: Mon, 27 Jan 2025 12:11:30 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: tlDx6rNcYe1G3efqfGDqc9fI8UHaUauD X-Proofpoint-GUID: tlDx6rNcYe1G3efqfGDqc9fI8UHaUauD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 Add a new trigger-sources property to enable synchronization across multiple devices. This property references the main device (or trigger provider) responsible for generating the pulse to drive the SYNC_IN of all devices in the setup. In addition to GPIO synchronization, The AD7768-1 also supports synchronization over SPI, which use is recommended when the GPIO cannot provide a pulse synchronous with the base MCLK signal. It consists of looping back the SYNC_OUT to the SYNC_IN pin and send a command via SPI to trigger the synchronization. SPI-based synchronization is enabled in the absence of adi,sync-in-gpios property. Since adi,sync-in-gpios is not long the only method, remove it from required properties. While at it, add description to the interrupt property. Signed-off-by: Jonathan Santos --- v2 Changes: * Patch added as replacement for adi,sync-in-spi patch. * addressed the request for a description to interrupts property. --- .../bindings/iio/adc/adi,ad7768-1.yaml | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index 3ce59d4d065f..3e119cf1754b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -26,7 +26,17 @@ properties: clock-names: const: mclk + trigger-sources: + description: + References the main device responsible for synchronization. In a single + device setup, reference the own node. + maxItems: 1 + interrupts: + description: + Specifies the interrupt line associated with the ADC. This refers + to the DRDY (Data Ready) pin, which signals when conversion results are + available. maxItems: 1 '#address-cells': @@ -46,6 +56,8 @@ properties: sampling. A pulse is always required if the configuration is changed in any way, for example if the filter decimation rate changes. As the line is active low, it should be marked GPIO_ACTIVE_LOW. + In the absence of this property, Synchronization over SPI will be + enabled. reset-gpios: maxItems: 1 @@ -57,6 +69,9 @@ properties: "#io-channel-cells": const: 1 + "#trigger-source-cells": + const: 0 + required: - compatible - reg @@ -65,7 +80,8 @@ required: - vref-supply - spi-cpol - spi-cpha - - adi,sync-in-gpios + - trigger-sources + - #trigger-source-cells patternProperties: "^channel@([0-9]|1[0-5])$": @@ -99,7 +115,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - adc@0 { + adc0: adc@0 { compatible = "adi,ad7768-1"; reg = <0>; spi-max-frequency = <2000000>; @@ -109,6 +125,8 @@ examples: interrupts = <25 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gpio>; adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + trigger-sources = <&adc0>; + #trigger-source-cells = <0>; reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>; clocks = <&ad7768_mclk>; clock-names = "mclk"; From patchwork Mon Jan 27 15:11:44 2025 Content-Type: text/plain; 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Mon, 27 Jan 2025 10:11:56 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:11:56 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFBiO3008394; Mon, 27 Jan 2025 10:11:47 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 03/16] dt-bindings: iio: adc: ad7768-1: Document GPIO controller Date: Mon, 27 Jan 2025 12:11:44 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: wo9AM1Q2OCjlqsigzHnD9z-ddrYxPWDX X-Proofpoint-GUID: wo9AM1Q2OCjlqsigzHnD9z-ddrYxPWDX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=878 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 The AD7768-1 ADC exports four bidirectional GPIOs accessible via register map. Document GPIO properties necessary to enable GPIO controller for this device. Signed-off-by: Jonathan Santos Reviewed-by: Rob Herring (Arm) --- v2 Changes: * New patch in v2. --- .../devicetree/bindings/iio/adc/adi,ad7768-1.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index 3e119cf1754b..da05c8448530 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -72,6 +72,14 @@ properties: "#trigger-source-cells": const: 0 + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is for the GPIO number: 0 to 3. + The second cell takes standard GPIO flags. + required: - compatible - reg @@ -121,6 +129,8 @@ examples: spi-max-frequency = <2000000>; spi-cpol; spi-cpha; + gpio-controller; + #gpio-cells = <2>; vref-supply = <&adc_vref>; interrupts = <25 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gpio>; From patchwork Mon Jan 27 15:12:05 2025 Content-Type: text/plain; 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Mon, 27 Jan 2025 10:12:17 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:12:17 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:12:17 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFC53N008403; Mon, 27 Jan 2025 10:12:08 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 04/16] dt-bindings: iio: adc: ad7768-1: add VMC output property Date: Mon, 27 Jan 2025 12:12:05 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: Xn24c3WgnxXIF78n0Z8YaCXR3SumBz4B X-Proofpoint-ORIG-GUID: Xn24c3WgnxXIF78n0Z8YaCXR3SumBz4B X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=807 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 The AD7768-1 provides a buffered common-mode voltage output on the VCM pin that can be used to bias analog input signals. Add adi,vcm-output to enable the configuration of the VCM output circuit. Signed-off-by: Jonathan Santos --- v2 Changes: * New patch in v2. --- .../bindings/iio/adc/adi,ad7768-1.yaml | 10 ++++++++++ include/dt-bindings/iio/adc/adi,ad7768-1.h | 16 ++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 include/dt-bindings/iio/adc/adi,ad7768-1.h diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index da05c8448530..e26513a9469b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -59,6 +59,15 @@ properties: In the absence of this property, Synchronization over SPI will be enabled. + adi,vcm-output: + description: | + Configures the Common-Mode Voltage Output. The VCM is provided by an + amplifier external to the AD7768-1 and can be used as common-mode voltage + by the ADC. There are 8 output voltage options available, and the macros + for these values can be found at dt-bindings/iio/adi,ad7768-1.h + items: + enum: [0, 1, 2, 3, 4, 5, 6, 7] + reset-gpios: maxItems: 1 @@ -132,6 +141,7 @@ examples: gpio-controller; #gpio-cells = <2>; vref-supply = <&adc_vref>; + adi,vcm-output = ; interrupts = <25 IRQ_TYPE_EDGE_RISING>; interrupt-parent = <&gpio>; adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; diff --git a/include/dt-bindings/iio/adc/adi,ad7768-1.h b/include/dt-bindings/iio/adc/adi,ad7768-1.h new file mode 100644 index 000000000000..469ea724c0d5 --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad7768-1.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD7768_1_H +#define _DT_BINDINGS_ADI_AD7768_1_H + +/* Sets VCM output to (AVDD1 − AVSS)/2 */ +#define AD7768_VCM_OUTPUT_AVDD1_AVSS_2 0x00 +#define AD7768_VCM_OUTPUT_2_5V 0x01 +#define AD7768_VCM_OUTPUT_2_05V 0x02 +#define AD7768_VCM_OUTPUT_1_9V 0x03 +#define AD7768_VCM_OUTPUT_1_65V 0x04 +#define AD7768_VCM_OUTPUT_1_1V 0x05 +#define AD7768_VCM_OUTPUT_0_9V 0x06 +#define AD7768_VCM_OUTPUT_OFF 0x07 + +#endif /* _DT_BINDINGS_ADI_AD7768_1_H */ From patchwork Mon Jan 27 15:12:17 2025 Content-Type: text/plain; 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Mon, 27 Jan 2025 10:12:28 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:12:28 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFCHAm008407; Mon, 27 Jan 2025 10:12:20 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 05/16] Documentation: ABI: add wideband filter type to sysfs-bus-iio Date: Mon, 27 Jan 2025 12:12:17 -0300 Message-ID: <351b15550f8d8e7126ed8253f3a8028c708327f8.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: heoPHEawcgOwUSIA-59iQ2mkauv_38Uz X-Proofpoint-ORIG-GUID: heoPHEawcgOwUSIA-59iQ2mkauv_38Uz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 The Wideband Low Ripple filter is used for AD7768-1 Driver. Document wideband filter option into filter_type_available attribute. Signed-off-by: Jonathan Santos --- v2 Changes: * Removed FIR mentions. --- Documentation/ABI/testing/sysfs-bus-iio | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index f83bd6829285..9b879e7732cd 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2291,6 +2291,8 @@ Description: * "sinc3+pf2" - Sinc3 + device specific Post Filter 2. * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. + * "wideband" - filter with wideband low ripple passband + and sharp transition band. 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Mon, 27 Jan 2025 10:12:41 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:12:40 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:12:40 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:12:40 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFCThn008411; Mon, 27 Jan 2025 10:12:32 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 06/16] iio: adc: ad7768-1: set MOSI idle state to prevent accidental reset Date: Mon, 27 Jan 2025 12:12:29 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: RU-F9FZJ5HaHDCGbpOvY-t2wMaH0LSA0 X-Proofpoint-GUID: RU-F9FZJ5HaHDCGbpOvY-t2wMaH0LSA0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=994 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 Datasheet recommends Setting the MOSI idle state to high in order to prevent accidental reset of the device when SCLK is free running. This happens when the controller clocks out a 1 followed by 63 zeros while the CS is held low. Check if SPI controller supports SPI_MOSI_IDLE_HIGH flag and set it. Fixes: a5f8c7da3dbe ("iio: adc: Add AD7768-1 ADC basic support") Signed-off-by: Jonathan Santos --- v2 Changes: * Only setup SPI_MOSI_IDLE_HIGH flag if the controller supports it, otherwise the driver continues the same. I realized that using bits_per_word does not avoid the problem that MOSI idle state is trying to solve. If the controller drives the MOSI low between bytes during a transfer, nothing happens. --- drivers/iio/adc/ad7768-1.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index c3cf04311c40..95ba89435652 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -574,6 +574,22 @@ static int ad7768_probe(struct spi_device *spi) return -ENOMEM; st = iio_priv(indio_dev); + /* + * Datasheet recommends SDI line to be kept high when + * data is not being clocked out of the controller + * and the spi clock is free running, to prevent + * accidental reset. + * Since many controllers do not support the + * SPI_MOSI_IDLE_HIGH flag yet, only request the MOSI + * idle state to enable if the controller supports it. + */ + if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) { + spi->mode |= SPI_MOSI_IDLE_HIGH; + ret = spi_setup(spi); + if (ret < 0) + return ret; + } + st->spi = spi; st->vref = devm_regulator_get(&spi->dev, "vref"); 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Mon, 27 Jan 2025 10:12:58 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:12:58 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:12:58 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:12:57 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFCiua008423; Mon, 27 Jan 2025 10:12:46 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 07/16] iio: adc: ad7768-1: convert driver to use regmap Date: Mon, 27 Jan 2025 12:12:43 -0300 Message-ID: <0968f9cfc55c5ac80492a88bbe95fc8ff7208fa5.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: AHekaWd_ZdkzEDftGqMuzIhqjjCls8ac X-Proofpoint-ORIG-GUID: AHekaWd_ZdkzEDftGqMuzIhqjjCls8ac X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 suspectscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 Convert the AD7768-1 driver to use the regmap API for register access. This change simplifies and standardizes register interactions, reducing code duplication and improving maintainability. Signed-off-by: Jonathan Santos --- v2 Changes: * New patch in v2. --- drivers/iio/adc/ad7768-1.c | 82 +++++++++++++++++++++++++++----------- 1 file changed, 58 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 95ba89435652..fb8d6fae5f8a 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -153,6 +154,7 @@ static const struct iio_chan_spec ad7768_channels[] = { struct ad7768_state { struct spi_device *spi; + struct regmap *regmap; struct regulator *vref; struct mutex lock; struct clk *mclk; @@ -176,12 +178,17 @@ struct ad7768_state { } data __aligned(IIO_DMA_MINALIGN); }; -static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, - unsigned int len) +static int ad7768_spi_reg_read(void *context, unsigned int addr, + unsigned int *val) { - unsigned int shift; + struct iio_dev *dev = context; + struct ad7768_state *st; + unsigned int shift, len; int ret; + st = iio_priv(dev); + /* Regular value size is 1 Byte, but 3 Bytes for ADC data */ + len = (addr == AD7768_REG_ADC_DATA) ? 3 : 1; shift = 32 - (8 * len); st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); @@ -190,13 +197,19 @@ static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, if (ret < 0) return ret; - return (be32_to_cpu(st->data.d32) >> shift); + *val = be32_to_cpu(st->data.d32) >> shift; + + return 0; } -static int ad7768_spi_reg_write(struct ad7768_state *st, +static int ad7768_spi_reg_write(void *context, unsigned int addr, unsigned int val) { + struct iio_dev *dev = context; + struct ad7768_state *st; + + st = iio_priv(dev); st->data.d8[0] = AD7768_WR_FLAG_MSK(addr); st->data.d8[1] = val & 0xFF; @@ -206,16 +219,16 @@ static int ad7768_spi_reg_write(struct ad7768_state *st, static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { - int regval; + int regval, ret; - regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); - if (regval < 0) - return regval; + ret = regmap_read(st->regmap, AD7768_REG_CONVERSION, ®val); + if (ret) + return ret; regval &= ~AD7768_CONV_MODE_MSK; regval |= AD7768_CONV_MODE(mode); - return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); + return regmap_write(st->regmap, AD7768_REG_CONVERSION, regval); } static int ad7768_scan_direct(struct iio_dev *indio_dev) @@ -234,9 +247,10 @@ static int ad7768_scan_direct(struct iio_dev *indio_dev) if (!ret) return -ETIMEDOUT; - readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); - if (readval < 0) - return readval; + ret = regmap_read(st->regmap, AD7768_REG_ADC_DATA, &readval); + if (ret) + return ret; + /* * Any SPI configuration of the AD7768-1 can only be * performed in continuous conversion mode. @@ -258,13 +272,11 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, mutex_lock(&st->lock); if (readval) { - ret = ad7768_spi_reg_read(st, reg, 1); - if (ret < 0) + ret = regmap_read(st->regmap, reg, readval); + if (ret) goto err_unlock; - *readval = ret; - ret = 0; } else { - ret = ad7768_spi_reg_write(st, reg, writeval); + ret = regmap_write(st->regmap, reg, writeval); } err_unlock: mutex_unlock(&st->lock); @@ -283,7 +295,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, else mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); - ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); + ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode); if (ret < 0) return ret; @@ -320,7 +332,7 @@ static int ad7768_set_freq(struct ad7768_state *st, */ pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); - ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); + ret = regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode); if (ret < 0) return ret; @@ -447,11 +459,11 @@ static int ad7768_setup(struct ad7768_state *st) * to 10. When the sequence is detected, the reset occurs. * See the datasheet, page 70. */ - ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3); + ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3); if (ret) return ret; - ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2); + ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2); if (ret) return ret; @@ -509,18 +521,19 @@ static int ad7768_buffer_postenable(struct iio_dev *indio_dev) * continuous read mode. Subsequent data reads do not require an * initial 8-bit write to query the ADC_DATA register. */ - return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01); + return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01); } static int ad7768_buffer_predisable(struct iio_dev *indio_dev) { struct ad7768_state *st = iio_priv(indio_dev); + unsigned int regval; /* * To exit continuous read mode, perform a single read of the ADC_DATA * reg (0x2C), which allows further configuration of the device. */ - return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); + return regmap_read(st->regmap, AD7768_REG_ADC_DATA, ®val); } static const struct iio_buffer_setup_ops ad7768_buffer_ops = { @@ -563,6 +576,20 @@ static int ad7768_set_channel_label(struct iio_dev *indio_dev, return 0; } +static const struct regmap_bus ad7768_regmap_bus = { + .reg_write = ad7768_spi_reg_write, + .reg_read = ad7768_spi_reg_read, + .reg_format_endian_default = REGMAP_ENDIAN_BIG, + .val_format_endian_default = REGMAP_ENDIAN_BIG, +}; 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Mon, 27 Jan 2025 10:12:59 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , , , Subject: [PATCH v2 08/16] iio: adc: ad7768-1: Add reset gpio Date: Mon, 27 Jan 2025 12:12:55 -0300 Message-ID: <722340b0efff3ed22a763ce6581c96ca403316d8.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: Vxwje_A1d_3SoSpnHvu-qlJ0MEzXETzo X-Proofpoint-ORIG-GUID: Vxwje_A1d_3SoSpnHvu-qlJ0MEzXETzo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 From: Sergiu Cuciurean Depending on the controller, the default state of a gpio can vary. This change excludes the probability that the dafult state of the ADC reset gpio will be HIGH if it will be passed as reference in the devicetree. Signed-off-by: Sergiu Cuciurean Reviewed-by: David Lechner --- v2 Changes: * Replaced usleep_range() for fsleep() and gpiod_direction_output() for gpiod_set_value_cansleep(). * Reset via SPI register is performed if the Reset GPIO is not defined. --- drivers/iio/adc/ad7768-1.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index fb8d6fae5f8a..17a49bf74637 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -163,6 +163,7 @@ struct ad7768_state { struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; + struct gpio_desc *gpio_reset; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* * DMA (thus cache coherency maintenance) may require the @@ -453,19 +454,30 @@ static int ad7768_setup(struct ad7768_state *st) { int ret; - /* - * Two writes to the SPI_RESET[1:0] bits are required to initiate - * a software reset. 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Mon, 27 Jan 2025 10:13:11 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 09/16] iio: adc: ad7768-1: remove unnecessary locking Date: Mon, 27 Jan 2025 12:13:08 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: 8jY4s75ewN2vI22jjL35FRfYYGj7hL9C X-Proofpoint-ORIG-GUID: 8jY4s75ewN2vI22jjL35FRfYYGj7hL9C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 suspectscore=0 mlxscore=0 clxscore=1015 mlxlogscore=997 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 The current locking is only preventing a triggered buffer Transfer and a debugfs register access from happening at the same time. If a register access happens during a buffered read, the action is doomed to fail anyway, since we need to write a magic value to exit continuous read mode. Remove locking from the trigger handler and use iio_device_claim_direct_mode() instead in the register access function. Signed-off-by: Jonathan Santos --- v2 Changes: * New patch in v2. It replaces the guard(mutex) patch. --- drivers/iio/adc/ad7768-1.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 17a49bf74637..5e2093be9b92 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -271,16 +271,16 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, struct ad7768_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&st->lock); - if (readval) { + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + if (readval) ret = regmap_read(st->regmap, reg, readval); - if (ret) - goto err_unlock; - } else { + else ret = regmap_write(st->regmap, reg, writeval); - } -err_unlock: - mutex_unlock(&st->lock); + + iio_device_release_direct_mode(indio_dev); return ret; } @@ -495,18 +495,15 @@ static irqreturn_t ad7768_trigger_handler(int irq, void *p) struct ad7768_state *st = iio_priv(indio_dev); int ret; - mutex_lock(&st->lock); - ret = spi_read(st->spi, &st->data.scan.chan, 3); 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Mon, 27 Jan 2025 10:13:33 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:13:33 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:13:33 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:13:33 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFDKd5008445; Mon, 27 Jan 2025 10:13:22 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , , , Subject: [PATCH v2 10/16] iio: adc: ad7768-1: Move buffer allocation to a separate function Date: Mon, 27 Jan 2025 12:13:19 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 4L8S55vDS4sHJR5uE6uznT0L5Nr82OAw X-Proofpoint-GUID: 4L8S55vDS4sHJR5uE6uznT0L5Nr82OAw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 From: Sergiu Cuciurean This change moves the buffer allocation in a separate function, making space for adding another type of iio buffer if needed. Signed-off-by: Sergiu Cuciurean --- v2 Changes: * Interrupt and completion moved out from ad7768_triggered_buffer_alloc(). --- drivers/iio/adc/ad7768-1.c | 44 ++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 5e2093be9b92..8487b9a06609 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -599,6 +599,31 @@ static const struct regmap_config ad7768_regmap_config = { .max_register = AD7768_REG_MCLK_COUNTER, }; +static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev) +{ + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return -ENOMEM; + + st->trig->ops = &ad7768_trigger_ops; + iio_trigger_set_drvdata(st->trig, indio_dev); + ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig); + if (ret) + return ret; + + indio_dev->trig = iio_trigger_get(st->trig); + + return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev, + &iio_pollfunc_store_time, + &ad7768_trigger_handler, + &ad7768_buffer_ops); +} + static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; @@ -669,20 +694,6 @@ static int ad7768_probe(struct spi_device *spi) return ret; } - st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", - indio_dev->name, - iio_device_id(indio_dev)); - if (!st->trig) - return -ENOMEM; - - st->trig->ops = &ad7768_trigger_ops; - iio_trigger_set_drvdata(st->trig, indio_dev); - ret = devm_iio_trigger_register(&spi->dev, st->trig); - if (ret) - return ret; - - indio_dev->trig = iio_trigger_get(st->trig); - init_completion(&st->completion); ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels)); @@ -696,10 +707,7 @@ static int ad7768_probe(struct spi_device *spi) if (ret) return ret; - ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, - &iio_pollfunc_store_time, - &ad7768_trigger_handler, - &ad7768_buffer_ops); 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Mon, 27 Jan 2025 10:13:46 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:13:46 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:13:46 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFDZ2Y008448; Mon, 27 Jan 2025 10:13:37 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , , , , Jonathan Santos Subject: [PATCH v2 11/16] iio: adc: ad7768-1: Add VCM output support Date: Mon, 27 Jan 2025 12:13:32 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: RsJgKsMBqDhQ6m_Xx55YtIUljbZmSLIW X-Proofpoint-GUID: RsJgKsMBqDhQ6m_Xx55YtIUljbZmSLIW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 From: Sergiu Cuciurean The VCM output voltage can be used as a common-mode voltage within the amplifier preconditioning circuits external to the AD7768-1. This change allows the user to configure VCM output trough a devicetree attribute. Co-developed-by: Jonathan Santos Signed-off-by: Jonathan Santos Signed-off-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Jonathan Santos --- v2 Changes: * VCM output support is now defined by a devicetree property, instead of and IIO attribute. --- drivers/iio/adc/ad7768-1.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 8487b9a06609..c540583808c2 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -24,6 +24,8 @@ #include #include +#include + /* AD7768 registers definition */ #define AD7768_REG_CHIP_TYPE 0x3 #define AD7768_REG_PROD_ID_L 0x4 @@ -347,6 +349,11 @@ static int ad7768_set_freq(struct ad7768_state *st, return 0; } +static int ad7768_set_vcm_output(struct ad7768_state *st, unsigned int mode) +{ + return regmap_write(st->regmap, AD7768_REG_ANALOG2, mode); +} + static ssize_t ad7768_sampling_freq_avail(struct device *dev, struct device_attribute *attr, char *buf) @@ -628,6 +635,7 @@ static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; struct iio_dev *indio_dev; + u32 val; int ret; indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -688,6 +696,18 @@ static int ad7768_probe(struct spi_device *spi) indio_dev->info = &ad7768_info; indio_dev->modes = INDIO_DIRECT_MODE; + ret = device_property_read_u32(&spi->dev, "adi,vcm-output", &val); + if (!ret) { + if (val > AD7768_VCM_OUTPUT_OFF) { + dev_err(&spi->dev, "Invalid VCM output value\n"); + return -EINVAL; + } + + ret = ad7768_set_vcm_output(st, val); + if (ret) + return ret; + } + ret = ad7768_setup(st); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); From patchwork Mon Jan 27 15:13:45 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13951537 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A3D513D897; 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Mon, 27 Jan 2025 10:13:59 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 50RFDviV011097 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Jan 2025 10:13:57 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:13:57 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:13:57 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFDjUS008452; Mon, 27 Jan 2025 10:13:48 -0500 From: Jonathan Santos To: , , CC: Sergiu Cuciurean , , , , , , , , , , Jonathan Santos Subject: [PATCH v2 12/16] iio: adc: ad7768-1: Add GPIO controller support Date: Mon, 27 Jan 2025 12:13:45 -0300 Message-ID: <4067fc67ef617edbaea0de21241d59d6ff8eaf98.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 1O3MApAxgVl2xwP2PzVkwLOiGX9P2M6X X-Proofpoint-GUID: 1O3MApAxgVl2xwP2PzVkwLOiGX9P2M6X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 From: Sergiu Cuciurean The AD7768-1 has the ability to control other local hardware (such as gain stages),to power down other blocks in the signal chain, or read local status signals over the SPI interface. This change exports the AD7768-1's four gpios and makes them accessible at an upper layer. Co-developed-by: Jonathan Santos Signed-off-by: Jonathan Santos Signed-off-by: Sergiu Cuciurean --- v2 Changes: * Replaced mutex for iio_device_claim_direct_mode(). * Use gpio-controller property to conditionally enable the GPIO support. * OBS: when the GPIO is configured as output, we should read the current state value from AD7768_REG_GPIO_WRITE. --- drivers/iio/adc/ad7768-1.c | 148 ++++++++++++++++++++++++++++++++++++- 1 file changed, 146 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index c540583808c2..e3ea078e6ec4 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -79,6 +81,19 @@ #define AD7768_CONV_MODE_MSK GENMASK(2, 0) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) +/* AD7768_REG_GPIO_CONTROL */ +#define AD7768_GPIO_UNIVERSAL_EN BIT(7) +#define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_WRITE */ +#define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_READ */ +#define AD7768_GPIO_READ_MSK GENMASK(3, 0) + +#define AD7768_GPIO_INPUT(x) 0x00 +#define AD7768_GPIO_OUTPUT(x) BIT(x) + #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) @@ -160,6 +175,8 @@ struct ad7768_state { struct regulator *vref; struct mutex lock; struct clk *mclk; + struct gpio_chip gpiochip; + unsigned int gpio_avail_map; unsigned int mclk_freq; unsigned int samp_freq; struct completion completion; @@ -309,6 +326,125 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return 0; } +static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, + AD7768_REG_GPIO_CONTROL, + BIT(offset), + AD7768_GPIO_INPUT(offset)); +} + +static int ad7768_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, + AD7768_REG_GPIO_CONTROL, + BIT(offset), + AD7768_GPIO_OUTPUT(offset)); +} + +static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + unsigned int val; + int ret; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); + if (ret < 0) + return ret; + + if (val & BIT(offset)) + ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); + else + ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(offset)); +} + +static void ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + unsigned int val; + int ret; + + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return; + + ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); + if (ret < 0) + return; + + if (val & BIT(offset)) + regmap_update_bits(st->regmap, + AD7768_REG_GPIO_WRITE, + BIT(offset), + (value << offset)); +} + +static int ad7768_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + + if (!(st->gpio_avail_map & BIT(offset))) + return -ENODEV; + + st->gpio_avail_map &= ~BIT(offset); + + return 0; +} + +static int ad7768_gpio_init(struct iio_dev *indio_dev) +{ + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UNIVERSAL_EN); + if (ret < 0) + return ret; + + st->gpio_avail_map = AD7768_GPIO_CONTROL_MSK; + st->gpiochip.label = "ad7768_1_gpios"; + st->gpiochip.base = -1; + st->gpiochip.ngpio = 4; + st->gpiochip.parent = &st->spi->dev; + st->gpiochip.can_sleep = true; + st->gpiochip.direction_input = ad7768_gpio_direction_input; + st->gpiochip.direction_output = ad7768_gpio_direction_output; + st->gpiochip.get = ad7768_gpio_get; + st->gpiochip.set = ad7768_gpio_set; + st->gpiochip.request = ad7768_gpio_request; + st->gpiochip.owner = THIS_MODULE; + + return gpiochip_add_data(&st->gpiochip, indio_dev); +} + static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { @@ -457,8 +593,9 @@ static const struct iio_info ad7768_info = { .debugfs_reg_access = &ad7768_reg_access, }; -static int ad7768_setup(struct ad7768_state *st) +static int ad7768_setup(struct iio_dev *indio_dev) { + struct ad7768_state *st = iio_priv(indio_dev); int ret; st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", @@ -491,6 +628,13 @@ static int ad7768_setup(struct ad7768_state *st) if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); + /* Only create a Chip GPIO if flagged for it */ + if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { + ret = ad7768_gpio_init(indio_dev); + if (ret < 0) + return ret; + } + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } @@ -708,7 +852,7 @@ static int ad7768_probe(struct spi_device *spi) return ret; } - ret = ad7768_setup(st); + ret = ad7768_setup(indio_dev); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); return ret; From patchwork Mon Jan 27 15:13:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13951538 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F15F013D52E; Mon, 27 Jan 2025 15:14:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737990867; cv=none; b=CgIQpWcd0aqZI6zV+jVGs2E+9zd4tQVQlEd/CjxoRUIzipWu1u+dyldjKJaRNvYaOVbXhARFmPgM6ofanoUn3TTLFy5oBHUwdCO5sWKLy2aGMYBzZAOO2y0zsIlBjJ69RElcr2Ee54SleerErlR/0xNI55a6Pb1VY+orakC//aQ= ARC-Message-Signature: i=1; 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Mon, 27 Jan 2025 10:14:11 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:14:11 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:14:10 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:14:10 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFDv68008456; Mon, 27 Jan 2025 10:13:59 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 13/16] iio: adc: ad7768-1: add multiple scan types to support 16-bits mode Date: Mon, 27 Jan 2025 12:13:56 -0300 Message-ID: <8bff69133cddd7e6be714781ea7655a427a6c32e.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: TZp7t-lwDtuhgjb-oocCLgAF3MBxUujd X-Proofpoint-ORIG-GUID: TZp7t-lwDtuhgjb-oocCLgAF3MBxUujd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 When the device is configured to Sinc5 filter and decimation x8, output data is reduced to 16-bits in order to support 1 MHz of sampling frequency due to clock limitation. Use multiple scan types feature to enable the driver to switch scan type in runtime, making possible to support both 24-bit and 16-bit resolution. Signed-off-by: Jonathan Santos --- v2 Changes: * Included the ".shift" value back to scan_type. * Changed the number of bytes from regmap_read instead of shifting the ADC sample value when the word size is lower (16-bits). --- drivers/iio/adc/ad7768-1.c | 73 ++++++++++++++++++++++++++++++++------ 1 file changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index e3ea078e6ec4..7686556c7808 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -136,6 +136,15 @@ struct ad7768_clk_configuration { enum ad7768_pwrmode pwrmode; }; +enum ad7768_scan_type { + AD7768_SCAN_TYPE_NORMAL, + AD7768_SCAN_TYPE_HIGH_SPEED, +}; + +static const int ad7768_mclk_div_rates[4] = { + 16, 8, 4, 2, +}; + static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, @@ -150,6 +159,23 @@ static const struct ad7768_clk_configuration ad7768_clk_config[] = { { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, }; +static const struct iio_scan_type ad7768_scan_type[] = { + [AD7768_SCAN_TYPE_NORMAL] = { + .sign = 's', + .realbits = 24, + .storagebits = 32, + .shift = 8, + .endianness = IIO_BE, + }, + [AD7768_SCAN_TYPE_HIGH_SPEED] = { + .sign = 's', + .realbits = 16, + .storagebits = 32, + .shift = 16, + .endianness = IIO_BE, + }, +}; + static const struct iio_chan_spec ad7768_channels[] = { { .type = IIO_VOLTAGE, @@ -159,13 +185,9 @@ static const struct iio_chan_spec ad7768_channels[] = { .indexed = 1, .channel = 0, .scan_index = 0, - .scan_type = { - .sign = 's', - .realbits = 24, - .storagebits = 32, - .shift = 8, - .endianness = IIO_BE, - }, + .has_ext_scan_type = 1, + .ext_scan_type = ad7768_scan_type, + .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type), }, }; @@ -178,6 +200,7 @@ struct ad7768_state { struct gpio_chip gpiochip; unsigned int gpio_avail_map; unsigned int mclk_freq; + unsigned int dec_rate; unsigned int samp_freq; struct completion completion; struct iio_trigger *trig; @@ -201,14 +224,19 @@ struct ad7768_state { static int ad7768_spi_reg_read(void *context, unsigned int addr, unsigned int *val) { + const struct iio_scan_type *scan_type; struct iio_dev *dev = context; struct ad7768_state *st; unsigned int shift, len; int ret; st = iio_priv(dev); + scan_type = iio_get_current_scan_type(dev, &dev->channels[0]); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + /* Regular value size is 1 Byte, but 3 Bytes for ADC data */ - len = (addr == AD7768_REG_ADC_DATA) ? 3 : 1; + len = (addr == AD7768_REG_ADC_DATA) ? BITS_TO_BYTES(scan_type->realbits) : 1; shift = 32 - (8 * len); st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); @@ -479,6 +507,8 @@ static int ad7768_set_freq(struct ad7768_state *st, if (ret < 0) return ret; + st->dec_rate = ad7768_clk_config[idx].clk_div / + ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, ad7768_clk_config[idx].clk_div); @@ -517,8 +547,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long info) { struct ad7768_state *st = iio_priv(indio_dev); + const struct iio_scan_type *scan_type; int scale_uv, ret; + scan_type = iio_get_current_scan_type(indio_dev, chan); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + switch (info) { case IIO_CHAN_INFO_RAW: ret = iio_device_claim_direct_mode(indio_dev); @@ -527,7 +562,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, ret = ad7768_scan_direct(indio_dev); if (ret >= 0) - *val = sign_extend32(ret, chan->scan_type.realbits - 1); + *val = sign_extend32(ret, scan_type->realbits - 1); iio_device_release_direct_mode(indio_dev); if (ret < 0) @@ -541,7 +576,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return scale_uv; *val = (scale_uv * 2) / 1000; - *val2 = chan->scan_type.realbits; + *val2 = scan_type->realbits; return IIO_VAL_FRACTIONAL_LOG2; @@ -585,11 +620,21 @@ static const struct attribute_group ad7768_group = { .attrs = ad7768_attributes, }; +static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st = iio_priv(indio_dev); + + return st->dec_rate == 8 ? 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Mon, 27 Jan 2025 10:14:21 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 50RFEJFO011116 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Jan 2025 10:14:19 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:14:19 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:14:19 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFE8MQ008462; Mon, 27 Jan 2025 10:14:11 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 14/16] iio: adc: ad7768-1: add support for Synchronization over SPI Date: Mon, 27 Jan 2025 12:14:08 -0300 Message-ID: <2d3c69d92a9688f4a20bd6de70f694482501f61c.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: gLuwNPe-ZQ33LUD6N_lP-bnCXPhZQVg6 X-Proofpoint-GUID: gLuwNPe-ZQ33LUD6N_lP-bnCXPhZQVg6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 The synchronization method using GPIO requires the generated pulse to be truly synchronous with the base MCLK signal. When it is not possible to do that in hardware, the datasheet recommends using synchronization over SPI, where the generated pulse is already synchronous with MCLK. This requires the SYNC_OUT pin to be connected to SYNC_IN pin. In multidevices setup, the SYNC_OUT from other devices can be used as synchronization source. Use trigger-sources property to enable device synchronization over SPI for single and multiple devices. Signed-off-by: Jonathan Santos --- v2 Changes: * Synchronization via SPI is enabled when the Sync GPIO is not defined. * now trigger-sources property indicates the synchronization provider or main device. The main device will be used to drive the SYNC_IN when requested (via GPIO or SPI). --- drivers/iio/adc/ad7768-1.c | 81 ++++++++++++++++++++++++++++++++++---- 1 file changed, 73 insertions(+), 8 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 7686556c7808..01ccbe0aa708 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -193,6 +193,7 @@ static const struct iio_chan_spec ad7768_channels[] = { struct ad7768_state { struct spi_device *spi; + struct spi_device *sync_source_spi; struct regmap *regmap; struct regulator *vref; struct mutex lock; @@ -206,6 +207,7 @@ struct ad7768_state { struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; struct gpio_desc *gpio_reset; + bool en_spi_sync; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* * DMA (thus cache coherency maintenance) may require the @@ -264,6 +266,21 @@ static int ad7768_spi_reg_write(void *context, return spi_write(st->spi, st->data.d8, 2); } +static int ad7768_send_sync_pulse(struct ad7768_state *st) +{ + if (st->en_spi_sync) { + st->data.d8[0] = AD7768_WR_FLAG_MSK(AD7768_REG_SYNC_RESET); + st->data.d8[1] = 0x00; + + return spi_write(st->sync_source_spi, st->data.d8, 2); + } else if (st->gpio_sync_in) { + gpiod_set_value_cansleep(st->gpio_sync_in, 1); + gpiod_set_value_cansleep(st->gpio_sync_in, 0); + } + + return 0; +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -348,10 +365,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return ret; /* A sync-in pulse is required every time the filter dec rate changes */ - gpiod_set_value(st->gpio_sync_in, 1); - gpiod_set_value(st->gpio_sync_in, 0); - - return 0; + return ad7768_send_sync_pulse(st); } static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) @@ -638,6 +652,58 @@ static const struct iio_info ad7768_info = { .debugfs_reg_access = &ad7768_reg_access, }; +static int ad7768_parse_trigger_sources(struct device *dev, struct ad7768_state *st) +{ + struct fwnode_reference_args args; + int ret; + + /* + * The AD7768-1 allows two primary methods for driving the SYNC_IN pin to synchronize + * one or more devices: + * 1. Using a GPIO to directly drive the SYNC_IN pin. + * 2. Using a SPI command, where the SYNC_OUT pin generates a synchronization pulse + * that loops back to the SYNC_IN pin. + * + * In multi-device setups, the SYNC_IN pin can also be driven by the SYNC_OUT pin of + * another device. To support this, we use the "trigger-source" property to get a + * reference to the "main" device responsible for generating the synchronization pulse. + * In a single-device setup, the "trigger-source" property should reference the device's + * own node. + */ + ret = fwnode_property_get_reference_args(dev_fwnode(dev), "trigger-sources", + "#trigger-source-cells", 0, 0, &args); + if (ret) { + dev_err(dev, "Failed to get trigger-sources reference: %d\n", ret); + return ret; + } + + st->gpio_sync_in = devm_gpiod_get_optional(args.fwnode->dev, "adi,sync-in", + GPIOD_OUT_LOW); + if (IS_ERR(st->gpio_sync_in)) + return PTR_ERR(st->gpio_sync_in); + + /* + * If the SYNC_IN GPIO is not defined, fall back to synchronization over SPI. + * Use the trigger-source reference to identify the main SPI device for generating + * the synchronization pulse. + */ + if (!st->gpio_sync_in) { + st->sync_source_spi = to_spi_device(args.fwnode->dev); + if (!st->sync_source_spi) { + dev_err(dev, + "Synchronization setup failed. GPIO is undefined and trigger-source reference is invalid\n"); + return -EINVAL; + } + + st->en_spi_sync = true; + } + + /* Release the fwnode reference after use */ + fwnode_handle_put(args.fwnode); + + return 0; +} + static int ad7768_setup(struct iio_dev *indio_dev) { struct ad7768_state *st = iio_priv(indio_dev); @@ -668,10 +734,9 @@ static int ad7768_setup(struct iio_dev *indio_dev) return ret; } - st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", - GPIOD_OUT_LOW); - if (IS_ERR(st->gpio_sync_in)) - return PTR_ERR(st->gpio_sync_in); + ret = ad7768_parse_trigger_sources(&st->spi->dev, st); + if (ret) + return ret; /* Only create a Chip GPIO if flagged for it */ if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { From patchwork Mon Jan 27 15:14:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13951540 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1C9D13D52E; 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Mon, 27 Jan 2025 10:14:22 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , , PopPaul2021 Subject: [PATCH v2 15/16] iio: adc: ad7768-1: add filter type and oversampling ratio attributes Date: Mon, 27 Jan 2025 12:14:19 -0300 Message-ID: <3a5684280e86df1e2cc2c9be291fa2807aa6cb02.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: Ze9XKNgkYDI4J5J-yQSpcAJjop9bR-Yg X-Proofpoint-GUID: Ze9XKNgkYDI4J5J-yQSpcAJjop9bR-Yg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 Separate filter type and decimation rate from the sampling frequency attribute. The new filter type attribute enables SINC3 and WIDEBAND filters, which were previously unavailable. Previously, combining decimation and MCLK divider in the sampling frequency obscured performance trade-offs. Lower MCLK divider settings increase power usage, while lower decimation rates reduce precision by decreasing averaging. By creating an oversampling attribute, which controls the decimation, users gain finer control over performance. The addition of those attributes allows a wider range of sampling frequencies and more access to the device features. Co-developed-by: PopPaul2021 Signed-off-by: PopPaul2021 Signed-off-by: Jonathan Santos --- v2 Changes: * Decimation_rate attribute replaced for oversampling_ratio. --- drivers/iio/adc/ad7768-1.c | 389 +++++++++++++++++++++++++++++++------ 1 file changed, 325 insertions(+), 64 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 01ccbe0aa708..6d0b430a8d54 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -5,6 +5,7 @@ * Copyright 2017 Analog Devices Inc. */ #include +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include "linux/util_macros.h" #include #include @@ -77,6 +79,10 @@ #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) +/* AD7768_SINC3_DEC_RATE */ +#define AD7768_SINC3_DEC_RATE_MSB_MSK GENMASK(12, 8) +#define AD7768_SINC3_DEC_RATE_LSB_MSK GENMASK(7, 0) + /* AD7768_REG_CONVERSION */ #define AD7768_CONV_MODE_MSK GENMASK(2, 0) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) @@ -97,6 +103,18 @@ #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) +/* Decimation Rate Limits */ +#define SINC5_DEC_RATE_MIN 8 +#define SINC5_DEC_RATE_MAX 1024 +#define SINC3_DEC_RATE_MIN 32 +#define SINC3_DEC_RATE_MAX 163840 +#define WIDEBAND_DEC_RATE_MIN 32 +#define WIDEBAND_DEC_RATE_MAX 1024 + +enum { + DEC_RATE, +}; + enum ad7768_conv_mode { AD7768_CONTINUOUS, AD7768_ONE_SHOT, @@ -118,22 +136,12 @@ enum ad7768_mclk_div { AD7768_MCLK_DIV_2 }; -enum ad7768_dec_rate { - AD7768_DEC_RATE_32 = 0, - AD7768_DEC_RATE_64 = 1, - AD7768_DEC_RATE_128 = 2, - AD7768_DEC_RATE_256 = 3, - AD7768_DEC_RATE_512 = 4, - AD7768_DEC_RATE_1024 = 5, - AD7768_DEC_RATE_8 = 9, - AD7768_DEC_RATE_16 = 10 -}; - -struct ad7768_clk_configuration { - enum ad7768_mclk_div mclk_div; - enum ad7768_dec_rate dec_rate; - unsigned int clk_div; - enum ad7768_pwrmode pwrmode; +enum ad7768_flt_type { + SINC5, + SINC5_DEC_X8, + SINC5_DEC_X16, + SINC3, + WIDEBAND }; enum ad7768_scan_type { @@ -145,18 +153,12 @@ static const int ad7768_mclk_div_rates[4] = { 16, 8, 4, 2, }; -static const struct ad7768_clk_configuration ad7768_clk_config[] = { - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, +static const int ad7768_dec_rate_values[6] = { + 32, 64, 128, 256, 512, 1024, +}; + +static const char * const ad7768_filter_enum[] = { + "sinc5", "sinc3", "wideband" }; static const struct iio_scan_type ad7768_scan_type[] = { @@ -176,12 +178,32 @@ static const struct iio_scan_type ad7768_scan_type[] = { }, }; +static int ad7768_get_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan); +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, unsigned int filter); + +static const struct iio_enum ad7768_flt_type_iio_enum = { + .items = ad7768_filter_enum, + .num_items = ARRAY_SIZE(ad7768_filter_enum), + .set = ad7768_set_fil_type_attr, + .get = ad7768_get_fil_type_attr, +}; + +static struct iio_chan_spec_ext_info ad7768_ext_info[] = { + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_flt_type_iio_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_flt_type_iio_enum), + { }, +}; + static const struct iio_chan_spec ad7768_channels[] = { { .type = IIO_VOLTAGE, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), - .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .ext_info = ad7768_ext_info, .indexed = 1, .channel = 0, .scan_index = 0, @@ -201,7 +223,9 @@ struct ad7768_state { struct gpio_chip gpiochip; unsigned int gpio_avail_map; unsigned int mclk_freq; - unsigned int dec_rate; + unsigned int mclk_div; + unsigned int oversampling_ratio; + enum ad7768_flt_type filter_type; unsigned int samp_freq; struct completion completion; struct iio_trigger *trig; @@ -223,6 +247,9 @@ struct ad7768_state { } data __aligned(IIO_DMA_MINALIGN); }; +static int ad7768_set_freq(struct ad7768_state *st, + unsigned int freq); + static int ad7768_spi_reg_read(void *context, unsigned int addr, unsigned int *val) { @@ -281,6 +308,31 @@ static int ad7768_send_sync_pulse(struct ad7768_state *st) return 0; } +static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div) +{ + unsigned int mclk_div_value; + int ret; + + guard(mutex)(&st->lock); + ret = ad7768_spi_reg_read(st, AD7768_REG_POWER_CLOCK, &mclk_div_value, 1); + if (ret) + return ret; + + mclk_div_value &= ~(AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK); + /* Set mclk_div value */ + mclk_div_value |= AD7768_PWR_MCLK_DIV(mclk_div); + /* + * Set power mode based on mclk_div value. + * ECO_MODE is only recommended for MCLK_DIV 16 + */ + if (mclk_div > AD7768_MCLK_DIV_16) + mclk_div_value |= AD7768_PWR_PWRMODE(AD7768_FAST_MODE); + else + mclk_div_value |= AD7768_PWR_PWRMODE(AD7768_ECO_MODE); + + return regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, mclk_div_value); +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -349,23 +401,183 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, return ret; } -static int ad7768_set_dig_fil(struct ad7768_state *st, - enum ad7768_dec_rate dec_rate) +static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, + unsigned int dec_rate) +{ + unsigned int dec_rate_msb, dec_rate_lsb, max_dec_rate; + int ret; + + guard(mutex)(&st->lock); + /* + * Maximum dec_rate is limited by the MCLK_DIV value + * and by the ODR. The edge case is for MCLK_DIV = 2 + * ODR = 50 SPS. + * max_dec_rate <= MCLK / (2 * 50) + */ + max_dec_rate = st->mclk_freq / 100; + dec_rate = clamp_t(unsigned int, dec_rate, 32, max_dec_rate); + /* + * Calculate the equivalent value to sinc3 decimation ratio + * to be written on the SINC3_DECIMATION_RATE register: + * Value = (DEC_RATE / 32) -1 + */ + dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1; + dec_rate_msb = FIELD_GET(AD7768_SINC3_DEC_RATE_MSB_MSK, dec_rate); + dec_rate_lsb = FIELD_GET(AD7768_SINC3_DEC_RATE_LSB_MSK, dec_rate); + + ret = regmap_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, dec_rate_msb); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_LSB, dec_rate_lsb); + if (ret) + return ret; + + st->oversampling_ratio = (dec_rate + 1) * 32; + + return 0; +} + +static int ad7768_set_dec_rate(struct ad7768_state *st, unsigned int dec_rate) { + unsigned int mode, dec_rate_reg; + int ret; + + dec_rate_reg = find_closest(dec_rate, ad7768_dec_rate_values, + ARRAY_SIZE(ad7768_dec_rate_values)); + + guard(mutex)(&st->lock); + ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); + if (ret) + return ret; + + mode &= ~AD7768_DIG_FIL_DEC_MSK; + mode |= AD7768_DIG_FIL_DEC_RATE(dec_rate_reg); + ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode); + if (ret) + return ret; + + st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_reg]; + + return 0; +} + +static int ad7768_set_filter_type(struct iio_dev *dev, + enum ad7768_flt_type filter_type) +{ + struct ad7768_state *st = iio_priv(dev); unsigned int mode; int ret; - if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) - mode = AD7768_DIG_FIL_FIL(dec_rate); - else - mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); + guard(mutex)(&st->lock); + ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); + if (ret) + return ret; + + mode &= ~AD7768_DIG_FIL_FIL_MSK; + mode |= AD7768_DIG_FIL_FIL(filter_type); ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode); if (ret < 0) return ret; - /* A sync-in pulse is required every time the filter dec rate changes */ - return ad7768_send_sync_pulse(st); + st->filter_type = filter_type; + + return 0; +} + +static int ad7768_configure_dig_fil(struct iio_dev *dev, + enum ad7768_flt_type filter_type, + unsigned int dec_rate) +{ + struct ad7768_state *st = iio_priv(dev); + int ret; + + if (filter_type == SINC3) { + ret = ad7768_set_filter_type(dev, SINC3); + if (ret) + return ret; + + /* recalculate the decimation for this filter mode */ + ret = ad7768_set_sinc3_dec_rate(st, dec_rate); + } else if (filter_type == WIDEBAND) { + ret = ad7768_set_filter_type(dev, filter_type); + if (ret) + return ret; + + /* recalculate the decimation rate */ + ret = ad7768_set_dec_rate(st, dec_rate); + } else { + /* For SINC5 filter */ + /* Decimation 8 and 16 are set in the digital filter field */ + if (dec_rate <= 8) { + ret = ad7768_set_filter_type(dev, SINC5_DEC_X8); + if (ret) + return ret; + + st->oversampling_ratio = 8; + } else if (dec_rate <= 16) { + ret = ad7768_set_filter_type(dev, SINC5_DEC_X16); + if (ret) + return ret; + + st->oversampling_ratio = 16; + } else { + ret = ad7768_set_filter_type(dev, SINC5); + if (ret) + return ret; + + ret = ad7768_set_dec_rate(st, dec_rate); + } + } + + return ret; +} + +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int filter) +{ + struct ad7768_state *st = iio_priv(dev); + int ret; + + /* + * Filters of types 0, 1, and 2 correspond to SINC5. + * For SINC3 and wideband filter types, an offset of 2 is added + * to align with the expected register values. + */ + if (filter != SINC5) + filter += 2; + + ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); + if (ret) + return ret; + + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); +} + +static int ad7768_get_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st = iio_priv(dev); + int ret; + unsigned int mode; + + ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); + if (ret) + return ret; + + mode = FIELD_GET(AD7768_DIG_FIL_FIL_MSK, mode); + /* Filter types from 0 to 2 are represented as SINC5 */ + if (mode < SINC3) + return SINC5; + + /* + * Remove the offset for the sinc3 and wideband filters + * to get the corresponding attribute enum value + */ + return mode - 2; } static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) @@ -490,43 +702,37 @@ static int ad7768_gpio_init(struct iio_dev *indio_dev) static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { - unsigned int diff_new, diff_old, pwr_mode, i, idx; + unsigned int diff_new, diff_old, i, idx; int res, ret; + freq = clamp_t(unsigned int, freq, 50, 1024000); diff_old = U32_MAX; idx = 0; - res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); + if (freq == 0) + return -EINVAL; + + res = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); /* Find the closest match for the desired sampling frequency */ - for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - diff_new = abs(res - ad7768_clk_config[i].clk_div); + for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + diff_new = abs(res - ad7768_mclk_div_rates[i]); if (diff_new < diff_old) { diff_old = diff_new; idx = i; } } - /* - * Set both the mclk_div and pwrmode with a single write to the - * POWER_CLOCK register - */ - pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | - AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); - ret = regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode); - if (ret < 0) - return ret; - - ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); - if (ret < 0) + /* Set both the mclk_div and pwrmode */ + ret = ad7768_set_mclk_div(st, idx); + if (ret) return ret; - st->dec_rate = ad7768_clk_config[idx].clk_div / - ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[idx].clk_div); + ad7768_mclk_div_rates[idx] * st->oversampling_ratio); - return 0; + /* A sync-in pulse is required every time the filter dec rate changes */ + return ad7768_send_sync_pulse(st); } static int ad7768_set_vcm_output(struct ad7768_state *st, unsigned int mode) @@ -540,13 +746,16 @@ static ssize_t ad7768_sampling_freq_avail(struct device *dev, { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ad7768_state *st = iio_priv(indio_dev); - unsigned int freq; + unsigned int freq, freq_filtered; int i, len = 0; - for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - freq = DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[i].clk_div); - len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); + freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio); + for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + freq = DIV_ROUND_CLOSEST(freq_filtered, + ad7768_mclk_div_rates[i]); + /* Sampling frequency cannot be lower than the minimum of 50 SPS */ + if (freq >= 50) + len += sysfs_emit_at(buf, len, "%d ", freq); } buf[len - 1] = '\n'; @@ -556,6 +765,37 @@ static ssize_t ad7768_sampling_freq_avail(struct device *dev, static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); +static ssize_t oversampling_ratio_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct ad7768_state *st = iio_priv(indio_dev); + int len = 0; + + /* Return oversampling ratio available in range format */ + buf[len++] = '['; + if (st->filter_type == SINC3) { + len += sysfs_emit_at(buf, len, "%d ", SINC3_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC3_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC3_DEC_RATE_MAX); + } else if (st->filter_type == WIDEBAND) { + len += sysfs_emit_at(buf, len, "%d ", WIDEBAND_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", WIDEBAND_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", WIDEBAND_DEC_RATE_MAX); + } else { + len += sysfs_emit_at(buf, len, "%d ", SINC5_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC5_DEC_RATE_MIN); + len += sysfs_emit_at(buf, len, "%d ", SINC5_DEC_RATE_MAX); } + + buf[len - 1] = ']'; + buf[len++] = '\n'; + + return len; +} + +static IIO_DEVICE_ATTR_RO(oversampling_ratio_available, 0); + static int ad7768_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -597,6 +837,11 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_SAMP_FREQ: *val = st->samp_freq; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val = st->oversampling_ratio; + return IIO_VAL_INT; } @@ -608,10 +853,19 @@ static int ad7768_write_raw(struct iio_dev *indio_dev, int val, int val2, long info) { struct ad7768_state *st = iio_priv(indio_dev); + int ret; switch (info) { case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_freq(st, val); + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret = ad7768_configure_dig_fil(indio_dev, st->filter_type, val); + if (ret) + return ret; + + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); default: return -EINVAL; } @@ -627,6 +881,7 @@ static int ad7768_read_label(struct iio_dev *indio_dev, static struct attribute *ad7768_attributes[] = { &iio_dev_attr_sampling_frequency_available.dev_attr.attr, + &iio_dev_attr_oversampling_ratio_available.dev_attr.attr, NULL }; @@ -639,7 +894,7 @@ static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, { struct ad7768_state *st = iio_priv(indio_dev); - return st->dec_rate == 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : + return st->oversampling_ratio == 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; } @@ -745,6 +1000,12 @@ static int ad7768_setup(struct iio_dev *indio_dev) return ret; } + /* + * Set Default Digital Filter configuration: + * SINC5 filter with x32 Decimation rate + */ + ret = ad7768_configure_dig_fil(indio_dev, SINC5, 32); + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } From patchwork Mon Jan 27 15:14:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Santos X-Patchwork-Id: 13951541 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FAA714A630; Mon, 27 Jan 2025 15:14:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; 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Mon, 27 Jan 2025 10:14:44 -0500 (EST) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 50RFEhnC011128 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Jan 2025 10:14:43 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Mon, 27 Jan 2025 10:14:43 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Mon, 27 Jan 2025 10:14:43 -0500 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 50RFEWPk008470; Mon, 27 Jan 2025 10:14:34 -0500 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH v2 16/16] iio: adc: ad7768-1: add low pass -3dB cutoff attribute Date: Mon, 27 Jan 2025 12:14:31 -0300 Message-ID: <91b697b66a42ead9e05dd4e79d6fb1e776c569d6.1737985435.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: YKygPqYe-rc38pZs783o70mI8dS4A2yp X-Proofpoint-GUID: YKygPqYe-rc38pZs783o70mI8dS4A2yp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-27_07,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501270121 Ad7768-1 has a different -3db frequency multiplier depending on the filter type configured. The cutoff frequency also varies according to the current ODR. Add a readonly low pass -3dB frequency cutoff attribute to clarify to the user which bandwidth is being allowed depending on the filter configurations. Signed-off-by: Jonathan Santos --- v2 Changes: * New patch in v2. --- drivers/iio/adc/ad7768-1.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 6d0b430a8d54..daf91ef6f77b 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -149,6 +149,18 @@ enum ad7768_scan_type { AD7768_SCAN_TYPE_HIGH_SPEED, }; +/* + * -3dB cutoff frequency multipliers (relative to ODR) for + * each filter type. Values are multiplied by 1000. + */ +static const int ad7768_filter_3db_odr_multiplier[] = { + [SINC5] = 204, + [SINC5_DEC_X8] = 204, + [SINC5_DEC_X16] = 204, + [SINC3] = 261, + [WIDEBAND] = 433, +}; + static const int ad7768_mclk_div_rates[4] = { 16, 8, 4, 2, }; @@ -202,7 +214,8 @@ static const struct iio_chan_spec ad7768_channels[] = { .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), .ext_info = ad7768_ext_info, .indexed = 1, .channel = 0, @@ -802,7 +815,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, { struct ad7768_state *st = iio_priv(indio_dev); const struct iio_scan_type *scan_type; - int scale_uv, ret; + int scale_uv, ret, temp; scan_type = iio_get_current_scan_type(indio_dev, chan); if (IS_ERR(scan_type)) @@ -842,6 +855,12 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *val = st->oversampling_ratio; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type]; + *val = DIV_ROUND_CLOSEST(temp, 1000); + return IIO_VAL_INT; }