From patchwork Tue Jan 28 12:00:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952483 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6867F19D8AC; Tue, 28 Jan 2025 12:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065696; cv=none; b=VmgCnkrdUDNOPHDKqaEYhe4ekzPxBAK9OLXqiV5Fu1iHFdxMTZlc8F0mUZyhu4MmCgLqUmY8Ix4GPLGvKeOf+nR+/pTtVM7+BgW1v02UCotoHtFRU/vZyoQsj6R6Pio/6Ht+hPWEV4ICGJbzU2ZiLy7BjodVNKMVWjsm+h6julM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065696; c=relaxed/simple; bh=A6D/dIr0/roT1Guo5HT4UUonoFll5nlYZUMj5aI4+Qs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uuDMADKx3EvSVf0hjTp2RbRvOKIqb7NV1iu0QBqXhOZ3IP6f/3lZzGZ10M4Np5gTcWuLbLL5o1c/CeGWPcpiFsJ/jjzSaIV9hERTs1obzYbBc7Xp16mF2lTfRN3uzsDHuoOWV1JMsUkf3fllmrWpXyOZlT1E5yOSdpktZUYWrQA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JyR1UtDf; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JyR1UtDf" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5db67d1bf0bso1487293a12.0; Tue, 28 Jan 2025 04:01:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065693; x=1738670493; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gfLycUoqALpenZs1PCwcqht3zj/rDndi4N2W7Tr/X5g=; b=JyR1UtDf4LKradl403ZoNur3BYRVD1sPhn43uOU9DmhNWIIRLqTRiGgN/d4+tF0M9R FL/KvyYDlaYPnRh0xpXqDSvu3bzDAeyhjWJ8I3uVvop0uDFZ0klvd2Dfj7axey5sXakP fcw9HJCCr9af6UEgdUBWWqRImJP4F6sYfpvogxfyH1uQKhGUc5Nz2SaLvejhl78mMF0+ 17N7t6ULboQlGfXGJGq/av5j1NLxLqIxaanpcnx6vqe0mR2N5orSdNEPCaer9J0dFCH7 iw84t7LAS3rScQYdWQ/LNXL8vSx2ExUnpLkX7X04MWbNUpH5g0/g6vI8UeRiaVNYTCEU qSFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065693; x=1738670493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gfLycUoqALpenZs1PCwcqht3zj/rDndi4N2W7Tr/X5g=; b=PhjPcwXcqXfxf3AdYJv/8IA8yvMWdvUsNDCg3Q5g0tSoG5ZamAmCvo1cGbH7MsbS1r d2MFhp1GXF1r1DqyumF/0odGUb15gNDd1vIAFUhJRfTAJ7fYiloUKQ82tKrxLeKxsNHt dVHI2kIzJG5QTz0dCxdGAnwFiuWAi7SYEMJvpJW0QctxAMBANd8IBvUFjzjMuwgWmp3f E8vecqbeH3In1aABxHYJJJrt4uvA1uX6fSakDctyUqJSiblayHCQwyU8b1aaEqNGKcjy NN2cicqQlnRbyE5grxwe+j/4pBkXKBhxQK7A1y9VPKuDhyck8gTE32CUEDCAKOXAQPFT sYEQ== X-Forwarded-Encrypted: i=1; AJvYcCUDgZPiD3yEuS6+cwr86Et52Ipq3OVQaehUU+DnMFE5dU9ff0nJUDnD0er7fGB5YxLtk457rgRMzdC2/qw=@vger.kernel.org X-Gm-Message-State: AOJu0YwCEkNf5bKbxwuqQgJIItkBgItzTY7hZJguPszhFVjBbRy/nfxc VZTuQmTTDBVUwa4Te/30qA87QNHfk1VtJ0G3h+Rqg9aLLCOrDO4F X-Gm-Gg: ASbGncv1vNjlvMDmWuGWRI1gpKv2YJqKKFM0/bvAPs+AeDtDLNxVI2yIvDR8+cU22Nf qQL6kN2qmWi3coo0LCipUQA/mI6Sff7FNiM+wb/2uoniXEcxU7T8U8nTxyKxHAV/6EsEnSrchSE o5fIhNUBemQ8L8GI5CNPsSQhEc/rP41AD36E7wrqRYqbhB09NgQr/5QRGVOb2oXgVPz4BEMRVHa UqlZlw8jLe7tru4QsUr13DqXRIgcGLvnpECdy9b+NQZ8X1NgRr1XkDctSe9pMm/46HAImjpYyoY pg+gClvIz2qWKUAezOuPxssW2P/hidXCZXxrb+qjd6WRFEGj4DYN62ecuPohTx6ux58Ayg== X-Google-Smtp-Source: AGHT+IEPSEyamTIjx/62Tk90uhAgRgiRetjPvgDhLOHVt+lqH5u7gpw5a3DIeL3Cl1F3SURJgos46w== X-Received: by 2002:a17:907:948a:b0:aa6:6792:8bce with SMTP id a640c23a62f3a-ab38b1b6f43mr1423097966b.3.1738065692393; Tue, 28 Jan 2025 04:01:32 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:31 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 01/12] iio: accel: adxl345: migrate constants to core Date: Tue, 28 Jan 2025 12:00:49 +0000 Message-Id: <20250128120100.205523-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The set of constants does not need to be exposed. Move constants to core to reduce namespace polution. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 86 ------------------------------ drivers/iio/accel/adxl345_core.c | 91 +++++++++++++++++++++++++++++++- 2 files changed, 89 insertions(+), 88 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index 517e494ba555..b5257dafb742 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -8,94 +8,8 @@ #ifndef _ADXL345_H_ #define _ADXL345_H_ -#define ADXL345_REG_DEVID 0x00 -#define ADXL345_REG_THRESH_TAP 0x1D -#define ADXL345_REG_OFSX 0x1E -#define ADXL345_REG_OFSY 0x1F -#define ADXL345_REG_OFSZ 0x20 -#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) - -/* Tap duration */ -#define ADXL345_REG_DUR 0x21 -/* Tap latency */ -#define ADXL345_REG_LATENT 0x22 -/* Tap window */ -#define ADXL345_REG_WINDOW 0x23 -/* Activity threshold */ -#define ADXL345_REG_THRESH_ACT 0x24 -/* Inactivity threshold */ -#define ADXL345_REG_THRESH_INACT 0x25 -/* Inactivity time */ -#define ADXL345_REG_TIME_INACT 0x26 -/* Axis enable control for activity and inactivity detection */ -#define ADXL345_REG_ACT_INACT_CTRL 0x27 -/* Free-fall threshold */ -#define ADXL345_REG_THRESH_FF 0x28 -/* Free-fall time */ -#define ADXL345_REG_TIME_FF 0x29 -/* Axis control for single tap or double tap */ -#define ADXL345_REG_TAP_AXIS 0x2A -/* Source of single tap or double tap */ -#define ADXL345_REG_ACT_TAP_STATUS 0x2B -/* Data rate and power mode control */ -#define ADXL345_REG_BW_RATE 0x2C -#define ADXL345_REG_POWER_CTL 0x2D -#define ADXL345_REG_INT_ENABLE 0x2E -#define ADXL345_REG_INT_MAP 0x2F -#define ADXL345_REG_INT_SOURCE 0x30 -#define ADXL345_REG_INT_SOURCE_MSK 0xFF #define ADXL345_REG_DATA_FORMAT 0x31 -#define ADXL345_REG_XYZ_BASE 0x32 -#define ADXL345_REG_DATA_AXIS(index) \ - (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) - -#define ADXL345_REG_FIFO_CTL 0x38 -#define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0) -/* 0: INT1, 1: INT2 */ -#define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5) -#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6) -#define ADXL345_REG_FIFO_STATUS 0x39 -#define ADXL345_REG_FIFO_STATUS_MSK 0x3F - -#define ADXL345_INT_OVERRUN BIT(0) -#define ADXL345_INT_WATERMARK BIT(1) -#define ADXL345_INT_FREE_FALL BIT(2) -#define ADXL345_INT_INACTIVITY BIT(3) -#define ADXL345_INT_ACTIVITY BIT(4) -#define ADXL345_INT_DOUBLE_TAP BIT(5) -#define ADXL345_INT_SINGLE_TAP BIT(6) -#define ADXL345_INT_DATA_READY BIT(7) - -/* - * BW_RATE bits - Bandwidth and output data rate. The default value is - * 0x0A, which translates to a 100 Hz output data rate - */ -#define ADXL345_BW_RATE GENMASK(3, 0) -#define ADXL345_BW_LOW_POWER BIT(4) -#define ADXL345_BASE_RATE_NANO_HZ 97656250LL - -#define ADXL345_POWER_CTL_STANDBY 0x00 -#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0) -#define ADXL345_POWER_CTL_SLEEP BIT(2) -#define ADXL345_POWER_CTL_MEASURE BIT(3) -#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4) -#define ADXL345_POWER_CTL_LINK BIT(5) - -/* Set the g range */ -#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) -/* Data is left justified */ -#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) -/* Up to 13-bits resolution */ -#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) #define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) -#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) -#define ADXL345_DATA_FORMAT_2G 0 -#define ADXL345_DATA_FORMAT_4G 1 -#define ADXL345_DATA_FORMAT_8G 2 -#define ADXL345_DATA_FORMAT_16G 3 - -#define ADXL345_DEVID 0xE5 -#define ADXL345_FIFO_SIZE 32 /* * In full-resolution mode, scale factor is maintained at ~4 mg/LSB diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index ed0291bea0f5..ffdb03ed7a25 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -14,13 +14,100 @@ #include #include -#include -#include #include +#include #include +#include #include "adxl345.h" +#define ADXL345_REG_DEVID 0x00 +#define ADXL345_REG_THRESH_TAP 0x1D +#define ADXL345_REG_OFSX 0x1E +#define ADXL345_REG_OFSY 0x1F +#define ADXL345_REG_OFSZ 0x20 +#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) + +/* Tap duration */ +#define ADXL345_REG_DUR 0x21 +/* Tap latency */ +#define ADXL345_REG_LATENT 0x22 +/* Tap window */ +#define ADXL345_REG_WINDOW 0x23 +/* Activity threshold */ +#define ADXL345_REG_THRESH_ACT 0x24 +/* Inactivity threshold */ +#define ADXL345_REG_THRESH_INACT 0x25 +/* Inactivity time */ +#define ADXL345_REG_TIME_INACT 0x26 +/* Axis enable control for activity and inactivity detection */ +#define ADXL345_REG_ACT_INACT_CTRL 0x27 +/* Free-fall threshold */ +#define ADXL345_REG_THRESH_FF 0x28 +/* Free-fall time */ +#define ADXL345_REG_TIME_FF 0x29 +/* Axis control for single tap or double tap */ +#define ADXL345_REG_TAP_AXIS 0x2A +/* Source of single tap or double tap */ +#define ADXL345_REG_ACT_TAP_STATUS 0x2B +/* Data rate and power mode control */ +#define ADXL345_REG_BW_RATE 0x2C +#define ADXL345_REG_POWER_CTL 0x2D +#define ADXL345_REG_INT_ENABLE 0x2E +#define ADXL345_REG_INT_MAP 0x2F +#define ADXL345_REG_INT_SOURCE 0x30 +#define ADXL345_REG_INT_SOURCE_MSK 0xFF +#define ADXL345_REG_XYZ_BASE 0x32 +#define ADXL345_REG_DATA_AXIS(index) \ + (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) + +#define ADXL345_REG_FIFO_CTL 0x38 +#define ADXL345_FIFO_CTL_SAMPLES_MSK GENMASK(4, 0) +/* 0: INT1, 1: INT2 */ +#define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5) +#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6) +#define ADXL345_REG_FIFO_STATUS 0x39 +#define ADXL345_REG_FIFO_STATUS_MSK 0x3F + +#define ADXL345_INT_OVERRUN BIT(0) +#define ADXL345_INT_WATERMARK BIT(1) +#define ADXL345_INT_FREE_FALL BIT(2) +#define ADXL345_INT_INACTIVITY BIT(3) +#define ADXL345_INT_ACTIVITY BIT(4) +#define ADXL345_INT_DOUBLE_TAP BIT(5) +#define ADXL345_INT_SINGLE_TAP BIT(6) +#define ADXL345_INT_DATA_READY BIT(7) + +/* + * BW_RATE bits - Bandwidth and output data rate. The default value is + * 0x0A, which translates to a 100 Hz output data rate + */ +#define ADXL345_BW_RATE GENMASK(3, 0) +#define ADXL345_BW_LOW_POWER BIT(4) +#define ADXL345_BASE_RATE_NANO_HZ 97656250LL + +#define ADXL345_POWER_CTL_STANDBY 0x00 +#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0) +#define ADXL345_POWER_CTL_SLEEP BIT(2) +#define ADXL345_POWER_CTL_MEASURE BIT(3) +#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4) +#define ADXL345_POWER_CTL_LINK BIT(5) + +/* Set the g range */ +#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) +/* Data is left justified */ +#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) +/* Up to 13-bits resolution */ +#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) +#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) +#define ADXL345_DATA_FORMAT_2G 0 +#define ADXL345_DATA_FORMAT_4G 1 +#define ADXL345_DATA_FORMAT_8G 2 +#define ADXL345_DATA_FORMAT_16G 3 + +#define ADXL345_DEVID 0xE5 +#define ADXL345_FIFO_SIZE 32 + #define ADXL345_FIFO_BYPASS 0 #define ADXL345_FIFO_FIFO 1 #define ADXL345_FIFO_STREAM 2 From patchwork Tue Jan 28 12:00:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952484 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A57491A2391; Tue, 28 Jan 2025 12:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065697; cv=none; b=lFmWjXGpF6plS/cJhqxk6/UKESJGYHyQQxuKFZJXrOY+v515d4zTMKLMoVBVHdMGQtVrmMYqN/kNLqDPOwlrDpIWjYALd1iUqUb6ZzHj8tQF++ofXZq8BZBo7Ae6g9WaFqvLbUFahQtTOLEM+2FjZ7RpSzkUQGw5c3KyLQfnz34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065697; c=relaxed/simple; bh=32pxGww22uXNRSE1h4GEPFMYm4JjozUP+kLSK2TuVGU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qDZ7zDqXXbNu/u0wntLmBzCgLBLLx3oQd8X11qFVd1HNGXI+itMHD3bXZ2CJh7KN+P26UnkCKL6KddYuAJYpV2AoA0spTSpdx+SaJM/gLV7SeAm5KcLf2McbSoc9i4wUD7c67owebUkT76/Zfef9sVmarvnvzCtMJly8hxxXD/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=I4mBYaGJ; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I4mBYaGJ" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-5dbf7d45853so1281251a12.1; Tue, 28 Jan 2025 04:01:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065694; x=1738670494; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iy4p7JxJyU0LbLEs05esQZqH8h+c7Oo1QTLQ6nSQRv8=; b=I4mBYaGJEykNjEh4xr/1gfiHEuwbLBTNeOwPiz9nCCG+OsFTjdlU7OgbO7xSR+GA6l h3WvptPz6VDr9R91TyATEU7YsN1viS1ddniMtmU0wcqoiFGlx7EJn3t93YJ3h+hn4VkN Dbkq1DJxtgzwhDKvU1Lkz8RmU+mdqleWygqtIRJWYuYk6KWvYVsTTOLN222sjSqhm7ft 9xCoAW88AjlHIY4KJp9nd9zlePK0rztUSyZJ3mDFGMosMS4r+QQ3eOA8jD4TJg/YGbOw 8Yn0uOwiPaqTmddHWvCGMcN93bxDJax4XXSdELWRJgihZruBUTsFoNmPsh+Xe2lXaE7l 4wlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065694; x=1738670494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iy4p7JxJyU0LbLEs05esQZqH8h+c7Oo1QTLQ6nSQRv8=; b=DWp1rJz3hIvqWG1fWzKhmTR+m/LiPISt+65jiHPqsz+xuERgAFEZT9OlIgrQu6yH4E 0PLYXMXVGkEVo3w8TBZiCG2VN18sK6GGh6aOn1TtlRBZ6ChFvOJfqErEd/3ksL6/9Bp7 QzrjvJT+vCe7h69vGcFIjNlcjs9ZhfLIjQteeNspp48mjYLWhv6uIRt9nBcGJXJDQAOK Xbn0HokvlQ070qRbXOCKqndKmy1xu80s/hL3BkQHrGRznWgggDq4ZjENKU3JYb7HnxDd 8waqz+mMD9QH5CIo2rUBkzuEhDBmjwcrte1G7HoS0YbJPq6r8N2e9FX/RIxATlRgewJp 6Inw== X-Forwarded-Encrypted: i=1; AJvYcCUwkFWfnqDt9BYyD/zLa38CCx07qducJzsD+HGjJp9DONqLLH13ERoobN2aSC0G6YDMQkM/cNSUTuSmqnY=@vger.kernel.org X-Gm-Message-State: AOJu0YzabJNJhoBQdAh0ehXWbbkpaF3Q6KGJ/KCUR7jcm8wLu+Qy/ofr tXwPdiOVC0RjNm2duPbYYWMW09UB/LAOX3kp6vW1FS7r5fohaMp5 X-Gm-Gg: ASbGncuvN/SdU08+aVRDWoAxeL690OXwlM67sOx7tBHObswwo4Z6n2pUubfExxHQH30 fK24Yc8BISK/ifYWS4Ln/LiXF966SB0I0Ht2O6XLO8Uuqxj7UCXsnzNzOA8FSAvAYEZobY5j26X aVA84VZsRT9OXUUPN1eGJPGqRQjjSDDgzEZZ/hgHGGSY9Y7ouLHnI598U0DwKZCzgq6ALjHmHPa 2WfbLPpVisBp5LGsmxAaJNK33v3WuYNYdrKuwZe2ya4sPltmfGx70A5szvl656Ed8DuZRJTQaqv UQa7X7opZQTDDYQDC3CYjU2SAqYjqdPdWY+w0tYevt+HcgsmZ3QuHeqNfZoo43VQsWlxvg== X-Google-Smtp-Source: AGHT+IEKXV7QElYUwfDqVcH7rzpBecIFcCv5h8XU4S7HREeyCDvE9mj6Omi5cxRHVFagSHCjM2dc5Q== X-Received: by 2002:a17:907:9715:b0:ab6:b8e0:4f25 with SMTP id a640c23a62f3a-ab6b8e05026mr150998666b.4.1738065693484; Tue, 28 Jan 2025 04:01:33 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:33 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 02/12] iio: accel: adxl345: reorganize measurement enable Date: Tue, 28 Jan 2025 12:00:50 +0000 Message-Id: <20250128120100.205523-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In order to have this function generically available a position at the top makes more sense. In upcomming patches for particular features the function needs to be available, to turn off measuring while changing settings, and turn it on again afterwards. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 54 ++++++++++++++++---------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index ffdb03ed7a25..142f12117627 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -163,6 +163,33 @@ static const unsigned long adxl345_scan_masks[] = { 0 }; +/** + * adxl345_set_measure_en() - Enable and disable measuring. + * + * @st: The device data. + * @en: Enable measurements, else standby mode. + * + * For lowest power operation, standby mode can be used. In standby mode, + * current consumption is supposed to be reduced to 0.1uA (typical). In this + * mode no measurements are made. Placing the device into standby mode + * preserves the contents of FIFO. + * + * Return: Returns 0 if successful, or a negative error value. + */ +static int adxl345_set_measure_en(struct adxl345_state *st, bool en) +{ + unsigned int val = en ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; + + return regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); +} + +static void adxl345_powerdown(void *ptr) +{ + struct adxl345_state *st = ptr; + + adxl345_set_measure_en(st, false); +} + static int adxl345_set_interrupts(struct adxl345_state *st) { int ret; @@ -301,33 +328,6 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } } -/** - * adxl345_set_measure_en() - Enable and disable measuring. - * - * @st: The device data. - * @en: Enable measurements, else standby mode. - * - * For lowest power operation, standby mode can be used. In standby mode, - * current consumption is supposed to be reduced to 0.1uA (typical). In this - * mode no measurements are made. Placing the device into standby mode - * preserves the contents of FIFO. - * - * Return: Returns 0 if successful, or a negative error value. - */ -static int adxl345_set_measure_en(struct adxl345_state *st, bool en) -{ - unsigned int val = en ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; - - return regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); -} - -static void adxl345_powerdown(void *ptr) -{ - struct adxl345_state *st = ptr; - - adxl345_set_measure_en(st, false); -} - static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200" ); From patchwork Tue Jan 28 12:00:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952486 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CBAF1A3042; Tue, 28 Jan 2025 12:01:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065700; cv=none; b=R47fldp+qafMm/IPe85VrL/eAbZ54xORzi8TdMEcpad9pvbE1fLtHGZRjuNYIYuVLotdqv+2syrpyVurX2XAN7iPxRSyD+SUoyPArOS1PoyjWn6665MT+HeBGXeJe1D1utksw/vBg7IxjdpRBFXzUhWXPncWFNFHMYOK8yAHgdM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065700; c=relaxed/simple; bh=dBVzk9hpS+UwdX5RwEmeSkQwWEzS04gHxTdHrRzaNPk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=epk5YmsiTUpfxnfOnDIIfyvJmeC+FRjQu6KVyN80GcY5cP28AN5NnmGeB+zrm3ngVPY4aflQmSaTAYsfGoP2X1sli6Xti7UQ5lchvSZPO+5/XvmncLCf/ujSYrfyWThHFwgSukpX9F1DdLmuZVifZJL5w7tlVKbv96aNGc9nKSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e0Ug9L4E; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e0Ug9L4E" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-aa6965ad2a5so82411966b.3; Tue, 28 Jan 2025 04:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065696; x=1738670496; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uXjpe3fdaVYUZIdxmPyTXbc7YGYYpIRM9KhUQttLI4Q=; b=e0Ug9L4Es8SOxy5L1VJT/IcpQj6d4Vzmi4IKcGCrdXwZBN01WMVkRjEXr6J0kU1eOh 7bHtMfdlPckoWOfn4+2Zqtent6GWBFV+ZPCe5IOOSuVDER2lCQkB2joCwsg3AyjUNq55 O7o5UXknRRF8d5TzTr76P4j6FyjBbVqw9VJzrZXeyxTcm821YqzQzJQubf2EVwCx+iHO mslbXIWh0m+YpJdLylbwIECWg/Ytm1U92tE90mLcBWOKlmva4X645BWhqnMtD/HAf9Wd E6eJLLJjK6VTJAmp9OFcATvyTSYRtoin7CDMxfdVUm5v6ZFko4bRSg8GZs8AQZt/I6+j /5mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065696; x=1738670496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uXjpe3fdaVYUZIdxmPyTXbc7YGYYpIRM9KhUQttLI4Q=; b=dpE6j7r6O+lSEUDlA2uh1cgsWWiKyrpfufDacw0gvLyIk6D4nY2hM74lpILl//kHZP jkISiAXVak2+n3yQBM3sI0a/eRkmmygKnYmVbnJpsEbiSJ2Cp+XU1hdesdcKzhgutImn 4Gkn8BCugkSpZrNarW8fL1WHVfHuQ9bv01VBoLncHPnMHu76yDsYA4vy6KXEQTHGb1/m bt6cEzhHeyC3vG7wePJgIXdaXGWGcALNeQiloqrkuaDHn+G+EZpkMPJmpEzrzvLd8YMP giXqgg3kF/q9Dv2Lj4O/iZVEWEj78xZVx9l2hvqI0L37N8tyjEUTUP9Yu5eubDn2NMQC CKAg== X-Forwarded-Encrypted: i=1; AJvYcCXKV0AoJcZItSXlvqodMNWtPmFWe3EL948yr6GZ9mi+iTfUrwEZF8cKQkiQ/MT9GS+PR5fQNtrF0OTcUKI=@vger.kernel.org X-Gm-Message-State: AOJu0Ywuaawak96wlS/Y4IQVb9UXEJ2KmK/mzndBnTLTRTCbAc2dDmZW jk7t98CYPHjS2n4KHW+5ZLlSHWEZGfgLUhOFcEzq0t5u1nioD27O X-Gm-Gg: ASbGncsJ3bRMvebxyL92N1sUO+iJ49PPDbvGLmno/AXgyYgB2cF2AX7y6yI1QjbD5qI Mmx0k+Nhhq8kdJs+YijtfeNfPTtbdrLfJ1r6iSwMB4t3KPsgt/gO9mX1kh1Pm7qDhDpPlIjefuj cqmlxCaSEaa2S5SZ2qOV17JM6v4nUyFUn424upJDwjcamZcR3R83QY8Yt2i32AA+odce2p9ntsq 9/EsnQg5SasgWKFf02ODcAnNZXLY0QB6ESbsLVqqCUAevtS1855PeSe/s7sjhPb7+KXMk128/Fi 2nNVyQ/KeqgKSN57m2Iq1hwCT7qPE7No95wY25IOkNNgOHb16yeQxsgiUBVIzQmqVFB95A== X-Google-Smtp-Source: AGHT+IEsGujAU1z3cAxFE6HXz7YLuwMRuX3pcGJLWuJuW1BwVE4LJW7difJXbk1tWpgFp1WSBWNyew== X-Received: by 2002:a17:907:969f:b0:ab3:2719:ca30 with SMTP id a640c23a62f3a-ab38b35c602mr1760114366b.10.1738065694527; Tue, 28 Jan 2025 04:01:34 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:34 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 03/12] iio: accel: adxl345: add debug register access Date: Tue, 28 Jan 2025 12:00:51 +0000 Message-Id: <20250128120100.205523-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the possibility to verify the content of the configuration registers of the sensor in preparation for upcomming feature implementations. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 142f12117627..8fbf0a43746f 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -296,6 +296,16 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int adxl345_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct adxl345_state *st = iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + return regmap_write(st->regmap, reg, writeval); +} + static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int value) { struct adxl345_state *st = iio_priv(indio_dev); @@ -554,6 +564,7 @@ static const struct iio_info adxl345_info = { .read_raw = adxl345_read_raw, .write_raw = adxl345_write_raw, .write_raw_get_fmt = adxl345_write_raw_get_fmt, + .debugfs_reg_access = &adxl345_reg_access, .hwfifo_set_watermark = adxl345_set_watermark, }; From patchwork Tue Jan 28 12:00:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952485 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AA1A1A2642; Tue, 28 Jan 2025 12:01:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065699; cv=none; b=V8L/nZwfMGcUTNTmd4ZDWg8mPYlPLqujNPXR/JBA6AUXHQTPaYjPjfTWEcXm64/5Ri3aVkPeT1ovTEKdGzEjPIvtYAyszZLb3abL9m3ncUvxrofHmKxuYfUzBO286xuBYjZQUB5DprsVl40YBzq2tGgLWbZFQvu7zzequOqdAyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065699; c=relaxed/simple; bh=ZFz+bNWBdxFwKvj5JBvO3WzvviDOLiFHaUfL5nFMdWk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GWfSRTqg4zatOBTLB+Il1OmtcPI0kT0IfCKyeZTo4+yl9YyVpiykH4tAs8Vp0LePtWm8sQykAytAA8+4PeSpOyXqJUTHivYVxArreabPkUfu6lCL+9aRRd38juEX/DFBF9A/7JoLlmcSSRQed4U2Q6ouX5tzx8AX//KC2lRYpts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bTAsiK8N; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bTAsiK8N" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-5dbe706f94fso1294765a12.2; Tue, 28 Jan 2025 04:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065696; x=1738670496; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NSksiAWnSWBTZBpd0M1uNpje3o8Xf8ZMdfKn4UpGQtU=; b=bTAsiK8N5NKSN0dz7eIWbJxR/L4xIX6+fzwFv7gNHJob9vLK17q+IRo+nZRC+a0Fu9 l6RXFgbBhXWmn6exSaFCBJp4bDY4uDjsOJ20afHWBpsR//1m6StH5+8Y78JM2uPacteB bVYf+v6ACm+LWjri9tTt+8UL3A37S1gCk1/vPIU0aXdTZPizPM/0rABfqw8eYh0nWMIF 0hCVROOjw5ARPKxFRS9h0qm379kQqNnSPvDCArTwD5v244DqYPK2eV4xQ0F86744tQdN IyWch4whdJS20fIXxkk4C+BX5/BXuX4eppPijr6p+UuutAq71pGWFguyrL9VeCNm1j6o aMlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065696; x=1738670496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NSksiAWnSWBTZBpd0M1uNpje3o8Xf8ZMdfKn4UpGQtU=; b=sxMcFzdZwQp/x9gunaC+v4jYyvQg3YvgEogD4FsNaN667fHS8SjdFB3R0rvnZBI28j gGxaGmcq+06m5s2qNCEFKVcZx4b4Ab1rRv6+whs+Tr4z+xITBFwZ5U3kgk1uAH5VX0S7 kd/k+nLwLHk1pvMd/tbcnIVYIiRwzg+y6tdVwzm+zFD7tROrD7ylo7jdK20jyytCP0/Y df6WAUSPQRO+rd4CGmeUPPd6YsWB//G+5mtAT5ntUbt3GXjdmAGX6Wj1+wENhQGUC1Fv qAHtipXCj/3ftrdQjmrvX2F5kDu5HfqDFlnip6lIA6rGulDa2tj0mxIRMBzKJPyMtDCb weTg== X-Forwarded-Encrypted: i=1; AJvYcCVD9Q8SRcmFKvX21ruYW5SjWoKxxTNAY22woZA8iJE/T1lO38xx2DCEbaRyF2dyJpsdx33wc37UgJlAMxA=@vger.kernel.org X-Gm-Message-State: AOJu0Yy30eh47+rL791Nl2LLikZYl36bT7jESlgmww4aPpA5CF+tFwqD S/0k7NHlS5l4Yhy7sblpBhwezpZubIuyFBOPPsNnH1FTdWMDk0gr X-Gm-Gg: ASbGncurqVcl+9GXo6Sj2wXTikaTFUynDWY6LTTN6unfTDNV9hpSL5gE/BY9i0SLxsC Z3u+zdMY8V/sLuVzh6Krhi6utWpX/qBHfZG+Xv3JEEmQ8jWvOyr7oaT3mAecMadbEoz7ENR6enG 2F9crzOUjtZw2ECXvcoH3t5z8Ifh5Ltx2gAfBshLAyMdNz4QFYuL2dHHQY/qgo8vrWmFQF3ZF9L Q0pRrh5IvL5dJI2Cyv0a7mA6Ygm8UVjtMTRUIGasra9L+ydIxQh1lS/EeOqApYOysveJdXP81f1 R+YX1D5EC4CK1vHACTGIeVCAFKLbPlkKaKXX5qO7HTPZi9lIl4Zi7ssCMxYZrs/XNpvWSA== X-Google-Smtp-Source: AGHT+IHA9mxdm48PiQgAzgx9xYQ6pmLui4qTn/LtbVMF20kQadgBYdTwi8ZbGp7T+Psix4WfCtQB2A== X-Received: by 2002:a17:907:948a:b0:aa6:6792:8bce with SMTP id a640c23a62f3a-ab38b1b6f43mr1423110066b.3.1738065695477; Tue, 28 Jan 2025 04:01:35 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:35 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 04/12] iio: accel: adxl345: reorganize irq handler Date: Tue, 28 Jan 2025 12:00:52 +0000 Message-Id: <20250128120100.205523-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Reorganize the IRQ handler. Move the overrun handling to the bottom. Overrun leads to reset the interrupt register. This also happens at evaluation of a particular interrupt event. So, actually it makes more sense to evaluate the event if possible, and only fall back to pure overrun handling as a last resort. Further simplify fetching the interrupt status function. Both is in preparation to build interrupt handling up for the handling of different detected events, implemented in follow up patches. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 8fbf0a43746f..7ee50a0b23ea 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -491,16 +491,9 @@ static const struct iio_buffer_setup_ops adxl345_buffer_ops = { .predisable = adxl345_buffer_predisable, }; -static int adxl345_get_status(struct adxl345_state *st) +static int adxl345_get_status(struct adxl345_state *st, unsigned int *int_stat) { - int ret; - unsigned int regval; - - ret = regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); - if (ret < 0) - return ret; - - return FIELD_GET(ADXL345_REG_INT_SOURCE_MSK, regval); + return regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, int_stat); } static int adxl345_fifo_push(struct iio_dev *indio_dev, @@ -536,14 +529,10 @@ static irqreturn_t adxl345_irq_handler(int irq, void *p) int int_stat; int samples; - int_stat = adxl345_get_status(st); - if (int_stat <= 0) + if (adxl345_get_status(st, &int_stat)) return IRQ_NONE; - if (int_stat & ADXL345_INT_OVERRUN) - goto err; - - if (int_stat & ADXL345_INT_WATERMARK) { + if (FIELD_GET(ADXL345_INT_WATERMARK, int_stat)) { samples = adxl345_get_samples(st); if (samples < 0) goto err; @@ -551,6 +540,10 @@ static irqreturn_t adxl345_irq_handler(int irq, void *p) if (adxl345_fifo_push(indio_dev, samples) < 0) goto err; } + + if (FIELD_GET(ADXL345_INT_OVERRUN, int_stat)) + goto err; + return IRQ_HANDLED; err: From patchwork Tue Jan 28 12:00:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952487 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EE381A704B; Tue, 28 Jan 2025 12:01:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065701; cv=none; b=SZGZgZ7oCnlpYdxjxcqO3csn4GP+w5qe0jToQ9eJq+9LbSj1oxvl/jYTHSsKB5fnx0iClFZ2bF604WmXi10ee+1Xop2w8t33xCUuDsZB3aJNDH6Uj6MnNUjlSnsnEBZLqU9ET3UDDq6fALVhfU4g99FPDGLHec6Lhg8sSteBb1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065701; c=relaxed/simple; bh=1ZzeU4vvT5hrrqqFWlVujd5Ofhi42mGcESIFn3eGmb8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mzuinKMkJb1EuF7Htl7a6NYX1HHjI1wH+8lBX1IoD29v/t34m4JqLUBnNtRXJh584iWhnRSvF2blui43vil+E5GrQh/ZunUROWYwglU2CdoVaDhZJe+71BYM981YVM8fk4d6icWhwhOj8Pk7lblmDFFMjpJVniNLzItqVnqFCOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Q7Cp1xDH; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Q7Cp1xDH" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-aa6954ec439so64939366b.1; Tue, 28 Jan 2025 04:01:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065697; x=1738670497; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rJzvPQN10ih5ynVfzQ0LEvRXOTLdbTFiXrE5gCxL/vc=; b=Q7Cp1xDHQ4kLDboYpPoydFB5kr+ggQBa78wQQRJ5byhQv3Vuzs55FOIRKQHLQC0hhn xcvN5+tYsC4E/gAmfG4SPkdKgSYPlEo/XeiypkrwFMhzcRUaO5rw0A4fqnD7YOrwyR70 Qa8HTP1FRJO5iiKGp/xo4kpw07CZkQ9/VjLNkXgDRe+9j6RSS19J9Om/aHMRRoHuHqjL wTpHKgiaLCzljPzCZRpR1qAUfrUR09c2rkucktc/83STkMG94whXqA0Iim22oRUL07tB NE1lEwQuVC0kHLW+LbVs4LUz/2pUsvvk4NTJbK6Vkvh8aoX2LKPeTVSpPrjkJE5unsfe J7LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065697; x=1738670497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rJzvPQN10ih5ynVfzQ0LEvRXOTLdbTFiXrE5gCxL/vc=; b=iyYAlUzw/cc+Mo1NOGudQIAUj+0CJyb+Gs5I+OZM0DowGc0Qcv8igeVikqoR8lwGBU mdJciHKJH0F2+LX7cfvHTCoJlOSbJGaKZUqN9lIQwLDAD0fcg3CLC5ue4LOglgbEQKm9 GzoDLj+y+sd1x0ObyyWu+Qc2NEIXY3qFnra4kXZO83eLYi1lgNwivLogW27ofKlAK+SU 6ApigmsyoCBvu0Jn9N3HCNAJhddxYobutsjcTXNeNHuUFUctTtbV+NJsYCV2TcOy6BgW Ys2mLAmAnSoIuaJjIEfpqUaBe2cuziyjrk2zjRqQacYqs0BGB+g/CGXFgfkiUK4pjlI9 dmvg== X-Forwarded-Encrypted: i=1; AJvYcCXInzVYI+sOLYvOYhuPiVMC8ITXMLe6IT5hwMtfjALaZszJRHiBu6UPYIC6l88NBPvxTKxt2xcnJgLaamg=@vger.kernel.org X-Gm-Message-State: AOJu0YwG2D1tDQZgBQTrMGfdY/XL8rJiDKK6gT9ufxYLEZpvckH0g0yt budVcmG1h1wP7qo6RUWs4qp5qkThJncL2D6/RF3nrdWCwRxBqK60kR0gow== X-Gm-Gg: ASbGncsuiDjEcayuBIKi7SM08sTtMaRv2G2uasQxip3KQc5Xw9r1FlolmzfhYYJSBsh BOihOVZfI3QBpcr+WJ9j/69HZOdoybp8yvi1Dq/vMgD9LwblY54/Ht1OickoSMFeDBvGEw9KiUf 72FV4+J5F00LT3Jsz5Do69fZtFTQVo3Y+kCL3WMC1nCnpbhlCoibbQOeiEQXtfzhxgaZt4wao74 5uwjXYPl10ZJ4EfHPlea/DaFtuJUGSX3etMFi26V6uMqtltjDFR3jn1QtZOpbwBeivphOEudRg0 2KpCkzI4wLuR9qYnHtq9dkIeu4pc4+PvcIliL4xfjKkdX7awvP7PnV5mp7fNHBIxvjFb3w== X-Google-Smtp-Source: AGHT+IEEiXGrx3rJ4ol7shqMfJimM2yt0nqTJgl+uTZ/z9E5T/dnGerABXS608N4LLRxS2sCePGq2A== X-Received: by 2002:a17:907:9803:b0:aa5:163c:69cb with SMTP id a640c23a62f3a-ab38b49a5cbmr1452806166b.12.1738065697260; Tue, 28 Jan 2025 04:01:37 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:36 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 05/12] iio: accel: adxl345: improve access to the interrupt enable register Date: Tue, 28 Jan 2025 12:00:53 +0000 Message-Id: <20250128120100.205523-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Split the current set_interrupts() functionality. Separate writing the interrupt map from writing the interrupt enable register. Move writing the interrupt map into the probe(). The interrupt map will setup which event finally will go over the INT line. Thus, all events are mapped to this interrupt line now once at the beginning. On the other side the function set_interrupts() will now be focussed on enabling interrupts for event features. Thus it will be renamed to write_interrupts() to better distinguish from further usage of get/set in the conext of the sensor features. Also, add the missing initial reset of the interrupt enable register. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 43 +++++++++++++++++--------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 7ee50a0b23ea..b55f6774b1e9 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -190,25 +190,9 @@ static void adxl345_powerdown(void *ptr) adxl345_set_measure_en(st, false); } -static int adxl345_set_interrupts(struct adxl345_state *st) +static inline int adxl345_write_interrupts(struct adxl345_state *st) { - int ret; - unsigned int int_enable = st->int_map; - unsigned int int_map; - - /* - * Any bits set to 0 in the INT map register send their respective - * interrupts to the INT1 pin, whereas bits set to 1 send their respective - * interrupts to the INT2 pin. The intio shall convert this accordingly. - */ - int_map = FIELD_GET(ADXL345_REG_INT_SOURCE_MSK, - st->intio ? st->int_map : ~st->int_map); - - ret = regmap_write(st->regmap, ADXL345_REG_INT_MAP, int_map); - if (ret) - return ret; - - return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, int_enable); + return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, st->int_map); } static int adxl345_read_raw(struct iio_dev *indio_dev, @@ -464,7 +448,7 @@ static int adxl345_buffer_postenable(struct iio_dev *indio_dev) struct adxl345_state *st = iio_priv(indio_dev); int ret; - ret = adxl345_set_interrupts(st); + ret = adxl345_write_interrupts(st); if (ret < 0) return ret; @@ -483,7 +467,7 @@ static int adxl345_buffer_predisable(struct iio_dev *indio_dev) return ret; st->int_map = 0x00; - return adxl345_set_interrupts(st); + return adxl345_write_interrupts(st); } static const struct iio_buffer_setup_ops adxl345_buffer_ops = { @@ -602,6 +586,8 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, return -ENODEV; st->fifo_delay = fifo_delay_default; + st->int_map = 0x00; /* reset interrupts */ + indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; indio_dev->modes = INDIO_DIRECT_MODE; @@ -609,6 +595,11 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, indio_dev->num_channels = ARRAY_SIZE(adxl345_channels); indio_dev->available_scan_masks = adxl345_scan_masks; + /* Reset interrupts at start up */ + ret = adxl345_write_interrupts(st); + if (ret) + return ret; + if (setup) { /* Perform optional initial bus specific configuration */ ret = setup(dev, st->regmap); @@ -659,6 +650,18 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, } if (st->intio != ADXL345_INT_NONE) { + /* + * Any bits set to 0 in the INT map register send their respective + * interrupts to the INT1 pin, whereas bits set to 1 send their respective + * interrupts to the INT2 pin. The intio shall convert this accordingly. + */ + regval = st->intio ? ADXL345_REG_INT_SOURCE_MSK + : ~ADXL345_REG_INT_SOURCE_MSK; + + ret = regmap_write(st->regmap, ADXL345_REG_INT_MAP, regval); + if (ret) + return ret; + /* FIFO_STREAM mode is going to be activated later */ ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &adxl345_buffer_ops); if (ret) From patchwork Tue Jan 28 12:00:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952488 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 266351A2391; Tue, 28 Jan 2025 12:01:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065703; cv=none; b=SINPD0lJXIIeQG5SdtE5EOVwb0VLuLWFOzvfG+iRkPUnMb9/do3kH4+HPV7Bjwx6uS6txU7Llk16Pb+IeYiGuLFg2AreIp2nSgHqjJjf33pLn3zWh6JXN1E1pKUMUEGtLSDR9pp1rU+pMspX8bA7LfX50dupUtXP/jSQR/2s6FY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065703; c=relaxed/simple; bh=px3EIy5ZuO4BmN8KqrxdtewctqEZJkoNUBSfYojLlQY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uwuCTJW9aok/kdv4/vuRdv9oPv4yNcNSfB2DZpc+1JUQuaVqyV8aqGDEi2QtVbHGCevgdaZY5be60yxjzcOCsIS3B7ldtS+KZ4Jl8wsX8duHnnml165mG8wPuaQQnaj+2UliReJxjiv3b0D1TDKPBIdBlzDCVySrZJjZrZ+3v/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hNv3WjqV; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hNv3WjqV" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-ab2f33766e6so73181866b.0; Tue, 28 Jan 2025 04:01:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065699; x=1738670499; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hgtfoHM2AMsUxihJMzmLY7ruAv0/tgz+oz8n9tt8xxk=; b=hNv3WjqVWvwqEmLqUDa3HGKbIRfW+3oie7K8Tdbj9LAI2/NvsATZ4lH+QfPT/utjA5 soUMJiG23vX7hdqYjLMJvWE8XtRwKgGXJ1KmD3M8rnWubHXI5tMOmD1cj3+/Dl5uGmEP p8iAfl6TYhWfs9ztEpLa12zTAL3PxZ1ollvnZQCv2xvNvKhqDgFEqmw/Ay7YFIOCXis6 tboHJZJNl45ghhwKrCxwSotcrVOcFSf2CSe9/L19ZYEeaut92akGYL5a0BuEcwwUOoC/ wtdsmqYl4P/5/A6wF6e4SsfBacO93otqaXOuv26Qv9HF2A/jB4KzVX/geV0sVgE7FErL oSQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065699; x=1738670499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hgtfoHM2AMsUxihJMzmLY7ruAv0/tgz+oz8n9tt8xxk=; b=a3XXS4zaej+AAhaG4GyEWpmwcGQdbW7vFlbkmJpFATs7rid/1RPgcbmMyfl1GQt4bA RHrJE2o0w0oClSUXzkffBDjI0coUN3hItS43Da0KWzTGSQAf7vnneqpLNSp2ZcKDIeHh 7oCqax1LIx/obxePR/jjXoUGpJsVCNJ4laveVMcmYgKfWxq2H1miUd7TD1aV8Z2eATJI +IZdtIHqvyKQnW96kIbaC5yAZDrLscYOxhwTmh8guuPa4PubXag/4BHwsmgBCR60gCyS /z3LI2Wmj/FVvafy0GoJWMb0YcnaMpfuZN/RLpWpRTLEp2oIvMz9DI4oLMqNssyAhCgp IByg== X-Forwarded-Encrypted: i=1; AJvYcCVVlTGGPsPNZ2Qf2y4K05uNICDINbRA8oMMIxKBE6xoZ2yXRk6eDB2f5HKFTfHC2HItmoE4TBBG7drqA/E=@vger.kernel.org X-Gm-Message-State: AOJu0YyaehKIC4/YhPMPcO4IfcFxWW+EwTw1F5EblrB42jFx24HZBXcA gwwtDvR3hzd19OVEM/+izoggjLTD9KYWfGr6p+dBkCrmARRA+xJt X-Gm-Gg: ASbGnctEgPb+YEVTlFmRaSKJVHafdUJIhz0sXAB9YhxsXB2gpZtvYxGdJB5RrLQWHFV N7me4vXSLWPAnMm8zSEM+DAvgEUaxfCcUQlJ4ssCc+9Oa+e8ElN7jMUYy5q+ndo9XU4BzILbN1m UBqWbYdt2gAz0OdvHXPMMkiCChPcKZb/HHHD8lpqU/fYvc40Y6NqB2klN4mtQKnJ1UcEIWuBOOl ej/8UjkhYz3pFpJm3+tXldUBlqIIVPR86kA4qRUV71ejYQaN2i6frDjSboXrqRWh4+Yc3Yeg9EO p11dcmy64UxjO/bswI9Lnu8eXvK9qVb/Sq6RoxwIKZXbhfWD6YJ+H8/1ryWeQtc+OI8KLZ4JfGJ eApZU X-Google-Smtp-Source: AGHT+IG9YcMyqVcOyOKxvCgI5pvLcVwqz1VxYsEhxraj/Tuk0zNf67E3u3XohCx3ODkJ6ivp7VzzlA== X-Received: by 2002:a17:907:d1b:b0:aab:8f0f:6919 with SMTP id a640c23a62f3a-ab38b3cd5femr1555413266b.11.1738065698972; Tue, 28 Jan 2025 04:01:38 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:38 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 06/12] iio: accel: adxl345: add single tap feature Date: Tue, 28 Jan 2025 12:00:54 +0000 Message-Id: <20250128120100.205523-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the single tap feature with a threshold in 62.5mg/LSB points and a scaled duration in us. Keep singletap threshold by means of IIO but add sysfs entry for the duration. Using a sysfs entry allow for a clearer naming of the handle to improve usage. Extend the channels for single enable x/y/z axis of the feature but also check if threshold (a.k.a "value") and duration have reasonable content. When an interrupt is caught it will be pushed to the according IIO channel. The function call structure is in preparation to be extended for an upcoming doubletap feature in the follow up patches. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 367 +++++++++++++++++++++++++++++++ 1 file changed, 367 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index b55f6774b1e9..0d991f3ec10c 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -118,6 +119,16 @@ #define ADXL345_INT1 0 #define ADXL345_INT2 1 +#define ADXL345_REG_TAP_AXIS_MSK GENMASK(2, 0) + +enum adxl345_axis { + ADXL345_Z_EN = BIT(0), + ADXL345_Y_EN = BIT(1), + ADXL345_X_EN = BIT(2), + /* Suppress double tap detection if value > tap threshold */ + ADXL345_TAP_SUPPRESS = BIT(3), +}; + struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; @@ -127,9 +138,24 @@ struct adxl345_state { u8 int_map; u8 watermark; u8 fifo_mode; + + u32 tap_axis_ctrl; + u8 tap_threshold; + u32 tap_duration_us; + __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); }; +static struct iio_event_spec adxl345_events[] = { + { + /* single tap */ + .type = IIO_EV_TYPE_GESTURE, + .dir = IIO_EV_DIR_SINGLETAP, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), + .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE), + }, +}; + #define ADXL345_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .modified = 1, \ @@ -146,6 +172,8 @@ struct adxl345_state { .storagebits = 16, \ .endianness = IIO_LE, \ }, \ + .event_spec = adxl345_events, \ + .num_event_specs = ARRAY_SIZE(adxl345_events), \ } enum adxl345_chans { @@ -190,11 +218,121 @@ static void adxl345_powerdown(void *ptr) adxl345_set_measure_en(st, false); } +static inline void adxl345_intmap_switch_bit(struct adxl345_state *st, + bool condition, u8 bit) +{ + st->int_map = condition ? st->int_map | bit : st->int_map & ~bit; +} + +static inline int adxl345_read_interrupts(struct adxl345_state *st, + unsigned int *interrupts) +{ + return regmap_read(st->regmap, ADXL345_REG_INT_ENABLE, interrupts); +} + static inline int adxl345_write_interrupts(struct adxl345_state *st) { return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, st->int_map); } +/* tap */ + +static int adxl345_write_tap_axis(struct adxl345_state *st, + enum adxl345_axis axis, bool en) +{ + st->tap_axis_ctrl = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, + en ? st->tap_axis_ctrl | axis + : st->tap_axis_ctrl & ~axis); + + return regmap_update_bits(st->regmap, ADXL345_REG_TAP_AXIS, + ADXL345_REG_TAP_AXIS_MSK, + FIELD_PREP(ADXL345_REG_TAP_AXIS_MSK, + st->tap_axis_ctrl)); +} + +static int _adxl345_set_tap_int(struct adxl345_state *st, bool state) +{ + bool axis_valid; + bool singletap_args_valid = false; + bool en = false; + + axis_valid = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, st->tap_axis_ctrl) > 0; + + /* + * Note: A value of 0 for threshold and/or dur may result in undesirable + * behavior if single tap/double tap interrupts are enabled. + */ + singletap_args_valid = st->tap_threshold > 0 && st->tap_duration_us > 0; + + en = axis_valid && singletap_args_valid; + + adxl345_intmap_switch_bit(st, state && en, ADXL345_INT_SINGLE_TAP); + + return adxl345_write_interrupts(st); +} + +static int adxl345_is_tap_en(struct adxl345_state *st, bool *en) +{ + int ret; + unsigned int regval; + + ret = adxl345_read_interrupts(st, ®val); + if (ret) + return ret; + + *en = FIELD_GET(ADXL345_INT_SINGLE_TAP, regval) > 0; + + return 0; +} + +static int adxl345_set_singletap_en(struct adxl345_state *st, + enum adxl345_axis axis, bool en) +{ + int ret; + + ret = adxl345_write_tap_axis(st, axis, en); + if (ret) + return ret; + + return _adxl345_set_tap_int(st, en); +} + +static int adxl345_set_tap_value(struct adxl345_state *st, u8 val) +{ + st->tap_threshold = val; + + return regmap_write(st->regmap, ADXL345_REG_THRESH_TAP, min(val, 0xFF)); +} + +static int _adxl345_set_tap_time(struct adxl345_state *st, u32 val_us) +{ + unsigned int regval; + + st->tap_duration_us = val_us; + + /* + * The scale factor is 1250us / LSB for tap_window_us and tap_latent_us. + * For tap_duration_us the scale factor is 625us / LSB. + */ + regval = DIV_ROUND_CLOSEST(val_us, 625); + + return regmap_write(st->regmap, ADXL345_REG_DUR, regval); +} + +static int adxl345_set_tap_duration(struct adxl345_state *st, u32 val_int, + u32 val_fract_us) +{ + /* + * Max value is 255 * 625 us = 0.159375 seconds + * + * Note: the scaling is similar to the scaling in the ADXL380 + */ + if (val_int || val_fract_us > 159375) + return -EINVAL; + + return _adxl345_set_tap_time(st, val_fract_us); +} + static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -275,6 +413,141 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, ADXL345_BW_RATE, clamp_val(ilog2(n), 0, ADXL345_BW_RATE)); + default: + return -EINVAL; + } + + return -EINVAL; +} + +static int adxl345_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct adxl345_state *st = iio_priv(indio_dev); + bool int_en; + bool axis_en; + int ret = -EFAULT; + + switch (type) { + case IIO_EV_TYPE_GESTURE: + switch (dir) { + case IIO_EV_DIR_SINGLETAP: + switch (chan->channel2) { + case IIO_MOD_X: + axis_en = FIELD_GET(ADXL345_X_EN, st->tap_axis_ctrl); + break; + case IIO_MOD_Y: + axis_en = FIELD_GET(ADXL345_Y_EN, st->tap_axis_ctrl); + break; + case IIO_MOD_Z: + axis_en = FIELD_GET(ADXL345_Z_EN, st->tap_axis_ctrl); + break; + default: + return -EINVAL; + } + + ret = adxl345_is_tap_en(st, &int_en); + if (ret) + return ret; + return int_en && axis_en; + default: + return -EINVAL; + } + default: + return -EINVAL; + } + + return ret; +} + +static int adxl345_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + int state) +{ + struct adxl345_state *st = iio_priv(indio_dev); + enum adxl345_axis axis; + + if (type != IIO_EV_TYPE_GESTURE) + return -EINVAL; + + switch (dir) { + case IIO_EV_DIR_SINGLETAP: + switch (chan->channel2) { + case IIO_MOD_X: + axis = ADXL345_X_EN; + break; + case IIO_MOD_Y: + axis = ADXL345_Y_EN; + break; + case IIO_MOD_Z: + axis = ADXL345_Z_EN; + break; + default: + return -EINVAL; + } + + return adxl345_set_singletap_en(st, axis, state); + default: + return -EINVAL; + } + + return -EINVAL; +} + +static int adxl345_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, + enum iio_event_type type, enum iio_event_direction dir, + enum iio_event_info info, int *val, int *val2) +{ + struct adxl345_state *st = iio_priv(indio_dev); + + if (type != IIO_EV_TYPE_GESTURE) + return -EINVAL; + + switch (info) { + case IIO_EV_INFO_VALUE: + /* + * The scale factor is 62.5mg/LSB (i.e. 0xFF = 16g) but + * not applied here. + */ + *val = sign_extend32(st->tap_threshold, 7); + return IIO_VAL_INT; + default: + return -EINVAL; + } + + return -EINVAL; +} + +static int adxl345_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int ret; + + if (type != IIO_EV_TYPE_GESTURE) + return -EINVAL; + + if (info == IIO_EV_INFO_VALUE) { + if (val < 0 || val > 255) + return -EINVAL; + + ret = adxl345_set_measure_en(st, false); + if (ret) + return ret; + + ret = adxl345_set_tap_value(st, val); + if (ret) + return ret; + + return adxl345_set_measure_en(st, true); } return -EINVAL; @@ -322,6 +595,58 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } } +#define ADXL345_generate_iio_dev_attr_FRACTIONAL(A, B, C, D, E) \ + static ssize_t in_accel_##A##_##C##_##E##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); \ + struct adxl345_state *st = iio_priv(indio_dev); \ + int vals[2]; \ + \ + vals[0] = st->B##_##C##_##E; \ + vals[1] = D; \ + \ + return iio_format_value(buf, IIO_VAL_FRACTIONAL, 2, vals); \ + } \ + \ + static ssize_t in_accel_##A##_##C##_##E##_store(struct device *dev, \ + struct device_attribute *attr, \ + const char *buf, size_t len) \ + { \ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); \ + struct adxl345_state *st = iio_priv(indio_dev); \ + int val_int, val_fract_us, ret; \ + \ + ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract_us); \ + if (ret) \ + return ret; \ + \ + ret = adxl345_set_measure_en(st, false); \ + if (ret) \ + return ret; \ + \ + adxl345_set_##B##_##C(st, val_int, val_fract_us); \ + \ + ret = adxl345_set_measure_en(st, true); \ + if (ret) \ + return ret; \ + \ + return len; \ + } \ + static IIO_DEVICE_ATTR_RW(in_accel_##A##_##C##_##E, 0) + +ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_singletap, tap, duration, MICRO, us); + +static struct attribute *adxl345_event_attrs[] = { + &iio_dev_attr_in_accel_gesture_singletap_duration_us.dev_attr.attr, + NULL +}; + +static const struct attribute_group adxl345_event_attrs_group = { + .attrs = adxl345_event_attrs, +}; + static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200" ); @@ -477,6 +802,17 @@ static const struct iio_buffer_setup_ops adxl345_buffer_ops = { static int adxl345_get_status(struct adxl345_state *st, unsigned int *int_stat) { + unsigned int regval; + bool check_tap_stat; + + check_tap_stat = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, st->tap_axis_ctrl) > 0; + + if (check_tap_stat) { + /* ACT_TAP_STATUS should be read before clearing the interrupt */ + if (regmap_read(st->regmap, ADXL345_REG_ACT_TAP_STATUS, ®val)) + return -EINVAL; + } + return regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, int_stat); } @@ -499,6 +835,25 @@ static int adxl345_fifo_push(struct iio_dev *indio_dev, return 0; } +static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat) +{ + s64 ts = iio_get_time_ns(indio_dev); + int ret; + + if (FIELD_GET(ADXL345_INT_SINGLE_TAP, int_stat)) { + ret = iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + IIO_MOD_X_OR_Y_OR_Z, + IIO_EV_TYPE_GESTURE, + IIO_EV_DIR_SINGLETAP), + ts); + if (ret) + return ret; + } + + return -ENOENT; +} + /** * adxl345_irq_handler() - Handle irqs of the ADXL345. * @irq: The irq being handled. @@ -516,6 +871,9 @@ static irqreturn_t adxl345_irq_handler(int irq, void *p) if (adxl345_get_status(st, &int_stat)) return IRQ_NONE; + if (adxl345_push_event(indio_dev, int_stat) == 0) + return IRQ_HANDLED; + if (FIELD_GET(ADXL345_INT_WATERMARK, int_stat)) { samples = adxl345_get_samples(st); if (samples < 0) @@ -538,9 +896,14 @@ static irqreturn_t adxl345_irq_handler(int irq, void *p) static const struct iio_info adxl345_info = { .attrs = &adxl345_attrs_group, + .event_attrs = &adxl345_event_attrs_group, .read_raw = adxl345_read_raw, .write_raw = adxl345_write_raw, .write_raw_get_fmt = adxl345_write_raw_get_fmt, + .read_event_config = adxl345_read_event_config, + .write_event_config = adxl345_write_event_config, + .read_event_value = adxl345_read_event_value, + .write_event_value = adxl345_write_event_value, .debugfs_reg_access = &adxl345_reg_access, .hwfifo_set_watermark = adxl345_set_watermark, }; @@ -588,6 +951,10 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st->int_map = 0x00; /* reset interrupts */ + /* Init with reasonable values */ + st->tap_threshold = 35; /* 35 [0x23] */ + st->tap_duration_us = 3; /* 3 [0x03] -> .001875 */ + indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; indio_dev->modes = INDIO_DIRECT_MODE; From patchwork Tue Jan 28 12:00:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952489 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0930D1A83F5; Tue, 28 Jan 2025 12:01:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065703; cv=none; b=MChd8WHi5XGkiFpRgo8M8kjIMgXZHqtmpsgwp20S9akn2Bev16DTZhKkHKWi8JlMo/1LeZwShvgkyLd5AGGoML/GlMUazubLbYzHBbjdpz4VYktRiDwL6Zlj09Ex8ilEQixhrp/sNGv2YAYTbbpjT1flZHl4XHX7Pz/z3BZYAVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065703; c=relaxed/simple; bh=7iT/vlJ7lXh9ywQynj9AdKB3+QbbMRgx59VT4fMBGrc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=vBWpwAlXIK4b714r+tTaESzhtETfxWYV5aPwSQuMYFuuub2MzRJTo06NoKQsl9TeJSpPepcAHUNgFIuhpbZ49TmMQWF/VY8p7zYDereZzwKrDgF95EvOdRCinQTH7EdUMkFPN5+xEW60tk5Y6gHKADkutJZQA56L1QycTp7s1ZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eseJ9fUi; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eseJ9fUi" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-aa6647a7556so108045166b.2; Tue, 28 Jan 2025 04:01:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065700; x=1738670500; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yYYgaTb6xqvrloCELcHIlYmxEn6xsQKeUcT+235aVsM=; b=eseJ9fUi3FREl8Man7Q4YvndkSwTyzsVsDyEJF5hgk351LSFBL2+r9sFC4rKnWfTMm 0LZpz1g73JmGLJBYiV3AdseLl+yuTwjFNMgF+/35s17u7Q/7YYAL7XkrYDKzo8irkauc +mbgCwerK0jIvcPeKaEsLtQWyNTMrKmsCpuIobVHZgSegV/tAgYuIoJc6q/Mv4fVKjSu FJdVnuk0RBJLWl5BlLNS9+O+ATWpzC5n8l9bt/CuyKyQWDfUkrb8h3Wd9xWyus7HFwdR TYGvJVVMqb3lSCGv3jz4N5dZOQMZm7wfK+PTPd3DIP5E2TQj0AJmazPoh/D1qpfsQjg1 qZ1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065700; x=1738670500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yYYgaTb6xqvrloCELcHIlYmxEn6xsQKeUcT+235aVsM=; b=wsE90n3DtRFxfGx/Get7xwLdrLjKAXTYnNnVsApsgJOmVs4XimBFJfzfaRV0y3sX6a N3Vb4/DP8KQ1avQh7A/kEdjOoYHMiWLcPZ0ObHyPDOi7VeVS8kon8kbSE4GdydKANZ7O 9GIyKUwJz5AqYeRjuBulzIHP2jJUwz6yFWINj01F3Y4pyvlhIBdae7NOV2Lm34pqGhfs X5HKE5JC7UEnrUfu7k0nM8Y8Im8VUcEIa7s5CVNZuqGhHifGihnWMxFnkVuBRHGqOrGu UKQ7V543HyV6KgXdGeUgKHevzxAZIE6gYYf3TrsZAeOzhABUVkU6fsX3REzG8FYQCOkb xpkA== X-Forwarded-Encrypted: i=1; AJvYcCUNVfEcw4mPA4XWHMHnBIAxqiiFT6k3rX5+c2C+66Ug3wA/BB1GOTTDavyM5Ub7tux4OydtIMNHxP//Lfs=@vger.kernel.org X-Gm-Message-State: AOJu0YyxAx3mqHXTu7qYoc/uOtppAeNKDS5Il3K8DiBcDK8QKM/ZxDlw /ucLRdcAAqoPn9inVUOKYLHzBcbAT8zXkPbePafbohBVIPYHVFYb X-Gm-Gg: ASbGncsMXG0RTVh+V7pCyZUQfnjo4+T8Y+2ZuaPckCBrUCIdNC6qqcf2AagYL/xOyyS RUEQVigiNvigGUV7oIY3KGqe3CasOLolTBY+92u89cormuydt6JsNenKK8S14kIRy6grVDU5xwL pZFZEZJUWeSs4bZ48XYHNtxU5qJUG9pOv7MqDmcaJylWRRh0BL8UQozTEf2l8GWwg36raijH6KH Xol88tc+N6HNytum0krtK3DrUZ5Dgvd+MCKYGJ/nx78hQEASN4e4TJGRU6blsooCc1a7uKemMX3 IQmy5D4CJYjYqtF1qUljIHmp5eK6Ea4q9ZsBZluubhf+AbKljzxJDVEK5EIZFSvnGTwUaA== X-Google-Smtp-Source: AGHT+IHtXm8zxX3d8GaRJZI0ZACALmRTB4xKRR4ZQzp337Jy5Ck26n4IZDs2S/pvWw+mTH4XwKymsQ== X-Received: by 2002:a17:907:3da3:b0:aa5:3e81:5abc with SMTP id a640c23a62f3a-ab65152babbmr1053882266b.1.1738065699967; Tue, 28 Jan 2025 04:01:39 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:39 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 07/12] iio: accel: adxl345: show tap status and direction Date: Tue, 28 Jan 2025 12:00:55 +0000 Message-Id: <20250128120100.205523-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Provide information in the iio tap event about the tap direction. This can be verified using 'iio_event_monior adxl345'. Reading out the ACT_TAP_STATUS register is also in preparation for activity events. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 0d991f3ec10c..7831ec511941 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -800,17 +800,26 @@ static const struct iio_buffer_setup_ops adxl345_buffer_ops = { .predisable = adxl345_buffer_predisable, }; -static int adxl345_get_status(struct adxl345_state *st, unsigned int *int_stat) +static int adxl345_get_status(struct adxl345_state *st, unsigned int *int_stat, + enum iio_modifier *act_tap_dir) { unsigned int regval; bool check_tap_stat; + *act_tap_dir = IIO_NO_MOD; check_tap_stat = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, st->tap_axis_ctrl) > 0; if (check_tap_stat) { /* ACT_TAP_STATUS should be read before clearing the interrupt */ if (regmap_read(st->regmap, ADXL345_REG_ACT_TAP_STATUS, ®val)) return -EINVAL; + + if (FIELD_GET(ADXL345_Z_EN, regval) > 0) + *act_tap_dir = IIO_MOD_Z; + else if (FIELD_GET(ADXL345_Y_EN, regval) > 0) + *act_tap_dir = IIO_MOD_Y; + else if (FIELD_GET(ADXL345_X_EN, regval) > 0) + *act_tap_dir = IIO_MOD_X; } return regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, int_stat); @@ -835,7 +844,8 @@ static int adxl345_fifo_push(struct iio_dev *indio_dev, return 0; } -static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat) +static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat, + enum iio_modifier act_tap_dir) { s64 ts = iio_get_time_ns(indio_dev); int ret; @@ -843,7 +853,7 @@ static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat) if (FIELD_GET(ADXL345_INT_SINGLE_TAP, int_stat)) { ret = iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, - IIO_MOD_X_OR_Y_OR_Z, + act_tap_dir, IIO_EV_TYPE_GESTURE, IIO_EV_DIR_SINGLETAP), ts); @@ -866,12 +876,13 @@ static irqreturn_t adxl345_irq_handler(int irq, void *p) struct iio_dev *indio_dev = p; struct adxl345_state *st = iio_priv(indio_dev); int int_stat; + enum iio_modifier act_tap_dir; int samples; - if (adxl345_get_status(st, &int_stat)) + if (adxl345_get_status(st, &int_stat, &act_tap_dir)) return IRQ_NONE; - if (adxl345_push_event(indio_dev, int_stat) == 0) + if (adxl345_push_event(indio_dev, int_stat, act_tap_dir) == 0) return IRQ_HANDLED; if (FIELD_GET(ADXL345_INT_WATERMARK, int_stat)) { From patchwork Tue Jan 28 12:00:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952490 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A30DD1ACEAF; Tue, 28 Jan 2025 12:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065706; cv=none; b=CFIHngBH56WvFETPVSwpSVbBWb4FhHVG88+w8EmHC/owc8C3gwcQH1igV4lXJ2n3/G7bwvJ2y/7uyRWYVTEBVADvxo31FaTDQp2XlgEmGOjUw9H8XXsleHGLG1mY4IwnjPbtQH6MyaZq0xfYdz3w0+2wAXst3KnfbTNHfIEhlDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065706; c=relaxed/simple; bh=E97KxUbL38FSBEO6mpg7NPFx2gC0CAYXgXakLUXyIpo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eHu6zjHHB5I4X4u2APRZm1wifMfmNkMy8GMfNTE1YRwMm2HBPPnR7P4iiI5GlUs7Pj4V0DDYnizN+2Oe8jEBnAORbbXW60YNtrAYywijXMwp2ORvUanjIpkVzptshGPGxrblcg/9B35ao+1Hhlcja2MocLwBOonVTstUoNnitB8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=El12VTVz; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="El12VTVz" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-aa6b500a685so91390866b.2; Tue, 28 Jan 2025 04:01:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065702; x=1738670502; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pK0C2HvJvXDr8HjTqLM0+B0C7fhzdaX3twoJh9FXeBU=; b=El12VTVz6q/Dp/uQhjfPMkKKBElJfpA8QDhS7RZO4Fp23akVfXJ8Gd+9dIkpgDl8mv z7A+fgAJle/+CWTQKRVmnU+RHV/i5kzmLZg9YZX4i+F+BEFCTfeW6vijBlkGpECJAzRf p1q30X7gVFklzBawarV+loGea4gxi6NYlauT+GOa3l/W4pW6Phd/fUHKNrJjXRfDlfFK l6Dnx6ozTjUgM8g8XSMn7S7BXedSw1AU0x1zCTqRxBJmGbcM+mMN6kREeUghrO20IZZF qDe8kN+C6drSRq+OmxoVF4b2jr0MqiJqcPQO2bk3zFMQ4HAe7oiCUA4ZUBX8v27LM8vG sZVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065702; x=1738670502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pK0C2HvJvXDr8HjTqLM0+B0C7fhzdaX3twoJh9FXeBU=; b=hTAENSvNcZnCaqqW2JYYL/7RB00DETRo9rwMTe7XecjFtocDTXXFMdFxnWVWB/DwNc rRxJtFN8c0joLpuebXKneu5xLEeSp2O9ArkPvrxRmVlqqyNzq1hqtelmSrg2IEUclreB XmW28+dTd6OWNxU4067ap4W9jI/UWMY8qgMFUsOQ8r+T5PZNQO+0ofKe8cDcGfneOdJU l5rmY4ATkgPCr8lK5xVVi1JruiZ1jQ5WRZoN4WnEoZcRKbK+S9ppGS694aXwE7ShsEuC q+4D3hAqvAXOswYPmlL0wmAs++k/douGC4YL4WunvJ028N1bG0zxD8bKr9NMsVaTKHfJ R4mQ== X-Forwarded-Encrypted: i=1; AJvYcCUy9dTOQPEIvEw5j6+U79E/JTBYOCnrF2/i85E+zRa9rObI2jpTURetP5q38/pYOztSwdiFeFLGRTwvmPw=@vger.kernel.org X-Gm-Message-State: AOJu0YxvZBtjacxwEGqbRPufptxS+QT8vop8aG7x2CUnPFjRDmmmZPgZ 38c0pr1o97SHaC7VRxgd9iCRHlFoY6128k/vhTqiZovVNu/XQdwr X-Gm-Gg: ASbGncstwM5ge7kJHSxRgjKB0xLXZL74lE17svknMeOgxiVgeG8X4kZmezGCDmS89dw pRJ0WKhIHL2sI5WLaAVoeFgf3/anJPacniHTzHu3swmQoqpUiKnPJ63GzTREiOebQ4ZBKDXoANe SSkux4mKzrecutkIJf10bF2BJhnWXHyFYKxOzOXjgjqm0PURPrPbtECrQ3/25R17WIWtdfv1XEv M85kcSAMY8bj4tl3AfV0/K+DUa1zxLHCAYEiC8fsXHLdWxggS6ffnnbP8wzN3Rc1rEMB/MjBI4r Tw5OxXEjiYQlLwDYlUc5SIAy4tUcrkZWhVnH81ELIbEeStytgulsO8g+559hqjYkQQQS+A== X-Google-Smtp-Source: AGHT+IHKyXeW+m07+W4HPLs5nlNMncnCSkYc1fzHV1dAnJXaLcvydq7W3CFac8V2g0UXj7YKcNZ5rQ== X-Received: by 2002:a17:906:dc8e:b0:aa6:9407:34d3 with SMTP id a640c23a62f3a-ab38b362140mr1524250466b.9.1738065701665; Tue, 28 Jan 2025 04:01:41 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:40 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 08/12] iio: accel: adxl345: add double tap feature Date: Tue, 28 Jan 2025 12:00:56 +0000 Message-Id: <20250128120100.205523-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the double tap feature of the sensor. The interrupt handler needs to catch and forwared the event to the IIO channel. The single tap implementation now is extended to deal with double tap as well. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 139 ++++++++++++++++++++++++++++--- 1 file changed, 127 insertions(+), 12 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 7831ec511941..f9e5f47ba303 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -129,6 +129,29 @@ enum adxl345_axis { ADXL345_TAP_SUPPRESS = BIT(3), }; +/* single/double tap */ +enum adxl345_tap_type { + ADXL345_SINGLE_TAP, + ADXL345_DOUBLE_TAP +}; + +static const unsigned int adxl345_tap_int_reg[2] = { + [ADXL345_SINGLE_TAP] = ADXL345_INT_SINGLE_TAP, + [ADXL345_DOUBLE_TAP] = ADXL345_INT_DOUBLE_TAP, +}; + +enum adxl345_tap_time_type { + ADXL345_TAP_TIME_LATENT, + ADXL345_TAP_TIME_WINDOW, + ADXL345_TAP_TIME_DUR +}; + +static const unsigned int adxl345_tap_time_reg[3] = { + [ADXL345_TAP_TIME_LATENT] = ADXL345_REG_LATENT, + [ADXL345_TAP_TIME_WINDOW] = ADXL345_REG_WINDOW, + [ADXL345_TAP_TIME_DUR] = ADXL345_REG_DUR, +}; + struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; @@ -142,6 +165,8 @@ struct adxl345_state { u32 tap_axis_ctrl; u8 tap_threshold; u32 tap_duration_us; + u32 tap_latent_us; + u32 tap_window_us; __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); }; @@ -154,6 +179,12 @@ static struct iio_event_spec adxl345_events[] = { .mask_separate = BIT(IIO_EV_INFO_ENABLE), .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE), }, + { + /* double tap */ + .type = IIO_EV_TYPE_GESTURE, + .dir = IIO_EV_DIR_DOUBLETAP, + .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE), + }, }; #define ADXL345_CHANNEL(index, reg, axis) { \ @@ -250,10 +281,12 @@ static int adxl345_write_tap_axis(struct adxl345_state *st, st->tap_axis_ctrl)); } -static int _adxl345_set_tap_int(struct adxl345_state *st, bool state) +static int _adxl345_set_tap_int(struct adxl345_state *st, + enum adxl345_tap_type type, bool state) { bool axis_valid; bool singletap_args_valid = false; + bool doubletap_args_valid = false; bool en = false; axis_valid = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, st->tap_axis_ctrl) > 0; @@ -264,14 +297,24 @@ static int _adxl345_set_tap_int(struct adxl345_state *st, bool state) */ singletap_args_valid = st->tap_threshold > 0 && st->tap_duration_us > 0; - en = axis_valid && singletap_args_valid; + if (type == ADXL345_SINGLE_TAP) { + en = axis_valid && singletap_args_valid; + } else { + /* doubletap: Window must be equal or greater than latent! */ + doubletap_args_valid = st->tap_latent_us > 0 && + st->tap_window_us > 0 && + st->tap_window_us >= st->tap_latent_us; + + en = axis_valid && singletap_args_valid && doubletap_args_valid; + } - adxl345_intmap_switch_bit(st, state && en, ADXL345_INT_SINGLE_TAP); + adxl345_intmap_switch_bit(st, state && en, adxl345_tap_int_reg[type]); return adxl345_write_interrupts(st); } -static int adxl345_is_tap_en(struct adxl345_state *st, bool *en) +static int adxl345_is_tap_en(struct adxl345_state *st, + enum adxl345_tap_type type, bool *en) { int ret; unsigned int regval; @@ -280,7 +323,8 @@ static int adxl345_is_tap_en(struct adxl345_state *st, bool *en) if (ret) return ret; - *en = FIELD_GET(ADXL345_INT_SINGLE_TAP, regval) > 0; + // TODO FIELD_GET() seems not possible here due to construct 'not const', any ideas? + *en = (adxl345_tap_int_reg[type] & regval) > 0; return 0; } @@ -294,7 +338,12 @@ static int adxl345_set_singletap_en(struct adxl345_state *st, if (ret) return ret; - return _adxl345_set_tap_int(st, en); + return _adxl345_set_tap_int(st, ADXL345_SINGLE_TAP, en); +} + +static int adxl345_set_doubletap_en(struct adxl345_state *st, bool en) +{ + return _adxl345_set_tap_int(st, ADXL345_DOUBLE_TAP, en); } static int adxl345_set_tap_value(struct adxl345_state *st, u8 val) @@ -304,19 +353,33 @@ static int adxl345_set_tap_value(struct adxl345_state *st, u8 val) return regmap_write(st->regmap, ADXL345_REG_THRESH_TAP, min(val, 0xFF)); } -static int _adxl345_set_tap_time(struct adxl345_state *st, u32 val_us) +static int _adxl345_set_tap_time(struct adxl345_state *st, + enum adxl345_tap_time_type type, u32 val_us) { unsigned int regval; - st->tap_duration_us = val_us; + switch (type) { + case ADXL345_TAP_TIME_WINDOW: + st->tap_window_us = val_us; + break; + case ADXL345_TAP_TIME_LATENT: + st->tap_latent_us = val_us; + break; + case ADXL345_TAP_TIME_DUR: + st->tap_duration_us = val_us; + break; + } /* * The scale factor is 1250us / LSB for tap_window_us and tap_latent_us. * For tap_duration_us the scale factor is 625us / LSB. */ - regval = DIV_ROUND_CLOSEST(val_us, 625); + if (type == ADXL345_TAP_TIME_DUR) + regval = DIV_ROUND_CLOSEST(val_us, 625); + else + regval = DIV_ROUND_CLOSEST(val_us, 1250); - return regmap_write(st->regmap, ADXL345_REG_DUR, regval); + return regmap_write(st->regmap, adxl345_tap_time_reg[type], regval); } static int adxl345_set_tap_duration(struct adxl345_state *st, u32 val_int, @@ -330,7 +393,35 @@ static int adxl345_set_tap_duration(struct adxl345_state *st, u32 val_int, if (val_int || val_fract_us > 159375) return -EINVAL; - return _adxl345_set_tap_time(st, val_fract_us); + return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_DUR, val_fract_us); +} + +static int adxl345_set_tap_window(struct adxl345_state *st, u32 val_int, + u32 val_fract_us) +{ + /* + * Max value is 255 * 1250 us = 0.318750 seconds + * + * Note: the scaling is similar to the scaling in the ADXL380 + */ + if (val_int || val_fract_us > 318750) + return -EINVAL; + + return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_WINDOW, val_fract_us); +} + +static int adxl345_set_tap_latent(struct adxl345_state *st, u32 val_int, + u32 val_fract_us) +{ + /* + * Max value is 255 * 1250 us = 0.318750 seconds + * + * Note: the scaling is similar to the scaling in the ADXL380 + */ + if (val_int || val_fract_us > 318750) + return -EINVAL; + + return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_LATENT, val_fract_us); } static int adxl345_read_raw(struct iio_dev *indio_dev, @@ -448,10 +539,15 @@ static int adxl345_read_event_config(struct iio_dev *indio_dev, return -EINVAL; } - ret = adxl345_is_tap_en(st, &int_en); + ret = adxl345_is_tap_en(st, ADXL345_SINGLE_TAP, &int_en); if (ret) return ret; return int_en && axis_en; + case IIO_EV_DIR_DOUBLETAP: + ret = adxl345_is_tap_en(st, ADXL345_DOUBLE_TAP, &int_en); + if (ret) + return ret; + return int_en; default: return -EINVAL; } @@ -491,6 +587,8 @@ static int adxl345_write_event_config(struct iio_dev *indio_dev, } return adxl345_set_singletap_en(st, axis, state); + case IIO_EV_DIR_DOUBLETAP: + return adxl345_set_doubletap_en(st, state); default: return -EINVAL; } @@ -637,9 +735,13 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, static IIO_DEVICE_ATTR_RW(in_accel_##A##_##C##_##E, 0) ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_singletap, tap, duration, MICRO, us); +ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, window, MICRO, us); +ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, latent, MICRO, us); static struct attribute *adxl345_event_attrs[] = { &iio_dev_attr_in_accel_gesture_singletap_duration_us.dev_attr.attr, + &iio_dev_attr_in_accel_gesture_doubletap_latent_us.dev_attr.attr, + &iio_dev_attr_in_accel_gesture_doubletap_window_us.dev_attr.attr, NULL }; @@ -861,6 +963,17 @@ static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat, return ret; } + if (FIELD_GET(ADXL345_INT_DOUBLE_TAP, int_stat)) { + ret = iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + act_tap_dir, + IIO_EV_TYPE_GESTURE, + IIO_EV_DIR_DOUBLETAP), + ts); + if (ret) + return ret; + } + return -ENOENT; } @@ -965,6 +1078,8 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, /* Init with reasonable values */ st->tap_threshold = 35; /* 35 [0x23] */ st->tap_duration_us = 3; /* 3 [0x03] -> .001875 */ + st->tap_window_us = 20; /* 20 [0x14] -> .025 */ + st->tap_latent_us = 20; /* 20 [0x14] -> .025 */ indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; From patchwork Tue Jan 28 12:00:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952491 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 768B71ACEBF; Tue, 28 Jan 2025 12:01:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065707; cv=none; b=NhE6Pvr4vqlnli+49VdjsbFLmVyrE1HnNl0p+WJlK+En6R6xDqMYvoddehk7fmCSmhynedCQYsJ3/2FN69a7Ghmfwiu5cGesZIR39lcvJpaTHFJIpgRbfEUH2fU44nuG6AG85Ji8w4BvTmfplqDblB+mJpm8bpiUSx/p1SsgSz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065707; c=relaxed/simple; bh=smBYyuU1n5MHiHwK6AtDzGI8tE9oqWL1TJdVd7NEdkY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tsTE4/BH9Bz0dHJUQ9B2+SjUiPlAfzXMTcLFv5vkb0kdrEJG0rVzkXbBT+WFV9aBV4wyVjGpw6ris6RpKCu+mE9cAOI5fvhHjwWToYvHpW+RKCkI2e1yF86x8ANvJh0uSL40MJGiE3eXDrz3rPuK8eEUzsCCt26ZojjGhucTQIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jMgbLT5W; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jMgbLT5W" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-ab30614c1d6so107598966b.1; Tue, 28 Jan 2025 04:01:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065703; x=1738670503; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SI/nnzNJ193vlwe+KhpBZKRWN7AdPR78xeiJg6BW9/8=; b=jMgbLT5WRot/10BbyDXf4o1qctt2MpoSphomh0n/OoJhSkTb9SBMAyYLSgTvOjBGcE V0RQXN0GR9HlyiUP2p51hCC1bD945wgXK7TTOIByl9/aqd7ZNznUzwNobJ/LyETycgnY oLNqobgEn37ImxbI5K0PrmIvdViWnNc612lmxuLbzaOwFqs9xtzRpjwNQjOXkt85vnbw E5ocvi8KxdmyHYm0M0iYJLu862YMxFeISyTfqENkXiSzDTgu5r9QN1OiiWpgFGUtfhyj mXsIZz7RAOYRbe6FfWvc8FEF1RHmu2uyN5RZPG7zeHbhfgwoZDwWDPO360eEmOMgQs7f RKMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065703; x=1738670503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SI/nnzNJ193vlwe+KhpBZKRWN7AdPR78xeiJg6BW9/8=; b=vj8MOvaM0K4PRctDQulUV8TQV689GU+eC2uuOs0QQx66PXtRT9HW3KeM1ZcBDDgzcJ +q+n+SokZ/caQ7pueFc+ziQO5bPv9gQyg5O57qYzVpBPwHvjwoSiNLqM5mQsYHc6BZas izK8I8mEgYxIsHboGXZQwSC9u4RUOwa2bHBx8Yw1pOkQW6FM2R0TzXz/UONpOuAIHjX7 deTuv0naoDL53qPWhLOl2BG0fnm9C3jhmp1Qmxz9huv1C5lTswdzg4JrUJLDgG7TP7+H i7oxUFBEenMlGui7usi3zeIhNsbcQ9kKarcolFSp8aXcRcy0CeGeSVAD/56wg+xTohkJ y/5g== X-Forwarded-Encrypted: i=1; AJvYcCXhWx3vkOrhCTw0Ht7wMZFIVkzwhUEoRN0lZRJTNKCMf1+3p1cplIw1e917hdle1mACaewYzrHhdfH+8vw=@vger.kernel.org X-Gm-Message-State: AOJu0YwuqID5A1Ra4iQc+JxpZg2i34P+zcPfTfuVSanxd1vm3TKg6z1d +VCBI2LkpGDiGIBvMAAvFKg7zFV+lDj5BkWN1iPnxMPDdjQ27VJN X-Gm-Gg: ASbGncuoRXOpx9tkWL6+vG4BYrsMfsgEk3V3NPFv8M2jgmabdjFBPtcLMC5ydyjpgnl RkeLDM9k1BrpLykm4uwPD2IU3n2l/avhyjJ3lR+xuYceyt5z9BkUNTzvN9xhiYAZSc8hDY7nCvk x7aYh90P7S0ytFDtTaJkfN5SbMjnFyUDvF7wamW0fskFLyrf61ObEbZ1gLB5OBPNfkA0zAEAIjj n3kTNlDkRmihu4Tw9Y2H4aB6wcSL9fpr7vM5W+tU6z7vRycaGoB4141KPQoBLu4iPrzgRsyE2D+ x7+H/8VzqY3mbTFhH+UEwQCtomfymk4pMwScAzRIor9ZSEa7jtLx7lUD5goLKJkNRHUwWQ== X-Google-Smtp-Source: AGHT+IE0si5YhOptbTHq1ER708uHctoL4MG4LmhhcIjfWXdwIwzQIZWmOkPXdGjGCqK5dHksg+r9LQ== X-Received: by 2002:a17:907:3e0d:b0:aac:619:6411 with SMTP id a640c23a62f3a-ab65167653cmr976882966b.11.1738065702649; Tue, 28 Jan 2025 04:01:42 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:42 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 09/12] iio: accel: adxl345: add double tap suppress bit Date: Tue, 28 Jan 2025 12:00:57 +0000 Message-Id: <20250128120100.205523-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the suppress bit feature to make double tap (in)sensitive to the configured threshold value for the tap feature. The feature is being enabled by a sysfs handle for enabling. This is also needed for further features in follow up patches. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 67 ++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index f9e5f47ba303..ef0a12fd59be 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -120,6 +120,7 @@ #define ADXL345_INT2 1 #define ADXL345_REG_TAP_AXIS_MSK GENMASK(2, 0) +#define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3) enum adxl345_axis { ADXL345_Z_EN = BIT(0), @@ -167,6 +168,7 @@ struct adxl345_state { u32 tap_duration_us; u32 tap_latent_us; u32 tap_window_us; + bool tap_suppressed; __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); }; @@ -346,6 +348,22 @@ static int adxl345_set_doubletap_en(struct adxl345_state *st, bool en) return _adxl345_set_tap_int(st, ADXL345_DOUBLE_TAP, en); } +static int adxl345_is_suppressed_en(struct adxl345_state *st, bool *en) +{ + *en = st->tap_suppressed; + + return 0; +} + +static int adxl345_set_suppressed_en(struct adxl345_state *st, bool en) +{ + st->tap_suppressed = en; + + return regmap_update_bits(st->regmap, ADXL345_REG_TAP_AXIS, + ADXL345_REG_TAP_SUPPRESS_MSK, + en ? ADXL345_TAP_SUPPRESS : ~ADXL345_TAP_SUPPRESS); +} + static int adxl345_set_tap_value(struct adxl345_state *st, u8 val) { st->tap_threshold = val; @@ -693,6 +711,52 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } } +#define ADXL345_generate_iio_dev_attr_EN(A, B) \ + static ssize_t in_accel_##A##_##B##_en_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); \ + struct adxl345_state *st = iio_priv(indio_dev); \ + bool en; \ + int val, ret; \ + \ + ret = adxl345_is_##B##_en(st, &en); \ + if (ret) \ + return ret; \ + val = en ? 1 : 0; \ + \ + return iio_format_value(buf, IIO_VAL_INT, 1, &val); \ + } \ + \ + static ssize_t in_accel_##A##_##B##_en_store(struct device *dev, \ + struct device_attribute *attr, \ + const char *buf, size_t len) \ + { \ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); \ + struct adxl345_state *st = iio_priv(indio_dev); \ + int val, ret; \ + \ + ret = kstrtoint(buf, 0, &val); \ + if (ret) \ + return ret; \ + \ + ret = adxl345_set_measure_en(st, false); \ + if (ret) \ + return ret; \ + \ + ret = adxl345_set_##B##_en(st, val > 0); \ + if (ret) \ + return ret; \ + \ + ret = adxl345_set_measure_en(st, true); \ + if (ret) \ + return ret; \ + \ + return len; \ + } \ + static IIO_DEVICE_ATTR_RW(in_accel_##A##_##B##_en, 0) + #define ADXL345_generate_iio_dev_attr_FRACTIONAL(A, B, C, D, E) \ static ssize_t in_accel_##A##_##C##_##E##_show(struct device *dev, \ struct device_attribute *attr, \ @@ -738,8 +802,11 @@ ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_singletap, tap, duration, MICRO ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, window, MICRO, us); ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, latent, MICRO, us); +ADXL345_generate_iio_dev_attr_EN(gesture_doubletap, suppressed); + static struct attribute *adxl345_event_attrs[] = { &iio_dev_attr_in_accel_gesture_singletap_duration_us.dev_attr.attr, + &iio_dev_attr_in_accel_gesture_doubletap_suppressed_en.dev_attr.attr, &iio_dev_attr_in_accel_gesture_doubletap_latent_us.dev_attr.attr, &iio_dev_attr_in_accel_gesture_doubletap_window_us.dev_attr.attr, NULL From patchwork Tue Jan 28 12:00:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952493 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DA981B0406; Tue, 28 Jan 2025 12:01:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065708; cv=none; b=V0FWLLupUPPYHSDUNfL4RI9ZKyxcvAqVCPRGpjAPD7xLYTSJ2Hw2SLsETniEAXxDbec+2vcBVO5/DDk2YtMknGhTcXSorsp3pGTRR0UMWPBH6HBXhSNuaC+61f7QyRLHrcAGnYcJgWSAVH3W8r2+OrnAXbSd7MKMuMpVYPUvfao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065708; c=relaxed/simple; bh=eJcQe/ALyxl5u6qJWeYq3Zd/bq2kll+r5Ce/fqpotuE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fInccv9t8wL38u/6AHmLCtnWNUBTPzrk1Es9V1TwFWFRFsywho/reim+XgGcpafeC4pTMpcSsUDKnc49+MNdWHyx4Dyfufg7FnydnruoFYBTPCUnUBswUxeHkKEEl4s1S2ImcEQwcpbjad2tuTk7xzKQ3h+Ol5F0sL8AXEBYQ14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GaCKqIFO; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GaCKqIFO" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-aa659775dd5so72135266b.0; Tue, 28 Jan 2025 04:01:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065704; x=1738670504; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cP32LcbMnrfeHU7TZ84P0nlILDpCVTWkGpH3nk2hrVk=; b=GaCKqIFOJkek//Jvq4YSaJsnbIBK+QE+21PgO6qaI/hg3jmUxcIUAFwakqNb9eLFNt SOojuyPMpfQO9bwVkCJTRLy7oN6IWEeMi6lKuvMyIPtcMlzOZA952Hmc+lnhmW5IvRqx VuUgCJGRaaDEBuQrPljzbfO431aEK4TY6EtQKz5hyCCygvGCNnLSvtHV+PySOpoR6/Xq uXx8thtD66R56rse1nXZPwQsDOt+ahDGJGg9un1u4JESpwaiBwXkFbNM3u9nleyuz1rI 1Hd4TVF1t/KzGFnTSpSJ+x0erpUdStWWqWU6JQHG3H+byNJemcZnsnSXmzLuu7MgcR3Q UbYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065704; x=1738670504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cP32LcbMnrfeHU7TZ84P0nlILDpCVTWkGpH3nk2hrVk=; b=bdVgwi3kCQ6BOSRHWdUBEV3lYlN2sqRQ7LEhzfQdE+Msc33cORBBKk5vCRb0JcXyFE JciQ8UcRY44jOKvKkzkeyXJzkPcUmgY66iJUDyeNBnChiSufw04gLT1gRbMUSNX5NSLS bivIhSL+ikX5OXSKLn5GBRsh+qi8AGUYb6bj/PA/EpJqKt4pdLIQUqPjqHv1TnP/4UP7 3JfJmq9XkxMt2EUcD000HgKoWP5lK5W6vQxNZq037v4Pl5r+aYPmIfrzbxM2Gx4I2E+U QAK9D5Li7KgqhhH4HHFFepUyUU++TcnN5RbzEIjmoav2tCSEUMu5DReJcMVfOgigG9wf zIOA== X-Forwarded-Encrypted: i=1; AJvYcCWHpkKOU3CwikqF4By3IrsF9XopXf6cKo2aW7ADybT6BfnJU7/o5xwsBuONXZ4wTsNCXrk1tIObZ/w0fMs=@vger.kernel.org X-Gm-Message-State: AOJu0YxQQM9aUgCj8xZPFuZjgctq1vB9h1CNveMEveKtT4j+jsSovgsC 7D0h7LUXAnqwg+GI8Em3o+krc4Yn7bUbAXYhLy5EbXVJBvexKd4g X-Gm-Gg: ASbGnctENAfBtaohaV+IqmhZVxY3v7XKPw9P4BpPUTGrx14XxJ/XyC2pQkEBs8eni2u UnqnvrtIK6vOpNxYOhXuS0s7Bb0GSdVqNHPZIi6WqKvF8+G4/138hXFfZyVv6K1UF6v6YjrkNN2 wXyOF9/uSwXVFnGR65krjLP/Dt3ESOjYVMfuDgQQhwcW9Nj7XtHCAmk4VSveNysBqF7+KK2eNIe 5g/uxvTuigvQJkGxJBY4Lf0OcSuDz+AyyUgWc0jEJ7ctwa5Hea1aR62iD+bO1dcrUEJ9HP/U4hd zL3eX3DiMKqorsaElvgrheBnmqvbUcKdVoKLTkg62FpqgWNtF1HA2Fw9v+JQpZ8GJP1Fvg== X-Google-Smtp-Source: AGHT+IEoVxCgF7YIqwIlY+SpTzN02pWtMaX8Ajan3U/u4LzehyIv2yb5Pgcqd6TLvlJe+PRrXaoaJA== X-Received: by 2002:a17:907:9803:b0:aa5:163c:69cb with SMTP id a640c23a62f3a-ab38b49a5cbmr1452836066b.12.1738065703568; Tue, 28 Jan 2025 04:01:43 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:43 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 10/12] iio: accel: adxl345: add freefall feature Date: Tue, 28 Jan 2025 12:00:58 +0000 Message-Id: <20250128120100.205523-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the freefall detection of the sensor together with a threshold and time parameter. Add sysfs handle to enable/disable the feature and introduce another sysfs macro. This is the third sysfs macro for sysfs handles of this sensor. The three sysfs macros allow to cover all sensor features and parameters. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 127 +++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index ef0a12fd59be..62d75d28b6fc 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -170,6 +170,9 @@ struct adxl345_state { u32 tap_window_us; bool tap_suppressed; + u8 ff_value; + u32 ff_time_ms; + __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE + 1] __aligned(IIO_DMA_MINALIGN); }; @@ -187,6 +190,11 @@ static struct iio_event_spec adxl345_events[] = { .dir = IIO_EV_DIR_DOUBLETAP, .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE), }, + { + /* free fall */ + .type = IIO_EV_TYPE_MAG, + .dir = IIO_EV_DIR_FALLING, + }, }; #define ADXL345_CHANNEL(index, reg, axis) { \ @@ -442,6 +450,61 @@ static int adxl345_set_tap_latent(struct adxl345_state *st, u32 val_int, return _adxl345_set_tap_time(st, ADXL345_TAP_TIME_LATENT, val_fract_us); } +/* ff */ + +static int adxl345_is_ff_en(struct adxl345_state *st, bool *en) +{ + int ret; + unsigned int regval; + + ret = adxl345_read_interrupts(st, ®val); + if (ret) + return ret; + + *en = FIELD_GET(ADXL345_INT_FREE_FALL, st->int_map) > 0; + + return 0; +} + +static int adxl345_set_ff_en(struct adxl345_state *st, bool en) +{ + bool ff_en = en && st->ff_value > 0 && st->ff_time_ms > 0; + + adxl345_intmap_switch_bit(st, ff_en, ADXL345_INT_FREE_FALL); + + return adxl345_write_interrupts(st); +} + +static int adxl345_set_ff_value(struct adxl345_state *st, u8 val) +{ + st->ff_value = val; + + return regmap_write(st->regmap, ADXL345_REG_THRESH_FF, val); +} + +static int adxl345_set_ff_time(struct adxl345_state *st, u32 val_int, + u32 val_fract_us) +{ + unsigned int regval; + int val_ms; + + /* + * max value is 255 * 5000 us = 1.275000 seconds + * + * Note: the scaling is similar to the scaling in the ADXL380 + */ + if (1000000 * val_int + val_fract_us > 1275000) + return -EINVAL; + + val_ms = val_int * 1000 + DIV_ROUND_UP(val_fract_us, 1000); + st->ff_time_ms = val_ms; + + regval = DIV_ROUND_CLOSEST(val_ms, 5); + + /* Values between 100ms and 350ms (0x14 to 0x46) are recommended. */ + return regmap_write(st->regmap, ADXL345_REG_TIME_FF, min(regval, 0xff)); +} + static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -711,6 +774,49 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } } +#define ADXL345_generate_iio_dev_attr_INT(A, B, C) \ + static ssize_t in_accel_##A##_##B##_##C##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ + { \ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); \ + struct adxl345_state *st = iio_priv(indio_dev); \ + int val; \ + \ + val = st->B##_##C; \ + \ + return iio_format_value(buf, IIO_VAL_INT, 1, &val); \ + } \ + \ + static ssize_t in_accel_##A##_##B##_##C##_store(struct device *dev, \ + struct device_attribute *attr, \ + const char *buf, size_t len) \ + { \ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); \ + struct adxl345_state *st = iio_priv(indio_dev); \ + int val, ret; \ + \ + ret = kstrtoint(buf, 0, &val); \ + if (ret) \ + return ret; \ + \ + if (val < 0 || val > 255) \ + return -EINVAL; \ + \ + ret = adxl345_set_measure_en(st, false); \ + if (ret) \ + return ret; \ + \ + adxl345_set_##B##_##C(st, val); \ + \ + ret = adxl345_set_measure_en(st, true); \ + if (ret) \ + return ret; \ + \ + return len; \ + } \ + static IIO_DEVICE_ATTR_RW(in_accel_##A##_##B##_##C, 0) + #define ADXL345_generate_iio_dev_attr_EN(A, B) \ static ssize_t in_accel_##A##_##B##_en_show(struct device *dev, \ struct device_attribute *attr, \ @@ -798,13 +904,20 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } \ static IIO_DEVICE_ATTR_RW(in_accel_##A##_##C##_##E, 0) +ADXL345_generate_iio_dev_attr_INT(freefall, ff, value); + ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_singletap, tap, duration, MICRO, us); ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, window, MICRO, us); ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, latent, MICRO, us); +ADXL345_generate_iio_dev_attr_FRACTIONAL(freefall, ff, time, MILLI, ms); +ADXL345_generate_iio_dev_attr_EN(freefall, ff); ADXL345_generate_iio_dev_attr_EN(gesture_doubletap, suppressed); static struct attribute *adxl345_event_attrs[] = { + &iio_dev_attr_in_accel_freefall_ff_en.dev_attr.attr, + &iio_dev_attr_in_accel_freefall_ff_value.dev_attr.attr, + &iio_dev_attr_in_accel_freefall_time_ms.dev_attr.attr, &iio_dev_attr_in_accel_gesture_singletap_duration_us.dev_attr.attr, &iio_dev_attr_in_accel_gesture_doubletap_suppressed_en.dev_attr.attr, &iio_dev_attr_in_accel_gesture_doubletap_latent_us.dev_attr.attr, @@ -1041,6 +1154,17 @@ static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat, return ret; } + if (FIELD_GET(ADXL345_INT_FREE_FALL, int_stat)) { + ret = iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + IIO_MOD_X_AND_Y_AND_Z, + IIO_EV_TYPE_MAG, + IIO_EV_DIR_FALLING), + ts); + if (ret) + return ret; + } + return -ENOENT; } @@ -1148,6 +1272,9 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st->tap_window_us = 20; /* 20 [0x14] -> .025 */ st->tap_latent_us = 20; /* 20 [0x14] -> .025 */ + st->ff_value = 8; /* 8 [0x08] */ + st->ff_time_ms = 32; /* 32 [0x20] -> 0.16 */ + indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; indio_dev->modes = INDIO_DIRECT_MODE; From patchwork Tue Jan 28 12:00:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952492 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A1DD1B0404; Tue, 28 Jan 2025 12:01:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065708; cv=none; b=V02HpNcIDIRcRCu0yvvu1WiedgA3DkjNjhQ3IBM+H/ch744J+uL3kNMNAZgoPSGFuw0Bk9eQK0+WZVFYeQ59gMwQ73J5pIk7ffUSx2EMQScNq8DV2xDJ3DBYfsHKtUe2glJX6PpaxaV5cbvlC8992Rgr9crd74DJ1oBrCBDt95A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065708; c=relaxed/simple; bh=ooSE/z8nHD4qO4yh+O7AGHDn8LEVgPgbJnX/wvZzEBY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JGxlybmnB00Jlt4FCqKchzWWXIyNh/A3fyqLeZg5VS+ZdI+qR2ptSsWeMlwi1cpck634LlsCpkz7vS/4oAxLuHO2gDH4lJFjG721ggb8apouHvFmWSsDy4SPYw0o5jvkSRbDCSaUg2n1kL/LkN8MghHM4fpYHG2APWidZ3IDaE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=isT3o6LU; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="isT3o6LU" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-aa6965ad2a5so82414866b.3; Tue, 28 Jan 2025 04:01:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065705; x=1738670505; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uxJICuKJGEvgJGZrYDbWlzD+OXLpb5BbFr8sRyR6UcY=; b=isT3o6LU35ARHilax//rRup7vzE0zxYHBbUmUjZiI3R+pto22HCi80wjm/3Anlxnru IVpoExBm9VeKUSyQiP5vfsvg5gnkDrTOhdhft8RYo8rrFtWMG9OFfJ+qJV+pzc5L1kWH ZEor3j2ZY4zTXuOXF1q2M8BZ2Q2tvyOT99jkuuDf2KFxBb4HQR8DRMlElm9B+YRMypep 9990LaiG/F1T1vJli6G+xaqfWQ/20rYGN8TdK0m6OUony0ALVJLJ2s5H+aemVyh5oEMB De3Im76rVR1XKEXlOUAdtmi1is0+SqW7wMhAUU4hQg0xRwOns3aynIvf/uUHGezlVWug cJSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065705; x=1738670505; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uxJICuKJGEvgJGZrYDbWlzD+OXLpb5BbFr8sRyR6UcY=; b=oQY/Wq4k0bQQkQLKKOpQ5/zj/0rP9jVVW5VwyQVNTmbzqCZ8Obb/o3sYViuuonDP31 IcP39/IE2jcLE8KPeGcvJu6PBguOnSB7ZE6EBItCl5XTXxCHUcwG+HfBv5w2IYu+85dR zD3DnqmogGVtQ/uRMD8P8Z2Z//+0q+x/0oDk+nG5NDET4fu7YL6GNLHfEc6Q+7hOxmLO jyZWDQh4zWCjBRRvuaFo31y+HOo7Qv5UfLECizqiozUJvPxOF0wZrYdCiJIOqpcfPPv8 BD9Y/FGeGvWf6dC+l8/yOY3eocvDygGUPxqHFij/5iAfjoR86DNwKTMjoBiq5M4uEofN O/xg== X-Forwarded-Encrypted: i=1; AJvYcCUUDUXXBddW5B8xox3GgJzjkGgrXGkr3pEfoOBhgrItrCmCFjo+DZHByylJnnbcdb4u3LZp/dPHehWMfDk=@vger.kernel.org X-Gm-Message-State: AOJu0YzReCnQcyFsk/IAEBSF+ExT9ZIGXuVrFEEHoZZsIyqpG48rzI5g 6J22HUCmQK9o35HZBON/JFEQvdH9YdHhwFnXMuajO6QkOPbxqhCE X-Gm-Gg: ASbGncsZNWcnrFGPQeK4VYmeEAZbAwWK2Bts2FtxpgTh216t2UtwlxARpwACNoIDhrG Ll5C0rodHQSDKQqiwg2kfniF18C8uiU2hxrdr2a6LN7ObdYZKDaSjYtO6lWH7/HqLZOKKWsO9if MTHscL8D+1KD5tQXZl4Uem453WmURM3GYkPW7Ey1dzdBD3jVilqxIGHJr08Ke4tbdI2+NEb4lKw QTz+GGqutA+5p54UkHCDgPmkdmWjMwZ2282e2257ayGYscduxvj9eeNgzre/p3bgnkEzbNuljLc vWYHXvQy5Mn5O8LXfV1cM6UdBkKqiZuh0ySF5nagbTtElD6yaZbIFAt7v1L3oGLy5/9gSA== X-Google-Smtp-Source: AGHT+IGxj/91ewZJORBmpFEOruy6g6SVAlbUfFsQe5K8dPIXsXkBeA4a8MMlRE9sLMYAAvdHzoMHGA== X-Received: by 2002:a17:907:969f:b0:ab3:2719:ca30 with SMTP id a640c23a62f3a-ab38b35c602mr1760150466b.10.1738065704501; Tue, 28 Jan 2025 04:01:44 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:44 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 11/12] iio: accel: adxl345: add activity feature Date: Tue, 28 Jan 2025 12:00:59 +0000 Message-Id: <20250128120100.205523-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the handling of activity events, also add sysfs entries to configure threshold values to trigger the event. Allow to push the event over to the iio channel. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 158 ++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 62d75d28b6fc..94c3ad818ba5 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -121,6 +121,8 @@ #define ADXL345_REG_TAP_AXIS_MSK GENMASK(2, 0) #define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3) +#define ADXL345_REG_ACT_AXIS_MSK GENMASK(6, 4) +#define ADXL345_REG_ACT_ACDC_MSK BIT(7) enum adxl345_axis { ADXL345_Z_EN = BIT(0), @@ -163,6 +165,10 @@ struct adxl345_state { u8 watermark; u8 fifo_mode; + u32 act_axis_ctrl; + bool act_ac; + u8 act_value; + u32 tap_axis_ctrl; u8 tap_threshold; u32 tap_duration_us; @@ -177,6 +183,11 @@ struct adxl345_state { }; static struct iio_event_spec adxl345_events[] = { + { + /* activity */ + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + }, { /* single tap */ .type = IIO_EV_TYPE_GESTURE, @@ -276,6 +287,117 @@ static inline int adxl345_write_interrupts(struct adxl345_state *st) return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, st->int_map); } +/* act/inact */ + +static int adxl345_write_act_axis(struct adxl345_state *st, bool en) +{ + int ret; + + /* + * A setting of 0 selects dc-coupled operation, and a setting of 1 + * enables ac-coupled operation. In dc-coupled operation, the current + * acceleration magnitude is compared directly with THRESH_ACT and + * THRESH_INACT to determine whether activity or inactivity is + * detected. + * + * In ac-coupled operation for activity detection, the acceleration + * value at the start of activity detection is taken as a reference + * value. New samples of acceleration are then compared to this + * reference value, and if the magnitude of the difference exceeds the + * THRESH_ACT value, the device triggers an activity interrupt. + * + * Similarly, in ac-coupled operation for inactivity detection, a + * reference value is used for comparison and is updated whenever the + * device exceeds the inactivity threshold. After the reference value + * is selected, the device compares the magnitude of the difference + * between the reference value and the current acceleration with + * THRESH_INACT. If the difference is less than the value in + * THRESH_INACT for the time in TIME_INACT, the device is considered + * inactive and the inactivity interrupt is triggered. + */ + ret = regmap_update_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL, + ADXL345_REG_ACT_ACDC_MSK, st->act_ac); + if (ret) + return ret; + + /* + * The ADXL345 allows for individually enabling/disabling axis for + * activity and inactivity detection, respectively. Here both axis are + * kept in sync, i.e. an axis will be generally enabled or disabled for + * both equally, activity and inactivity detection. + */ + st->act_axis_ctrl = en + ? st->act_axis_ctrl | ADXL345_REG_ACT_AXIS_MSK + : st->act_axis_ctrl & ~ADXL345_REG_ACT_AXIS_MSK; + + ret = regmap_update_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL, + ADXL345_REG_ACT_AXIS_MSK, + st->act_axis_ctrl); + if (ret) + return ret; + + return 0; +} + +static int adxl345_set_act_int(struct adxl345_state *st) +{ + bool args_valid; + bool axis_en; + + axis_en = FIELD_GET(ADXL345_REG_ACT_AXIS_MSK, st->act_axis_ctrl) > 0; + args_valid = axis_en && st->act_value > 0; + adxl345_intmap_switch_bit(st, args_valid, ADXL345_INT_ACTIVITY); + + return adxl345_write_interrupts(st); +} + +static int _adxl345_is_act_en(struct adxl345_state *st, bool *en) +{ + int ret; + unsigned int regval; + + ret = adxl345_read_interrupts(st, ®val); + if (ret) + return ret; + + *en = FIELD_GET(ADXL345_INT_ACTIVITY, regval) > 0; + + return 0; +} + +static int _adxl345_set_act_en(struct adxl345_state *st, bool en) +{ + int ret; + + ret = adxl345_write_act_axis(st, en); + if (ret) + return ret; + + return adxl345_set_act_int(st); +} + +static int adxl345_is_act_en(struct adxl345_state *st, bool *en) +{ + return _adxl345_is_act_en(st, en); +} + +static int adxl345_set_act_en(struct adxl345_state *st, bool en) +{ + return _adxl345_set_act_en(st, en); +} + +static int _adxl345_set_act_value(struct adxl345_state *st, u8 val) +{ + st->act_value = val; + + return regmap_write(st->regmap, ADXL345_REG_THRESH_ACT, val); +} + +static int adxl345_set_act_value(struct adxl345_state *st, u8 val) +{ + return _adxl345_set_act_value(st, val); +} + /* tap */ static int adxl345_write_tap_axis(struct adxl345_state *st, @@ -904,6 +1026,7 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } \ static IIO_DEVICE_ATTR_RW(in_accel_##A##_##C##_##E, 0) +ADXL345_generate_iio_dev_attr_INT(activity, act, value); ADXL345_generate_iio_dev_attr_INT(freefall, ff, value); ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_singletap, tap, duration, MICRO, us); @@ -911,10 +1034,13 @@ ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, window, MICRO, ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, latent, MICRO, us); ADXL345_generate_iio_dev_attr_FRACTIONAL(freefall, ff, time, MILLI, ms); +ADXL345_generate_iio_dev_attr_EN(activity, act); ADXL345_generate_iio_dev_attr_EN(freefall, ff); ADXL345_generate_iio_dev_attr_EN(gesture_doubletap, suppressed); static struct attribute *adxl345_event_attrs[] = { + &iio_dev_attr_in_accel_activity_act_en.dev_attr.attr, + &iio_dev_attr_in_accel_activity_act_value.dev_attr.attr, &iio_dev_attr_in_accel_freefall_ff_en.dev_attr.attr, &iio_dev_attr_in_accel_freefall_ff_value.dev_attr.attr, &iio_dev_attr_in_accel_freefall_time_ms.dev_attr.attr, @@ -1087,20 +1213,25 @@ static int adxl345_get_status(struct adxl345_state *st, unsigned int *int_stat, { unsigned int regval; bool check_tap_stat; + bool check_act_stat; *act_tap_dir = IIO_NO_MOD; check_tap_stat = FIELD_GET(ADXL345_REG_TAP_AXIS_MSK, st->tap_axis_ctrl) > 0; + check_act_stat = FIELD_GET(ADXL345_REG_ACT_AXIS_MSK, st->act_axis_ctrl) > 0; - if (check_tap_stat) { + if (check_tap_stat || check_act_stat) { /* ACT_TAP_STATUS should be read before clearing the interrupt */ if (regmap_read(st->regmap, ADXL345_REG_ACT_TAP_STATUS, ®val)) return -EINVAL; - if (FIELD_GET(ADXL345_Z_EN, regval) > 0) + if ((FIELD_GET(ADXL345_Z_EN, regval >> 4) + | FIELD_GET(ADXL345_Z_EN, regval)) > 0) *act_tap_dir = IIO_MOD_Z; - else if (FIELD_GET(ADXL345_Y_EN, regval) > 0) + else if ((FIELD_GET(ADXL345_Y_EN, regval >> 4) + | FIELD_GET(ADXL345_Y_EN, regval)) > 0) *act_tap_dir = IIO_MOD_Y; - else if (FIELD_GET(ADXL345_X_EN, regval) > 0) + else if ((FIELD_GET(ADXL345_X_EN, regval >> 4) + | FIELD_GET(ADXL345_X_EN, regval)) > 0) *act_tap_dir = IIO_MOD_X; } @@ -1154,6 +1285,17 @@ static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat, return ret; } + if (FIELD_GET(ADXL345_INT_ACTIVITY, int_stat)) { + ret = iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + act_tap_dir, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + ts); + if (ret) + return ret; + } + if (FIELD_GET(ADXL345_INT_FREE_FALL, int_stat)) { ret = iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, @@ -1264,6 +1406,13 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, return -ENODEV; st->fifo_delay = fifo_delay_default; + /* + * If the feature is enabled, scan all axis for activity and or + * inactivity, and set activity and inactivity to the same ac / dc + * setup. + */ + st->act_axis_ctrl = ADXL345_REG_ACT_AXIS_MSK; + st->act_ac = 0; st->int_map = 0x00; /* reset interrupts */ /* Init with reasonable values */ @@ -1272,6 +1421,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st->tap_window_us = 20; /* 20 [0x14] -> .025 */ st->tap_latent_us = 20; /* 20 [0x14] -> .025 */ + st->act_value = 6; /* 6 [0x06] */ st->ff_value = 8; /* 8 [0x08] */ st->ff_time_ms = 32; /* 32 [0x20] -> 0.16 */ From patchwork Tue Jan 28 12:01:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13952494 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8F5E1B412A; Tue, 28 Jan 2025 12:01:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065709; cv=none; b=d1fiPy/GwmNGBffeIY4ufQH12PtsGffzVHcVUXz/RlcREA3k9T1Q1BuLspktXXAg9pZx8ogjNWGDKi9LYrbyLO3bjtytOquT0sQqJHOWclfwsmAvQ+EdLHvOaVqyv6/R6j0zFifwRuge6D4eOmDmorYGYcxRm2fMyRUakIrOtQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738065709; c=relaxed/simple; bh=b0Y4qK+EtkUXFA8A7omBr2akO/7BYmyJxAD6GQedwaI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I3Zng/K9E9M6vmnAh1lpW+5rN8g+NUacLnE2rf0UHrVPDwgIeUB8XDazDTdPaMJHi3yKQKWAWKHj4agVPoN/b5kXtZLHV1wMv5cxpYkVlnsgYNRH7r/t+i/fNEN6EyNYjTadHNVfvoH3bmdm1W0GRObUrnsk86pXSLZtsiCbCM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=g2dDZVCU; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g2dDZVCU" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-aa6a38e64e4so93391966b.0; Tue, 28 Jan 2025 04:01:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738065706; x=1738670506; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZZAln2CNkbhURcsDHLTlOdLPcb+aZKD8RZcU3/8yIGQ=; b=g2dDZVCUpGPDMLQOS8BfMQDp0WVAn7y8RReHjbFc7xQkDyMg9y57zy7b8jzzr1RHok I7lSKUllFw7lFlA99/baCu35R03fsuk4y/6juI2feZxbRPas4RoPdviOUs3/lkHFHnUO 8NcCkqXBNDVH3ORcURZMfnAKOL6T0FpsZLqwhtuHjncZM3FB7qk4Xev6pTti4PRngC3I G28cgizu5xmvFWuzYPDviLsANYWSmsDE0Ni/mhh0CvlQiy0ufzc1QHwafBK2ZgtNBQlA imkS5uhDdLpyfHVbFmAbbwnmdUgbUVzPQmFusb3Q08TSvvs/9S0ZZDhPsIHwmndLMa5F WzFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738065706; x=1738670506; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZZAln2CNkbhURcsDHLTlOdLPcb+aZKD8RZcU3/8yIGQ=; b=LCl6/BLYS+FWVKPAJztKUSzHki6dNwZY41GDNFdn+SnIEx6EUADl7BubMVf7BAAkpy 7rrbpmnflCXSABBKsW4/XdOuHNauDjnlC49WJnbbZ6CtEVsWyWzlR0/zEb3Yy7FJe1Jc ORPxaHrAPFt3XmaabDzIG96C5R2jCdhLqeD70tuXf9S81oli8/ISP+XQUa4oKj5k0dZu Hqmlyq4/O10UJ9nPn8HTlWlaPlsTWNVNYL5Kua5I/Ni9Fbr3Kj8lFViYNZFnhQtal8im 0ipTVBQAxz9W19lwyk233rbHaYqGwrrNYfM0ArzSCZzy3Z/kKSDVt6dPvGDlxxNVwTDa fZqQ== X-Forwarded-Encrypted: i=1; AJvYcCUnA7Q6SwrGtIViZq4oVes0H/2QgVvVhyDkHXvgJoiJQO8z60SUvqQB/qjgPQRTrNGOqv4Er+62PwONIW8=@vger.kernel.org X-Gm-Message-State: AOJu0Yz3SKav6oR1uR4XOUsNuD7NbqWqpMQTwk1MVkTGT1vaVfyGXx9Y +Rp+969VvbdiqW39YgP3YgfifmgGz0OOAoP2afp7g9ZetOssl0nH X-Gm-Gg: ASbGncungpEbpZBfFeim9nItT1SO+fyA+gPR8N5zkj5mkM6Dw79uvGEkNAgr7dxTD3y 1hhW2faBB7KbUQVLLSf7vei7y70Y2RFt8N2w8ub9wT8LvyXxPlSJ7I3Q1WYBK7kOC2h9FboajYx buYEnITyj/Sp8EBBxNGaHAzoxBuwn2LooGCjaIR9GsyelbY1xMgIpuEHZaZx8KsaXUgFiwCOpBs dOSfX290JEhaIYk9hRRIpeGIyvc4vlAyyXC1/713/RAIWI/VKcAcN31iChC/4uL7sFOnDN3BEnO mUzkMffC4XSAULYhwZgKS8IdnE+W9CrVepc74PWMo6G0B6i+TXHK77k1jvQrzBhU4vGOAg== X-Google-Smtp-Source: AGHT+IFDKhCaAdGcEdaRC+OcWusjUkxRXv3jBSWYwfmcSpsWKk1kuqZr8WvKf3SyJy6JX3ErWqyLGQ== X-Received: by 2002:a17:907:1b20:b0:ab6:92dc:8b98 with SMTP id a640c23a62f3a-ab692dc9244mr478974066b.8.1738065705586; Tue, 28 Jan 2025 04:01:45 -0800 (PST) Received: from d9dabf0abd47.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab69f8555b7sm418865966b.71.2025.01.28.04.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jan 2025 04:01:45 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v1 12/12] iio: accel: adxl345: add inactivity feature Date: Tue, 28 Jan 2025 12:01:00 +0000 Message-Id: <20250128120100.205523-13-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250128120100.205523-1-l.rubusch@gmail.com> References: <20250128120100.205523-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add handling for inactivity events, together with threshold and timeout to trigger the event. The event could be used for ODR and g range reduction for power saving using low power modes or sleep modes, not covered by this patch. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 167 ++++++++++++++++++++++++++----- 1 file changed, 142 insertions(+), 25 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 94c3ad818ba5..b9f42c56e8f1 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -123,6 +123,8 @@ #define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3) #define ADXL345_REG_ACT_AXIS_MSK GENMASK(6, 4) #define ADXL345_REG_ACT_ACDC_MSK BIT(7) +#define ADXL345_REG_INACT_AXIS_MSK GENMASK(2, 0) +#define ADXL345_REG_INACT_ACDC_MSK BIT(3) enum adxl345_axis { ADXL345_Z_EN = BIT(0), @@ -155,6 +157,32 @@ static const unsigned int adxl345_tap_time_reg[3] = { [ADXL345_TAP_TIME_DUR] = ADXL345_REG_DUR, }; +/* activity/inactivity */ +enum adxl345_activity_type { + ADXL345_ACTIVITY, + ADXL345_INACTIVITY +}; + +static const unsigned int adxl345_act_int_reg[2] = { + [ADXL345_ACTIVITY] = ADXL345_INT_ACTIVITY, + [ADXL345_INACTIVITY] = ADXL345_INT_INACTIVITY, +}; + +static const unsigned int adxl345_act_thresh_reg[2] = { + [ADXL345_ACTIVITY] = ADXL345_REG_THRESH_ACT, + [ADXL345_INACTIVITY] = ADXL345_REG_THRESH_INACT, +}; + +static const unsigned int adxl345_act_acdc_msk[2] = { + [ADXL345_ACTIVITY] = ADXL345_REG_ACT_ACDC_MSK, + [ADXL345_INACTIVITY] = ADXL345_REG_INACT_ACDC_MSK +}; + +static const unsigned int adxl345_act_axis_msk[2] = { + [ADXL345_ACTIVITY] = ADXL345_REG_ACT_AXIS_MSK, + [ADXL345_INACTIVITY] = ADXL345_REG_INACT_AXIS_MSK +}; + struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; @@ -169,6 +197,11 @@ struct adxl345_state { bool act_ac; u8 act_value; + u32 inact_axis_ctrl; + bool inact_ac; + u8 inact_value; + u8 inact_time_s; + u32 tap_axis_ctrl; u8 tap_threshold; u32 tap_duration_us; @@ -188,6 +221,11 @@ static struct iio_event_spec adxl345_events[] = { .type = IIO_EV_TYPE_THRESH, .dir = IIO_EV_DIR_RISING, }, + { + /* inactivity */ + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + }, { /* single tap */ .type = IIO_EV_TYPE_GESTURE, @@ -289,7 +327,8 @@ static inline int adxl345_write_interrupts(struct adxl345_state *st) /* act/inact */ -static int adxl345_write_act_axis(struct adxl345_state *st, bool en) +static int adxl345_write_act_axis(struct adxl345_state *st, + enum adxl345_activity_type type, bool en) { int ret; @@ -316,7 +355,9 @@ static int adxl345_write_act_axis(struct adxl345_state *st, bool en) * inactive and the inactivity interrupt is triggered. */ ret = regmap_update_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL, - ADXL345_REG_ACT_ACDC_MSK, st->act_ac); + adxl345_act_acdc_msk[type], + (type == ADXL345_ACTIVITY + ? st->act_ac : st->inact_ac)); if (ret) return ret; @@ -326,32 +367,52 @@ static int adxl345_write_act_axis(struct adxl345_state *st, bool en) * kept in sync, i.e. an axis will be generally enabled or disabled for * both equally, activity and inactivity detection. */ - st->act_axis_ctrl = en - ? st->act_axis_ctrl | ADXL345_REG_ACT_AXIS_MSK - : st->act_axis_ctrl & ~ADXL345_REG_ACT_AXIS_MSK; + if (type == ADXL345_ACTIVITY) { + st->act_axis_ctrl = en + ? st->act_axis_ctrl | ADXL345_REG_ACT_AXIS_MSK + : st->act_axis_ctrl & ~ADXL345_REG_ACT_AXIS_MSK; + + ret = regmap_update_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL, + adxl345_act_axis_msk[type], + st->act_axis_ctrl); + if (ret) + return ret; - ret = regmap_update_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL, - ADXL345_REG_ACT_AXIS_MSK, - st->act_axis_ctrl); - if (ret) - return ret; + } else { + st->inact_axis_ctrl = en + ? st->inact_axis_ctrl | ADXL345_REG_INACT_AXIS_MSK + : st->inact_axis_ctrl & ~ADXL345_REG_INACT_AXIS_MSK; + ret = regmap_update_bits(st->regmap, ADXL345_REG_ACT_INACT_CTRL, + adxl345_act_axis_msk[type], + st->inact_axis_ctrl); + if (ret) + return ret; + } return 0; } -static int adxl345_set_act_int(struct adxl345_state *st) +static int adxl345_set_act_int(struct adxl345_state *st, + enum adxl345_activity_type type) { bool args_valid; bool axis_en; - axis_en = FIELD_GET(ADXL345_REG_ACT_AXIS_MSK, st->act_axis_ctrl) > 0; - args_valid = axis_en && st->act_value > 0; - adxl345_intmap_switch_bit(st, args_valid, ADXL345_INT_ACTIVITY); + if (type == ADXL345_ACTIVITY) { + axis_en = FIELD_GET(ADXL345_REG_ACT_AXIS_MSK, st->act_axis_ctrl) > 0; + args_valid = axis_en && st->act_value > 0; + } else { + axis_en = FIELD_GET(ADXL345_REG_INACT_AXIS_MSK, st->inact_axis_ctrl) > 0; + args_valid = axis_en && st->inact_value > 0 && + st->inact_time_s > 0; + } + adxl345_intmap_switch_bit(st, args_valid, adxl345_act_int_reg[type]); return adxl345_write_interrupts(st); } -static int _adxl345_is_act_en(struct adxl345_state *st, bool *en) +static int _adxl345_is_act_en(struct adxl345_state *st, + enum adxl345_activity_type type, bool *en) { int ret; unsigned int regval; @@ -360,42 +421,76 @@ static int _adxl345_is_act_en(struct adxl345_state *st, bool *en) if (ret) return ret; - *en = FIELD_GET(ADXL345_INT_ACTIVITY, regval) > 0; + *en = (adxl345_act_int_reg[type] & regval) > 0; return 0; } -static int _adxl345_set_act_en(struct adxl345_state *st, bool en) +static int _adxl345_set_act_en(struct adxl345_state *st, + enum adxl345_activity_type type, bool en) { int ret; - ret = adxl345_write_act_axis(st, en); + ret = adxl345_write_act_axis(st, type, en); if (ret) return ret; - return adxl345_set_act_int(st); + return adxl345_set_act_int(st, type); } static int adxl345_is_act_en(struct adxl345_state *st, bool *en) { - return _adxl345_is_act_en(st, en); + return _adxl345_is_act_en(st, ADXL345_ACTIVITY, en); } static int adxl345_set_act_en(struct adxl345_state *st, bool en) { - return _adxl345_set_act_en(st, en); + return _adxl345_set_act_en(st, ADXL345_ACTIVITY, en); } -static int _adxl345_set_act_value(struct adxl345_state *st, u8 val) +static int adxl345_is_inact_en(struct adxl345_state *st, bool *en) { - st->act_value = val; + return _adxl345_is_act_en(st, ADXL345_INACTIVITY, en); +} - return regmap_write(st->regmap, ADXL345_REG_THRESH_ACT, val); +static int adxl345_set_inact_en(struct adxl345_state *st, bool en) +{ + return _adxl345_set_act_en(st, ADXL345_INACTIVITY, en); +} + +static int _adxl345_set_act_value(struct adxl345_state *st, + enum adxl345_activity_type type, u8 val) +{ + switch (type) { + case ADXL345_ACTIVITY: + st->act_value = val; + break; + case ADXL345_INACTIVITY: + st->inact_value = val; + break; + default: + return -EINVAL; + } + + return regmap_write(st->regmap, adxl345_act_thresh_reg[type], val); } static int adxl345_set_act_value(struct adxl345_state *st, u8 val) { - return _adxl345_set_act_value(st, val); + return _adxl345_set_act_value(st, ADXL345_ACTIVITY, val); +} + +static int adxl345_set_inact_value(struct adxl345_state *st, u8 val) +{ + return _adxl345_set_act_value(st, ADXL345_INACTIVITY, val); +} + +static int adxl345_set_inact_time_s(struct adxl345_state *st, u32 val_s) +{ + st->inact_time_s = min(val_s, 0xff); + + return regmap_write(st->regmap, ADXL345_REG_TIME_INACT, + st->inact_time_s); } /* tap */ @@ -1027,6 +1122,8 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, static IIO_DEVICE_ATTR_RW(in_accel_##A##_##C##_##E, 0) ADXL345_generate_iio_dev_attr_INT(activity, act, value); +ADXL345_generate_iio_dev_attr_INT(activity, inact, value); +ADXL345_generate_iio_dev_attr_INT(activity, inact, time_s); ADXL345_generate_iio_dev_attr_INT(freefall, ff, value); ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_singletap, tap, duration, MICRO, us); @@ -1035,12 +1132,16 @@ ADXL345_generate_iio_dev_attr_FRACTIONAL(gesture_doubletap, tap, latent, MICRO, ADXL345_generate_iio_dev_attr_FRACTIONAL(freefall, ff, time, MILLI, ms); ADXL345_generate_iio_dev_attr_EN(activity, act); +ADXL345_generate_iio_dev_attr_EN(activity, inact); ADXL345_generate_iio_dev_attr_EN(freefall, ff); ADXL345_generate_iio_dev_attr_EN(gesture_doubletap, suppressed); static struct attribute *adxl345_event_attrs[] = { &iio_dev_attr_in_accel_activity_act_en.dev_attr.attr, &iio_dev_attr_in_accel_activity_act_value.dev_attr.attr, + &iio_dev_attr_in_accel_activity_inact_en.dev_attr.attr, + &iio_dev_attr_in_accel_activity_inact_value.dev_attr.attr, + &iio_dev_attr_in_accel_activity_inact_time_s.dev_attr.attr, &iio_dev_attr_in_accel_freefall_ff_en.dev_attr.attr, &iio_dev_attr_in_accel_freefall_ff_value.dev_attr.attr, &iio_dev_attr_in_accel_freefall_time_ms.dev_attr.attr, @@ -1296,6 +1397,17 @@ static int adxl345_push_event(struct iio_dev *indio_dev, int int_stat, return ret; } + if (FIELD_GET(ADXL345_INT_INACTIVITY, int_stat)) { + ret = iio_push_event(indio_dev, + IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, + IIO_MOD_X_OR_Y_OR_Z, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_FALLING), + ts); + if (ret) + return ret; + } + if (FIELD_GET(ADXL345_INT_FREE_FALL, int_stat)) { ret = iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, @@ -1412,6 +1524,8 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, * setup. */ st->act_axis_ctrl = ADXL345_REG_ACT_AXIS_MSK; + st->inact_axis_ctrl = ADXL345_REG_INACT_AXIS_MSK; + st->inact_ac = 0; /* 0 [dc] */ st->act_ac = 0; st->int_map = 0x00; /* reset interrupts */ @@ -1422,6 +1536,9 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st->tap_latent_us = 20; /* 20 [0x14] -> .025 */ st->act_value = 6; /* 6 [0x06] */ + st->inact_value = 4; /* 4 [0x04] */ + st->inact_time_s = 3; /* 3 [0x03] -> 3 */ + st->ff_value = 8; /* 8 [0x08] */ st->ff_time_ms = 32; /* 32 [0x20] -> 0.16 */