From patchwork Tue Jan 28 15:51:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6C5CC02194 for ; Tue, 28 Jan 2025 16:05:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 662ED10E6AC; Tue, 28 Jan 2025 16:05:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="V9EoaXnT"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9399910E6AA; Tue, 28 Jan 2025 16:05:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738080359; x=1769616359; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=bDgT4VIxg/jIp6PmRyFC4l9u0NF6je1nknLzt8juq/g=; b=V9EoaXnT91huA6E584nb9B/8GaIHjIVwGTv90MsMctIRA2fVb9WTFLHF W9vQYlsPoMJViUEdNC7sBj6+BZo1nXUVK3R7nqdR1Hkx5nYnQvjIQ83EN DfdZFCSKGeToizu50SuXV0fhM9XJThg2CHiejQiPnexk7TO+Y44za2vPh quLJRR/sN3C+eDrjyDq3SlKOw8n1i8S0d/480KWfL8k4ol515J5yqx2OP dixz9TunU5GRFfOW5gAuxLYEEFQjK7VDlJXXY33e0O5/2jHhcvZBF8Rhf 0GS2vcrXB0EDj1UeI85vQVp4gd4N1gU5DGFephFj4pnBClk33fLijWqlw g==; X-CSE-ConnectionGUID: TWFBjtEoQGSLcg3IsjIsBw== X-CSE-MsgGUID: c/6mjQwcSNWRO89Ej+k6IQ== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38744996" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38744996" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:05:58 -0800 X-CSE-ConnectionGUID: NBcLSwP0S5OaxNJp9KQRTA== X-CSE-MsgGUID: ZwmX8mAHSKWysi0r6ngizg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976880" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:05:56 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:07 +0530 Subject: [PATCH v8 01/14] drm: Define histogram structures exposed to user MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-1-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display Histogram is an array of bins and can be generated in many ways referred to as modes. Ex: HSV max(RGB), Wighted RGB etc. Understanding the histogram data format(Ex: HSV max(RGB)) Histogram is just the pixel count. For a maximum resolution of 10k (10240 x 4320 = 44236800) 25 bits should be sufficient to represent this along with a buffer of 7 bits(future use) u32 is being considered. max(RGB) can be 255 i.e 0xFF 8 bit, considering the most significant 5 bits, hence 32 bins. Below mentioned algorithm illustrates the histogram generation in hardware. hist[32] = {0}; for (i = 0; i < resolution; i++) { bin = max(RGB[i]); bin = bin >> 3; /* consider the most significant bits */ hist[bin]++; } If the entire image is Red color then max(255,0,0) is 255 so the pixel count of each pixels will be placed in the last bin. Hence except hist[31] all other bins will have a value zero. Generated histogram in this case would be hist[32] = {0,0,....44236800} Description of the structures, properties defined are documented in the header file include/uapi/drm/drm_mode.h v8: Added doc for HDR planes, removed reserved variables (Dmitry) Signed-off-by: Arun R Murthy --- include/uapi/drm/drm_mode.h | 65 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index c082810c08a8b234ef2672ecf54fc8c05ddc2bd3..b8b7b18843ae7224263a9c61b20ac6cbf5df69e9 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1355,6 +1355,71 @@ struct drm_mode_closefb { __u32 pad; }; +/** + * enum drm_mode_histogram + * + * @DRM_MODE_HISTOGRAM_HSV_MAX_RGB: + * Maximum resolution at present 10k, 10240x4320 = 44236800 + * can be denoted in 25bits. With an additional 7 bits in buffer each bin + * can be a u32 value. + * For SDL, Maximum value of max(RGB) is 255, so max 255 bins. + * If the most significant 5 bits are considered, then bins = 2^5 + * will be 32 bins. + * For HDR, maximum value of max(RGB) is 65535, so max 65535 bins. + * For illustration consider a full RED image of 10k resolution considering all + * 8 bits histogram would look like hist[255] = {0,0,....44236800} with SDR + * plane similarly with HDR the same would look like hist[65535] = + * {0,0,0,....44236800} + */ +enum drm_mode_histogram { + DRM_MODE_HISTOGRAM_HSV_MAX_RGB = 0x01, +}; + +/** + * struct drm_histogram_caps + * + * @histogram_mode: histogram generation modes, defined in the + * enum drm_mode_histogram + * @bins_count: number of bins for a chosen histogram mode. For illustration + * refer the above defined histogram mode. + */ +struct drm_histogram_caps { + __u32 histogram_mode; + __u32 bins_count; +}; + +/** + * struct drm_histogram_config + * + * @hist_mode_data: address to the histogram mode specific data if any + * @nr_hist_mode_data: number of elements pointed by the address in + * hist_mode_data + * @hist_mode: histogram mode(HSV max(RGB), RGB, LUMA etc) + * @enable: flag to enable/disable histogram + */ +struct drm_histogram_config { + __u64 hist_mode_data; + __u32 nr_hist_mode_data; + enum drm_mode_histogram hist_mode; + bool enable; +}; + +/** + * struct drm_histogram + * + * @config: histogram configuration data pointed by struct drm_histogram_config + * @data_ptr: pointer to the array of histogram. + * Histogram is an array of bins. Data format for each bin depends + * on the histogram mode. Refer to the above histogram modes for + * more information. + * @nr_elements: number of bins in the histogram. + */ +struct drm_histogram { + struct drm_histogram_config config; + __u64 data_ptr; + __u32 nr_elements; +}; + #if defined(__cplusplus) } #endif From patchwork Tue Jan 28 15:51:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09FF8C0218A for ; Tue, 28 Jan 2025 16:06:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 943D410E6A6; Tue, 28 Jan 2025 16:06:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="E+okObu3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id AFC4110E6B7; Tue, 28 Jan 2025 16:06:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738080361; x=1769616361; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ia+sh2CQwce45X1pCiIjAZyP9C4WGk7gW7FRcb6u2S8=; b=E+okObu3wnT8ibOR++lyaXAlvN+bwOUyryu2qMktODgMioY4ehhV/ndx eli7G9na0BPUmDgk33SEiam00nOvtlQsKGitkuhnZg+eDxDe2rFG6+Tbi TDvH0vXwO2YiTKsvSQjDihcTGX23r5eJvpHAcwSxVjj4qICKpFKZJ9GDj kP6MGD7uhI0mT5NCx8ti0eIj882HnyqUdWBy9+UQT6h1mjy4gvDV6Ebsb 70lAO/0LSLHKD8Q1pcq7+JMdgjL2vmHbyWdtmMjKXyQ/wwMFR/BB85HhM 7YgTodcqvi3bFLdNIxUoPREa44YSSsclV6kOXSkDv/y8P0P7LsX/Apo/s Q==; X-CSE-ConnectionGUID: /kJyrDAbQo2KBI9qBkeExw== X-CSE-MsgGUID: FUQI8IH9R6CbkIEML/bIdA== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745002" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745002" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:01 -0800 X-CSE-ConnectionGUID: CoIglWB1Srqz2MRmEsMa3w== X-CSE-MsgGUID: 1wQlZBQ/Qli27WIwhL1xfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976889" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:05:58 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:08 +0530 Subject: [PATCH v8 02/14] drm: Define ImageEnhancemenT LUT structures exposed to user MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-2-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" ImageEnhancemenT(IET) hardware interpolates the LUT value to generate the enhanced output image. LUT takes an input value, outputs a new value based on the data within the LUT. 1D LUT can remap individual input values to new output values based on the LUT sample. LUT can be interpolated by the hardware by multiple modes Ex: Direct Lookup LUT, Multiplicative LUT etc The list of supported mode by hardware along with the format(exponent mantissa) is exposed to user by the iet_lut_caps property. Maximum format being 8.24 i.e 8 exponent and 24 mantissa. For illustration a hardware supporting 1.9 format denotes this as 0x10001FF. In order to know the exponent do a bitwise AND with 0xF000000. The LUT value to be provided by user would be a 10bit value with 1 bit integer and 9 bit fractional value. Multiple formats can be supported, hence pointer is used over here. User can then provide the LUT with any one of the supported modes in any of the supported formats. The entries in the LUT can vary depending on the hardware capability with max being 255. This will also be exposed as iet_lut_caps so user can generate a LUT with the specified entries. v8: define enum for iet_mode, add more doc for iet modes (Dmitry) Signed-off-by: Arun R Murthy --- include/uapi/drm/drm_mode.h | 68 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index b8b7b18843ae7224263a9c61b20ac6cbf5df69e9..006be62218bf1e985c2ca6352cb04110a38d1e84 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1420,6 +1420,74 @@ struct drm_histogram { __u32 nr_elements; }; +/** + * enum drm_iet_mode + * @DRM_MODE_IET_LOOKUP_LUT: + * LUT values are points on exponential graph with x axis and y-axis y=f(x) + * This f(x) can be the algorithm, defined by the user space algorithm. + * When this LUT table is passed to the hardware it signifies how the hardware + * should use this table to get the LUT values. In this mode its direct lookup + * table. x-axis corresponds to input pixel value and y-axis corresponds to + * the output pixel value. + * + * @DRM_MODE_IET_MULTIPLICATIVE: + * LUT values, x and y are points on negative exponential graph with + * x-axis and y-axis (y = y/x). The value passed by the user will be + * in y/x i.e OutPixel/InPixel. X co-ordinate proportional to pixel value + * and Y-cordinate is the multiplier factor, i.e x-axis in pixels and + * y-axis is OutPixel/InPixel. so upon multiplying x, y is obtained, + * hence multiplicative. + * The format of LUT can at max be 8.24(8integer 24 fractional) + * represented by u32. 32bit is the container and if 16.16 is chosen + * then it doesn't make sense to boost the pixel by 2^16. Hence set aside + * 8bit for integer 2^8 thereby boosting the pixel by a value 255 which + * itself is a huge boost factor. Remaining 24bits out of the 32bit + * container is fractional part. This is also optimal for implementing + * in the hardware. + * Depending on the hardware capability and exponent mantissa can be + * chosen within this limits. + */ +enum drm_iet_mode { + DRM_MODE_IET_LOOKUP_LUT = 0x01, + DRM_MODE_IET_MULTIPLICATIVE = 0x02, +}; + +/** + * struct drm_iet_caps + * + * @iet_mode: pixel factor enhancement modes defined in enum drm_iet_mode. + * Multiple modes can be supported by hardware, the value can be + * ORed. + * @iet_sample_format: holds the address of an array of u32 LUT sample formats + * depending on the hardware capability. Max being 8.24 + * Doing a bitwise AND will get the present sample. + * Ex: for 1 integer 9 fraction AND with 0x10001FF + * @nr_iet_sample_formats: number of iet_sample_formsts supported by the + * hardware + * @nr_iet_lut_entries: number of LUT entries + */ +struct drm_iet_caps { + __u32 iet_mode; + __u64 iet_sample_format; + __u32 nr_iet_sample_formats; + __u32 nr_iet_lut_entries; +}; + +/** + * struct drm_iet_1dlut_sample + * @iet_lut: the address in the field describes the format of the data + * corresponding to the @iet_mode + * In case of direct lookup this is NULL, in case of + * multiplicative mode LUT exponent and mantissa format. + * @nr_elements: number of entries pointed by the data @iet_lut + * @iet_mode: image enhancement mode, this will also convey the channel. + */ +struct drm_iet_1dlut_sample { + __u64 iet_lut; + __u32 nr_elements; + enum drm_iet_mode iet_mode; +}; + #if defined(__cplusplus) } #endif From patchwork Tue Jan 28 15:51:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC74AC02192 for ; Tue, 28 Jan 2025 16:06:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BF1C10E6C6; Tue, 28 Jan 2025 16:06:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RORGxcXc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 48BFF10E6A8; Tue, 28 Jan 2025 16:06:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738080363; x=1769616363; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=jdyoIsZnmolIT/eXOYhdQ7bf4YcpfOxAKAvdt+cKmqE=; b=RORGxcXcKULXY43gQHJQI8hpvcNJN648MdwkBocXugvFZujzlilL5SUM 0QJdryD4RHaroLrLXb86aFlo+9u8r1vzP868TySFG4wAZZew5rMk9U73x +YA68Cr57KaM3OczSS0QW2bp3gZCxv4y7kaNKGsgG/FLd6dsrdHRGRsLQ fFzkFok0P/92GMmbyJcx103fawKr8tWXwtTjc2bvQTz8rfWH6P76E0xmn vB858Rv5KFyRbOmx8ecTE49mzRUaLMQjDBOr6rncaFveY8WOksx0HqAm4 JNmqRzmCq77AYiZdhk9oC1llTCENUB2z0w/SyPRxX9NxZEmlwj/AHQA4A g==; X-CSE-ConnectionGUID: SOYW1x5RQuOvYDj/WmwIjA== X-CSE-MsgGUID: 4tsQkhvLQsKJXuHQefhMOg== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745011" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745011" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:03 -0800 X-CSE-ConnectionGUID: LSj8ut0lRVCk217+1FxfZg== X-CSE-MsgGUID: 7v9H/ccoTjm5xC2GVabssA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976908" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:00 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:09 +0530 Subject: [PATCH v8 03/14] drm/crtc: Expose API to create drm crtc property for histogram MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-3-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add drm-crtc property for histogram and for the properties added add the corresponding get/set_property. v8: Rebased Signed-off-by: Arun R Murthy --- drivers/gpu/drm/drm_atomic_state_helper.c | 14 ++++++ drivers/gpu/drm/drm_atomic_uapi.c | 15 +++++++ drivers/gpu/drm/drm_crtc.c | 73 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 44 +++++++++++++++++++ 4 files changed, 146 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 519228eb109533d2596e899a57b571fa0995824f..dfe6293f7a42d034da3de593094019ca15014a02 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -143,6 +143,12 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, drm_property_blob_get(state->ctm); if (state->gamma_lut) drm_property_blob_get(state->gamma_lut); + if (state->histogram_caps) + drm_property_blob_get(state->histogram_caps); + if (state->histogram_enable) + drm_property_blob_get(state->histogram_enable); + if (state->histogram_data) + drm_property_blob_get(state->histogram_data); state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -156,6 +162,8 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, /* Self refresh should be canceled when a new update is available */ state->active = drm_atomic_crtc_effectively_active(state); state->self_refresh_active = false; + + state->histogram_updated = false; } EXPORT_SYMBOL(__drm_atomic_helper_crtc_duplicate_state); @@ -215,6 +223,12 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); drm_property_blob_put(state->gamma_lut); + if (state->histogram_caps) + drm_property_blob_put(state->histogram_caps); + if (state->histogram_enable) + drm_property_blob_put(state->histogram_enable); + if (state->histogram_data) + drm_property_blob_put(state->histogram_data); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 370dc676e3aa543c9827b50df20df78f02b738c9..459d30898196c94392a7f916b1fa9ca3a334eea8 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -415,6 +415,15 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, return -EFAULT; set_out_fence_for_crtc(state->state, crtc, fence_ptr); + } else if (property == crtc->histogram_enable_property) { + ret = drm_property_replace_blob_from_id(dev, + &state->histogram_enable, + val, + -1, + sizeof(struct drm_histogram_config), + &replaced); + state->histogram_updated |= replaced; + return ret; } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; } else if (crtc->funcs->atomic_set_property) { @@ -452,6 +461,12 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; else if (property == config->prop_out_fence_ptr) *val = 0; + else if (property == crtc->histogram_caps_property) + *val = (state->histogram_caps) ? state->histogram_caps->base.id : 0; + else if (property == crtc->histogram_enable_property) + *val = (state->histogram_enable) ? state->histogram_enable->base.id : 0; + else if (property == crtc->histogram_data_property) + *val = (state->histogram_data) ? state->histogram_data->base.id : 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; else if (crtc->funcs->atomic_get_property) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 46655339003db2a1b43441434839e26f61d79b4e..d10b29aff725e40bdb93e6bd0828347db40fa3e8 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -959,3 +959,76 @@ bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state) return hweight32(crtc_state->encoder_mask) > 1; } EXPORT_SYMBOL(drm_crtc_in_clone_mode); + +/** + * drm_crtc_create_histogram_property: create histogram properties + * + * @crtc: pointer to the struct drm_crtc. + * @caps: pointer to the struct drm_histogram_caps, holds the + * histogram hardware capabilities. + * + * The property HISTOGRAM_CAPS exposes the hardware capability for + * histogram which includes the histogram mode, number of bins etc + * The property HISTOGRAM_ENABLE allows user to enable/disable the + * histogram feature and also configure the hardware. + * Upon KMD enabling by writing to the hardware registers, histogram + * is generated. Histogram is composed of 'n' bins with each bin + * being an integer(pixel count). + * An event HISTOGRAM will be sent to the user. User upon receiving this + * event can read the hardware generated histogram using crtc property + * HISTOGRAM_DATA. + * User can use this histogram data to enhance the image or in shaders. + * + * Property HISTOGRAM_CAPS is a blob pointing to the struct drm_histogram_caps + * Description of the structure is in include/uapi/drm/drm_mode.h + * Property HISTOGRAM_ENABLE is a blob pointing to the struct + * drm_histogram_config + * Description of the structure is in include/uapi/drm/drm_mode.h + * Property HISTOGRAM_DATA is a blob pointing to the struct drm_histogram + * Description of the structure is in include/uapi/drm/drm_mode.h + * + * RETURNS: + * Zero for success or -errno + */ +int drm_crtc_create_histogram_property(struct drm_crtc *crtc, + struct drm_histogram_caps *caps) +{ + struct drm_property *prop; + struct drm_property_blob *blob; + struct drm_histogram_caps *blob_data; + + blob = drm_property_create_blob(crtc->dev, + sizeof(struct drm_histogram_caps), + NULL); + if (IS_ERR(blob)) + return -1; + blob_data = blob->data; + blob_data->histogram_mode = caps->histogram_mode; + blob_data->bins_count = caps->bins_count; + + prop = drm_property_create(crtc->dev, DRM_MODE_PROP_ATOMIC | + DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB, + "HISTOGRAM_CAPS", blob->base.id); + if (!prop) + return -ENOMEM; + drm_object_attach_property(&crtc->base, prop, 0); + crtc->histogram_caps_property = prop; + + prop = drm_property_create(crtc->dev, DRM_MODE_PROP_ATOMIC | + DRM_MODE_PROP_BLOB, "HISTOGRAM_ENABLE", 0); + if (!prop) + return -ENOMEM; + drm_object_attach_property(&crtc->base, prop, 0); + crtc->histogram_enable_property = prop; + + prop = drm_property_create(crtc->dev, DRM_MODE_PROP_ATOMIC | + DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB, + "HISTOGRAM_DATA", 0); + if (!prop) + return -ENOMEM; + drm_object_attach_property(&crtc->base, prop, 0); + crtc->histogram_data_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_histogram_property); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index caa56e039da2a748cf40ebf45b37158acda439d9..2da803749bdf03c07268be4e075793ef4e4eb99a 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -274,6 +274,32 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; + /** + * @histogram_caps: + * + * The blob points to the structure drm_histogram_caps. + * For more info on the elements of the struct drm_histogram_caps + * see include/uapi/drm/drm_mode.h + */ + struct drm_property_blob *histogram_caps; + /** + * @histogram_enable: + * + * The blob points to the structure drm_histogram_config. + * For more information on the elements of struct drm_histogram_config + * see include/uapi/drm/drm_mode.h + */ + struct drm_property_blob *histogram_enable; + /** + * @histogram_data: + * + * The blob points to the structure drm_histogram. + * For more information on the elements of struct drm_histogram + * see include/uapi/drm/drm_mode.h + */ + struct drm_property_blob *histogram_data; + bool histogram_updated; + /** * @target_vblank: * @@ -1088,6 +1114,22 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @histogram_caps_property: Optional CRTC property for getting the + * histogram hardware capability. + */ + struct drm_property *histogram_caps_property; + /** + * @histogram_enable_property: Optional CRTC property for enabling or + * disabling global histogram. + */ + struct drm_property *histogram_enable_property; + /** + * @histogram_data_proeprty: Optional CRTC property for getting the + * histogram blob data. + */ + struct drm_property *histogram_data_property; + /** * @state: * @@ -1324,4 +1366,6 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state); +int drm_crtc_create_histogram_property(struct drm_crtc *crtc, + struct drm_histogram_caps *caps); #endif /* __DRM_CRTC_H__ */ From patchwork Tue Jan 28 15:51:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C8C1C02194 for ; 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X-CSE-ConnectionGUID: M/GN0HjvQcKmmqzNJI4Iew== X-CSE-MsgGUID: TARWuCPVRJulkZ+gP7FEEg== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745018" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745018" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:05 -0800 X-CSE-ConnectionGUID: CkcBz0phTFegqv+yIr91SQ== X-CSE-MsgGUID: andAbKGNTZ22WMpRIGpRow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976917" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:03 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:10 +0530 Subject: [PATCH v8 04/14] drm/crtc: Expose API to create drm crtc property for IET LUT MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-4-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add drm-crtc property for IET 1DLUT and for the properties added add corresponding get/set_property. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/drm_atomic_state_helper.c | 9 ++++++ drivers/gpu/drm/drm_atomic_uapi.c | 13 ++++++++ drivers/gpu/drm/drm_crtc.c | 54 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 36 +++++++++++++++++++++ 4 files changed, 112 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index dfe6293f7a42d034da3de593094019ca15014a02..ceab90cec57cc580afcf334e275982827e9b0e0d 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -149,6 +149,10 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, drm_property_blob_get(state->histogram_enable); if (state->histogram_data) drm_property_blob_get(state->histogram_data); + if (state->iet_lut_caps) + drm_property_blob_get(state->iet_lut_caps); + if (state->iet_lut) + drm_property_blob_get(state->iet_lut); state->mode_changed = false; state->active_changed = false; state->planes_changed = false; @@ -164,6 +168,7 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, state->self_refresh_active = false; state->histogram_updated = false; + state->iet_lut_updated = false; } EXPORT_SYMBOL(__drm_atomic_helper_crtc_duplicate_state); @@ -229,6 +234,10 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state) drm_property_blob_put(state->histogram_enable); if (state->histogram_data) drm_property_blob_put(state->histogram_data); + if (state->iet_lut_caps) + drm_property_blob_put(state->iet_lut_caps); + if (state->iet_lut) + drm_property_blob_put(state->iet_lut); } EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 459d30898196c94392a7f916b1fa9ca3a334eea8..f31d24d80cc082b38c611b12f36f281fa7404869 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -424,6 +424,15 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, &replaced); state->histogram_updated |= replaced; return ret; + } else if (property == crtc->iet_lut_property) { + ret = drm_property_replace_blob_from_id(dev, + &state->iet_lut, + val, + -1, + sizeof(struct drm_iet_1dlut_sample), + &replaced); + state->iet_lut_updated |= replaced; + return ret; } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; } else if (crtc->funcs->atomic_set_property) { @@ -467,6 +476,10 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->histogram_enable) ? state->histogram_enable->base.id : 0; else if (property == crtc->histogram_data_property) *val = (state->histogram_data) ? state->histogram_data->base.id : 0; + else if (property == crtc->iet_lut_caps_property) + *val = (state->iet_lut_caps) ? state->iet_lut_caps->base.id : 0; + else if (property == crtc->iet_lut_property) + *val = (state->iet_lut) ? state->iet_lut->base.id : 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; else if (crtc->funcs->atomic_get_property) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index d10b29aff725e40bdb93e6bd0828347db40fa3e8..850d98d7f9c8965c7a5e9ac5505e355042041449 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1032,3 +1032,57 @@ int drm_crtc_create_histogram_property(struct drm_crtc *crtc, return 0; } EXPORT_SYMBOL(drm_crtc_create_histogram_property); + +/** + * drm_crtc_create_iet_lut_property + * + * @crtc: pointer to the struct drm_crtc. + * @caps: pointer to the struct drm_iet_caps, holds the + * image enhancement LUT hardware capabilities. + * + * This 1DLUT is used by the hardware to enahance the image. Hardware + * interpolates this LUT value to generate the enhanced output image. + * + * The blob property IET_LUT_CAPS points to the struct drm_iet_lut_caps + * The blob property IET_LUT points to the struct drm_iet_1dlut_sample + * Description of the structure is in include/uapi/drm/drm_mode.h + * + * RETURNS: + * Zero for success or -errno + */ +int drm_crtc_create_iet_lut_property(struct drm_crtc *crtc, + struct drm_iet_caps *caps) +{ + struct drm_property *prop; + struct drm_iet_caps *blob_data; + struct drm_property_blob *blob; + + blob = drm_property_create_blob(crtc->dev, + sizeof(struct drm_iet_caps), + NULL); + if (IS_ERR(blob)) + return -1; + blob_data = blob->data; + blob_data->iet_mode = caps->iet_mode; + blob_data->nr_iet_sample_formats = caps->nr_iet_sample_formats; + blob_data->nr_iet_lut_entries = caps->nr_iet_lut_entries; + blob_data->iet_sample_format = caps->iet_sample_format; + + prop = drm_property_create(crtc->dev, DRM_MODE_PROP_ATOMIC | + DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB, + "IET_LUT_CAPS", blob->base.id); + if (!prop) + return -ENOMEM; + drm_object_attach_property(&crtc->base, prop, 0); + crtc->iet_lut_caps_property = prop; + + prop = drm_property_create(crtc->dev, DRM_MODE_PROP_ATOMIC | + DRM_MODE_PROP_BLOB, "IET_LUT", 0); + if (!prop) + return -ENOMEM; + drm_object_attach_property(&crtc->base, prop, 0); + crtc->iet_lut_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_iet_lut_property); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 2da803749bdf03c07268be4e075793ef4e4eb99a..bc85ab16d5c817773a1d8b415eb256d08c13c709 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -300,6 +300,29 @@ struct drm_crtc_state { struct drm_property_blob *histogram_data; bool histogram_updated; + /** + * @iet_lut_caps: + * + * The blob points to the structure drm_iet_lut_caps. + * For more info on the elements of the struct drm_iet_lut_caps + * see include/uapi/drm/drm_mode.h + */ + struct drm_property_blob *iet_lut_caps; + /** + * @iet_lut: + * + * The blob points to the struct drm_lut_sample + * For more information on the elements of struct drm_lut_sample + * see include/uapi/drm/drm_mode.h + */ + struct drm_property_blob *iet_lut; + /** + * @iet_lut_updates: + * + * Convey that the image enhanced data has been updated by the user + */ + bool iet_lut_updated; + /** * @target_vblank: * @@ -1130,6 +1153,17 @@ struct drm_crtc { */ struct drm_property *histogram_data_property; + /** + * @iet_lut_caps_property: Optional CRTC property for getting the + * iet LUT hardware capability. + */ + struct drm_property *iet_lut_caps_property; + /** + * @iet_lut_proeprty: Optional CRTC property for writing the + * image enhanced LUT + */ + struct drm_property *iet_lut_property; + /** * @state: * @@ -1368,4 +1402,6 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, bool drm_crtc_in_clone_mode(struct drm_crtc_state *crtc_state); int drm_crtc_create_histogram_property(struct drm_crtc *crtc, struct drm_histogram_caps *caps); +int drm_crtc_create_iet_lut_property(struct drm_crtc *crtc, + struct drm_iet_caps *caps); #endif /* __DRM_CRTC_H__ */ From patchwork Tue Jan 28 15:51:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E61E5C02195 for ; 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X-CSE-ConnectionGUID: YDlRFnzbS9W44DLgrMZX3A== X-CSE-MsgGUID: 2H4YZl9tRKmYyuuiCVtzYw== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745023" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745023" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:08 -0800 X-CSE-ConnectionGUID: WmjZ5trgQDCcmojO4/k82A== X-CSE-MsgGUID: 4s99Yu9+SzeuYg2roQPd1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976931" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:05 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:11 +0530 Subject: [PATCH v8 05/14] drm/i915/histogram: Define registers for histogram MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-5-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the register/bit definitions for global histogram. v2: Intended the register contents, removed unused regs (Jani) Bspec: 4270 Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal --- .../gpu/drm/i915/display/intel_histogram_regs.h | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h new file mode 100644 index 0000000000000000000000000000000000000000..1252b4f339a63f70f44e249bdeae87805bee20fc --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_HISTOGRAM_REGS_H__ +#define __INTEL_HISTOGRAM_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* GLOBAL_HIST related registers */ +#define _DPST_CTL_A 0x490C0 +#define _DPST_CTL_B 0x491C0 +#define DPST_CTL(pipe) _MMIO_PIPE(pipe, _DPST_CTL_A, _DPST_CTL_B) +#define DPST_CTL_IE_HIST_EN REG_BIT(31) +#define DPST_CTL_RESTORE REG_BIT(28) +#define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) +#define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) +#define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) +#define DPST_CTL_BIN_REG_FUNC_SEL REG_BIT(11) +#define DPST_CTL_BIN_REG_FUNC_TC REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 0) +#define DPST_CTL_BIN_REG_FUNC_IE REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 1) +#define DPST_CTL_BIN_REG_MASK REG_GENMASK(6, 0) +#define DPST_CTL_BIN_REG_CLEAR REG_FIELD_PREP(DPST_CTL_BIN_REG_MASK, 0) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_2INT_8FRAC REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 1) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 0) +#define DPST_CTL_HIST_MODE_YUV REG_FIELD_PREP(DPST_CTL_HIST_MODE, 0) +#define DPST_CTL_HIST_MODE_HSV REG_FIELD_PREP(DPST_CTL_HIST_MODE, 1) + +#define _DPST_GUARD_A 0x490C8 +#define _DPST_GUARD_B 0x491C8 +#define DPST_GUARD(pipe) _MMIO_PIPE(pipe, _DPST_GUARD_A, _DPST_GUARD_B) +#define DPST_GUARD_HIST_INT_EN REG_BIT(31) +#define DPST_GUARD_HIST_EVENT_STATUS REG_BIT(30) +#define DPST_GUARD_INTERRUPT_DELAY_MASK REG_GENMASK(29, 22) +#define DPST_GUARD_INTERRUPT_DELAY(val) REG_FIELD_PREP(DPST_GUARD_INTERRUPT_DELAY_MASK, val) +#define DPST_GUARD_THRESHOLD_GB_MASK REG_GENMASK(21, 0) +#define DPST_GUARD_THRESHOLD_GB(val) REG_FIELD_PREP(DPST_GUARD_THRESHOLD_GB_MASK, val) + +#define _DPST_BIN_A 0x490C4 +#define _DPST_BIN_B 0x491C4 +#define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) +#define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) +#define DPST_BIN_BUSY REG_BIT(31) + +#endif /* __INTEL_HISTOGRAM_REGS_H__ */ From patchwork Tue Jan 28 15:51:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9601C02190 for ; Tue, 28 Jan 2025 16:06:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3FE8C10E6C8; Tue, 28 Jan 2025 16:06:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G3kzZ+hY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5066310E6B9; Tue, 28 Jan 2025 16:06:10 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="145976941" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:08 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:12 +0530 Subject: [PATCH v8 06/14] drm/i915/histogram: Add support for histogram MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-6-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Statistics is generated from the image frame that is coming to display and an event is sent to user after reading this histogram data. v2: forward declaration in header file along with error handling (Jani) v3: Replaced i915 with intel_display (Suraj) v4: Removed dithering enable/disable (Vandita) New patch for histogram register definitions (Suraj) v5: IET LUT pgm follow the seq in spec and removed change to TC at end (Suraj) v8: Retained only the Histogram part and move IET LUT to a different patch. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_histogram.c | 157 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_histogram.h | 48 +++++++ 4 files changed, 208 insertions(+) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 4caa8e30bc98387d45212fbc7cea8b38687bd0d5..f993b19174ba79c0bcc34994619937be7d2797ed 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -270,6 +270,7 @@ i915-y += \ display/intel_hdcp.o \ display/intel_hdcp_gsc.o \ display/intel_hdcp_gsc_message.o \ + display/intel_histogram.o \ display/intel_hotplug.o \ display/intel_hotplug_irq.o \ display/intel_hti.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index cb51b7936f9338caaf14b1c6f7bbcc4327da4ef1..761fefed9376439c0ee5d346e8110a219ad0a586 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1434,6 +1434,8 @@ struct intel_crtc { /* for loading single buffered registers during vblank */ struct pm_qos_request vblank_pm_qos; + struct intel_histogram *histogram; + #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; #endif diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c new file mode 100644 index 0000000000000000000000000000000000000000..26eae8f40d0bf642546d583546782e22d5cefa9c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2025 Intel Corporation + */ + +#include +#include +#include + +#include "i915_reg.h" +#include "i915_drv.h" +#include "intel_de.h" +#include "intel_display.h" +#include "intel_display_types.h" +#include "intel_histogram.h" +#include "intel_histogram_regs.h" + +/* 3.0% of the pipe's current pixel count, hw does x4 */ +#define HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT 300 +/* Precision factor for threshold guardband */ +#define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000 +#define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04 + +int intel_histogram_atomic_check(struct intel_crtc *intel_crtc) +{ + struct intel_histogram *histogram = intel_crtc->histogram; + + /* TODO: Restrictions for enabling histogram */ + histogram->can_enable = true; + + return 0; +} + +static int intel_histogram_enable(struct intel_crtc *intel_crtc, u8 mode) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + int pipe = intel_crtc->pipe; + u64 res; + u32 gbandthreshold; + + if (!histogram || !histogram->can_enable) + return -EINVAL; + + if (histogram->enable) + return 0; + + /* enable histogram, clear DPST_CTL bin reg func select to TC */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT | + DPST_CTL_ENHANCEMENT_MODE_MASK | DPST_CTL_IE_MODI_TABLE_EN, + ((mode == DRM_MODE_HISTOGRAM_HSV_MAX_RGB) ? + DPST_CTL_BIN_REG_FUNC_TC : 0) | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV | + DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC | + DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); + + /* Re-Visit: check if wait for one vblank is required */ + drm_crtc_wait_one_vblank(&intel_crtc->base); + + /* TODO: Program GuardBand Threshold needs to be moved to modeset path */ + res = (intel_crtc->config->hw.adjusted_mode.vtotal * + intel_crtc->config->hw.adjusted_mode.htotal); + + gbandthreshold = (res * HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT) / + HISTOGRAM_GUARDBAND_PRECISION_FACTOR; + + /* Enable histogram interrupt mode */ + intel_de_rmw(display, DPST_GUARD(pipe), + DPST_GUARD_THRESHOLD_GB_MASK | + DPST_GUARD_INTERRUPT_DELAY_MASK | DPST_GUARD_HIST_INT_EN, + DPST_GUARD_THRESHOLD_GB(gbandthreshold) | + DPST_GUARD_INTERRUPT_DELAY(HISTOGRAM_DEFAULT_GUARDBAND_DELAY) | + DPST_GUARD_HIST_INT_EN); + + /* Clear pending interrupts has to be done on separate write */ + intel_de_rmw(display, DPST_GUARD(pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); + + histogram->enable = true; + + return 0; +} + +static void intel_histogram_disable(struct intel_crtc *intel_crtc) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + int pipe = intel_crtc->pipe; + + if (!histogram) + return; + + /* If already disabled return */ + if (histogram->enable) + return; + + /* Clear pending interrupts and disable interrupts */ + intel_de_rmw(display, DPST_GUARD(pipe), + DPST_GUARD_HIST_INT_EN | DPST_GUARD_HIST_EVENT_STATUS, 0); + + /* disable DPST_CTL Histogram mode */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_IE_HIST_EN, 0); + + histogram->enable = false; +} + +int intel_histogram_update(struct intel_crtc *intel_crtc, + struct drm_histogram_config *config) +{ + struct intel_display *display = to_intel_display(intel_crtc); + + if (config->enable) { + if (config->hist_mode != DRM_MODE_HISTOGRAM_HSV_MAX_RGB) { + drm_err(display->drm, + "Only max(RGB) mode is supported for histogram\n"); + return -EINVAL; + } + return intel_histogram_enable(intel_crtc, config->hist_mode); + } + + intel_histogram_disable(intel_crtc); + return 0; +} + +void intel_histogram_finish(struct intel_crtc *intel_crtc) +{ + struct intel_histogram *histogram = intel_crtc->histogram; + + kfree(histogram); +} + +int intel_histogram_init(struct intel_crtc *crtc) +{ + struct intel_histogram *histogram; + struct drm_histogram_caps *histogram_caps; + + /* Allocate histogram internal struct */ + histogram = kzalloc(sizeof(*histogram), GFP_KERNEL); + if (!histogram) + return -ENOMEM; + histogram_caps = kzalloc(sizeof(*histogram_caps), GFP_KERNEL); + if (!histogram_caps) + return -ENOMEM; + + histogram_caps->histogram_mode = DRM_MODE_HISTOGRAM_HSV_MAX_RGB; + histogram_caps->bins_count = HISTOGRAM_BIN_COUNT; + + crtc->histogram = histogram; + histogram->crtc = crtc; + histogram->can_enable = false; + histogram->caps = histogram_caps; + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h new file mode 100644 index 0000000000000000000000000000000000000000..5ea19ef2d3ecadf1ac159a784f51278fdde593de --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_HISTOGRAM_H__ +#define __INTEL_HISTOGRAM_H__ + +#include +#include + +struct delayed_work; +struct drm_property_blob; +struct drm_histogram_config; +struct drm_histogram_caps; +struct intel_crtc; + +#define HISTOGRAM_BIN_COUNT 32 + +struct intel_histogram { + struct drm_histogram_caps *caps; + struct intel_crtc *crtc; + struct delayed_work work; + bool enable; + bool can_enable; + u32 bin_data[HISTOGRAM_BIN_COUNT]; +}; + +enum intel_global_hist_status { + INTEL_HISTOGRAM_ENABLE, + INTEL_HISTOGRAM_DISABLE, +}; + +enum intel_global_histogram { + INTEL_HISTOGRAM, +}; + +enum intel_global_hist_lut { + INTEL_HISTOGRAM_PIXEL_FACTOR, +}; + +int intel_histogram_atomic_check(struct intel_crtc *intel_crtc); +int intel_histogram_update(struct intel_crtc *intel_crtc, + struct drm_histogram_config *config); +int intel_histogram_init(struct intel_crtc *intel_crtc); +void intel_histogram_finish(struct intel_crtc *intel_crtc); + +#endif /* __INTEL_HISTOGRAM_H__ */ From patchwork Tue Jan 28 15:51:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A778EC02190 for ; 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X-CSE-ConnectionGUID: RBPTNNgCRjqVqwBJS8BruQ== X-CSE-MsgGUID: nx4rl+w9QPWfqgC6DChuPw== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745037" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745037" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:12 -0800 X-CSE-ConnectionGUID: haFJSwxKTbW9JX3SWqQpCg== X-CSE-MsgGUID: Uy2+qByWRb2NJYRTJg1ipQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976959" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:10 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:13 +0530 Subject: [PATCH v8 07/14] drm/xe: Add histogram support to Xe builds MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-7-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Histogram added as part of i915/display driver. Adding the same for xe as well. Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal Acked-by: Dmitry Baryshkov --- drivers/gpu/drm/xe/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 80ab87cfeecbcf9f64183e938a8b15efe71459ed..7ee23d31a1a3584852708c4e17ad179a47e5b6b9 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -248,6 +248,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_hdcp.o \ i915-display/intel_hdcp_gsc_message.o \ i915-display/intel_hdmi.o \ + i915-display/intel_histogram.o \ i915-display/intel_hotplug.o \ i915-display/intel_hotplug_irq.o \ i915-display/intel_hti.o \ From patchwork Tue Jan 28 15:51:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6ECEC02198 for ; Tue, 28 Jan 2025 16:06:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DC4210E6CD; Tue, 28 Jan 2025 16:06:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bdedSRNx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id F028310E6A8; Tue, 28 Jan 2025 16:06:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738080375; x=1769616375; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Xi3rmepOT+QDZwxMSeAmTdLHFlvMnAaCS2P6jIqmz8k=; b=bdedSRNxWqV/fQzJ9yKrH62GYkimoAIwSEIMIQTVug5+iKm2a7CQI64F 046XqIydbS1Ta6fVlSl9UtWfTE8L+rvDNGmg5lqNMI16CvtVLAtaOcODU +5EuHo5PbGTQaeJYil5dhJWUNXDMck4z43/5S1H05GrlIRIlHQaz2+wZf PQafyH9eeFTssLyEkiEXY4BUg9aSG6h4+cfTEBk4GO+Z4Mp5CN1HHM/aZ WCyZYQ4shj9LGTn+nPSFacNE5YHFVHjRBaolBSGFJymkEOi4zs4d2tcXd w3TSNikT98koWZ3kJNT1YmE9ImCqvQkMsec3r59qisikox7AWRYlj/GD3 w==; X-CSE-ConnectionGUID: +E7mc2bVSvmDUQ/quJ7ncQ== X-CSE-MsgGUID: 7HO9At6NR5ClPEX0g4dG3w== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745042" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745042" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:15 -0800 X-CSE-ConnectionGUID: UgvRGSJQQCmvix7dc4y3HQ== X-CSE-MsgGUID: lVX6R9AbRmOASVb9GFnhmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145976976" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:12 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:14 +0530 Subject: [PATCH v8 08/14] drm/i915/histogram: histogram interrupt handling MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-8-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Upon enabling histogram an interrupt is trigerred after the generation of the statistics. This patch registers the histogram interrupt and handles the interrupt. v2: Added intel_crtc backpointer to intel_histogram struct (Jani) Removed histogram_wq and instead use dev_priv->unodered_eq (Jani) v3: Replaced drm_i915_private with intel_display (Suraj) Refactored the histogram read code (Jani) v4: Rebased after addressing comments on patch 1 v5: removed the retry logic and moved to patch7 (Jani) Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +- drivers/gpu/drm/i915/display/intel_histogram.c | 106 ++++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_histogram.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 5 +- 4 files changed, 115 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d9734fcd0d45b9f7c2891730e73b7e1d59c206ad..b62c3cdfd6a0607d9d2e1caa0d71edb0aa99fdbb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -21,6 +21,7 @@ #include "intel_fdi_regs.h" #include "intel_fifo_underrun.h" #include "intel_gmbus.h" +#include "intel_histogram.h" #include "intel_hotplug_irq.h" #include "intel_pipe_crc_regs.h" #include "intel_pmdemand.h" @@ -1230,6 +1231,9 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_FIFO_UNDERRUN) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + if (iir & GEN9_PIPE_HISTOGRAM_EVENT) + intel_histogram_irq_handler(display, pipe); + fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); if (fault_errors) drm_err_ratelimited(&dev_priv->drm, @@ -1827,7 +1831,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_display *display = &dev_priv->display; u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | - GEN8_PIPE_CDCLK_CRC_DONE; + GEN8_PIPE_CDCLK_CRC_DONE | GEN9_PIPE_HISTOGRAM_EVENT; u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index 26eae8f40d0bf642546d583546782e22d5cefa9c..4f3dcbabfe96e955a65874718272c4beb53b0827 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -19,7 +19,104 @@ #define HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT 300 /* Precision factor for threshold guardband */ #define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000 -#define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04 +#define HISTOGRAM_BIN_READ_RETRY_COUNT 5 + +static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + int index; + u32 dpstbin; + + for (index = 0; index < ARRAY_SIZE(histogram->bin_data); index++) { + dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); + if (!(dpstbin & DPST_BIN_BUSY)) { + histogram->bin_data[index] = dpstbin & DPST_BIN_DATA_MASK; + } else + return false; + } + return true; +} + +static void intel_histogram_handle_int_work(struct work_struct *work) +{ + struct intel_histogram *histogram = container_of(work, + struct intel_histogram, work.work); + struct intel_crtc *intel_crtc = histogram->crtc; + struct intel_display *display = to_intel_display(intel_crtc); + char event[] = "HISTOGRAM=1", pipe_id[21]; + char *histogram_event[] = { event, pipe_id, NULL }; + int retry; + + snprintf(pipe_id, sizeof(pipe_id), + "PIPE=%u", intel_crtc->base.base.id); + + /* + * TODO: PSR to be exited while reading the Histogram data + * Set DPST_CTL Bin Reg function select to TC + * Set DPST_CTL Bin Register Index to 0 + */ + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + for (retry = 0; retry < HISTOGRAM_BIN_READ_RETRY_COUNT; retry++) { + if (intel_histogram_get_data(intel_crtc)) { + u32 *data; + struct drm_histogram *hist; + + data = kzalloc(sizeof(data) * sizeof(histogram->bin_data), GFP_KERNEL); + if (!data) + return; + memcpy(histogram->bin_data, data, sizeof(histogram->bin_data)); + hist = kzalloc(sizeof(struct drm_histogram), GFP_KERNEL); + if (!hist) + return; + hist->data_ptr = *data; + hist->nr_elements = sizeof(histogram->bin_data); + + /* TODO: fill the drm_histogram_config data back this drm_histogram struct */ + drm_property_replace_global_blob(display->drm, + &intel_crtc->base.state->histogram_data, + sizeof(struct drm_histogram), + hist, &intel_crtc->base.base, + intel_crtc->base.histogram_data_property); + /* Notify user for Histogram readiness */ + if (kobject_uevent_env(&display->drm->primary->kdev->kobj, + KOBJ_CHANGE, histogram_event)) + drm_err(display->drm, + "Sending HISTOGRAM event failed\n"); + break; + } + } + if (retry >= HISTOGRAM_BIN_READ_RETRY_COUNT) { + drm_err(display->drm, "Histogram bin read failed with max retry\n"); + return; + } + + /* Enable histogram interrupt */ + intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, + DPST_GUARD_HIST_INT_EN); + + /* Clear histogram interrupt by setting histogram interrupt status bit*/ + intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); +} + +void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe) +{ + struct intel_crtc *intel_crtc = + to_intel_crtc(drm_crtc_from_index(display->drm, pipe)); + struct intel_histogram *histogram = intel_crtc->histogram; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + + if (!histogram->enable) { + drm_err(display->drm, + "Spurious interrupt, histogram not enabled\n"); + return; + } + + queue_delayed_work(i915->unordered_wq, + &histogram->work, 0); +} int intel_histogram_atomic_check(struct intel_crtc *intel_crtc) { @@ -71,7 +168,7 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc, u8 mode) DPST_GUARD_THRESHOLD_GB_MASK | DPST_GUARD_INTERRUPT_DELAY_MASK | DPST_GUARD_HIST_INT_EN, DPST_GUARD_THRESHOLD_GB(gbandthreshold) | - DPST_GUARD_INTERRUPT_DELAY(HISTOGRAM_DEFAULT_GUARDBAND_DELAY) | + DPST_GUARD_INTERRUPT_DELAY(0x04) | DPST_GUARD_HIST_INT_EN); /* Clear pending interrupts has to be done on separate write */ @@ -104,6 +201,7 @@ static void intel_histogram_disable(struct intel_crtc *intel_crtc) intel_de_rmw(display, DPST_CTL(pipe), DPST_CTL_IE_HIST_EN, 0); + cancel_delayed_work(&histogram->work); histogram->enable = false; } @@ -129,6 +227,7 @@ void intel_histogram_finish(struct intel_crtc *intel_crtc) { struct intel_histogram *histogram = intel_crtc->histogram; + cancel_delayed_work_sync(&histogram->work); kfree(histogram); } @@ -153,5 +252,8 @@ int intel_histogram_init(struct intel_crtc *crtc) histogram->can_enable = false; histogram->caps = histogram_caps; + INIT_DEFERRABLE_WORK(&histogram->work, + intel_histogram_handle_int_work); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h index 5ea19ef2d3ecadf1ac159a784f51278fdde593de..b44ba3afc94f79f291f4e5ebdd04dcf9434b48a4 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.h +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -14,6 +14,8 @@ struct drm_property_blob; struct drm_histogram_config; struct drm_histogram_caps; struct intel_crtc; +struct intel_display; +enum pipe; #define HISTOGRAM_BIN_COUNT 32 @@ -39,6 +41,7 @@ enum intel_global_hist_lut { INTEL_HISTOGRAM_PIXEL_FACTOR, }; +void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe); int intel_histogram_atomic_check(struct intel_crtc *intel_crtc); int intel_histogram_update(struct intel_crtc *intel_crtc, struct drm_histogram_config *config); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b9e2aa1c6f8afefade761b8d291bb62efb96e53c..fc451783c9c23bfdd74a2dfc78be40c9d576fb56 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1599,7 +1599,7 @@ #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define PIPE_HISTOGRAM_EVENT_ENABLE (1UL << 23) #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) @@ -1622,7 +1622,7 @@ #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) -#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_HISTOGRAM_EVENT_STATUS (1UL << 7) #define PIPE_A_PSR_STATUS_VLV (1UL << 6) #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) @@ -2224,6 +2224,7 @@ #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ #define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) +#define GEN9_PIPE_HISTOGRAM_EVENT REG_BIT(12) /* skl+ */ #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ From patchwork Tue Jan 28 15:51:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35EF3C02199 for ; Tue, 28 Jan 2025 16:06:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE37610E6BF; Tue, 28 Jan 2025 16:06:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nrgpBErD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 462A910E6D0; Tue, 28 Jan 2025 16:06:17 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="145976991" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:14 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:15 +0530 Subject: [PATCH v8 09/14] drm/i915/histogram: Hook i915 histogram with drm histogram MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-9-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Handle histogram caps and histogram config property in i915 driver. Fill the histogram hardware capability and act upon the histogram config property to enable/disable histogram in i915. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_crtc.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index e69b28779ac551bde56c9c3d394e784275a9b69e..b90017409a23de2a214ca43d32ba537998ea0f78 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -28,6 +28,7 @@ #include "intel_drrs.h" #include "intel_dsi.h" #include "intel_fifo_underrun.h" +#include "intel_histogram.h" #include "intel_pipe_crc.h" #include "intel_psr.h" #include "intel_sprite.h" @@ -211,6 +212,7 @@ static struct intel_crtc *intel_crtc_alloc(void) static void intel_crtc_free(struct intel_crtc *crtc) { intel_crtc_destroy_state(&crtc->base, crtc->base.state); + intel_histogram_finish(crtc); kfree(crtc); } @@ -381,6 +383,11 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); + intel_histogram_init(crtc); + if (drm_crtc_create_histogram_property(&crtc->base, + crtc->histogram->caps)) + drm_err(&dev_priv->drm, "Failed to initialize histogram properties\n"); + intel_color_crtc_init(crtc); intel_drrs_crtc_init(crtc); intel_crtc_crc_init(crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7d68d652c1bc91acc68281c4761f688f3779bd79..c38a33ee90aef144931215254f178ba955f998b0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -93,6 +93,7 @@ #include "intel_fifo_underrun.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h" +#include "intel_histogram.h" #include "intel_hotplug.h" #include "intel_link_bw.h" #include "intel_lvds.h" @@ -4675,6 +4676,12 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (ret) return ret; + if (crtc_state->uapi.histogram_updated) { + ret = intel_histogram_atomic_check(crtc); + if (ret) + return ret; + } + return 0; } @@ -7933,6 +7940,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) */ old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); + + if (new_crtc_state->uapi.histogram_updated) + intel_histogram_update(crtc, + (struct drm_histogram_config *) + new_crtc_state->uapi.histogram_enable->data); } /* Underruns don't always raise interrupts, so check manually */ From patchwork Tue Jan 28 15:51:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C72B4C0219B for ; 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X-CSE-ConnectionGUID: CSO0Omq2RI6BGrxaWP/wpg== X-CSE-MsgGUID: P2mdLf8fQBOSA7i12u7yCw== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745051" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745051" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:19 -0800 X-CSE-ConnectionGUID: XueTAyU9Sw6n2Isq4QV+GA== X-CSE-MsgGUID: bTon9kX3T5SXNXEbKI6Nyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145977000" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:17 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:16 +0530 Subject: [PATCH v8 10/14] drm/i915/iet: Add support to writing the IET LUT data MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-10-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" User created LUT can be fed back to the hardware so that the hardware can apply this LUT data to see the enhancement in the image. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_histogram.c | 70 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_histogram.h | 4 ++ 2 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index 4f3dcbabfe96e955a65874718272c4beb53b0827..aa02e7ce42b930a858de4ad7e0d39d93fa7d4298 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -20,6 +20,7 @@ /* Precision factor for threshold guardband */ #define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000 #define HISTOGRAM_BIN_READ_RETRY_COUNT 5 +#define IET_SAMPLE_FORMAT_1_INT_9_FRACT 0x1000009 static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) { @@ -223,6 +224,60 @@ int intel_histogram_update(struct intel_crtc *intel_crtc, return 0; } +int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, + struct drm_property_blob *blob) +{ + struct intel_histogram *histogram = intel_crtc->histogram; + struct intel_display *display = to_intel_display(intel_crtc); + int pipe = intel_crtc->pipe; + int i = 0; + struct drm_iet_1dlut_sample *iet; + u32 *data; + int ret; + + if (!histogram) + return -EINVAL; + + if (!histogram->enable) { + drm_err(display->drm, "histogram not enabled"); + return -EINVAL; + } + + if (!data) { + drm_err(display->drm, "enhancement LUT data is NULL"); + return -EINVAL; + } + + /* Set DPST_CTL Bin Reg function select to IE & wait for a vblabk */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_IE); + + drm_crtc_wait_one_vblank(&intel_crtc->base); + + /* Set DPST_CTL Bin Register Index to 0 */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_MASK, DPST_CTL_BIN_REG_CLEAR); + + iet = (struct drm_iet_1dlut_sample *)blob->data; + data = kzalloc(sizeof(data) * iet->nr_elements, GFP_KERNEL); + if (!data) + return -ENOMEM; + ret = copy_from_user(data, (uint32_t __user *)(unsigned long)iet->iet_lut, + sizeof(uint32_t) * iet->nr_elements); + if (ret) + return ret; + + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + intel_de_rmw(display, DPST_BIN(pipe), + DPST_BIN_DATA_MASK, data[i]); + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); + } + kfree(data); + drm_property_blob_put(intel_crtc->base.state->iet_lut); + + return 0; +} + void intel_histogram_finish(struct intel_crtc *intel_crtc) { struct intel_histogram *histogram = intel_crtc->histogram; @@ -235,6 +290,8 @@ int intel_histogram_init(struct intel_crtc *crtc) { struct intel_histogram *histogram; struct drm_histogram_caps *histogram_caps; + struct drm_iet_caps *iet_caps; + u32 *iet_format; /* Allocate histogram internal struct */ histogram = kzalloc(sizeof(*histogram), GFP_KERNEL); @@ -247,10 +304,23 @@ int intel_histogram_init(struct intel_crtc *crtc) histogram_caps->histogram_mode = DRM_MODE_HISTOGRAM_HSV_MAX_RGB; histogram_caps->bins_count = HISTOGRAM_BIN_COUNT; + iet_caps = kzalloc(sizeof(*iet_caps), GFP_KERNEL); + if (!iet_caps) + return -ENOMEM; + + iet_caps->iet_mode = DRM_MODE_IET_MULTIPLICATIVE; + iet_caps->nr_iet_sample_formats = 1; + iet_caps->nr_iet_lut_entries = HISTOGRAM_IET_LENGTH; + iet_format = kzalloc(sizeof(u32)*iet_caps->nr_iet_sample_formats, + GFP_KERNEL); + *iet_format = IET_SAMPLE_FORMAT_1_INT_9_FRACT; + iet_caps->iet_sample_format = *iet_format; + crtc->histogram = histogram; histogram->crtc = crtc; histogram->can_enable = false; histogram->caps = histogram_caps; + histogram->iet_caps = iet_caps; INIT_DEFERRABLE_WORK(&histogram->work, intel_histogram_handle_int_work); diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h index b44ba3afc94f79f291f4e5ebdd04dcf9434b48a4..0999d1720c7abee8907c77896e4b1e6ff756160f 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.h +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -18,9 +18,11 @@ struct intel_display; enum pipe; #define HISTOGRAM_BIN_COUNT 32 +#define HISTOGRAM_IET_LENGTH 33 struct intel_histogram { struct drm_histogram_caps *caps; + struct drm_iet_caps *iet_caps; struct intel_crtc *crtc; struct delayed_work work; bool enable; @@ -45,6 +47,8 @@ void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe); int intel_histogram_atomic_check(struct intel_crtc *intel_crtc); int intel_histogram_update(struct intel_crtc *intel_crtc, struct drm_histogram_config *config); +int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, + struct drm_property_blob *blob); int intel_histogram_init(struct intel_crtc *intel_crtc); void intel_histogram_finish(struct intel_crtc *intel_crtc); From patchwork Tue Jan 28 15:51:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDAEBC02195 for ; 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X-CSE-ConnectionGUID: AVf2R6wvRNGRns7rKoPHAA== X-CSE-MsgGUID: UoiNMR/nSB+h5kYZfk9T6g== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745055" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745055" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:22 -0800 X-CSE-ConnectionGUID: dWEl1nkyTh+ZXQbNsus5pA== X-CSE-MsgGUID: rMNU/I3jRUSR07Yep0SEvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145977009" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:19 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:17 +0530 Subject: [PATCH v8 11/14] drm/i915/crtc: Hook i915 IET LUT with the drm IET properties MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-11-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Upon drm getting the IET LUT value from the user through the IET_LUT property, i915 driver will write the LUT table to the hardware registers. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index b90017409a23de2a214ca43d32ba537998ea0f78..4e6c790f53ffe375e1b496fe48e9dc10e05bf11b 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -387,6 +387,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) if (drm_crtc_create_histogram_property(&crtc->base, crtc->histogram->caps)) drm_err(&dev_priv->drm, "Failed to initialize histogram properties\n"); + if (drm_crtc_create_iet_lut_property(&crtc->base, + crtc->histogram->iet_caps)) + drm_err(&dev_priv->drm, "Failed to initialize histogram properties\n"); intel_color_crtc_init(crtc); intel_drrs_crtc_init(crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c38a33ee90aef144931215254f178ba955f998b0..673012e716e448b4aef0db530f5eeb44edc14265 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7945,6 +7945,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_histogram_update(crtc, (struct drm_histogram_config *) new_crtc_state->uapi.histogram_enable->data); + if (new_crtc_state->uapi.iet_lut_updated) + intel_histogram_set_iet_lut(crtc, new_crtc_state->uapi.iet_lut); } /* Underruns don't always raise interrupts, so check manually */ From patchwork Tue Jan 28 15:51:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 641A7C02192 for ; Tue, 28 Jan 2025 16:06:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BEB2F10E6BE; Tue, 28 Jan 2025 16:06:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kZAzASAc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5577110E6BE; Tue, 28 Jan 2025 16:06:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738080384; x=1769616384; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=S3tCtPwDyTrwZ4hW+8pXWh+mAnLjcAgep9k6JveBlI0=; b=kZAzASAcrTqPWdjvvNxyrgNe1sm6MzavdHPU8+DRxiQOkJYDfL5TAsC2 MAYMvlTQpyEaD8OGv8cZqcl+IwBdSuuYQ5zUQ/WTgN8R8KucaabJvOvXt n2MBHjA4FcCjdvJpj2EavPGvhYj1Qk4pVRBlvuLagb1ScS/bzN/4XUg1Y yhQ2P4W+yWsO66Sdyh5BVBwqE45jbP22bM0FDPHHhF/EiRlatPgRE8mt2 gI3dzjtLCj/3mCJsVpsOXzF7Aiv6wY/T5Hqp4iFpbOifymXW4CCDU6YhH jQ+sFrAsxE/BTH/PzFlT9f+BcsmRZVCDeMacL7VpcbTkmjOUjR2wLl2Zw Q==; X-CSE-ConnectionGUID: E95/aH4tRj+RzJ7D1V7sqw== X-CSE-MsgGUID: /1U//4gISUu8Cr8wqdxtbw== X-IronPort-AV: E=McAfee;i="6700,10204,11329"; a="38745063" X-IronPort-AV: E=Sophos;i="6.13,241,1732608000"; d="scan'208";a="38745063" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2025 08:06:24 -0800 X-CSE-ConnectionGUID: un3bJSB9RW6s1zoio1Fgrw== X-CSE-MsgGUID: ow/6p6DoSOqydWmv3vzlQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="145977020" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:21 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:18 +0530 Subject: [PATCH v8 12/14] drm/i915/histogram: histogram delay counter doesnt reset MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-12-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The delay counter for histogram does not reset and as a result the histogram bin never gets updated. Workaround would be to use save and restore histogram register. v2: Follow the seq in interrupt handler Restore DPST bit 0 read/write dpst ctl rg Restore DPST bit 1 and Guardband Delay Interrupt counter = 0 (Suraj) v3: updated wa version for display 13 and 14 Wa: 14014889975 Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_histogram.c | 14 ++++++++++++++ drivers/gpu/drm/i915/display/intel_histogram_regs.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index aa02e7ce42b930a858de4ad7e0d39d93fa7d4298..dd4ab30795df48011013c019d7525e046cdd5404 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -52,6 +52,11 @@ static void intel_histogram_handle_int_work(struct work_struct *work) snprintf(pipe_id, sizeof(pipe_id), "PIPE=%u", intel_crtc->base.base.id); + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 13, 14)) + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_RESTORE, 0); + /* * TODO: PSR to be exited while reading the Histogram data * Set DPST_CTL Bin Reg function select to TC @@ -93,6 +98,15 @@ static void intel_histogram_handle_int_work(struct work_struct *work) return; } + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 13, 14)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT | + DPST_CTL_RESTORE, + DPST_CTL_GUARDBAND_INTERRUPT_DELAY(0x0) | + DPST_CTL_RESTORE); + /* Enable histogram interrupt */ intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, DPST_GUARD_HIST_INT_EN); diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index 1252b4f339a63f70f44e249bdeae87805bee20fc..213c9f483567cb19a47b44953749f6baf0afe9e7 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -16,6 +16,8 @@ #define DPST_CTL_RESTORE REG_BIT(28) #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) #define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT REG_GENMASK(23, 16) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY(val) REG_FIELD_PREP(DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT, val) #define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) #define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) From patchwork Tue Jan 28 15:51:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13952736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09EE4C02194 for ; Tue, 28 Jan 2025 16:06:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 65FC410E6B7; Tue, 28 Jan 2025 16:06:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="g57D9eDd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7B1FC10E6AD; Tue, 28 Jan 2025 16:06:26 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="145977032" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:24 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:19 +0530 Subject: [PATCH v8 13/14] drm/i915/histogram: Histogram changes for Display 20+ MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-13-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In Display 20+, new registers are added for setting index, reading histogram and writing the IET. v2: Removed duplicate code (Jani) v3: Moved histogram core changes to earlier patches (Jani/Suraj) v4: Rebased after addressing comments on patch 1 v5: Added the retry logic from patch3 and rebased the patch series v6: optimize wite_iet() (Suraj) Bspec: 68895 Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_histogram.c | 108 +++++++++++++++------ .../gpu/drm/i915/display/intel_histogram_regs.h | 25 +++++ 2 files changed, 104 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index dd4ab30795df48011013c019d7525e046cdd5404..f6844449e4bb6167116d223af316e5f3a5e8707c 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -22,6 +22,37 @@ #define HISTOGRAM_BIN_READ_RETRY_COUNT 5 #define IET_SAMPLE_FORMAT_1_INT_9_FRACT 0x1000009 +static void set_bin_index_0(struct intel_display *display, enum pipe pipe) +{ + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_IE_INDEX(pipe), + DPST_IE_BIN_INDEX_MASK, DPST_IE_BIN_INDEX(0)); + else + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_MASK, + DPST_CTL_BIN_REG_CLEAR); +} + +static void write_iet(struct intel_display *display, enum pipe pipe, + u32 *data) +{ + int i; + + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_IE_BIN(pipe), + DPST_IE_BIN_DATA_MASK, + DPST_IE_BIN_DATA(data[i])); + else + intel_de_rmw(display, DPST_BIN(pipe), + DPST_BIN_DATA_MASK, + DPST_BIN_DATA(data[i])); + + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", + i, data[i]); + } +} + static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) { struct intel_display *display = to_intel_display(intel_crtc); @@ -29,12 +60,27 @@ static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) int index; u32 dpstbin; + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_HIST_INDEX(intel_crtc->pipe), + DPST_HIST_BIN_INDEX_MASK, + DPST_HIST_BIN_INDEX(0)); + else + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + for (index = 0; index < ARRAY_SIZE(histogram->bin_data); index++) { - dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); + dpstbin = intel_de_read(display, (DISPLAY_VER(display) >= 20 ? + DPST_HIST_BIN(intel_crtc->pipe) : + DPST_BIN(intel_crtc->pipe))); if (!(dpstbin & DPST_BIN_BUSY)) { - histogram->bin_data[index] = dpstbin & DPST_BIN_DATA_MASK; - } else + histogram->bin_data[index] = dpstbin & (DISPLAY_VER(display) >= 20 ? + DPST_HIST_BIN_DATA_MASK : + DPST_BIN_DATA_MASK); + } else { + drm_err(display->drm, "Histogram bin busy, retyring\n"); + fsleep(2); return false; + } } return true; } @@ -62,8 +108,6 @@ static void intel_histogram_handle_int_work(struct work_struct *work) * Set DPST_CTL Bin Reg function select to TC * Set DPST_CTL Bin Register Index to 0 */ - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); for (retry = 0; retry < HISTOGRAM_BIN_READ_RETRY_COUNT; retry++) { if (intel_histogram_get_data(intel_crtc)) { u32 *data; @@ -156,17 +200,27 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc, u8 mode) if (histogram->enable) return 0; - - /* enable histogram, clear DPST_CTL bin reg func select to TC */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | - DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT | - DPST_CTL_ENHANCEMENT_MODE_MASK | DPST_CTL_IE_MODI_TABLE_EN, - ((mode == DRM_MODE_HISTOGRAM_HSV_MAX_RGB) ? - DPST_CTL_BIN_REG_FUNC_TC : 0) | DPST_CTL_IE_HIST_EN | - DPST_CTL_HIST_MODE_HSV | - DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC | - DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); + /* enable histogram, clear DPST_BIN reg and select TC function */ + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE, + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV); + else + /* enable histogram, clear DPST_CTL bin reg func select to TC */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE | + DPST_CTL_IE_TABLE_VALUE_FORMAT | + DPST_CTL_ENHANCEMENT_MODE_MASK | + DPST_CTL_IE_MODI_TABLE_EN, + ((mode == DRM_MODE_HISTOGRAM_HSV_MAX_RGB) ? + DPST_CTL_BIN_REG_FUNC_TC : 0) | + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV | + DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC | + DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); /* Re-Visit: check if wait for one vblank is required */ drm_crtc_wait_one_vblank(&intel_crtc->base); @@ -244,7 +298,6 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, struct intel_histogram *histogram = intel_crtc->histogram; struct intel_display *display = to_intel_display(intel_crtc); int pipe = intel_crtc->pipe; - int i = 0; struct drm_iet_1dlut_sample *iet; u32 *data; int ret; @@ -262,15 +315,15 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, return -EINVAL; } - /* Set DPST_CTL Bin Reg function select to IE & wait for a vblabk */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_IE); - drm_crtc_wait_one_vblank(&intel_crtc->base); + if (DISPLAY_VER(display) < 20) { + /* Set DPST_CTL Bin Reg function select to IE & wait for a vblabk */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL, + DPST_CTL_BIN_REG_FUNC_IE); + } - /* Set DPST_CTL Bin Register Index to 0 */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_MASK, DPST_CTL_BIN_REG_CLEAR); + set_bin_index_0(display, pipe); iet = (struct drm_iet_1dlut_sample *)blob->data; data = kzalloc(sizeof(data) * iet->nr_elements, GFP_KERNEL); @@ -281,11 +334,8 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, if (ret) return ret; - for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { - intel_de_rmw(display, DPST_BIN(pipe), - DPST_BIN_DATA_MASK, data[i]); - drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); - } + write_iet(display, pipe, data); + kfree(data); drm_property_blob_put(intel_crtc->base.state->iet_lut); diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index 213c9f483567cb19a47b44953749f6baf0afe9e7..3fbb9c2deaae6278d5a832dfb61ef860de0c6f21 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -45,6 +45,31 @@ #define _DPST_BIN_B 0x491C4 #define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) #define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) +#define DPST_BIN_DATA(val) REG_FIELD_PREP(DPST_BIN_DATA_MASK, val) #define DPST_BIN_BUSY REG_BIT(31) +#define _DPST_HIST_INDEX_A 0x490D8 +#define _DPST_HIST_INDEX_B 0x491D8 +#define DPST_HIST_INDEX(pipe) _MMIO_PIPE(pipe, _DPST_HIST_INDEX_A, _DPST_HIST_INDEX_B) +#define DPST_HIST_BIN_INDEX_MASK REG_GENMASK(4, 0) +#define DPST_HIST_BIN_INDEX(val) REG_FIELD_PREP(DPST_HIST_BIN_INDEX_MASK, val) + +#define _DPST_HIST_BIN_A 0x490C4 +#define _DPST_HIST_BIN_B 0x491C4 +#define DPST_HIST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_HIST_BIN_A, _DPST_HIST_BIN_B) +#define DPST_HIST_BIN_BUSY REG_BIT(31) +#define DPST_HIST_BIN_DATA_MASK REG_GENMASK(30, 0) + +#define _DPST_IE_BIN_A 0x490CC +#define _DPST_IE_BIN_B 0x491CC +#define DPST_IE_BIN(pipe) _MMIO_PIPE(pipe, _DPST_IE_BIN_A, _DPST_IE_BIN_B) +#define DPST_IE_BIN_DATA_MASK REG_GENMASK(9, 0) +#define DPST_IE_BIN_DATA(val) REG_FIELD_PREP(DPST_IE_BIN_DATA_MASK, val) + +#define _DPST_IE_INDEX_A 0x490DC +#define _DPST_IE_INDEX_B 0x491DC +#define DPST_IE_INDEX(pipe) _MMIO_PIPE(pipe, _DPST_IE_INDEX_A, _DPST_IE_INDEX_B) +#define DPST_IE_BIN_INDEX_MASK REG_GENMASK(6, 0) +#define DPST_IE_BIN_INDEX(val) REG_FIELD_PREP(DPST_IE_BIN_INDEX_MASK, val) + #endif /* __INTEL_HISTOGRAM_REGS_H__ */ From patchwork Tue Jan 28 15:51:20 2025 Content-Type: text/plain; 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d="scan'208";a="145977051" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa001.jf.intel.com with ESMTP; 28 Jan 2025 08:06:26 -0800 From: Arun R Murthy Date: Tue, 28 Jan 2025 21:21:20 +0530 Subject: [PATCH v8 14/14] drm/i915/histogram: Enable pipe dithering MIME-Version: 1.0 Message-Id: <20250128-dpst-v8-14-871b94d777f8@intel.com> References: <20250128-dpst-v8-0-871b94d777f8@intel.com> In-Reply-To: <20250128-dpst-v8-0-871b94d777f8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: suraj.kandpal@intel.com, dmitry.baryshkov@linaro.org, Arun R Murthy X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable pipe dithering while enabling histogram to overcome some atrifacts seen on the screen. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_histogram.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index f6844449e4bb6167116d223af316e5f3a5e8707c..ead9c2391d460f459dfca8e99ea423a34418e67d 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -22,6 +22,13 @@ #define HISTOGRAM_BIN_READ_RETRY_COUNT 5 #define IET_SAMPLE_FORMAT_1_INT_9_FRACT 0x1000009 +static void intel_histogram_enable_dithering(struct intel_display *display, + enum pipe pipe) +{ + intel_de_rmw(display, PIPE_MISC(pipe), PIPE_MISC_DITHER_ENABLE, + PIPE_MISC_DITHER_ENABLE); +} + static void set_bin_index_0(struct intel_display *display, enum pipe pipe) { if (DISPLAY_VER(display) >= 20) @@ -200,6 +207,10 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc, u8 mode) if (histogram->enable) return 0; + + /* Pipe Dithering should be enabled with histogram */ + intel_histogram_enable_dithering(display, pipe); + /* enable histogram, clear DPST_BIN reg and select TC function */ if (DISPLAY_VER(display) >= 20) intel_de_rmw(display, DPST_CTL(pipe),