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While atu.cpu_address happens to be the same here, it actually represents the parent bus address before ATU, which may not always align with the CPU address. Using resource start ensures correctness and clarity. Signed-off-by: Frank Li --- change from v9 to v10 - new patch --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ffaded8f2df7b..ae3fd2a5dbf85 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -908,7 +908,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) if (ret) return ret; - mem = ioremap(atu.cpu_addr, pci->region_align); + mem = ioremap(pci->pp.msg_res->start, pci->region_align); if (!mem) return -ENOMEM; From patchwork Tue Jan 28 22:07:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13953229 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013024.outbound.protection.outlook.com [40.107.159.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E924F19ADA2 for ; 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The ATU translates parent bus addresses to PCI addresses, which are often the same as CPU addresses but can differ in systems where the bus fabric translates addresses before passing them to the PCIe controller. This renaming clarifies the purpose and avoids confusion. Signed-off-by: Frank Li --- change from v9 to v10 - new patch --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 +++--- drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++---- drivers/pci/controller/dwc/pcie-designware.c | 34 +++++++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 2 +- 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8e07d432e74f2..80ac2f9e88eb5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -128,7 +128,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, - dma_addr_t cpu_addr, enum pci_barno bar, + dma_addr_t parent_bus_addr, enum pci_barno bar, size_t size) { int ret; @@ -146,7 +146,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, } ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type, - cpu_addr, bar, size); + parent_bus_addr, bar, size); if (ret < 0) { dev_err(pci->dev, "Failed to program IB window\n"); return ret; @@ -181,7 +181,7 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, return ret; set_bit(free_win, ep->ob_window_map); - ep->outbound_addr[free_win] = atu->cpu_addr; + ep->outbound_addr[free_win] = atu->parent_bus_addr; return 0; } @@ -333,7 +333,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, atu.func_no = func_no; atu.type = PCIE_ATU_TYPE_MEM; - atu.cpu_addr = addr; + atu.parent_bus_addr = addr; atu.pci_addr = pci_addr; atu.size = size; ret = dw_pcie_ep_outbound_atu(ep, &atu); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ae3fd2a5dbf85..1206b26bff3f2 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -616,7 +616,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, type = PCIE_ATU_TYPE_CFG1; atu.type = type; - atu.cpu_addr = pp->cfg0_base; + atu.parent_bus_addr = pp->cfg0_base; atu.pci_addr = busdev; atu.size = pp->cfg0_size; @@ -641,7 +641,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, if (pp->cfg0_io_shared) { atu.type = PCIE_ATU_TYPE_IO; - atu.cpu_addr = pp->io_base; + atu.parent_bus_addr = pp->io_base; atu.pci_addr = pp->io_bus_addr; atu.size = pp->io_size; @@ -667,7 +667,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, if (pp->cfg0_io_shared) { atu.type = PCIE_ATU_TYPE_IO; - atu.cpu_addr = pp->io_base; + atu.parent_bus_addr = pp->io_base; atu.pci_addr = pp->io_bus_addr; atu.size = pp->io_size; @@ -736,7 +736,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.index = i; atu.type = PCIE_ATU_TYPE_MEM; - atu.cpu_addr = entry->res->start; + atu.parent_bus_addr = entry->res->start; atu.pci_addr = entry->res->start - entry->offset; /* Adjust iATU size if MSG TLP region was allocated before */ @@ -758,7 +758,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pci->num_ob_windows > ++i) { atu.index = i; atu.type = PCIE_ATU_TYPE_IO; - atu.cpu_addr = pp->io_base; + atu.parent_bus_addr = pp->io_base; atu.pci_addr = pp->io_bus_addr; atu.size = pp->io_size; @@ -902,7 +902,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) atu.size = resource_size(pci->pp.msg_res); atu.index = pci->pp.msg_atu_index; - atu.cpu_addr = pci->pp.msg_res->start; + atu.parent_bus_addr = pci->pp.msg_res->start; ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072c..9d0a5f75effcc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -470,25 +470,25 @@ static inline u32 dw_pcie_enable_ecrc(u32 val) int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu) { - u64 cpu_addr = atu->cpu_addr; + u64 parent_bus_addr = atu->parent_bus_addr; u32 retries, val; u64 limit_addr; if (pci->ops && pci->ops->cpu_addr_fixup) - cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); + parent_bus_addr = pci->ops->cpu_addr_fixup(pci, parent_bus_addr); - limit_addr = cpu_addr + atu->size - 1; + limit_addr = parent_bus_addr + atu->size - 1; - if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || - !IS_ALIGNED(cpu_addr, pci->region_align) || + if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) || + !IS_ALIGNED(parent_bus_addr, pci->region_align) || !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { return -EINVAL; } dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, - lower_32_bits(cpu_addr)); + lower_32_bits(parent_bus_addr)); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, - upper_32_bits(cpu_addr)); + upper_32_bits(parent_bus_addr)); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, lower_32_bits(limit_addr)); @@ -502,7 +502,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, upper_32_bits(atu->pci_addr)); val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); - if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && + if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; if (dw_pcie_ver_is(pci, 490A)) @@ -545,13 +545,13 @@ static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg } int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, - u64 cpu_addr, u64 pci_addr, u64 size) + u64 parent_bus_addr, u64 pci_addr, u64 size) { u64 limit_addr = pci_addr + size - 1; u32 retries, val; if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) || - !IS_ALIGNED(cpu_addr, pci->region_align) || + !IS_ALIGNED(parent_bus_addr, pci->region_align) || !IS_ALIGNED(pci_addr, pci->region_align) || !size) { return -EINVAL; } @@ -568,9 +568,9 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, upper_32_bits(limit_addr)); dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, - lower_32_bits(cpu_addr)); + lower_32_bits(parent_bus_addr)); dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET, - upper_32_bits(cpu_addr)); + upper_32_bits(parent_bus_addr)); val = type; if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) && @@ -597,18 +597,18 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, } int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar, size_t size) + int type, u64 parent_bus_addr, u8 bar, size_t size) { u32 retries, val; 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Typical PCI data flow involves: CPU (CPU address) -> Bus Fabric (Intermediate address) -> PCI Controller (PCI bus address) -> PCI Bus. While most bus fabrics preserve address consistency, some modify addresses to intermediate values. The `parent_bus_offset` enables PCI controllers to translate these intermediate addresses correctly to PCI bus addresses. Pave the road to remove hardcoded cpu_addr_fixup() and similar patterns in PCI controller drivers. Signed-off-by: Frank Li --- change from v9 to v10 - new patch --- drivers/pci/bus.c | 11 +++++++++-- drivers/pci/of.c | 12 +++++++++++- include/linux/pci.h | 2 ++ include/linux/resource_ext.h | 1 + 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 98910bc0fcc4e..52e88c391e256 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -31,8 +31,8 @@ struct pci_bus_resource { struct resource *res; }; -void pci_add_resource_offset(struct list_head *resources, struct resource *res, - resource_size_t offset) +void pci_add_resource_parent_bus_offset(struct list_head *resources, struct resource *res, + resource_size_t offset, resource_size_t parent_bus_offset) { struct resource_entry *entry; @@ -43,8 +43,15 @@ void pci_add_resource_offset(struct list_head *resources, struct resource *res, } entry->offset = offset; + entry->parent_bus_offset = parent_bus_offset; resource_list_add_tail(entry, resources); } + +void pci_add_resource_offset(struct list_head *resources, struct resource *res, + resource_size_t offset) +{ + pci_add_resource_parent_bus_offset(resources, res, offset, 0); +} EXPORT_SYMBOL(pci_add_resource_offset); void pci_add_resource(struct list_head *resources, struct resource *res) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 7a806f5c0d201..aa4a2e266c55e 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -402,7 +402,17 @@ static int devm_of_pci_get_host_bridge_resources(struct device *dev, res->flags &= ~IORESOURCE_MEM_64; } - pci_add_resource_offset(resources, res, res->start - range.pci_addr); + /* + * IORESOURCE_IO res->start is io space start address. + * IORESOURCE_MEM res->start is cpu start address, which is the + * same as range.cpu_addr. + * + * Use (range.cpu_addr - range.parent_bus_addr) to align both + * IO and MEM's parent_bus_offset always offset to cpu address. + */ + + pci_add_resource_parent_bus_offset(resources, res, res->start - range.pci_addr, + range.cpu_addr - range.parent_bus_addr); } /* Check for dma-ranges property */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa5..0d7e67b47be47 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1510,6 +1510,8 @@ static inline void pci_release_config_region(struct pci_dev *pdev, void pci_add_resource(struct list_head *resources, struct resource *res); void pci_add_resource_offset(struct list_head *resources, struct resource *res, resource_size_t offset); +void pci_add_resource_parent_bus_offset(struct list_head *resources, struct resource *res, + resource_size_t offset, resource_size_t parent_bus_offset); void pci_free_resource_list(struct list_head *resources); void pci_bus_add_resource(struct pci_bus *bus, struct resource *res); struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); diff --git a/include/linux/resource_ext.h b/include/linux/resource_ext.h index ff0339df56afc..b6ec6cc318203 100644 --- a/include/linux/resource_ext.h +++ b/include/linux/resource_ext.h @@ -24,6 +24,7 @@ struct resource_entry { struct list_head node; struct resource *res; /* In master (CPU) address space */ resource_size_t offset; /* Translation offset for bridge */ + resource_size_t parent_bus_offset; /* Parent bus address offset for bridge */ struct resource __res; /* Default storage for res */ }; From patchwork Tue Jan 28 22:07:37 2025 Content-Type: text/plain; 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Most system's bus fabric use 1:1 map between input and output address. but some hardware like i.MX8QXP doesn't use 1:1 map. See below diagram: ┌─────────┐ ┌────────────┐ ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ 0x7ff8_0000─┼───┘ │ │ │ │ │ │ │ │ │ │ │ │ │ PCI Addr 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► │ │ │ │ │ 0 0x7000_0000─┼────────►├─────────┐ │ │ │ └─────────┘ │ └──────► CfgSpace ─┼────────────► BUS Fabric │ │ │ 0 │ │ │ └──────────► MemSpace ─┼────────────► IA: 0x8000_0000 │ │ 0x8000_0000 └────────────┘ bus@5f000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; Term Intermediate address (IA) here means the address just before PCIe controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can be removed. Signed-off-by: Frank Li --- chagne from v8 to v9 - use resoure_entry parent_bus_offset to simple code logic - add check for use_parent_dt_ranges and cpu_addr_fixup to make sure only one set. Change from v7 to v8 - Add dev_warning_once at dw_pcie_iatu_detect() to reminder cpu_addr_fixup() user to correct their code - use 'use_parent_dt_ranges' control enable use dt parent bus node ranges. - rename dw_pcie_get_untranslate_addr to dw_pcie_get_parent_addr(). - of_property_read_reg() already have comments, so needn't add more. - return actual err code from function Change from v6 to v7 Add a resource_size_t parent_bus_addr local varible to fix 32bit build error. | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/ Chagne from v5 to v6 -add comments for of_property_read_reg(). Change from v4 to v5 - remove confused 0x5f00_0000 range in sample dts. - reorder address at above diagram. Change from v3 to v4 - none Change from v2 to v3 - %s/cpu_untranslate_addr/parent_bus_addr/g - update diagram. - improve commit message. Change from v1 to v2 - update because patch1 change get untranslate address method. - add using_dtbus_info in case break back compatibility for exited platform. --- drivers/pci/controller/dwc/pcie-designware-host.c | 34 +++++++++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++ 3 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 1206b26bff3f2..a0c8e6f66ec4d 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -413,8 +413,10 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) res->name = "msg"; res->flags = win->res->flags | IORESOURCE_BUSY; - if (!devm_request_resource(pci->dev, win->res, res)) + if (!devm_request_resource(pci->dev, win->res, res)) { pp->msg_res = res; + pp->msg_parent_bus_offset = win->parent_bus_offset; + } } } @@ -427,6 +429,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct resource_entry *win; struct pci_host_bridge *bridge; struct resource *res; + int index; int ret; raw_spin_lock_init(&pp->lock); @@ -448,6 +451,26 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (IS_ERR(pp->va_cfg0_base)) return PTR_ERR(pp->va_cfg0_base); + if (pci->use_parent_dt_ranges) { + if (pci->ops->cpu_addr_fixup) { + dev_err(dev, "Use parent bus DT ranges, cpu_addr_fixup() must be removed\n"); + return -EINVAL; + } + + index = of_property_match_string(np, "reg-names", "config"); + if (index < 0) + return -EINVAL; + + /* + * Retrieve the parent bus address of PCI config space. + * If the parent bus ranges in the device tree provide + * the correct address conversion information, set + * 'use_parent_dt_ranges' to true, The + * 'cpu_addr_fixup()' can be eliminated. + */ + of_property_read_reg(np, index, &pp->cfg0_base, NULL); + } + bridge = devm_pci_alloc_host_bridge(dev, 0); if (!bridge) return -ENOMEM; @@ -460,6 +483,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_size = resource_size(win->res); pp->io_bus_addr = win->res->start - win->offset; pp->io_base = pci_pio_to_address(win->res->start); + /* In case ranges in pci node provide wrong information */ + if (pci->use_parent_dt_ranges) + pp->io_base -= win->parent_bus_offset; } /* Set default bus ops */ @@ -739,6 +765,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.parent_bus_addr = entry->res->start; atu.pci_addr = entry->res->start - entry->offset; + /* In case ranges in pci node provide wrong information */ + if (pci->use_parent_dt_ranges) + atu.parent_bus_addr -= entry->parent_bus_offset; + /* Adjust iATU size if MSG TLP region was allocated before */ if (pp->msg_res && pp->msg_res->parent == entry->res) atu.size = resource_size(entry->res) - @@ -902,7 +932,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) atu.size = resource_size(pci->pp.msg_res); atu.index = pci->pp.msg_atu_index; - atu.parent_bus_addr = pci->pp.msg_res->start; + atu.parent_bus_addr = pci->pp.msg_res->start - pci->pp.msg_parent_bus_offset; ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 9d0a5f75effcc..909b14986660c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -841,6 +841,15 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) pci->region_align = 1 << fls(min); pci->region_limit = (max << 32) | (SZ_4G - 1); + if (pci->ops && pci->ops->cpu_addr_fixup) { + /* + * If the parent 'ranges' property in DT correctly describes + * the address translation, cpu_addr_fixup() callback is not + * needed. + */ + dev_warn_once(pci->dev, "cpu_addr_fixup() usage detected. Please fix DT!\n"); + } + dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n", dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F", pci->num_ob_windows, pci->num_ib_windows, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ac23604c829f4..483911ab9e629 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -380,6 +380,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + resource_size_t msg_parent_bus_offset; bool use_linkup_irq; }; @@ -465,6 +466,13 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + /* + * This flag indicates that the vendor driver uses devicetree 'ranges' + * property to allow iATU to use the Intermediate Address (IA) for + * outbound mapping. Using this flag also avoids the usage of + * 'cpu_addr_fixup' callback implementation in the driver. + */ + bool use_parent_dt_ranges; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Tue Jan 28 22:07:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13953232 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013057.outbound.protection.outlook.com [40.107.159.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C9671F55E8 for ; Tue, 28 Jan 2025 22:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.159.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738102133; cv=fail; b=IFwQzgfa2gsP5xii3KmR4kPMckMGujyAcw4aatANjLp5BVgkiW5maBlM85R1qTboDnZf8q9owGxg59Dv8MF79yyLVNKnlYkrlOHjRC+VNTObNipvJxWLvozvIY30py4NtIHF0EALoh1MASvDdIlQNIWIlzlLoj+/QS7CL0f7Fho= ARC-Message-Signature: i=2; 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The bus fabric generally passes the same address to the PCIe EP controller, but some bus fabrics map the address before sending it to the PCIe EP controller. Above diagram, CPU write data to outbound windows address 0x7000_0000, Bus fabric map it to 0x8000_0000. ATU should use bus address 0x8000_0000 as input address and map to PCI address 0xA000_0000 (dynamic alloc and assign from pci device driver in host side). Previously, 'cpu_addr_fixup()' was used to handle address conversion. Now, the device tree provides this information, preferring a common method. bus@5f000000 { compatible = "simple-bus"; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie-ep@5f010000 { reg = <0x80000000 0x10000000>; reg-names ="addr_space"; ... }; ... }; 'ranges' in bus@5f000000 descript how address map from CPU address to bus address. Use `of_property_read_reg()` to obtain the bus address and set it to the ATU correctly, eliminating the need for vendor-specific cpu_addr_fixup(). Use 'use_parent_dt_ranges' to indicate device tree reflect correctly bus address translation in case break compatibility. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Change from v8 to v9 - change bus_addr_base to parent_bus_addr - fix dw_pcie_find_index() address compare, which cause atu allocate failure when run many time test. Change from v7 to v8 - Add Mani's reviewedby tag - s/convert/map in commit message - update comments for of_property_read_reg() - use 'use_parent_dt_ranges' Change from v6 to v7 - none Change from v5 to v6 - update diagram - Add comments for of_property_read_reg() - Remove unrelated 0x5f00_0000 in commit message Change from v3 to v4 - change parent_bus_addr to u64 to fix 32bit build error | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202410230328.BTHareG1-lkp@intel.com/ Change from v2 to v3 - Add using_dtbus_info to control if use device tree bus ranges information. --- drivers/pci/controller/dwc/pcie-designware-ep.c | 21 +++++++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 80ac2f9e88eb5..d0d6c4e8df80c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "pcie-designware.h" @@ -279,11 +280,12 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr, u32 *atu_index) { + phys_addr_t parent_bus_addr = addr - ep->phys_base + ep->parent_bus_addr; u32 index; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); for (index = 0; index < pci->num_ob_windows; index++) { - if (ep->outbound_addr[index] != addr) + if (ep->outbound_addr[index] != parent_bus_addr) continue; *atu_index = index; return 0; @@ -333,7 +335,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, atu.func_no = func_no; atu.type = PCIE_ATU_TYPE_MEM; - atu.parent_bus_addr = addr; + atu.parent_bus_addr = addr - ep->phys_base + ep->parent_bus_addr; atu.pci_addr = pci_addr; atu.size = size; ret = dw_pcie_ep_outbound_atu(ep, &atu); @@ -901,6 +903,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; + int index; INIT_LIST_HEAD(&ep->func_list); @@ -913,6 +916,20 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -EINVAL; ep->phys_base = res->start; + ep->parent_bus_addr = ep->phys_base; + + if (pci->use_parent_dt_ranges) { + index = of_property_match_string(np, "reg-names", "addr_space"); + if (index < 0) + return -EINVAL; + + /* + * Get the untranslated bus address from devicetree to use it + * as the iATU CPU address in dw_pcie_ep_map_addr(). + */ + of_property_read_reg(np, index, &ep->parent_bus_addr, NULL); + } + ep->addr_size = resource_size(res); if (ep->ops->pre_init) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 483911ab9e629..3d9bf2b43bcf2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -413,6 +413,7 @@ struct dw_pcie_ep { struct list_head func_list; const struct dw_pcie_ep_ops *ops; phys_addr_t phys_base; + u64 parent_bus_addr; size_t addr_size; size_t page_size; u8 bar_to_atu[PCI_STD_NUM_BARS]; From patchwork Tue Jan 28 22:07:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13953233 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013021.outbound.protection.outlook.com [40.107.159.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E75E81F560B for ; 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'ep->outbound_addr[n]', representing 'parent_bus_address', might be 0 on some hardware, which trims high address bits through bus fabric before sending to the PCIe controller. Replace the iteration logic with 'for_each_set_bit()' to ensure only allocated map windows are iterated when determining the ATU index from a given address. Signed-off-by: Frank Li --- change from v8 to v9 - new patch --- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index d0d6c4e8df80c..c1767450541a4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -284,7 +284,7 @@ static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr, u32 index; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - for (index = 0; index < pci->num_ob_windows; index++) { + for_each_set_bit(index, ep->ob_window_map, pci->num_ob_windows) { if (ep->outbound_addr[index] != parent_bus_addr) continue; *atu_index = index; From patchwork Tue Jan 28 22:07:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13953234 Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazon11010038.outbound.protection.outlook.com [52.101.69.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34FEC1F63E0 for ; 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Acked-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Change from v8 to v9 - rebase latest linux-next (close enough to v6.14-rc1) Change from v7 to v8 - add mani and richard's review/ack tag - use varible 'use_parent_dt_ranges' Change from v2 to v7 - none Change from v1 to v2 - set using_dtbus_info true --- drivers/pci/controller/dwc/pci-imx6.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 90ace941090f9..d1eb535df73e1 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1217,22 +1217,6 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } -static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) -{ - struct imx_pcie *imx_pcie = to_imx_pcie(pcie); - struct dw_pcie_rp *pp = &pcie->pp; - struct resource_entry *entry; - - if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_CPU_ADDR_FIXUP)) - return cpu_addr; - - entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); - if (!entry) - return cpu_addr; - - return cpu_addr - entry->offset; -} - /* * In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2 * register is reserved, so the generic DWC implementation of sending the @@ -1263,7 +1247,6 @@ static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops = { static const struct dw_pcie_ops dw_pcie_ops = { .start_link = imx_pcie_start_link, .stop_link = imx_pcie_stop_link, - .cpu_addr_fixup = imx_pcie_cpu_addr_fixup, }; static void imx_pcie_ep_init(struct dw_pcie_ep *ep) @@ -1645,6 +1628,7 @@ static int imx_pcie_probe(struct platform_device *pdev) if (ret) return ret; + pci->use_parent_dt_ranges = true; if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { ret = imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0)