From patchwork Wed Jan 29 09:16:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Kondratiev X-Patchwork-Id: 13953544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E139EC02193 for ; Wed, 29 Jan 2025 09:17:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GqOOvM1Tai+YO/WB3GvpzX9xCIza2wuDIHd2fOfvenM=; b=Q0QO+wuFb6ZYe/ lNSMyYkHWnNH3SPQJrcxBhiNR7BH8zhx5cHqxh+uInzp+YhH8QJsBy/7Hbdzh/HD99Y9+w0Fds96z qlspcs/KH19zIoFribJkBNa38kzqWpMxoNPJYUTgfpkzQNakplYu1nKOymx3D9XsiIDfDeLAkoklf 4Jfs2R2lS5BJ2P8iIDvx7PZf5F3SIf/IzB9hxio1RYf0g9q//48w3+wmBg3LdMRCfL3sXG2EOA/fy m08dbVkXccjOMx8dz922w578NwwF6wnjbgRaKLO29RMOh1NoK+GU03X7tcTGIWlDCI+Wj+Zt3KX8M BnXpuuKeKK/ZruxWWzTQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1td4Bp-00000006d3r-1wMB; Wed, 29 Jan 2025 09:16:53 +0000 Received: from esa3.hc555-34.eu.iphmx.com ([207.54.77.50]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1td4Bj-00000006d2N-3JyM for linux-riscv@lists.infradead.org; Wed, 29 Jan 2025 09:16:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1738142207; x=1769678207; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RuLMyg00bccCqWy5ag3jnD3Wp6i4VgyvkXDG4+7ywCc=; b=XWIFWXXT9scOvXaOr5Kg1GqmCz+/Jwk5256Aaf2xI738LPaelMXqZPAK ntcdzbzRa5bm0tje0kZOGOUzxOauAYfbHUcY7eV4sMtHPpJqEnWfqCo5H DVa6S5PKVL0OxNANkKQ5WnfTAhlh4aBKD4gY2pxF/6ffld4T6I7d7speJ Wl9nSOTPPvnNyG7FlNHXBrNnJIO0rFKJf3E1G1ra485DkLfgLStwZfRSd xM/h04j0bxVfBy8ZrpJOdSD/1rcNko4sQHEvi/ZXjgGgSJiZT8nMQxf2B RTyosAmj/nllZUzlAm3EFBQkORljRatVKXcYAcgHJV+55b5ETfWYJsJ0/ A==; X-CSE-ConnectionGUID: vZ3/icCeRI61AiJMgzrgqg== X-CSE-MsgGUID: V/nDsDSjRkyhxc9AR4IfxA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces01_data.me-corp.lan) ([146.255.191.134]) by esa3.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2025 11:16:43 +0200 X-CSE-ConnectionGUID: tbf5rMDISg2CrWsetK4ZqA== X-CSE-MsgGUID: POnzwu9sQI+9OTm8Qn89Kw== Received: from unknown (HELO epgd022.me-corp.lan) ([10.154.54.6]) by ces01_data.me-corp.lan with SMTP; 29 Jan 2025 11:16:42 +0200 Received: by epgd022.me-corp.lan (sSMTP sendmail emulation); Wed, 29 Jan 2025 11:16:42 +0200 From: Vladimir Kondratiev To: Anup Patel , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Vladimir Kondratiev Subject: [PATCH v5 1/2] dt-bindings: interrupt-controller: add risc-v,aplic hart indexes Date: Wed, 29 Jan 2025 11:16:36 +0200 Message-ID: <20250129091637.1667279-2-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250129091637.1667279-1-vladimir.kondratiev@mobileye.com> References: <87ed0o87qg.ffs@tglx> <20250129091637.1667279-1-vladimir.kondratiev@mobileye.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250129_011648_180016_FB5D88ED X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Document optional property "riscv,hart-indexes" Risc-V APLIC specification defines "hart index" in [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, this document says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indexes specified in optional APLIC property "riscv,hart-indexes" that should be array of u32 elements, one per interrupt target. If this property not specified, fallback is to use logical hart indexes within the domain. [1]: https://github.com/riscv/riscv-aia Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Reviewed-by: Rob Herring (Arm) --- .../bindings/interrupt-controller/riscv,aplic.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml index 190a6499c932..bef00521d5da 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -91,6 +91,14 @@ properties: Firmware must configure interrupt delegation registers based on interrupt delegation list. + riscv,hart-indexes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16384 + description: + A list of hart indexes that APLIC should use to address each hart + that is mentioned in the "interrupts-extended" + dependencies: riscv,delegation: [ "riscv,children" ] From patchwork Wed Jan 29 09:16:37 2025 Content-Type: text/plain; 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Wed, 29 Jan 2025 11:16:43 +0200 From: Vladimir Kondratiev To: Anup Patel , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Vladimir Kondratiev Subject: [PATCH v5 2/2] irqchip/riscv-aplic: add support for hart indexes Date: Wed, 29 Jan 2025 11:16:37 +0200 Message-ID: <20250129091637.1667279-3-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250129091637.1667279-1-vladimir.kondratiev@mobileye.com> References: <87ed0o87qg.ffs@tglx> <20250129091637.1667279-1-vladimir.kondratiev@mobileye.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250129_011652_224629_8C1CECC2 X-CRM114-Status: GOOD ( 19.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Risc-V APLIC specification defines "hart index" in [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, this document says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indexes specified in optional APLIC property "riscv,hart-indexes" that should be array of u32 elements, one per interrupt target. If this property not specified, fallback is to use logical hart indexes within the domain. [1]: https://github.com/riscv/riscv-aia Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel --- drivers/irqchip/irq-riscv-aplic-direct.c | 25 +++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c index 7cd6b646774b..ea61329decb2 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -31,7 +31,7 @@ struct aplic_direct { }; struct aplic_idc { - unsigned int hart_index; + u32 hart_index; void __iomem *regs; struct aplic_direct *direct; }; @@ -219,6 +219,21 @@ static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, return 0; } +static int aplic_direct_get_hart_index(struct device *dev, u32 logical_index, + u32 *hart_index) +{ + static const char *prop_hart_index = "riscv,hart-indexes"; + struct device_node *np = to_of_node(dev->fwnode); + + if (!np || !of_property_present(np, prop_hart_index)) { + *hart_index = logical_index; + return 0; + } + + return of_property_read_u32_index(np, prop_hart_index, + logical_index, hart_index); +} + int aplic_direct_setup(struct device *dev, void __iomem *regs) { int i, j, rc, cpu, current_cpu, setup_count = 0; @@ -265,8 +280,12 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) cpumask_set_cpu(cpu, &direct->lmask); idc = per_cpu_ptr(&aplic_idcs, cpu); - idc->hart_index = i; - idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + rc = aplic_direct_get_hart_index(dev, i, &idc->hart_index); + if (rc) { + dev_warn(dev, "hart index not found for IDC%d\n", i); + continue; + } + idc->regs = priv->regs + APLIC_IDC_BASE + idc->hart_index * APLIC_IDC_SIZE; idc->direct = direct; aplic_idc_set_delivery(idc, true);