From patchwork Wed Jan 29 16:37:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953935 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8D6081DF75C; Wed, 29 Jan 2025 16:51:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169516; cv=none; b=s8n8PGRxfboR2LZYrX0DXOeH/efW3TBL0cPLhqFmWGSEuwfoxZkn5ZFjaiNVNuc/2iDMuMz7k2ZNyjnIfRb77HQOyrIx1vk3Jf+e8PVl2L9HX6zmQLIxg1O46jBCj9rjZmYhmAhy0UPlxhvSItJQaBztffwx+KHB7SzWeklA3yQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169516; c=relaxed/simple; bh=9Awco8bh02tDySRKOsPRww6f9FIo7X0VENeVmK7Y2Tw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CyYPOLKL2t8BTy8yno9qVsZQ+y9dneagShdU5iJMKxryQ6X8KIscyQt4miZqe6hWDCuBAhUvnzKP8BO0xXhcwKQT5RmoDK9LMpPv7jizadY4DSlsC04JxGwxTPheaZK+a5xAb4hNVRQb7ptnDnBOXLefHlArV8p0XsWE2fBF5jo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: KUrJTWu+RTqcc4S60ZXDZg== X-CSE-MsgGUID: f71asUKkQYudLlbuFKhCkw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:51:44 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 68942402E786; Thu, 30 Jan 2025 01:51:41 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Thierry Bultel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] dt-bindings: soc: Document Renesas RZ/T2H (R9A09G077) SoC Date: Wed, 29 Jan 2025 16:37:37 +0000 Message-ID: <20250129165122.2980-2-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add RZ/T2H (R9A09G077) and variants in documentation. Signed-off-by: Thierry Bultel --- .../devicetree/bindings/soc/renesas/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd..33f9e37a3d3d 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -535,6 +535,14 @@ properties: - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support - const: renesas,r9a09g057 + - description: RZ/T2H (R9A09G077) + items: + - enum: + - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 + - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security + - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security + - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security + additionalProperties: true ... From patchwork Wed Jan 29 16:37:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953936 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BF5C51E0DB5; Wed, 29 Jan 2025 16:51:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169521; cv=none; b=F7rvXZkCrZ2+/nNDEYAaOY1yWl7rVMSntRdNE2ycv41yt8svL5s+1zEBd5woFTGCGXzVT1q9cy4q34e8yxYtgog3Kktf3J2KR0v5Nan2lyJMAjlp0o9gyZ7swRB09aDqu9J7q7YsB5p31h+BXWa8QTUZDJsHo76rbLLgUx0RfIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169521; c=relaxed/simple; bh=CUH9n+oPHOWyM3u6BZlgaSX/u3UOlrz9vO5jpb8oU30=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D7jJFxRtnb6oohp8GwwpERhAFXnS6lGIGLqRXltqf5qTX4SgFoPVAbgxZmLn3F/1WwdH8rSNW7cSVqWqgPxjUUfxVepefvhZBslx0sQC3LCAMnpr0LJVe08jHXHP3kUXXdlYCPKaSVzSJR4sQYAfvYCYvjhdEzaZyNy0ZTS4nR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: hShsvux3TAmY5SDmWSSOGA== X-CSE-MsgGUID: CJI+EUM4RICmJ+c+MDvTyQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:51:58 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9567F402EEE6; Thu, 30 Jan 2025 01:51:46 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Thierry Bultel Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC Date: Wed, 29 Jan 2025 16:37:38 +0000 Message-ID: <20250129165122.2980-3-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document RZ/T2H (a.k.a r9a09g077) in SCI binding. Signed-off-by: Thierry Bultel --- .../bindings/serial/renesas,rzsci.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml diff --git a/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml new file mode 100644 index 000000000000..70e83bbcc79d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communication Interface + +maintainers: + - Thierry Bultel + - Geert Uytterhoeven + +allOf: + - $ref: serial.yaml# + +description: | + The SCI is configurable to asynchronous and synchronous serial + interfaces: + - Asynchronous interfaces (UART and Asynchronous Communications Interface + Adapter (ACIA)) + - 8-bit clock synchronous interface + - Simple I2C (master-only) + - Simple SPI + - Smart card interface + - Manchester mode + - Asynchronous interfaces (UART, RS485 and Asynchronous Communications + Interface Adapter (ACIA)) + The smart card interface complies with the ISO/IEC 7816-3 standard for + electronic signals and transmission protocol. Each SCI has FIFO buffers to + enable continuous and full-duplex communication, and the data transfer speed + can be configured independently using a baud rate generator. + +properties: + compatible: + const: renesas,r9a09g077-sci # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + + interrupt-names: + items: + - const: eri + - const: rxi + - const: txi + - const: tei + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + + aliases { + serial0 = &sci0; + }; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-sci"; + reg = <0x80005000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A09G077_SCI0_CLK>; + clock-names = "fck"; + power-domains = <&cpg>; + }; From patchwork Wed Jan 29 16:37:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953938 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1A47D1DFD9D; Wed, 29 Jan 2025 16:52:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169535; cv=none; b=KGTFS5PL3UQP+ZspkxfGilzpvZQaH57ZM0OV4ik8IzXky+VIYnJfYDEhyBcpAjHyIBajdbwH7ajNPIJFhRRk7R+B0ZPJmEKNsXngW3DdGQiDuXAlYC68eNID2FSby7caFUyzYvRJZq6VXklYETMSW4G1PB3Z+3vQse9nDsto4ks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169535; c=relaxed/simple; bh=PciLRxlqOAQOhDRRebMPFJhjUC7nYaS41DSDwIYNE6E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O8jmvtE/v0xhowLTo/X81iSw121lprAWL+E5TPqgLJ13X7OlpXxCsaSQRjeJGXGv4eKm0XXaU5EZZv3BnSzDo6q3drmRiVilXAyivHB12GLmNPQOiagYiFTZfJsqHYzuERhkkMoyVlZZmqbkIfBnCV5AKMDrSNDZpW4DV2rBYeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: ACh6jKLUSzS6w8fYzSYjNQ== X-CSE-MsgGUID: VJZKxVavRAutuoqbQz9xjQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:07 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 166E8402F520; Thu, 30 Jan 2025 01:51:53 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Thierry Bultel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] dt-bindings: soc: Document the Renesas RZ/T2H Evaluation board for the R9A09G077 SoC Date: Wed, 29 Jan 2025 16:37:39 +0000 Message-ID: <20250129165122.2980-4-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the RZ/T2H Evaluation board (r9a9g077m44-dev) in documentation. Signed-off-by: Thierry Bultel --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 33f9e37a3d3d..331a007dbe35 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -537,6 +537,8 @@ properties: - description: RZ/T2H (R9A09G077) items: + - enum: + - renesas,r9a9g077m44-dev # RZ/T2H Evaluation Board - enum: - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security From patchwork Wed Jan 29 16:37:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953939 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 32E261E04BD; Wed, 29 Jan 2025 16:52:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169538; cv=none; b=eK+JhNBbBomip/XrmCaqOqckOH1IMH4VgtgC7zUe0XY1OmmMBmcNnfv93GvSRli1T9Z2RGEcJVmYd/oCv3I71ItCgZuPml5MzI06CmnF52WPegWyUrJ5kcANzfS92gHGNRVzU8o5OHss3dO6BXVYPyoZLrpoMZpsJ09LUF6mIj0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169538; c=relaxed/simple; bh=9lLPFIXz6ZQceuk/AtSkSJ0SfJktgU8m3ojTa4ld+d0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WRTwZ1UD8iD5UFMvD8jl9ifVYTuI5s80PsN09lGea7CQyRptgR5wLHwsWY7VLX2u4Yq1puc8QUD2AI0rmN2+3b7156P7LRkeyAWY2Vph9CLx5gxfmWrJ1iNWwrkDjOnv+3jueVjoZTnz26aaQIFV7mJ9R6IVKtn1xyrBgKDjU0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: pMXj4B3YSs2NyQm8dJ20ZA== X-CSE-MsgGUID: 3Pil8R0NQAeozhfuZSwFWg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:13 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 66D24402E786; Thu, 30 Jan 2025 01:51:59 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Thierry Bultel Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] dt-bindings: clock: Document cpg bindings for the Renesas RZ/T2H SoC Date: Wed, 29 Jan 2025 16:37:40 +0000 Message-ID: <20250129165122.2980-5-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document RZ/T2H (a.k.a r9a09g077) CPG (Clock Pulse Generator) binding. Add the header file for the resets and clocks definitions. Signed-off-by: Thierry Bultel --- .../bindings/clock/renesas,rzt2h-cpg.yaml | 73 +++++++++ include/dt-bindings/clock/r9a09g077-cpg.h | 144 ++++++++++++++++++ 2 files changed, 217 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml create mode 100644 include/dt-bindings/clock/r9a09g077-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml new file mode 100644 index 000000000000..9a3a00126d2b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,rzt2h-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H(P) Clock Pulse Generator (CPG) + +maintainers: + - Thierry Bultel + +description: + On Renesas RZ/T2H SoCs, the CPG (Clock Pulse Generator) handles generation + and control of clock signals for the IP modules, generation and control of resets, + and control over booting, low power consumption and power supply domains. + +properties: + compatible: + const: renesas,r9a09g077-cpg + + reg: + maxItems: 1 + + clocks: + items: + - description: EXTAL clock input + - description: LOCO clock input + + clock-names: + items: + - const: extal + - const: loco + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + , + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number, also defined , + const: 2 + + '#power-domain-cells': + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the reset number, as defined in + . + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10420000 { + compatible = "renesas,r9a09g077-cpg"; + reg = <0x10420000 0x10000>; + clocks = <&extal>, <&loco>; + clock-names = "extal", "loco"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/r9a09g077-cpg.h b/include/dt-bindings/clock/r9a09g077-cpg.h new file mode 100644 index 000000000000..413c428478df --- /dev/null +++ b/include/dt-bindings/clock/r9a09g077-cpg.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ + +#include + +/* R9A09G077 CPG Core Clocks */ +#define R9A09G077_CA55C0 0 +#define R9A09G077_CA55C1 1 +#define R9A09G077_CA55C2 2 +#define R9A09G077_CA55C3 3 +#define R9A09G077_SDHIHS 4 +#define R9A09G077_CLK_PLL1_ETH_PHY 5 +#define R9A09G077_CLK_OSC_ETH_PHY 6 +#define R9A09G077_CLK_ETHPHY 7 +#define R9A09G077_PCLKAH 8 +#define R9A09G077_PCLKAM 9 +#define R9A09G077_PCLKAL 10 +#define R9A09G077_CLK_SEL_ETH_PHY 11 +#define R9A09G077_DFI 12 +#define R9A09G077_PCLKH 13 +#define R9A09G077_PCLKM 14 +#define R9A09G077_PCLKL 15 +#define R9A09G077_PCLKGPTL 16 +#define R9A09G077_PCLKSHOST 17 +#define R9A09G077_PCLKRTC 18 +#define R9A09G077_USB 19 +#define R9A09G077_SPI0 20 +#define R9A09G077_SPI1 21 +#define R9A09G077_SPI2 22 +#define R9A09G077_SPI3 23 +#define R9A09G077_ETCLKA 24 +#define R9A09G077_ETCLKB 25 +#define R9A09G077_ETCLKC 26 +#define R9A09G077_ETCLKD 27 +#define R9A09G077_ETCLKE 28 +#define R9A09G077_ETHCLKE 29 +#define R9A09G077_ETHCLK_EXTAL 30 +#define R9A09G077_ETH_REFCLK 31 +#define R9A09G077_LCDC_CLKA 32 +#define R9A09G077_LCDC_CLKP 33 +#define R9A09G077_CA55 34 +#define R9A09G077_LCDC_CLKD 35 + +/* R9A09G077 Module Clocks */ +#define R9A09G077_SCI0_CLK 0 +#define R9A09G077_CA55_CORE0_CLK 1 +#define R9A09G077_CA55_CORE1_CLK 2 +#define R9A09G077_CA55_CORE2_CLK 3 +#define R9A09G077_CA55_CORE3_CLK 4 +#define R9A09G077_PCIE_CLK 5 +#define R9A09G077_USB_CLK 6 +#define R9A09G077_SDHI0_CLK 7 +#define R9A09G077_SDHI1_CLK 8 +#define R9A09G077_MTU3_CLK 9 +#define R9A09G077_GPT0_CLK 10 +#define R9A09G077_GPT1_CLK 11 +#define R9A09G077_ACD0_CLK 12 +#define R9A09G077_ACD1_CLK 13 +#define R9A09G077_ACD2_CLK 14 +#define R9A09G077_GMAC0_CLK 15 +#define R9A09G077_GMAC1_CLK 16 +#define R9A09G077_GMAC2_CLK 17 +#define R9A09G077_SHOSTIF_CLK 18 +#define R9A09G077_IIC0_CLK 19 +#define R9A09G077_IIC1_CLK 20 +#define R9A09G077_IIC2_CLK 21 +#define R9A09G077_DOC_CLK 22 +#define R9A09G077_CMT0_CLK 23 +#define R9A09G077_CMT1_CLK 24 +#define R9A09G077_CMT2_CLK 25 +#define R9A09G077_CMTW0_CLK 26 +#define R9A09G077_CMTW1_CLK 27 +#define R9A09G077_SPI0_CLK 28 +#define R9A09G077_SPI1_CLK 29 +#define R9A09G077_SPI2_CLK 30 +#define R9A09G077_SPI3_CLK 31 +#define R9A09G077_SCI1_CLK 32 +#define R9A09G077_SCI2_CLK 33 +#define R9A09G077_SCI3_CLK 34 +#define R9A09G077_SCI4_CLK 35 +#define R9A09G077_SCI5_CLK 36 +#define R9A09G077_SCIE0_CLK 37 +#define R9A09G077_SCIE1_CLK 38 +#define R9A09G077_SCIE2_CLK 39 +#define R9A09G077_SCIE3_CLK 40 +#define R9A09G077_SCIE4_CLK 41 +#define R9A09G077_SCIE5_CLK 42 +#define R9A09G077_SCIE6_CLK 43 +#define R9A09G077_SCIE7_CLK 44 +#define R9A09G077_SCIE8_CLK 45 +#define R9A09G077_SCIE9_CLK 46 +#define R9A09G077_SCIE10_CLK 47 +#define R9A09G077_SCIE11_CLK 48 +#define R9A09G077_RTC_CLK 49 +#define R9A09G077_ETHSS_CLK 50 +#define R9A09G077_ETHSW_CLK 51 +#define R9A09G077_GPT2_CLK 52 +#define R9A09G077_GPT3_CLK 53 +#define R9A09G077_GPT4_CLK 54 +#define R9A09G077_GPT5_CLK 55 +#define R9A09G077_GPT6_CLK 56 +#define R9A09G077_GPT7_CLK 57 +#define R9A09G077_GPT8_CLK 58 +#define R9A09G077_GPT9_CLK 59 +#define R9A09G077_GPT10_CLK 60 +#define R9A09G077_CANFD_CLK 61 +#define R9A09G077_TSU_CLK 62 +#define R9A09G077_LCDC_CLK 63 + +/* R9A09G077 Resets */ +#define R9A09G077_xSPI0_RST 0 +#define R9A09G077_xSPI1_RST 1 +#define R9A09G077_GMAC0_PCLKH_RST 2 +#define R9A09G077_GMAC0_PCLKM_RST 3 +#define R9A09G077_ETHSW_RST 4 +#define R9A09G077_ESC_BUS_RST 5 +#define R9A09G077_ESC_IP_RST 6 +#define R9A09G077_ETH_SUBSYSTEM_RST 7 +#define R9A09G077_MII_CONVERT_RST 8 +#define R9A09G077_GMAC1_PCLKAH_RST 9 +#define R9A09G077_GMAC1_PCLKAM_RST 10 +#define R9A09G077_GMAC2_PCLKAH_RST 11 +#define R9A09G077_GMAC2_PCLKAM_RST 12 +#define R9A09G077_SHOSTIF_MASTER_RST 13 +#define R9A09G077_SHOSTIF_SLAVE_RST 14 +#define R9A09G077_SHOSTIF_IP_RST 15 +#define R9A09G077_DDRSS_RST_N_RST 16 +#define R9A09G077_DDRSS_PWROKIN_RST 17 +#define R9A09G077_DDRSS_RST_RST 18 +#define R9A09G077_DDRSS_AXI0_RST 19 +#define R9A09G077_DDRSS_AXI1_RST 20 +#define R9A09G077_DDRSS_AXI2_RST 21 +#define R9A09G077_DDRSS_AXI3_RST 22 +#define R9A09G077_DDRSS_AXI4_RST 23 +#define R9A09G077_DDRSS_MC_RST 24 +#define R9A09G077_PCIE_RST 25 +#define R9A09G077_DDRSS_PHY_RST 26 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ \ No newline at end of file From patchwork Wed Jan 29 16:37:41 2025 Content-Type: text/plain; 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Signed-off-by: Thierry Bultel --- drivers/soc/renesas/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 9f7fe02310b9..058ac0b53ffe 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -351,6 +351,11 @@ config ARCH_R9A09G057 help This enables support for the Renesas RZ/V2H(P) SoC variants. +config ARCH_R9A09G077 + bool "ARM64 Platform support for RZ/T2H" + help + This enables support for the Renesas RZ/T2H SoC variants. + endif # ARM64 if RISCV From patchwork Wed Jan 29 16:37:42 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953940 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 678911E0B96; Wed, 29 Jan 2025 16:52:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169545; cv=none; b=UVInTgVpm+bJMMLbTPTASnGysXGW9kAucGxr0Edz4xmOw9UOTmmOI8BVMn79GMyr/vuffZ2tiEwvPXA6glUnQE/JypYK4AjIkwU+Y7oWpz6EfJ9rZtGP9sMY2l1ahGMfd62A6oZ/EoN+4K8+V8d0TQgazZihjcZAQX8HOtVXK5A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169545; c=relaxed/simple; bh=S1YlamGvfyYIHqKDspZxNsMrULeFfB9ETiy9leItYGA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MHp7xo21J387QBcOtnfcBJmWAPVmh4FvscvEfdiXbPXz9yq/nHhCNqMFsds8RGE+cI7R2qBKibIlqB7yPuA46dUyfc6ZngOjASZPOJzRcZTA7S9gocZKFWxrIwmMAH8FFj+6QL98dqUDbm9E7NOjYK1SEX4JgqwttjZPP4/KM4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 52MEr7l3T3OcsOhzATj4oA== X-CSE-MsgGUID: oq38GtBGTsqXL69VdmOIOw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:22 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8B66C402F02E; Thu, 30 Jan 2025 01:52:10 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 06/14] clk: renesas: Add support for RZ/T2H family clock Date: Wed, 29 Jan 2025 16:37:42 +0000 Message-ID: <20250129165122.2980-7-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the CPG driver for T2H family. Signed-off-by: Thierry Bultel --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/rzt2h-cpg.c | 549 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzt2h-cpg.h | 201 ++++++++++++ 4 files changed, 755 insertions(+) create mode 100644 drivers/clk/renesas/rzt2h-cpg.c create mode 100644 drivers/clk/renesas/rzt2h-cpg.h diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index ff01f5f0ed20..7ad59be2099d 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -237,6 +237,10 @@ config CLK_RZV2H bool "RZ/V2H(P) family clock support" if COMPILE_TEST select RESET_CONTROLLER +config CLK_RZT2H + bool "RZ/T2H family clock support" if COMPILE_TEST + select RESET_CONTROLLER + config CLK_RENESAS_VBATTB tristate "Renesas VBATTB clock controller" depends on ARCH_RZG2L || COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 82efaa835ac7..bd9f0b54fcda 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o obj-$(CONFIG_CLK_RCAR_GEN4_CPG) += rcar-gen4-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o +obj-$(CONFIG_CLK_RZT2H) += rzt2h-cpg.o obj-$(CONFIG_CLK_RZV2H) += rzv2h-cpg.o # Generic diff --git a/drivers/clk/renesas/rzt2h-cpg.c b/drivers/clk/renesas/rzt2h-cpg.c new file mode 100644 index 000000000000..79dacbd2b186 --- /dev/null +++ b/drivers/clk/renesas/rzt2h-cpg.c @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/T2H Clock Pulse Generator + * + * Copyright (C) 2025 Renesas Electronics Corp. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "rzt2h-cpg.h" + +#ifdef DEBUG +#define WARN_DEBUG(x) WARN_ON(x) +#else +#define WARN_DEBUG(x) do { } while (0) +#endif + +#define GET_SHIFT(val) FIELD_GET(GENMASK(19, 12), val) +#define GET_WIDTH(val) FIELD_GET(GENMASK(11, 8), val) +#define GET_REG_OFFSET(val) FIELD_GET(GENMASK(31, 20), val) + +/** + * struct rzt2h_cpg_priv - Clock Pulse Generator Private Data + * + * @rcdev: Reset controller entity + * @info: Pointer to platform data + * @dev: CPG device + * @cpg_base0: CPG register block base address 0 + * @cpg_base1: CPG register block base address 1 + * @clks: Array containing all Core and Module Clocks + * @rmw_lock: protects register accesses + * @hw: clock hw + * @num_core_clks: Number of Core Clocks in clks[] + * @num_mod_clks: Number of Module Clocks in clks[] + * @num_resets: Number of Module Resets in info->resets[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + */ +struct rzt2h_cpg_priv { + struct reset_controller_dev rcdev; + const struct rzt2h_cpg_info *info; + struct device *dev; + void __iomem *cpg_base0, *cpg_base1; + struct clk **clks; + spinlock_t rmw_lock; + struct clk_hw hw; + unsigned int num_core_clks; + unsigned int num_mod_clks; + unsigned int num_resets; + unsigned int last_dt_core_clk; +}; + +#define rcdev_to_priv(x) container_of(x, struct rzt2h_cpg_priv, rcdev) + +static void rzt2h_cpg_del_clk_provider(void *data) +{ + of_clk_del_provider(data); +} + +static struct clk * __init +rzt2h_cpg_div_clk_register(const struct cpg_core_clk *core, + void __iomem *base, + struct rzt2h_cpg_priv *priv) +{ + struct device *dev = priv->dev; + struct clk **clks = priv->clks; + const struct clk *parent; + const char *parent_name; + struct clk_hw *clk_hw; + + parent = clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + parent_name = __clk_get_name(parent); + + if (core->dtable) { + clk_hw = clk_hw_register_divider_table(dev, core->name, + parent_name, 0, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, + core->dtable, + &priv->rmw_lock); + } else { + clk_hw = clk_hw_register_divider(dev, core->name, + parent_name, 0, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->flag, &priv->rmw_lock); + } + if (IS_ERR(clk_hw)) + return ERR_CAST(clk_hw); + + return clk_hw->clk; +} + +static struct clk * __init +rzt2h_cpg_mux_clk_register(const struct cpg_core_clk *core, + void __iomem *base, + struct rzt2h_cpg_priv *priv) +{ + const struct clk_hw *clk_hw; + + clk_hw = devm_clk_hw_register_mux(priv->dev, core->name, + core->parent_names, core->num_parents, + core->flag, + base + GET_REG_OFFSET(core->conf), + GET_SHIFT(core->conf), + GET_WIDTH(core->conf), + core->mux_flags, &priv->rmw_lock); + if (IS_ERR(clk_hw)) + return ERR_CAST(clk_hw); + + return clk_hw->clk; +} + +struct pll_clk { + void __iomem *base; + struct rzt2h_cpg_priv *priv; + struct clk_hw hw; + unsigned int conf; + unsigned int type; +}; +#define to_pll(_hw) container_of(_hw, struct pll_clk, hw) + +static struct clk +*rzt2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int clkidx = clkspec->args[1]; + struct rzt2h_cpg_priv *priv = data; + struct device *dev = priv->dev; + const char *type; + struct clk *clk; + + switch (clkspec->args[0]) { + case CPG_CORE: + type = "core"; + if (clkidx > priv->last_dt_core_clk) { + dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); + return ERR_PTR(-EINVAL); + } + clk = priv->clks[clkidx]; + break; + + case CPG_MOD: + type = "module"; + if (clkidx >= priv->num_mod_clks) { + dev_err(dev, "Invalid %s clock index %u\n", type, + clkidx); + return ERR_PTR(-EINVAL); + } + clk = priv->clks[priv->num_core_clks + clkidx]; + break; + + default: + dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); + return ERR_PTR(-EINVAL); + } + + if (IS_ERR(clk)) + dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, + PTR_ERR(clk)); + else + dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", + clkspec->args[0], clkspec->args[1], clk, + clk_get_rate(clk)); + return clk; +} + +static void __init +rzt2h_cpg_register_core_clk(const struct cpg_core_clk *core, + const struct rzt2h_cpg_info *info, + struct rzt2h_cpg_priv *priv) +{ + struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent; + unsigned int id = core->id, div = core->div; + struct device *dev = priv->dev; + const char *parent_name; + + WARN_DEBUG(id >= priv->num_core_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + + /* Skip NULLified clock */ + if (!core->name) + return; + + switch (core->type) { + case CLK_TYPE_IN: + clk = of_clk_get_by_name(priv->dev->of_node, core->name); + break; + case CLK_TYPE_FF: + WARN_DEBUG(core->parent >= priv->num_core_clks); + parent = priv->clks[core->parent]; + if (IS_ERR(parent)) { + clk = parent; + goto fail; + } + + parent_name = __clk_get_name(parent); + clk = clk_register_fixed_factor(NULL, core->name, + parent_name, CLK_SET_RATE_PARENT, + core->mult, div); + break; + case CLK_TYPE_DIV: + if (core->sel_base > 0) + clk = rzt2h_cpg_div_clk_register(core, + priv->cpg_base1, priv); + else + clk = rzt2h_cpg_div_clk_register(core, + priv->cpg_base0, priv); + break; + case CLK_TYPE_MUX: + clk = rzt2h_cpg_mux_clk_register(core, priv->cpg_base0, priv); + break; + default: + goto fail; + } + + if (IS_ERR_OR_NULL(clk)) + goto fail; + + priv->clks[id] = clk; + return; + +fail: + dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", + core->name, PTR_ERR(clk)); +} + +/** + * struct mstp_clock - MSTP gating clock + * + * @hw: handle between common and hardware-specific interfaces + * @priv: CPG/MSTP private data + * @sibling: pointer to the other coupled clock + * @baseaddr: register base address + * @enabled: soft state of the clock, if it is coupled with another clock + * @off: register offset + * @bit: ON/MON bit + */ +struct mstp_clock { + struct rzt2h_cpg_priv *priv; + struct mstp_clock *sibling; + void __iomem *baseaddr; + struct clk_hw hw; + bool enabled; + u32 off; + u8 bit; +}; +#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw) +static int rzt2h_mod_clock_is_enabled(struct clk_hw *hw) +{ + struct mstp_clock *clock = to_mod_clock(hw); + struct rzt2h_cpg_priv *priv = clock->priv; + u32 bitmask = BIT(clock->bit); + u32 value; + + if (!clock->off) { + dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk); + return 1; + } + value = readl(clock->baseaddr + clock->off); + + /* For all Module Stop registers, read bit meaning is as such: + * 0: Release from the module-stop state + * 1: Transition to the module-stop state is made + */ + + return !(value & bitmask); +} + +static const struct clk_ops rzt2h_mod_clock_ops = { + .is_enabled = rzt2h_mod_clock_is_enabled, +}; + +static void __init +rzt2h_cpg_register_mod_clk(const struct rzt2h_mod_clk *mod, + const struct rzt2h_cpg_info *info, + struct rzt2h_cpg_priv *priv) +{ + struct mstp_clock *clock = NULL; + struct device *dev = priv->dev; + unsigned int id = mod->id; + struct clk_init_data init; + struct clk *parent, *clk; + const char *parent_name; + unsigned int i; + + WARN_DEBUG(id < priv->num_core_clks); + WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + + /* Skip NULLified clock */ + if (!mod->name) + return; + + parent = priv->clks[mod->parent]; + if (IS_ERR(parent)) { + clk = parent; + goto fail; + } + + clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); + if (!clock) { + clk = ERR_PTR(-ENOMEM); + goto fail; + } + + init.name = mod->name; + init.ops = &rzt2h_mod_clock_ops; + init.flags = CLK_SET_RATE_PARENT; + for (i = 0; i < info->num_crit_mod_clks; i++) + if (id == info->crit_mod_clks[i]) { + dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n", + mod->name); + init.flags |= CLK_IS_CRITICAL; + break; + } + + parent_name = __clk_get_name(parent); + init.parent_names = &parent_name; + init.num_parents = 1; + + clock->off = mod->addr; + clock->bit = mod->bit; + clock->baseaddr = mod->sel_base ? priv->cpg_base1 : priv->cpg_base0; + clock->priv = priv; + clock->hw.init = &init; + + clk = devm_clk_register(dev, &clock->hw); + if (IS_ERR(clk)) + goto fail; + + priv->clks[id] = clk; + + return; + +fail: + dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", + mod->name, PTR_ERR(clk)); +} + +static bool rzt2h_cpg_is_pm_clk(const struct of_phandle_args *clkspec) +{ + if (clkspec->args_count != 2) + return false; + + switch (clkspec->args[0]) { + case CPG_MOD: + return true; + + default: + return false; + } +} + +static int rzt2h_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev) +{ + struct device_node *np = dev->of_node; + struct of_phandle_args clkspec; + unsigned int i = 0; + bool once = true; + struct clk *clk; + int error; + + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, + &clkspec)) { + if (!rzt2h_cpg_is_pm_clk(&clkspec)) { + of_node_put(clkspec.np); + continue; + } + + if (once) { + once = false; + error = pm_clk_create(dev); + if (error) { + of_node_put(clkspec.np); + goto err; + } + } + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + if (IS_ERR(clk)) { + error = PTR_ERR(clk); + goto fail_destroy; + } + error = pm_clk_add_clk(dev, clk); + if (error) { + dev_err(dev, "pm_clk_add_clk failed %d\n", error); + goto fail_put; + } + i++; + } + + return 0; + +fail_put: + clk_put(clk); + +fail_destroy: + pm_clk_destroy(dev); +err: + return error; +} + +static void rzt2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev) +{ + if (!pm_clk_no_clocks(dev)) + pm_clk_destroy(dev); +} + +static void rzt2h_cpg_genpd_remove(void *data) +{ + pm_genpd_remove(data); +} + +static int __init rzt2h_cpg_add_clk_domain(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct generic_pm_domain *genpd; + int ret; + + genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL); + if (!genpd) + return -ENOMEM; + + genpd->name = np->name; + genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | + GENPD_FLAG_ACTIVE_WAKEUP; + genpd->attach_dev = rzt2h_cpg_attach_dev; + genpd->detach_dev = rzt2h_cpg_detach_dev; + ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false); + if (ret) + return ret; + + ret = devm_add_action_or_reset(dev, rzt2h_cpg_genpd_remove, genpd); + if (ret) + return ret; + + return of_genpd_add_provider_simple(np, genpd); +} + +static int __init rzt2h_cpg_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct rzt2h_cpg_info *info; + struct rzt2h_cpg_priv *priv; + unsigned int nclks, i; + struct clk **clks; + int error; + + info = of_device_get_match_data(dev); + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->info = info; + spin_lock_init(&priv->rmw_lock); + + priv->cpg_base0 = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->cpg_base1)) + return PTR_ERR(priv->cpg_base0); + + priv->cpg_base1 = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(priv->cpg_base1)) + return PTR_ERR(priv->cpg_base1); + + nclks = info->num_total_core_clks + info->num_hw_mod_clks; + clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->clks = clks; + priv->num_core_clks = info->num_total_core_clks; + priv->num_mod_clks = info->num_hw_mod_clks; + priv->num_resets = info->num_resets; + priv->last_dt_core_clk = info->last_dt_core_clk; + + for (i = 0; i < nclks; i++) + clks[i] = ERR_PTR(-ENOENT); + + for (i = 0; i < info->num_core_clks; i++) + rzt2h_cpg_register_core_clk(&info->core_clks[i], info, priv); + + for (i = 0; i < info->num_mod_clks; i++) + rzt2h_cpg_register_mod_clk(&info->mod_clks[i], info, priv); + + error = of_clk_add_provider(np, rzt2h_cpg_clk_src_twocell_get, priv); + if (error) + return error; + + error = devm_add_action_or_reset(dev, rzt2h_cpg_del_clk_provider, np); + if (error) + return error; + + return rzt2h_cpg_add_clk_domain(dev); +} + +static const struct of_device_id rzt2h_cpg_match[] = { +#ifdef CONFIG_CLK_R9A09G077 + { + .compatible = "renesas,r9a09g077-cpg", + .data = &r9a09g077_cpg_info, + }, +#endif + { /* sentinel */ } +}; + +static struct platform_driver rzt2h_cpg_driver = { + .driver = { + .name = "rzt2-cpg", + .of_match_table = rzt2h_cpg_match, + }, +}; + +static int __init rzt2h_cpg_init(void) +{ + return platform_driver_probe(&rzt2h_cpg_driver, rzt2h_cpg_probe); +} + +subsys_initcall(rzt2h_cpg_init); diff --git a/drivers/clk/renesas/rzt2h-cpg.h b/drivers/clk/renesas/rzt2h-cpg.h new file mode 100644 index 000000000000..d9d28608e4c3 --- /dev/null +++ b/drivers/clk/renesas/rzt2h-cpg.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/T2H Clock Pulse Generator + * + * Copyright (C) 2025 Renesas Electronics Corp. + * + */ + +#ifndef __RENESAS_RZT2H_CPG_H__ +#define __RENESAS_RZT2H_CPG_H__ + +#define SCKCR 0x00 +#define SCKCR2 0x04 +#define SCKCR3 0x08 +#define SCKCR4 0x0C +#define PMSEL 0x10 +#define PMSEL_PLL0 BIT(0) +#define PMSEL_PLL2 BIT(2) +#define PMSEL_PLL3 BIT(3) +#define PLL0EN BIT(0) +#define PLL2EN BIT(0) +#define PLL3EN BIT(0) +#define PLL0MON 0x20 +#define PLL0EN_REG 0x30 +#define PLL0_SSC_CTR 0x34 +#define PLL1MON 0x40 +#define LOCOCR 0x70 +#define HIZCTRLEN 0x80 +#define PLL2MON 0x90 +#define PLL2EN_REG 0xA0 +#define PLL2_SSC_CTR 0xAC +#define PLL3MON 0xB0 +#define PLL3EN_REG 0xC0 +#define PLL3_VCO_CTR0 0xC4 +#define PLL3_VCO_CTR1 0xC8 +#define PLL4MON 0xD0 +#define PHYSEL BIT(21) + + +#define MRCTLA 0x240 +#define MRCTLE 0x250 +#define MRCTLI 0x260 +#define MRCTLM 0x270 + +#define DDIV_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) + +#define DIVCA55 DDIV_PACK(SCKCR2, 8, 4) +#define DIVCA55S DDIV_PACK(SCKCR2, 12, 1) +#define DIVCR520 DDIV_PACK(SCKCR2, 2, 2) +#define DIVCR521 DDIV_PACK(SCKCR2, 0, 2) +#define DIVLCDC DDIV_PACK(SCKCR3, 20, 3) +#define DIVCKIO DDIV_PACK(SCKCR, 16, 3) +#define DIVETHPHY DDIV_PACK(SCKCR, 21, 1) +#define DIVCANFD DDIV_PACK(SCKCR, 20, 1) +#define DIVSPI0 DDIV_PACK(SCKCR3, 0, 2) +#define DIVSPI1 DDIV_PACK(SCKCR3, 2, 2) +#define DIVSPI2 DDIV_PACK(SCKCR3, 4, 2) +#define DIVSPI3 DDIV_PACK(SCKCR2, 16, 2) + +#define SEL_PLL_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) + +#define SEL_PLL SEL_PLL_PACK(SCKCR, 22, 1) + +/** + * Definitions of CPG Core Clocks + * + * These include: + * - Clock outputs exported to DT + * - External input clocks + * - Internal CPG clocks + */ +struct cpg_core_clk { + const char *name; + const struct clk_div_table *dtable; + const char * const *parent_names; + unsigned int id; + unsigned int parent; + unsigned int div; + unsigned int mult; + unsigned int type; + unsigned int conf; + int flag; + int mux_flags; + int num_parents; + int sel_base; +}; + +enum clk_types { + /* Generic */ + CLK_TYPE_IN, /* External Clock Input */ + CLK_TYPE_MAIN, + CLK_TYPE_FF, /* Fixed Factor Clock */ + CLK_TYPE_PLL, + CLK_TYPE_SAM_PLL, + + /* Clock with divider */ + CLK_TYPE_DIV, + + /* Clock with clock source selector */ + CLK_TYPE_MUX, + + /* Clock with SD clock source selector */ + CLK_TYPE_SD_MUX, +}; + +#define DEF_TYPE(_name, _id, _type...) \ + { .name = _name, .id = _id, .type = _type } +#define DEF_BASE(_name, _id, _type, _parent...) \ + DEF_TYPE(_name, _id, _type, .parent = _parent) +#define DEF_INPUT(_name, _id) \ + DEF_TYPE(_name, _id, CLK_TYPE_IN) +#define DEF_FIXED(_name, _id, _parent, _mult, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) +#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag, _sel_base) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, .sel_base = _sel_base, \ + .parent = _parent, .dtable = _dtable, .flag = _flag) +#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \ + _mux_flags) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ + .parent_names = _parent_names, .num_parents = _num_parents, \ + .flag = _flag, .mux_flags = _mux_flags) + +/** + * struct rzt2h_mod_clk - Module Clocks definitions + * + * @name: handle between common and hardware-specific interfaces + * @id: clock index in array containing all Core and Module Clocks + * @parent: id of parent clock + * @addr: register address + * @sel_base: selects base address + * @is_coupled: flag to indicate coupled clock + * @bit: ON/OFF bit + */ +struct rzt2h_mod_clk { + const char *name; + unsigned int id; + unsigned int parent; + u32 addr; + int sel_base; + bool is_coupled; + u8 bit; +}; + +#define DEF_MOD_BASE(_name, _id, _parent, _addr, _bit, _sel_base, _is_coupled) { \ + .name = (_name), \ + .id = MOD_CLK_BASE + (_id), \ + .parent = (_parent), \ + .addr = (_addr), \ + .bit = (_bit), \ + .sel_base = (_sel_base), \ + .is_coupled = (_is_coupled) \ +} + +#define DEF_MOD(_name, _id, _parent, _addr, _bit, _sel_base) \ + DEF_MOD_BASE(_name, _id, _parent, _addr, _bit, _sel_base, false) + +/** + * struct rzt2_cpg_info - SoC-specific CPG Description + * + * @core_clks: Array of Core Clock definitions + * @num_core_clks: Number of entries in core_clks[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @num_total_core_clks: Total number of Core Clocks (exported + internal) + * + * @mod_clks: Array of Module Clock definitions + * @num_mod_clks: Number of entries in mod_clks[] + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware + * + * @resets: Array of Module Reset definitions + * @num_resets: Number of entries in resets[] + * + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that + * should not be disabled without a knowledgeable driver + * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + */ +struct rzt2h_cpg_info { + /* Core Clocks */ + const struct cpg_core_clk *core_clks; + unsigned int num_core_clks; + unsigned int last_dt_core_clk; + unsigned int num_total_core_clks; + + /* Module Clocks */ + const struct rzt2h_mod_clk *mod_clks; + unsigned int num_mod_clks; + unsigned int num_hw_mod_clks; + + /* Resets */ + const struct rzt2h_reset *resets; + unsigned int num_resets; + + /* Critical Module Clocks that should not be disabled */ + const unsigned int *crit_mod_clks; + unsigned int num_crit_mod_clks; +}; + +extern const struct rzt2h_cpg_info r9a09g077_cpg_info; + +#endif From patchwork Wed Jan 29 16:37:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953941 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 198A11FC8; Wed, 29 Jan 2025 16:52:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: IDtV4LKDRvS7vps2fR9HLA== X-CSE-MsgGUID: TotjPwt9R6C/KqP090jv2A== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:28 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 46953402E096; Thu, 30 Jan 2025 01:52:15 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 07/14] clk: renesas: Add support for R9A09G077 SoC Date: Wed, 29 Jan 2025 16:37:43 +0000 Message-ID: <20250129165122.2980-8-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the R9A09G077 SoC specific definitions to the CPG driver. Signed-off-by: Thierry Bultel --- drivers/clk/renesas/Kconfig | 5 ++ drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g077-cpg.c | 100 ++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+) create mode 100644 drivers/clk/renesas/r9a09g077-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 7ad59be2099d..017ae990d50c 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -41,6 +41,7 @@ config CLK_RENESAS select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_R9A09G057 if ARCH_R9A09G057 + select CLK_R9A09G077 if ARCH_R9A09G077 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -198,6 +199,10 @@ config CLK_R9A09G057 bool "RZ/V2H(P) clock support" if COMPILE_TEST select CLK_RZV2H +config CLK_R9A09G077 + bool "RZ/T2H clock support" if COMPILE_TEST + select CLK_RZT2H + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index bd9f0b54fcda..fe11b10bc451 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o +obj-$(CONFIG_CLK_R9A09G077) += r9a09g077-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c new file mode 100644 index 000000000000..0b2895c796d1 --- /dev/null +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r9a09g077 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2025 Renesas Electronics Corp. + * + */ + +#include +#include +#include +#include + +#include + +#include "rzt2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + /* External Input Clocks */ + LAST_DT_CORE_CLK = R9A09G077_LCDC_CLKD, + CLK_EXTAL, + CLK_LOCO, + + /* Internal Core Clocks */ + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_SEL_PLL0, + CLK_SEL_CLK_PLL0, + CLK_SEL_PLL1, + CLK_SEL_CLK_PLL1, + CLK_SEL_PLL2, + CLK_SEL_CLK_PLL2, + CLK_SEL_PLL4, + CLK_SEL_CLK_PLL4, + CLK_SEL_CLK_SRC, + CLK_SEL_EXTAL, + CLK_SEL_LOCO, + CLK_PLL3_INPUT, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct clk_div_table dtable_1_2[] = { + {0, 2}, + {15, 1}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const sel_clk_pll0[] = { ".sel_loco", ".sel_pll0" }; +static const char * const sel_clk_pll1[] = { ".sel_loco", ".sel_pll1" }; +static const char * const sel_clk_pll4[] = { ".sel_loco", ".sel_pll4" }; + +static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("loco", CLK_LOCO), + + /* Internal Core Clocks */ + DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 48, 1), + DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 40, 1), + DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 96, 1), + DEF_FIXED(".sel_pll0", CLK_SEL_PLL0, CLK_PLL0, 1, 1), + DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL, + sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), 0, CLK_MUX_READ_ONLY), + DEF_FIXED(".sel_pll1", CLK_SEL_PLL1, CLK_PLL1, 1, 1), + DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL, + sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), 0, CLK_MUX_READ_ONLY), + DEF_FIXED(".sel_pll4", CLK_SEL_PLL4, CLK_PLL4, 1, 1), + DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL, + sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), 0, CLK_MUX_READ_ONLY), + + /* Core output clk */ + DEF_DIV("CA55", R9A09G077_CA55, CLK_SEL_CLK_PLL0, DIVCA55, + dtable_1_2, CLK_DIVIDER_HIWORD_MASK, 1), + DEF_FIXED("PCLKM", R9A09G077_PCLKM, CLK_SEL_CLK_PLL1, 1, 8), + DEF_FIXED("PCLKGPTL", R9A09G077_PCLKGPTL, CLK_SEL_CLK_PLL1, 1, 2), +}; + +static const struct rzt2h_mod_clk r9a09g077_mod_clks[] __initconst = { + DEF_MOD("sci0", R9A09G077_SCI0_CLK, R9A09G077_PCLKM, 0x300, 8, 0), +}; + +const struct rzt2h_cpg_info r9a09g077_cpg_info = { + /* Core Clocks */ + .core_clks = r9a09g077_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g077_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r9a09g077_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g077_mod_clks), + .num_hw_mod_clks = R9A09G077_LCDC_CLK + 1, +}; From patchwork Wed Jan 29 16:37:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953943 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 980111DFE00; Wed, 29 Jan 2025 16:52:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: r0C+xfkESVemYdAI28xLBQ== X-CSE-MsgGUID: 6APepqd8TLOvZc05OxeGLQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:49 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E5CD7402D14A; Thu, 30 Jan 2025 01:52:35 +0900 (JST) From: Thierry Bultel To: Greg Kroah-Hartman , Jiri Slaby , Geert Uytterhoeven , Magnus Damm Cc: Thierry Bultel , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 11/14] serial: sh-sci: Add support for RZ/T2H SCI Date: Wed, 29 Jan 2025 16:37:47 +0000 Message-ID: <20250129165122.2980-12-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define a new RZSCI port type, and the RSCI 32 bits registers set. The RZ/T2H SCI has a a fifo, and a quite different set of registers from the orginal SH SCI ones. DMA is not supported yet. Signed-off-by: Thierry Bultel --- drivers/tty/serial/Kconfig | 7 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/rzsci.c | 484 +++++++++++++++++++++++++++++++ drivers/tty/serial/rzsci.h | 12 + drivers/tty/serial/sh-sci.c | 20 +- include/linux/serial_sci.h | 3 +- include/uapi/linux/serial_core.h | 3 + 7 files changed, 524 insertions(+), 6 deletions(-) create mode 100644 drivers/tty/serial/rzsci.c create mode 100644 drivers/tty/serial/rzsci.h diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 45f0f779fbf9..72b563f2e9ba 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -671,6 +671,13 @@ config SERIAL_SH_SCI_DMA depends on SERIAL_SH_SCI && DMA_ENGINE default ARCH_RENESAS +config SERIAL_RZ_SCI + tristate "Support for Renesas RZ/T2H SCI variant" + depends on SERIAL_SH_SCI + help + Support for the RZ/T2H SCI variant with fifo. + Say Y if you want to be able to the RZ/T2H SCI serial port. + config SERIAL_HS_LPC32XX tristate "LPC32XX high speed serial port support" depends on ARCH_LPC32XX || COMPILE_TEST diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 6ff74f0a9530..537e0a0fc047 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o obj-$(CONFIG_SERIAL_QE) += ucc_uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o obj-$(CONFIG_SERIAL_RP2) += rp2.o +obj-$(CONFIG_SERIAL_RZ_SCI) += rzsci.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o diff --git a/drivers/tty/serial/rzsci.c b/drivers/tty/serial/rzsci.c new file mode 100644 index 000000000000..7a6452600123 --- /dev/null +++ b/drivers/tty/serial/rzsci.c @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include "rzsci.h" + +/* RSCI registers */ +#define RDR 0x00 +#define TDR 0x04 +#define CCR0 0x08 +#define CCR1 0x0C +#define CCR2 0x10 +#define CCR3 0x14 +#define CCR4 0x18 +#define FCR 0x24 +#define DCR 0x30 +#define CSR 0x48 +#define FRSR 0x50 +#define FTSR 0x54 +#define CFCLR 0x68 +#define FFCLR 0x70 + +/* RDR (Receive Data Register) */ +#define RDR_FER BIT(28) /* Framing Error */ +#define RDR_PER BIT(27) /* Parity Error */ +#define RDR_ORER BIT(24) /* Overrun Error */ +#define RDR_FFER BIT(12) /* FIFO Framing Error */ +#define RDR_FPER BIT(11) /* FIFO Parity Error */ +#define RDR_DR BIT(10) /* Incoming Data Ready */ +#define RDR_MPB BIT(9) /* Multiprocessor Bit */ +#define RDR_RDAT_MSK GENMASK(8, 0) + +/* TDR (Transmit Data Register) */ +#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */ +#define TDR_TDAT_9BIT_LSHIFT 0 +#define TDR_TDAT_9BIT_VAL 0x1FF +#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT) + +/* CCR0 (Common Control Register 0) */ +#define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */ +#define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */ +#define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */ +#define CCR0_RIE BIT(16) /* Receive Interrupt Enable */ +#define CCR0_IDSEL BIT(10) /* ID Frame Select */ +#define CCR0_DCME BIT(9) /* Data Compare Match Enable */ +#define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */ +#define CCR0_TE BIT(4) /* Transmit Enable */ +#define CCR0_RE BIT(0) /* Receive Enable */ + +/* CCR1 (Common Control Register 1) */ +#define CCR1_NFEN BIT(28) /* Digital Noise Filter Function */ +#define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */ +#define CCR1_SPLP BIT(16) /* Loopback Control */ +#define CCR1_RINV BIT(13) /* RxD invert */ +#define CCR1_TINV BIT(12) /* TxD invert */ +#define CCR1_PM BIT(9) /* Parity Mode */ +#define CCR1_PE BIT(8) /* Parity Enable */ +#define CCR1_SPB2IO BIT(5) /* Serial Port Break I/O */ +#define CCR1_SPB2DT BIT(4) /* Serial Port Break Data Select */ +#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */ +#define CCR1_CTSE BIT(0) /* CTS Enable */ + +/* CCR2 (Common Control Register 2) */ +#define CCR2_INIT 0xFF000004 +#define CCR2_CKS_TCLK (0) /* TCLK clock */ +#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */ +#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */ +#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */ +#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */ +#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */ +#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */ +#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */ + +/* CCR3 (Common Control Register 3) */ +#define CCR3_INIT 0x1283 +#define CCR3_BLK BIT(29) /* Block Transfer Mode */ +#define CCR3_GM BIT(28) /* GSM Mode */ +#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */ +#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */ +#define CCR3_DEN BIT(21) /* Driver Enabled */ +#define CCR3_FM BIT(20) /* FIFO Mode Select */ +#define CCR3_MP BIT(19) /* Multi-Processor Mode */ +#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */ +#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */ +#define CCR3_STP BIT(14) /* Stop bit Length */ +#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */ +#define CCR3_LSBF BIT(12) /* LSB First select */ +#define CCR3_CHR1 BIT(9) /* Character Length */ +#define CCR3_CHR0 BIT(8) /* Character Length */ +#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */ +#define CCR3_CPOL BIT(1) /* Clock Polarity Select */ +#define CCR3_CPHA BIT(0) /* Clock Phase Select */ + +/* FCR (FIFO Control Register) */ +#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */ +#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */ +#define FCR_DRES BIT(0) /* Incoming Data Ready Error Select */ +#define FCR_RTRG4_0 GENMASK(20, 16) +#define FCR_TTRG GENMASK(12, 8) + +/* CSR (Common Status Register) */ +#define CSR_RDRF BIT(31) /* Receive Data Full */ +#define CSR_TEND BIT(30) /* Transmit End Flag */ +#define CSR_TDRE BIT(29) /* Transmit Data Empty */ +#define CSR_FER BIT(28) /* Framing Error */ +#define CSR_PER BIT(27) /* Parity Error */ +#define CSR_MFF BIT(26) /* Mode Fault Error */ +#define CSR_ORER BIT(24) /* Overrun Error */ +#define CSR_DFER BIT(18) /* Data Compare Match Framing Error */ +#define CSR_DPER BIT(17) /* Data Compare Match Parity Error */ +#define CSR_DCMF BIT(16) /* Data Compare Match */ +#define CSR_RXDMON BIT(15) /* Serial Input Data Monitor */ +#define CSR_ERS BIT(4) /* Error Signal Status */ + +#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) +#define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear) + +#define RSCI_DEFAULT_ERROR_MASK (CSR_PER | CSR_FER) + +#define RSCI_RDxF_CLEAR (CFCLR_RDRFC) +#define RSCI_ERROR_CLEAR (CFCLR_PERC | CFCLR_FERC) +#define RSCI_TDxE_CLEAR (CFCLR_TDREC) +#define RSCI_BREAK_CLEAR (CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC) + +/* FRSR (FIFO Receive Status Register) */ +#define FRSR_R5_0 GENMASK(13, 8) /* Receive FIFO Data Count */ +#define FRSR_DR BIT(0) /* Receive Data Ready */ + +/* CFCLR (Common Flag CLear Register) */ +#define CFCLR_RDRFC BIT(31) /* RDRF Clear */ +#define CFCLR_TDREC BIT(29) /* TDRE Clear */ +#define CFCLR_FERC BIT(28) /* FER Clear */ +#define CFCLR_PERC BIT(27) /* PER Clear */ +#define CFCLR_MFFC BIT(26) /* MFF Clear */ +#define CFCLR_ORERC BIT(24) /* ORER Clear */ +#define CFCLR_DFERC BIT(18) /* DFER Clear */ +#define CFCLR_DPERC BIT(17) /* DPER Clear */ +#define CFCLR_DCMFC BIT(16) /* DCMF Clear */ +#define CFCLR_ERSC BIT(4) /* ERS Clear */ +#define CFCLR_CLRFLAG (CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \ + CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \ + CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC) + +/* FFCLR (FIFO Flag CLear Register) */ +#define FFCLR_DRC BIT(0) /* DR Clear */ + +#define DCR_DEPOL BIT(0) + +static u32 rzsci_serial_in(struct uart_port *p, int offset) +{ + return ioread32(p->membase + offset); +} + +static void rzsci_serial_out(struct uart_port *p, int offset, int value) +{ + iowrite32(value, p->membase + offset); +} + +static void rzsci_clear_DRxC(struct uart_port *port) +{ + rzsci_serial_out(port, CFCLR, CFCLR_RDRFC); + rzsci_serial_out(port, FFCLR, FFCLR_DRC); +} + +static void rzsci_clear_SCxSR(struct uart_port *port, unsigned int mask) +{ + rzsci_serial_out(port, CFCLR, mask); +} + +static void rzsci_start_rx(struct uart_port *port) +{ + unsigned int ctrl; + + ctrl = rzsci_serial_in(port, CCR0); + ctrl |= CCR0_RIE; + rzsci_serial_out(port, CCR0, ctrl); +} + +static void rzsci_set_termios(struct uart_port *port, struct ktermios *termios, + const struct ktermios *old) +{ + struct sci_port *s = to_sci_port(port); + unsigned long flags; + + /* + * For now, only RX enabling is supported + */ + + sci_port_enable(s); + uart_port_lock_irqsave(port, &flags); + + if (termios->c_cflag & CREAD) + rzsci_start_rx(port); + + uart_port_unlock_irqrestore(port, flags); + sci_port_disable(s); +} + +static int rzsci_txfill(struct uart_port *port) +{ + return rzsci_serial_in(port, FTSR); +} + +static int rzsci_rxfill(struct uart_port *port) +{ + u32 val = rzsci_serial_in(port, FRSR); + return FIELD_GET(FRSR_R5_0, val); +} + +static unsigned int rzsci_tx_empty(struct uart_port *port) +{ + unsigned int status = rzsci_serial_in(port, CSR); + unsigned int in_tx_fifo = rzsci_txfill(port); + + return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0; +} + +static void rzsci_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + /* not supported yet */ + return; +} + +static unsigned int rzsci_get_mctrl(struct uart_port *port) +{ + /* not supported yet */ + return 0; +} + +static void rzsci_clear_CFC(struct uart_port *port, unsigned int mask) +{ + rzsci_serial_out(port, CFCLR, mask); +} + +static void rzsci_start_tx(struct uart_port *port) +{ + struct sci_port *sp = to_sci_port(port); + u32 ctrl; + + if (sp->chan_tx) + return; + + /* + * TE (Transmit Enable) must be set after setting TIE + * (Transmit Interrupt Enable) or in the same instruction + * to start the transmit process. + */ + ctrl = rzsci_serial_in(port, CCR0); + ctrl |= CCR0_TIE | CCR0_TE; + rzsci_serial_out(port, CCR0, ctrl); +} + +static void rzsci_stop_tx(struct uart_port *port) +{ + u32 ctrl; + + ctrl = rzsci_serial_in(port, CCR0); + ctrl &= ~CCR0_TIE; + + rzsci_serial_out(port, CCR0, ctrl); +} + +static void rzsci_stop_rx(struct uart_port *port) +{ + u32 ctrl; + + ctrl = rzsci_serial_in(port, CCR0); + ctrl &= ~CCR0_RIE; + + rzsci_serial_out(port, CCR0, ctrl); +} + +static int rzsci_txroom(struct uart_port *port) +{ + return port->fifosize - rzsci_txfill(port); +} + +static void rzsci_transmit_chars(struct uart_port *port) +{ + struct tty_port *tport = &port->state->port; + unsigned int stopped = uart_tx_stopped(port); + u32 status, ctrl; + int count; + + status = rzsci_serial_in(port, CSR); + if (!(status & CSR_TDRE)) { + ctrl = rzsci_serial_in(port, CCR0); + if (kfifo_is_empty(&tport->xmit_fifo)) + ctrl &= ~CCR0_TIE; + else + ctrl |= CCR0_TIE; + rzsci_serial_out(port, CCR0, ctrl); + return; + } + + count = rzsci_txroom(port); + + do { + unsigned char c; + + if (port->x_char) { + c = port->x_char; + port->x_char = 0; + } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) + break; + + rzsci_clear_CFC(port, CFCLR_TDREC); + rzsci_serial_out(port, TDR, c); + + port->icount.tx++; + } while (--count > 0); + + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (kfifo_is_empty(&tport->xmit_fifo)) { + ctrl = rzsci_serial_in(port, CCR0); + ctrl &= ~CCR0_TIE; + ctrl |= CCR0_TEIE; + rzsci_serial_out(port, CCR0, ctrl); + } +} + +static void rzsci_receive_chars(struct uart_port *port) +{ + struct tty_port *tport = &port->state->port; + int i, count, copied = 0; + u32 status, frsr_status = 0; + unsigned char flag; + + status = rzsci_serial_in(port, CSR); + frsr_status = rzsci_serial_in(port, FRSR); + + if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR)) + return; + + while (1) { + /* Don't copy more bytes than there is room for in the buffer */ + count = tty_buffer_request_room(tport, rzsci_rxfill(port)); + + /* If for any reason we can't copy more data, we're done! */ + if (count == 0) + break; + + for (i = 0; i < count; i++) { + char c; + + status = rzsci_serial_in(port, CSR); + c = rzsci_serial_in(port, RDR) & RDR_RDAT_MSK; + + if (uart_handle_sysrq_char(port, c)) { + count--; + i--; + continue; + } + + /* Store data and status */ + if (status & CSR_FER) { + flag = TTY_FRAME; + port->icount.frame++; + } else if (status & CSR_PER) { + flag = TTY_PARITY; + port->icount.parity++; + } else + flag = TTY_NORMAL; + + tty_insert_flip_char(tport, c, flag); + } + + rzsci_serial_in(port, CSR); /* dummy read */ + rzsci_clear_DRxC(port); + + copied += count; + port->icount.rx += count; + } + + if (copied) { + /* Tell the rest of the system the news. New characters! */ + tty_flip_buffer_push(tport); + } else { + /* TTY buffers full; read from RX reg to prevent lockup */ + rzsci_serial_in(port, RDR); + rzsci_serial_in(port, CSR); /* dummy read */ + rzsci_clear_DRxC(port); + } +} + +static void rzsci_poll_put_char(struct uart_port *port, unsigned char c) +{ + u32 status; + + do { + status = rzsci_serial_in(port, CSR); + } while (!(status & CSR_TDRE)); + + rzsci_serial_out(port, TDR, c); + rzsci_clear_SCxSR(port, CFCLR_TDREC); + return; +} + +static unsigned int rzci_get_ctrl_temp(struct uart_port *port, unsigned int) +{ + struct sci_port *s = to_sci_port(port); + + return s->params->param_bits.rxtx_enable | CCR0_TIE; +} + +static const char *rzsci_type(struct uart_port *port) +{ + return "rzsci"; +} + +static const struct sci_common_regs rzsci_common_regs = { + .status = CSR, + .control = CCR0, +}; + +static const struct sci_port_params_bits rzsci_port_param_bits = { + .rxtx_enable = CCR0_RE | CCR0_TE, + .te_clear = CCR0_TE | CCR0_TEIE, + .poll_sent_bits = CSR_TDRE | CSR_TEND, +}; + +static const struct sci_port_params rzsci_port_params = { + .fifosize = 16, + .overrun_reg = CSR, + .overrun_mask = CSR_ORER, + .sampling_rate_mask = SCI_SR(32), + .error_mask = RSCI_DEFAULT_ERROR_MASK, + .error_clear = RSCI_ERROR_CLEAR, + .param_bits = rzsci_port_param_bits, + .common_regs = &rzsci_common_regs, +}; + +static const struct uart_ops rzt2_sci_uart_ops = { + .tx_empty = rzsci_tx_empty, + .set_mctrl = rzsci_set_mctrl, + .get_mctrl = rzsci_get_mctrl, + .start_tx = rzsci_start_tx, + .stop_tx = rzsci_stop_tx, + .stop_rx = rzsci_stop_rx, + .startup = sci_startup, + .flush_buffer = sci_flush_buffer, + .set_termios = rzsci_set_termios, + .pm = sci_pm, + .type = rzsci_type, + .release_port = sci_release_port, + .request_port = sci_request_port, + .config_port = sci_config_port, + .verify_port = sci_verify_port, +}; + +static const struct sci_port_ops rzsci_port_ops = { + .read_reg = rzsci_serial_in, + .write_reg = rzsci_serial_out, + .clear_SCxSR = rzsci_clear_SCxSR, + .transmit_chars = rzsci_transmit_chars, + .receive_chars = rzsci_receive_chars, + .poll_put_char = rzsci_poll_put_char, + .get_ctrl_temp = rzci_get_ctrl_temp, +}; + +struct sci_of_data sci_r9a09g077_data = { + .type = PORT_RZSCI, + .regtype = SCIx_RZT2H_SCI_REGTYPE, + .ops = &rzsci_port_ops, + .uart_ops = &rzt2_sci_uart_ops, + .params = &rzsci_port_params, +}; + +#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON + +static int __init rzt2hsci_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + return early_console_setup(device, &sci_r9a09g077_data); +} + +OF_EARLYCON_DECLARE(rzsci, "renesas,r9a09g077-sci", rzt2hsci_early_console_setup); + +#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ diff --git a/drivers/tty/serial/rzsci.h b/drivers/tty/serial/rzsci.h new file mode 100644 index 000000000000..2840b65e7010 --- /dev/null +++ b/drivers/tty/serial/rzsci.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __RZT2_SCI_H__ +#define __RZT2_SCI_H__ + +#include "sh-sci_common.h" + +#ifdef CONFIG_SERIAL_RZ_SCI +extern struct sci_of_data sci_r9a09g077_data; +#endif + +#endif /* __RZT2_SCI_H__ */ diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index c58c0793c521..3c0e503295e9 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -54,6 +54,7 @@ #include #endif +#include "rzsci.h" #include "serial_mctrl_gpio.h" #include "sh-sci.h" #include "sh-sci_common.h" @@ -1804,7 +1805,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) unsigned long flags; u32 ctrl; - if (port->type != PORT_SCI) + if (port->type != PORT_SCI && port->type != PORT_RZSCI) return sci_tx_interrupt(irq, ptr); uart_port_lock_irqsave(port, &flags); @@ -2988,10 +2989,10 @@ static int sci_init_single(struct platform_device *dev, } /* - * The fourth interrupt on SCI port is transmit end interrupt, so + * The fourth interrupt on SCI and RZSCI port is transmit end interrupt, so * shuffle the interrupts. */ - if (p->type == PORT_SCI) + if (p->type == PORT_SCI || p->type == PORT_RZSCI) swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); /* The SCI generates several interrupts. They can be muxed together or @@ -3038,6 +3039,9 @@ static int sci_init_single(struct platform_device *dev, else sci_port->rx_trigger = 8; break; + case PORT_RZSCI: + sci_port->rx_trigger = 15; + break; default: sci_port->rx_trigger = 1; break; @@ -3269,7 +3273,7 @@ static void sci_remove(struct platform_device *dev) if (port->port.fifosize > 1) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); - if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) + if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || type == PORT_RZSCI) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); } @@ -3300,6 +3304,12 @@ static const struct of_device_id of_sci_match[] __maybe_unused = { .compatible = "renesas,scif-r9a09g057", .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), }, +#ifdef CONFIG_SERIAL_RZ_SCI + { + .compatible = "renesas,r9a09g077-sci", + .data = &sci_r9a09g077_data, + }, +#endif /* CONFIG_SERIAL_RZ_SCI */ /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3504,7 +3514,7 @@ static int sci_probe(struct platform_device *dev) return ret; } if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || - sp->port.type == PORT_HSCIF) { + sp->port.type == PORT_HSCIF || sp->port.type == PORT_RZSCI) { ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) { diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 0f2f50b8d28e..787fd9a96711 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h @@ -38,6 +38,7 @@ enum { SCIx_HSCIF_REGTYPE, SCIx_RZ_SCIFA_REGTYPE, SCIx_RZV2H_SCIF_REGTYPE, + SCIx_RZT2H_SCI_REGTYPE, SCIx_NR_REGTYPES, }; @@ -50,7 +51,7 @@ struct plat_sci_port_ops { * Platform device specific platform_data struct */ struct plat_sci_port { - unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ + unsigned int type; /* SCI / SCIF / IRDA / HSCIF / RZSCI */ upf_t flags; /* UPF_* flags */ unsigned int sampling_rate; diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 9c007a106330..30fbbef599f4 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -231,6 +231,9 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* SH-SCI */ +#define PORT_RZSCI 124 + /* Generic type identifier for ports which type is not important to userspace. */ #define PORT_GENERIC (-1) From patchwork Wed Jan 29 16:37:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953942 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1F8CB1DFE00; Wed, 29 Jan 2025 16:52:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169567; cv=none; b=e+eCZqwUzhQIXSb701Sij+PKwFPcrvHRURwx8eW69VLTkI+7ecNK6kDSQ3SN1s6e2lKoK9Wy8yy3C1/TuT7V16RCfJZTWqDST9r9Xr6FBh9hw9iZ2/DqjQNNb7MCJbnC9qkWk98Zu/xHpTTd3Oofi6nQAsf7IZ5Ya3NM3xh0fIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169567; c=relaxed/simple; bh=NUT/d3UeYWQltVBqEhEx9CsCqthGyzfLH4Fa5L4NTqI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kaz+3DumdQ56+lSOiK0ZsjpFRi5WpPBkb0xspzMH5Ee0YwmzZsJexU305haDLbF5++bH0z1l5u4X4r1iylEB5NMKfAkMWL3euQXNdPwrlHLqOzr5DmT8+GhzTc5KtrBXTD3bCUU8w2+tq8zykxoZrAqDRxRIU8SmYAFhEBcIp38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: l+3Q2I5FQFSP2+nLSI7oBw== X-CSE-MsgGUID: 8Q46k3C3SJiIM9rg9VrBiQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 30 Jan 2025 01:52:44 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id F2724402F02E; Thu, 30 Jan 2025 01:52:40 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Thierry Bultel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC Date: Wed, 29 Jan 2025 16:37:48 +0000 Message-ID: <20250129165122.2980-13-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the initial dtsi for the RZ/T2H Soc: - gic - armv8-timer - cpg clock - sci0 uart also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps all 4 CPUs enabled, for consistency with later support of -m24 and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively, and that will use /delete-node/ to disable the missing CPUs. Signed-off-by: Thierry Bultel --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 129 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi | 8 ++ 2 files changed, 137 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi new file mode 100644 index 000000000000..55a2b1bd8100 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g077"; + #address-cells = <2>; + #size-cells = <2>; + + extal: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + loco: loco { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-sci"; + reg = <0 0x80005000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A09G077_SCI0_CLK>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + cpg: clock-controller@80280000 { + compatible = "renesas,r9a09g077-cpg"; + reg = <0 0x80280000 0 0x1000>, + <0 0x81280000 0 0x9000>; + clocks = <&extal>, <&loco>; + clock-names = "extal", "loco"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + gic: interrupt-controller@83000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x83000000 0 0x40000>, + <0x0 0x83040000 0 0x160000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi new file mode 100644 index 000000000000..f54bb50829db --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H 4-core SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include "r9a09g077.dtsi" From patchwork Wed Jan 29 16:37:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 13953944 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 64F731DFE00; Wed, 29 Jan 2025 16:53:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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30 Jan 2025 01:53:01 +0900 Received: from wvbox.administration.lan (unknown [10.226.92.145]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3E80A402F02E; Thu, 30 Jan 2025 01:52:45 +0900 (JST) From: Thierry Bultel To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Thierry Bultel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board Date: Wed, 29 Jan 2025 16:37:49 +0000 Message-ID: <20250129165122.2980-14-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the initial device tree for the RZ/T2H evaluation board. Signed-off-by: Thierry Bultel --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 37 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 97228a3cb99c..422ff9ccd05e 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb +dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts new file mode 100644 index 000000000000..f2b448aaec82 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H Development EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g077m44.dtsi" + +/ { + model = "Renesas Development EVK based on r9a09g077m44"; + compatible = "renesas,r9a9g077m44-rzt2h-evk", "renesas,r9a9g077"; + + aliases { + serial0 = &sci0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + +}; + +&extal { + clock-frequency = <25000000>; +}; + +&loco { + clock-frequency = <1000000>; +}; + +&sci0 { + status = "okay"; +};