From patchwork Thu Jan 30 13:00:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13954538 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC8DE1BC07A for ; Thu, 30 Jan 2025 13:01:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.104.207.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738242077; cv=none; b=fYNyaBp56NomAOcEhr5SvoDkpfGg0/GvLmJ2VJFxVUEqasHmRJL+U1xhdPvBX/wq2JVtdNuZJZRh0PDwfUiV+X1QkUpR5U2I0W/qxG5NMJv3wYQBUnCSE5cNz7BKuXLkcN4SfS0nXTnU4b7JNaGQ0A/wJwDhy8kb8GdXeQNroNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738242077; c=relaxed/simple; bh=PYb5PVqFei0MECxubIFcxESnWkCFmAzq6ua5HfuqqbE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UXwpWBazCK6pvuOeGtMvU5GBmnxo3v3woLoFCPRLWw85zRpbqBurZiO8xRWAlE+TNNcDVvHsMoRORBru7cNbxKxYGpsOSZMWzSKt5Wnj9dDtS95m6gxP4KwFrx75GL46e/TWOQdrwtC0euZuiUCrHtP3pRYFd3c5AA3AOwsRaW0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b=G2NOuVP8; dkim=fail (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=UR1yUV+7 reason="key not found in DNS"; arc=none smtp.client-ip=93.104.207.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="G2NOuVP8"; dkim=fail reason="key not found in DNS" (0-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="UR1yUV+7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1738242075; x=1769778075; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xq5ntvdixTiMxw1S/ZM1ceyovGwDVcIx7hfQrpd8SjY=; b=G2NOuVP8PvEo1c16WaMgWMwjYAGN9QpLlMJUa47EP66zIia0FMAe0Hqu gPv9Q0Dzn/sVnkO9hc66b/vgA1ZHkEF16riAImThahDqRpa/TFyJtkc5n RgAcxxXUPdfiiqjwiAbSD8qbYiVUdsFF+mbSAFfVCbYLa+2aQp2fuDAKP r8fa/wxqQZYiN9DdBHK7lXbZaA6pYaeXTAdyyJzKCRp/zl3XTngogxIt8 5HgV/O81DjRgVFlX46VEFNRc85+KzPA0mAwlw/E3GqJY0fOheVGPe23RL xOhtVC0LwTQ0GMHUz02YibwI4B2mpc/MLSo6MLoW+p3fJFLydeFqTppk8 A==; X-CSE-ConnectionGUID: Xpw1lbTSSA+LmV+tlAdbqA== X-CSE-MsgGUID: Jg7Qd6jUTN2CIa1azzepQA== X-IronPort-AV: E=Sophos;i="6.13,245,1732575600"; d="scan'208";a="41374598" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 30 Jan 2025 14:01:13 +0100 X-CheckPoint: {679B7819-39-31397509-E321C4C4} X-MAIL-CPID: 9BA95ED871756AC7173E720217D157CF_0 X-Control-Analysis: str=0001.0A682F21.679B781A.0002,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 141261675B4; Thu, 30 Jan 2025 14:01:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1738242069; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xq5ntvdixTiMxw1S/ZM1ceyovGwDVcIx7hfQrpd8SjY=; b=UR1yUV+70I+An2YmuusWORYL4BjlpiS/BTwBrJNm/+PFoMO9bDCS9TKCI2EMrLOBBHNhFo rYWa1E/gvtMOEcDdLpSaRWOYZwM2gpm+fM/q0bR98mVFPmf4bGKRZMBH7hoJhZdLPslodI SOOt31ld5pQa1rTVVysSFN3s99mD75x6zn9TE4eX8Q+UFisk/bE8oX6grAgpo26rttsikU RJ1Ly+346pXDyUqVWjBG2EcX2mrIv2NBBK7XrqM0HCy79RrMMTGKRsj1cIwqMrf+8zCQBc +8IL7ffBGiKcmRznMDIejAMqPvt/8r3VMM/27R3lpvmKlIAXl9CGmMnKBSjMsw== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Srinivas Kandagatla Cc: Alexander Stein , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: nvmem: imx-ocotp: Add i.MX8M Nano access controller definitions Date: Thu, 30 Jan 2025 14:00:58 +0100 Message-Id: <20250130130101.1040824-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130130101.1040824-1-alexander.stein@ew.tq-group.com> References: <20250130130101.1040824-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 These are the definition for the bindings of imx-ocotp for disabling fuses. Signed-off-by: Alexander Stein Reviewed-by: Frank Li Acked-by: Conor Dooley --- include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h diff --git a/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h b/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h new file mode 100644 index 0000000000000..6e554edefd488 --- /dev/null +++ b/include/dt-bindings/nvmem/fsl,imx8mn-ocotp.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef _DT_BINDINGS_NVMEM_IMX8MN_OCOTP_H +#define _DT_BINDINGS_NVMEM_IMX8MN_OCOTP_H + +#define IMX8MN_OCOTP_M7_DISABLE 0 +#define IMX8MN_OCOTP_M7_MPU_DISABLE 1 +#define IMX8MN_OCOTP_M7_FPU_DISABLE 2 +#define IMX8MN_OCOTP_USB_OTG1_DISABLE 3 +#define IMX8MN_OCOTP_GPU3D_DISABLE 4 +#define IMX8MN_OCOTP_MIPI_DSI_DISABLE 5 +#define IMX8MN_OCOTP_ENET_DISABLE 6 +#define IMX8MN_OCOTP_MIPI_CSI_DISABLE 7 +#define IMX8MN_OCOTP_ASRC_DISABLE 8 + +#endif From patchwork Thu Jan 30 13:00:59 2025 Content-Type: text/plain; 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Thu, 30 Jan 2025 14:01:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1738242074; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1qhRbu605zRQmNnQr5f4yNDwmxxb+PPe4g8I5X68vQg=; b=P9QJefT0IPrYF3Smx7qjegIOujC1UdIQEbRkT1xuE8bxTOBvLsqHGEeFdzscAwcDJ+gPGb KhIWzDI0KjaHF5c5j839jT73xUxiBsm02iB7yk8iUQ9MZ5WkNsGpPW8z3ES3OlYLCJxkuW HXffa0F/I1ilKFp1Re9HSa9rEi7YpsFIxQuUPcW97pguod14f+wOP212efR6FeMjeBD753 TXnXa2unORAgGjIoydKlpc9jGkc7Jr5HImyeJvGzIBtFaT0i8t9E+/HjJ12qYjMkDUKAX8 wFITMOScrgV+WjGgf6CdSduR2v1THwCDpXYoVWmol7A+MM0toQlPZuLP4xZkdw== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Srinivas Kandagatla Cc: Alexander Stein , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] nvmem: imx-ocotp: Sort header alphabetically Date: Thu, 30 Jan 2025 14:00:59 +0100 Message-Id: <20250130130101.1040824-3-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130130101.1040824-1-alexander.stein@ew.tq-group.com> References: <20250130130101.1040824-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 Move linux/delay.h to the right position. Signed-off-by: Alexander Stein Reviewed-by: Frank Li --- drivers/nvmem/imx-ocotp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 79dd4fda03295..c5086a16450ac 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -22,7 +23,6 @@ #include #include #include -#include #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the * OTP Bank0 Word0 From patchwork Thu Jan 30 13:01:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13954540 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEC281E5726 for ; Thu, 30 Jan 2025 13:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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If not allowed to be accessed, detach the node Signed-off-by: Alexander Stein Reviewed-by: Frank Li --- drivers/nvmem/Kconfig | 3 ++ drivers/nvmem/imx-ocotp.c | 105 +++++++++++++++++++++++++++++++++++++- 2 files changed, 107 insertions(+), 1 deletion(-) diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 8671b7c974b93..ba5c928cab520 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP This driver can also be built as a module. If so, the module will be called nvmem-imx-ocotp. + If built as modules, any other driver relying on this working + as access controller also needs to be a module as well. + config NVMEM_IMX_OCOTP_ELE tristate "i.MX On-Chip OTP Controller support" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index c5086a16450ac..e3ea026a37d0d 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -23,6 +23,7 @@ #include #include #include +#include #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the * OTP Bank0 Word0 @@ -91,11 +92,20 @@ struct ocotp_ctrl_reg { u32 bm_rel_shadows; }; +#define OCOTP_MAX_NUM_GATE_WORDS 4 + +struct disable_fuse { + u32 fuse_addr; + u32 mask; +}; + struct ocotp_params { unsigned int nregs; unsigned int bank_address_words; void (*set_timing)(struct ocotp_priv *priv); struct ocotp_ctrl_reg ctrl; + u32 num_disables; + struct disable_fuse *disables; }; static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) @@ -552,11 +562,25 @@ static const struct ocotp_params imx8mm_params = { .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, }; +struct disable_fuse imx8mn_disable_fuse[] = { + [IMX8MN_OCOTP_M7_DISABLE] = { .fuse_addr = 20, .mask = BIT(8) }, + [IMX8MN_OCOTP_M7_MPU_DISABLE] = { .fuse_addr = 20, .mask = BIT(9) }, + [IMX8MN_OCOTP_M7_FPU_DISABLE] = { .fuse_addr = 20, .mask = BIT(10) }, + [IMX8MN_OCOTP_USB_OTG1_DISABLE] = { .fuse_addr = 20, .mask = BIT(11) }, + [IMX8MN_OCOTP_GPU3D_DISABLE] = { .fuse_addr = 20, .mask = BIT(24) }, + [IMX8MN_OCOTP_MIPI_DSI_DISABLE] = { .fuse_addr = 20, .mask = BIT(28) }, + [IMX8MN_OCOTP_ENET_DISABLE] = { .fuse_addr = 20, .mask = BIT(29) }, + [IMX8MN_OCOTP_MIPI_CSI_DISABLE] = { .fuse_addr = 20, .mask = BIT(30) }, + [IMX8MN_OCOTP_ASRC_DISABLE] = { .fuse_addr = 20, .mask = BIT(31) }, +}; + static const struct ocotp_params imx8mn_params = { .nregs = 256, .bank_address_words = 0, .set_timing = imx_ocotp_set_imx6_timing, .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, + .num_disables = ARRAY_SIZE(imx8mn_disable_fuse), + .disables = imx8mn_disable_fuse, }; static const struct ocotp_params imx8mp_params = { @@ -589,6 +613,81 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem, cell->read_post_process = imx_ocotp_cell_pp; } +static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 id) +{ + u32 addr, mask, ret, val; + + if (id >= priv->params->num_disables) { + dev_err(priv->dev, "Index %d too large\n", id); + return -EACCES; + } + + addr = priv->params->disables[id].fuse_addr; + mask = priv->params->disables[id].mask; + + ret = imx_ocotp_read(priv, addr, &val, sizeof(val)); + if (ret) + return ret; + + dev_dbg(priv->dev, "id:%d addr:%#x mask:0x%08x\n", id, addr, mask); + /* true means disabled */ + if (val & mask) + return -EACCES; + + return 0; +} + +static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent) +{ + struct device *dev = priv->dev; + + for_each_available_child_of_node_scoped(parent, child) { + struct of_phandle_args args; + u32 id, idx = 0; + + while (!of_parse_phandle_with_args(child, "access-controllers", + "#access-controller-cells", + idx++, &args)) { + of_node_put(args.np); + if (args.np != dev->of_node) + continue; + + /* Only support one cell */ + if (args.args_count != 1) { + dev_err(dev, "wrong args count\n"); + continue; + } + + id = args.args[0]; + + dev_dbg(dev, "Checking node: %pOF disable ID: %d\n", child, id); + + if (imx_ocotp_check_access(priv, id)) { + of_detach_node(child); + dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n", + child); + } + } + + imx_ocotp_grant_access(priv, child); + } + + return 0; +} + +static int imx_ocotp_access_control(struct ocotp_priv *priv) +{ + struct device_node *root __free(device_node) = of_find_node_by_path("/"); + + if (!priv->params->disables) + return 0; + + if (WARN_ON(!root)) + return -EINVAL; + + return imx_ocotp_grant_access(priv, root); +} + static int imx_ocotp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -622,9 +721,13 @@ static int imx_ocotp_probe(struct platform_device *pdev) imx_ocotp_clr_err_if_set(priv); clk_disable_unprepare(priv->clk); + platform_set_drvdata(pdev, priv); + nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); - return PTR_ERR_OR_ZERO(nvmem); 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Signed-off-by: Alexander Stein --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a5f9cfb46e5dd..b023724679b80 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "imx8mn-pinfunc.h" @@ -431,6 +432,7 @@ easrc: easrc@300c0000 { firmware-name = "imx/easrc/easrc-imx8mn.bin"; fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; + access-controllers = <&ocotp IMX8MN_OCOTP_ASRC_DISABLE>; status = "disabled"; }; }; @@ -571,6 +573,7 @@ ocotp: efuse@30350000 { clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; /* * The register address below maps to the MX8M @@ -1053,6 +1056,7 @@ fec1: ethernet@30be0000 { nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; fsl,stop-mode = <&gpr 0x10 3>; + access-controllers = <&ocotp IMX8MN_OCOTP_ENET_DISABLE>; status = "disabled"; }; @@ -1091,6 +1095,7 @@ mipi_dsi: dsi@32e10000 { clock-names = "bus_clk", "sclk_mipi"; interrupts = ; power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_DSI_DISABLE>; status = "disabled"; ports { @@ -1195,6 +1200,7 @@ mipi_csi: mipi-csi@32e30000 { <&clk IMX8MN_CLK_DISP_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; + access-controllers = <&ocotp IMX8MN_OCOTP_MIPI_CSI_DISABLE>; status = "disabled"; ports { @@ -1225,6 +1231,7 @@ usbotg1: usb@32e40000 { phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; power-domains = <&pgc_hsiomix>; + access-controllers = <&ocotp IMX8MN_OCOTP_USB_OTG1_DISABLE>; status = "disabled"; }; @@ -1288,6 +1295,7 @@ gpu: gpu@38000000 { <400000000>, <1200000000>; power-domains = <&pgc_gpumix>; + access-controllers = <&ocotp IMX8MN_OCOTP_GPU3D_DISABLE>; }; gic: interrupt-controller@38800000 {