From patchwork Thu Jan 30 13:29:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A08A4C02190 for ; Thu, 30 Jan 2025 13:29:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbl-0004f1-PF; Thu, 30 Jan 2025 08:29:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbk-0004ed-8a for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:24 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbi-0001Of-Nv for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:24 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 6D486A40C33; Thu, 30 Jan 2025 13:27:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DC2AC4CEE0; Thu, 30 Jan 2025 13:29:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243759; bh=kFS5JPLZ6Yq0LhIiT+AHVHk3BwDkleBFMtJ92/ovT10=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mTLybAPFPWgDU06R5MM9/rXroJ//GYDbaFqi+UMKYLHyzBFzvKDoDbbUhwMzg0SAU TT/gl4jTFxuE/8AABXAMwBjDtAuJB5X11lIlDHKQu5N3SZ5qwRlpO7nxs+JAkJj6gi mzwgvF2lHISfHxy/B2THVbTtCPm32QLHqOIHDBLS3ZVV7uzmlZDnIlpkpZpXuX3v00 gFIEHOypI3n4VkEu2h96ZS15j88XZsSY5JgmaKYrvJsNqLyyoDApD1WVnD4hgMTZPi 7rcIV7UjfXY18H0PSiv8vj45veKiOAj5rbFkLElz/A1pJkegyt4XhOIbJdx47cwseb /hcMdD4JkMZpw== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 1/9] MAINTAINERS: Add myself as HPPA maintainer Date: Thu, 30 Jan 2025 14:29:06 +0100 Message-ID: <20250130132915.16846-2-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Since I contribute quite some code to hppa, I'd like to step up and become the secondary maintainer for HPPA beside Richard. Additionally change status of hppa machines to maintained as I will take care of them. Signed-off-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7be3d8f431..dbf39cfbb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -251,6 +251,7 @@ F: target/hexagon/gen_idef_parser_funcs.py HPPA (PA-RISC) TCG CPUs M: Richard Henderson +M: Helge Deller S: Maintained F: target/hppa/ F: disas/hppa.c @@ -1188,8 +1189,8 @@ HP-PARISC Machines ------------------ HP B160L, HP C3700 M: Richard Henderson -R: Helge Deller -S: Odd Fixes +M: Helge Deller +S: Maintained F: configs/devices/hppa-softmmu/default.mak F: hw/display/artist.c F: hw/hppa/ From patchwork Thu Jan 30 13:29:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E754AC0218F for ; Thu, 30 Jan 2025 13:29:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbm-0004fM-QF; Thu, 30 Jan 2025 08:29:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbl-0004eu-Fq for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:25 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbj-0001Oc-OW for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:25 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id AD6525C03F5; Thu, 30 Jan 2025 13:28:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45903C4CED2; Thu, 30 Jan 2025 13:29:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243761; bh=JbHKUaoOT21JZo4ZqtXrin1/f4CIQEzf3APbV087HeE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JC9T691IGiVHRdPbkiWHNiePlwOf3n0EfgC8nG2YTaZI6HQ+EH56dnk0Vca/tjDn2 Sw2fCb9oTcXs9a0PB7snyC7d6EU1XEuhm0Nw0slIc0pf2s2DcCCS+HuQtAzH3/B1Qx HggAD55thebR84dw6xr7KeOiIVJS78TzWi6OlsDapHpCDEMGaxHqgE8osAYlDdQBoK 1m7ePSJvlqadyS+f5+Txdmu8IPuwNZ/+2LrmCKjS1p7XMLdC2nf8ey4AI0lZnI/62h q9e//ANNzHuCmCTVDgemuCzHNtdHJIiJ0ilRQ1UyasM6/ooviEs+O5IBEhEw6JnZWw gu7imh/z17fig== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 2/9] hppa: Sync contents of hppa_hardware.h header file with SeaBIOS-hppa Date: Thu, 30 Jan 2025 14:29:07 +0100 Message-ID: <20250130132915.16846-3-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The hppa_hardware.h header file holds many constants for addresses and offsets which are needed while building the firmware (SeaBIOS-hppa) and while setting up the virtual machine in QEMU. This patch brings it in sync between both source code repositories. Signed-off-by: Helge Deller Acked-by: Richard Henderson --- hw/hppa/hppa_hardware.h | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h index a276240967..21c777cba6 100644 --- a/hw/hppa/hppa_hardware.h +++ b/hw/hppa/hppa_hardware.h @@ -6,6 +6,11 @@ #define FIRMWARE_START 0xf0000000 #define FIRMWARE_END 0xf0800000 +#define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */ + +#define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ + +#define MEM_PDC_ENTRY 0x4800 /* PDC entry address */ #define DEVICE_HPA_LEN 0x00100000 @@ -18,6 +23,7 @@ #define LASI_UART_HPA 0xffd05000 #define LASI_SCSI_HPA 0xffd06000 #define LASI_LAN_HPA 0xffd07000 +#define LASI_RTC_HPA 0xffd09000 #define LASI_LPT_HPA 0xffd02000 #define LASI_AUDIO_HPA 0xffd04000 #define LASI_PS2KBD_HPA 0xffd08000 @@ -27,16 +33,23 @@ #define CPU_HPA 0xfffb0000 #define MEMORY_HPA 0xfffff000 -#define PCI_HPA DINO_HPA /* PCI bus */ #define IDE_HPA 0xf9000000 /* Boot disc controller */ +#define ASTRO_HPA 0xfed00000 +#define ELROY0_HPA 0xfed30000 +#define ELROY2_HPA 0xfed32000 +#define ELROY8_HPA 0xfed38000 +#define ELROYc_HPA 0xfed3c000 +#define ASTRO_MEMORY_HPA 0xfed10200 + +#define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */ /* offsets to DINO HPA: */ #define DINO_PCI_ADDR 0x064 #define DINO_CONFIG_DATA 0x068 #define DINO_IO_DATA 0x06c -#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) -#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) +#define PORT_PCI_CMD hppa_port_pci_cmd +#define PORT_PCI_DATA hppa_port_pci_data #define FW_CFG_IO_BASE 0xfffa0000 @@ -46,9 +59,24 @@ #define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */ #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ +#define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */ #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ #define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */ -#define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ +#define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */ + +/* ASTRO Memory and I/O regions */ +#define ASTRO_BASE_HPA 0xfffed00000 +#define ELROY0_BASE_HPA 0xfffed30000 /* ELROY0_HPA */ + +#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ + +#define LMMIO_DIRECT0_BASE 0x300 +#define LMMIO_DIRECT0_MASK 0x308 +#define LMMIO_DIRECT0_ROUTE 0x310 + +/* space register hashing */ +#define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */ +#define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */ #endif From patchwork Thu Jan 30 13:29:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 662A8C0218A for ; Thu, 30 Jan 2025 13:29:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbo-0004hZ-Pk; Thu, 30 Jan 2025 08:29:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbm-0004fI-DX for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:26 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbk-0001Oy-GK for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:26 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id ACA7AA40395; Thu, 30 Jan 2025 13:27:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DFC71C4CEE0; Thu, 30 Jan 2025 13:29:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243763; bh=8JVAwIADkG+JebhPJNIZp30+tTso8du5rqRv5ZLqBuI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pG+zGNOt0DeGn14lh9kWSjOKmMCUyFSFEVKNTFweeOwSWWeWTZEpXipu82D2svfdC hRdeFHulEcKIv+ArHEKfJyodLjj3NVZnNMuu8YShB0xrWzK4hswuEulZap2O0enV+x xqpSVpaX2wLl/t+57i03+Z2xOE9VP+SnVzNkGRYDqYbpW1tI0KW7NqWATpn44WMDlj xDHsqiXaKno877pqflZcm3O5G0L48be7T6UxXS0FbS+4Tn0cFpR8FHFUGOvxyT5aQo wkCevZcSXs8luEoptnpdj2/ZfqPZUZLis7GW9rNdGmbsXdVhqsg0lcHR9ax4RV3sKY I/qMQKuZmZuYg== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 3/9] disas/hppa: implement mfdiag/mtdiag disassembly Date: Thu, 30 Jan 2025 14:29:08 +0100 Message-ID: <20250130132915.16846-4-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The various PA-RISC CPUs implement different CPU-specific diag instructions (mfdiag, mtdiag, mfcpu, mtcpu, ...) to access CPU-internal diagnose/configuration registers, e.g. for cache control, managing space register hashing, control front panel LEDs and read status of the hardware reset button. Those instructions are mostly undocumented, but are used by ODE, HP-UX and Linux. This patch adds some neccessary instructions for PCXL and PCXU CPUs. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- disas/hppa.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/disas/hppa.c b/disas/hppa.c index 49e2231ae6..2b58434966 100644 --- a/disas/hppa.c +++ b/disas/hppa.c @@ -606,7 +606,7 @@ struct pa_opcode In the args field, the following characters are unused: - ' " - / 34 6789:; ' + ' " - / 34 678 :; ' '@ C M [\] ' '` e g } ' @@ -650,6 +650,7 @@ Also these: | 6 bit field length at 19,27:31 (fixed extract/deposit) A 13 bit immediate at 18 (to support the BREAK instruction) ^ like b, but describes a control register + 9 like b, but describes a diagnose register ! sar (cr11) register D 26 bit immediate at 31 (to support the DIAG instruction) $ 9 bit immediate at 28 (to support POPBTS) @@ -1322,13 +1323,19 @@ static const struct pa_opcode pa_opcodes[] = { "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +/* completely undocumented, but used by ODE, HP-UX and Linux: */ +{ "mfcpu_pcxu", 0x140008a0, 0xfc9fffe0, "9,t", pa20, 0}, /* PCXU: mfdiag */ +{ "mtcpu_pcxu", 0x14001840, 0xfc00ffff, "x,9", pa20, 0}, + /* These may be specific to certain versions of the PA. Joel claimed they were 72000 (7200?) specific. However, I'm almost certain the mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mfcpu_c", 0x14000600, 0xfc00ffff, "9,x", pa10, 0}, /* PCXL: for dr0 and dr8 only */ +{ "mfcpu_t", 0x14001400, 0xfc9fffe0, "9,t", pa10, 0}, /* PCXL: all dr except dr0 and dr8 */ +{ "mtcpu_pcxl", 0x14000240, 0xfc00ffff, "x,9", pa11, 0}, /* PCXL: mtcpu for dr0 and dr8 */ { "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, { "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, @@ -1336,6 +1343,9 @@ static const struct pa_opcode pa_opcodes[] = { "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, { "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, +/* instead of showing D only, show all other registers too */ +{ "diag", 0x14000000, 0xfc000000, "D x,9,t", pa10, 0}, + /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ { "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, @@ -1801,6 +1811,12 @@ fput_creg (unsigned reg, disassemble_info *info) (*info->fprintf_func) (info->stream, "%s", control_reg[reg]); } +static void +fput_dreg (unsigned reg, disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, "dr%d", reg); +} + /* Print constants with sign. */ static void @@ -2007,6 +2023,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info) case '^': fput_creg (GET_FIELD (insn, 6, 10), info); break; + case '9': + fput_dreg (GET_FIELD (insn, 6, 10), info); + break; case 't': fput_reg (GET_FIELD (insn, 27, 31), info); break; From patchwork Thu Jan 30 13:29:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCD29C0218F for ; Thu, 30 Jan 2025 13:31:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbp-0004iC-Dl; Thu, 30 Jan 2025 08:29:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbn-0004fW-A2 for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:27 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbl-0001PK-T6 for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:27 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id EF3C15C03D9; Thu, 30 Jan 2025 13:28:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8604DC4CED2; Thu, 30 Jan 2025 13:29:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243764; bh=wtPYEkp/rYjrO4/L11LpwqkfMFGmuvFU+26iDChJ36Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QYH0APFYck0qvyHcFAYeGgGfkqI9Sdt8f7CuWaBnwPrCH36hyMoTPG5TfCMBt3vXU c1L6objD8F2RbKKVORzN8JRtcRxwXOV1ELD2dxuTvdWfyxgSZ054Ja5LdHotz42JpV yjyi8IJjgK/2U4VeCDwd8Y4l+hpltUxXLtbEHPgTnClZi3eE4HOMkGcBvncOZ8a90N mPKoAId5sbegsrEfrdyiORCCSCuv5lDy8ee3TmisHE3jR24/2PWCHRJkHwjzyxSJXT lTHY4bzgGenMWVrUdgnz3QvWShuxKvybDwI9RVOLNbX9Zw07NmCbYunXqIq+i5KMYX h2dRgwo0/t7UA== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 4/9] target/hppa: Add CPU diagnose registers Date: Thu, 30 Jan 2025 14:29:09 +0100 Message-ID: <20250130132915.16846-5-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Add the diagnose registers (%dr) to the CPUArchState. Those are mostly undocumented and control cache behaviour, memory behaviour, reset button management and many other related internal CPU things. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/machine.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index beea42d105..b858986c41 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -232,6 +232,7 @@ typedef struct CPUArchState { target_ulong cr[32]; /* control registers */ target_ulong cr_back[2]; /* back of cr17/cr18 */ target_ulong shadow[7]; /* shadow registers */ + target_ulong dr[32]; /* diagnose registers */ /* * During unwind of a memory insn, the base register of the address. diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 211bfcf640..bb47a2e689 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -198,6 +198,7 @@ static const VMStateField vmstate_env_fields[] = { VMSTATE_UINT64(iasq_b, CPUHPPAState), VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + VMSTATE_UINT64_ARRAY(dr, CPUHPPAState, 32), VMSTATE_END_OF_LIST() }; @@ -208,8 +209,8 @@ static const VMStateDescription * const vmstate_env_subsections[] = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .fields = vmstate_env_fields, .subsections = vmstate_env_subsections, }; From patchwork Thu Jan 30 13:29:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DCE9C0218A for ; Thu, 30 Jan 2025 13:31:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbr-0004iN-2W; Thu, 30 Jan 2025 08:29:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbo-0004hh-Um for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:28 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbn-0001Pa-FK for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:28 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 98B255C03F5; Thu, 30 Jan 2025 13:28:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2BA64C4CED2; Thu, 30 Jan 2025 13:29:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243766; bh=EdUmbIHS6wsR+QKUpjXCHpozaxkbBLR0Vx1ZIKvUOQA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GW2nmuwaG7u68z50KfCKJGTsZPi+mPl0vSZTHkxWya2QuMFW1iavQZqSJ4zCR0NmY Vs/H0sXg3RMcOQtEI0GNIqUQGz9dIHVdsQINLo9henL8OHRoEIX4YRmvU2uS9MVicb WRS/duEPIIO1v29/dwriY0FS6yFdy8iGJE1C0l8KJWS8IKiF0xqA/Dpgf1qHUKS084 jVLpatEBnFvCGjbQGwmGeAYAvs6xQQue128Nh+QjWpzEheFDQ1D+hOehu2RWb8tm7l 3otLger7RwcoGRk5jerBxPIjBpKGbMmRaLa84J2I5jU1weWu7992IcZYfRJoBV/uis yqQR+hXX1838g== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 5/9] target/hppa: Drop diag_getshadowregs_pa2 and diag_putshadowregs_pa2 Date: Thu, 30 Jan 2025 14:29:10 +0100 Message-ID: <20250130132915.16846-6-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in commit 3bdf20819e68 based on some analysis of ODE code, but now they conflict with the generic mfdiag/mtdiag instructions. I believe the former analysis was wrong, so remove them again. Note that all diag instructions are badly documented, so most things are based on reverse engineering and thus may be wrong. Signed-off-by: Helge Deller Fixes: 3bdf20819e68 ("target/hppa: Add diag instructions to set/restore shadow registers") Reviewed-by: Richard Henderson --- target/hppa/insns.decode | 2 -- target/hppa/translate.c | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 71074a64c1..527c453443 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -646,8 +646,6 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 # For 64-bit PA8700 (PCX-W2) - diag_getshadowregs_pa2 000101 00 0111 1000 0001 1000 0100 0000 - diag_putshadowregs_pa2 000101 00 0111 0000 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dc04f9f3c0..30fba5297a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4593,21 +4593,11 @@ static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a) return !ctx->is_pa20 && do_getshadowregs(ctx); } -static bool trans_diag_getshadowregs_pa2(DisasContext *ctx, arg_empty *a) -{ - return ctx->is_pa20 && do_getshadowregs(ctx); -} - static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) { return !ctx->is_pa20 && do_putshadowregs(ctx); } -static bool trans_diag_putshadowregs_pa2(DisasContext *ctx, arg_empty *a) -{ - return ctx->is_pa20 && do_putshadowregs(ctx); -} - static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); From patchwork Thu Jan 30 13:29:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88B5DC0218A for ; Thu, 30 Jan 2025 13:31:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbs-0004is-4r; Thu, 30 Jan 2025 08:29:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbq-0004iF-7x for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:30 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbo-0001PK-OP for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:29 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 3C86E5C05CD; Thu, 30 Jan 2025 13:28:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C83CBC4CED2; Thu, 30 Jan 2025 13:29:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243768; bh=TTZQ3gdFh6H6hJ0o3arXtbhMAP/Olm8bzx/GKUy+TWI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=go3z/Y+Y96v0V6FQYz7+I5P/d55oszu4HB5K71ZxBLUpMW7KjGxXX95PL3RU1iXi4 XKrmrYvGy+6vOMq2EVU+40u4Rm3zyOvqiYV8Muwi69n3WIDxl++HseRic1GvGaUUI/ VucfxOFlYGm08T8ZxoRp+4Mf+HdQtfnWiJu+KlX0I8AWiYgwiniKopvj+Qfziwz8o5 ShtcnAoDfXlURLlEZHnMF7vDQHm4doRP9jmqc8YVxIE9yXP3gpOX5leRPiG2BQfU9R Ji2ujXsHKv5quUDTgv226+sfTPH65GbxgsybYqBfTNBlEd173JLvQmEIC4KlJi1nIK ilUQ1Tot2JMqw== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 6/9] target/hppa: Add instruction decoding for mfdiag and mtdiag Date: Thu, 30 Jan 2025 14:29:11 +0100 Message-ID: <20250130132915.16846-7-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag instructions which modify the diagnose registers. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/insns.decode | 4 ++++ target/hppa/translate.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 527c453443..4eaac750ea 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -644,8 +644,12 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 # For 32-bit PA-7300LC (PCX-L2) diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 + diag_mfdiag 000101 dr:5 rt:5 0000 0110 0000 0000 + diag_mtdiag 000101 dr:5 r1:5 0001 0110 0000 0000 # For 64-bit PA8700 (PCX-W2) + diag_mfdiag 000101 dr:5 0 0000 0000 1000 101 rt:5 + diag_mtdiag 000101 dr:5 r1:5 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 30fba5297a..7b9d3deb39 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4598,6 +4598,26 @@ static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) return !ctx->is_pa20 && do_putshadowregs(ctx); } +static bool trans_diag_mfdiag(DisasContext *ctx, arg_diag_mfdiag *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + TCGv_i64 dest = dest_gpr(ctx, a->rt); + tcg_gen_ld_i64(dest, tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + save_gpr(ctx, a->rt, dest); + return nullify_end(ctx); +} + +static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + return nullify_end(ctx); +} + static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); From patchwork Thu Jan 30 13:29:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADCDEC0218A for ; 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d=kernel.org; s=k20201202; t=1738243769; bh=UThlWjqG888IPofGfuoGum5DaEYXPS/+ciipEBddP2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dk5RNJ9Z8HlrPmxdPlGy3+2tUes2nDK1WEgHRvM2e15hIK822GDRL+zO3ZhS+fArO IV5aFZPm2YuRtmbkJCRz/po7gKEDONumZId9vpuhRnKimrKLyOkfB58ftSA/JDBz5B Xz4Qqt+qXok5yple/wj5DR2MYuYKCIiQo7k36BIO9lY8Ysh0N0jCAcbxwYDpMnCwja SA4KscMvP5zQyvMHDtxIumtfhAHE/zH3OTUsLYc1QDIt6QYwmHdnU/GO3EN318utqb msORvLBk6bxQaYiemrpgJRcu9YG9eUcN/vrIqgTw6RWeawYOTg0RSg9H6JAN+O1rDD PAvhE1Fstpwrw== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 7/9] target/hppa: 64-bit CPUs start with space register hashing enabled Date: Thu, 30 Jan 2025 14:29:12 +0100 Message-ID: <20250130132915.16846-8-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Turn on space register hashing for 64-bit CPUs when reset. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4..c86f9190d2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,6 +28,7 @@ #include "exec/translation-block.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" +#include "hw/hppa/hppa_hardware.h" static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -217,6 +218,10 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); cpu_hppa_loaded_fr0(env); + + /* 64-bit machines start with space-register hashing enabled in %dr2 */ + env->dr[2] = hppa_is_pa20(env) ? HPPA64_DIAG_SPHASH_ENABLE : 0; + cpu_hppa_put_psw(env, PSW_M); } From patchwork Thu Jan 30 13:29:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13954605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B854DC0218A for ; Thu, 30 Jan 2025 13:31:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdUbw-0004jm-SG; Thu, 30 Jan 2025 08:29:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbv-0004jY-Cd for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:35 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdUbt-0001QM-7a for qemu-devel@nongnu.org; Thu, 30 Jan 2025 08:29:34 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id D9093A40C33; Thu, 30 Jan 2025 13:27:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1812CC4CEE0; Thu, 30 Jan 2025 13:29:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738243771; bh=BYfsk9mjOAfmii9ee7cXUGYp4P96i++oFF3tclaK0Jw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QHorGZhTOJqX7Q77lgz9La0P/5CbtJ2aLEGeJo8SIWNWqSdLfnS45ZFZxc1C7c+8b wsAnYO+Bi9o5cVjfZ8KLI66KgBMc0ZKHeCrgUrNdxwDID5Ngg01x9S56NM4vPdlX0K M9s8fTA5V68RaU5ZcjDiR/4jXN2f5QnDzdwL1heS1pV6KyycmeJ/KAoU+5eZigxVuy XMhl5Neo9pZ3XB1sn9MAQIM6cixUkASgRSIn5Advu1gelNJr1LrHKJBfBpxHJNfxNQ plYKBaI7Sy6u8ZRNO6TaNgXfM8HGCbKC7na3JcpLoL3Rgs+8+QfY10S9sjcUTHQ3xE iA9KMv0roXHTg== From: deller@kernel.org To: qemu-devel@nongnu.org, Stefan Hajnoczi , Richard Henderson , Peter Maydell Cc: deller@gmx.de Subject: [PULL 8/9] target/hppa: Implement space register hashing for 64-bit HP-UX Date: Thu, 30 Jan 2025 14:29:13 +0100 Message-ID: <20250130132915.16846-9-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250130132915.16846-1-deller@kernel.org> References: <20250130132915.16846-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The Linux kernel turns space-register hashing off unconditionally at bootup. That code was provided by HP at the beginning of the PA-RISC Linux porting effort, and I don't know why it was decided then why Linux should not use space register hashing. 32-bit HP-UX versions seem to not use space register hashing either. But for 64-bit HP-UX versions, Sven Schnelle noticed that space register hashing needs to be enabled and is required, otherwise the HP-UX kernel will crash badly. On 64-bit CPUs space register hashing is controlled by a bit in diagnose register %dr2. Since we want to support Linux and 32- and 64-bit HP-UX, we need to fully emulate the diagnose registers and handle specifically the bit in %dr2. This patch adds the code to calculate the gva memory mask based on the space-register hashing bit in %dr2 and the PSW_W (64-bit) flag. The value is cached in the gva_offset_mask variable in CPUArchState and recalculated at every modification of the CPU PSW or %dr2. Signed-off-by: Helge Deller Suggested-by: Sven Schnelle Suggested-by: Richard Henderson Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 9 +++++++-- target/hppa/cpu.h | 20 ++++++++------------ target/hppa/helper.c | 25 +++++++++++++++++++++++-- target/hppa/helper.h | 1 + target/hppa/int_helper.c | 10 ++++++---- target/hppa/mem_helper.c | 5 +++++ target/hppa/sys_helper.c | 4 ++-- target/hppa/translate.c | 10 +++++++++- 8 files changed, 61 insertions(+), 23 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c86f9190d2..5655677431 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -45,8 +45,9 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) { CPUHPPAState *env = cpu_env(cs); - return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); + return hppa_form_gva_mask(env->gva_offset_mask, + (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, @@ -91,6 +92,10 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, & (env->sr[4] == env->sr[7])) { flags |= TB_FLAG_SR_SAME; } + if ((env->psw & PSW_W) && + (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE)) { + flags |= TB_FLAG_SPHASH; + } #endif *pcsbase = cs_base; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index b858986c41..7be4a1d380 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -223,6 +223,7 @@ typedef struct CPUArchState { target_ulong psw_cb; /* in least significant bit of next nibble */ target_ulong psw_cb_msb; /* boolean */ + uint64_t gva_offset_mask; /* cached address mask based on PSW and %dr2 */ uint64_t iasq_f; uint64_t iasq_b; @@ -320,27 +321,20 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb, #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU -static inline uint64_t gva_offset_mask(target_ulong psw) -{ - return (psw & PSW_W - ? MAKE_64BIT_MASK(0, 62) - : MAKE_64BIT_MASK(0, 32)); -} - -static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, - target_ulong off) +static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask, + uint64_t spc, target_ulong off) { #ifdef CONFIG_USER_ONLY - return off & gva_offset_mask(psw); + return off & gva_offset_mask; #else - return spc | (off & gva_offset_mask(psw)); + return spc | (off & gva_offset_mask); #endif } static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, target_ulong off) { - return hppa_form_gva_psw(env->psw, spc, off); + return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); @@ -354,6 +348,7 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 +#define TB_FLAG_SPHASH 0x800 #define CS_BASE_DIFFPAGE (1 << 12) #define CS_BASE_DIFFSPACE (1 << 13) @@ -362,6 +357,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); +void update_gva_offset_mask(CPUHPPAState *env); void cpu_hppa_loaded_fr0(CPUHPPAState *env); #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d4b1a3cd5a..ac7f58f0af 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" +#include "hw/hppa/hppa_hardware.h" target_ulong cpu_hppa_get_psw(CPUHPPAState *env) { @@ -59,6 +60,22 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) return psw; } +void update_gva_offset_mask(CPUHPPAState *env) +{ + uint64_t gom; + + if (env->psw & PSW_W) { + gom = (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE) + ? MAKE_64BIT_MASK(0, 62) & + ~((uint64_t)HPPA64_PDC_CACHE_RET_SPID_VAL << 48) + : MAKE_64BIT_MASK(0, 62); + } else { + gom = MAKE_64BIT_MASK(0, 32); + } + + env->gva_offset_mask = gom; +} + void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { uint64_t reserved; @@ -98,6 +115,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) cb |= ((psw >> 9) & 1) << 8; cb |= ((psw >> 8) & 1) << 4; env->psw_cb = cb; + + update_gva_offset_mask(env); } void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) @@ -133,9 +152,11 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", env->iasq_f >> 32, w, m & env->iaoq_f, - hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_mask(env->gva_offset_mask, env->iasq_f, + env->iaoq_f), env->iasq_b >> 32, w, m & env->iaoq_b, - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); + hppa_form_gva_mask(env->gva_offset_mask, env->iasq_b, + env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/helper.h b/target/hppa/helper.h index de411923d9..8369855d78 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -99,6 +99,7 @@ DEF_HELPER_FLAGS_2(ptlb_l, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tl, env, tl) DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_1(update_gva_offset_mask, TCG_CALL_NO_RWG, void, env) DEF_HELPER_1(diag_btlb, void, env) DEF_HELPER_1(diag_console_output, void, env) #endif diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 58695def82..7d48643bb6 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -94,11 +94,12 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; int i = cs->exception_index; - uint64_t old_psw; + uint64_t old_psw, old_gva_offset_mask; /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); + old_gva_offset_mask = env->gva_offset_mask; /* step 2 -- Note PSW_W is masked out again for pa1.x */ cpu_hppa_put_psw(env, @@ -112,9 +113,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) */ if (old_psw & PSW_C) { env->cr[CR_IIASQ] = - hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32; + hppa_form_gva_mask(old_gva_offset_mask, env->iasq_f, env->iaoq_f) >> 32; env->cr_back[0] = - hppa_form_gva_psw(old_psw, env->iasq_b, env->iaoq_b) >> 32; + hppa_form_gva_mask(old_gva_offset_mask, env->iasq_b, env->iaoq_b) >> 32; } else { env->cr[CR_IIASQ] = 0; env->cr_back[0] = 0; @@ -165,7 +166,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) if (old_psw & PSW_C) { int prot, t; - vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); + vaddr = hppa_form_gva_mask(old_gva_offset_mask, + env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, 0, 0, &paddr, &prot); if (t >= 0) { diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b8c3e55170..304f0b61e2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -824,3 +824,8 @@ uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f) } return iaoq_f; } + +void HELPER(update_gva_offset_mask)(CPUHPPAState *env) +{ + update_gva_offset_mask(env); +} diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index da5b569de8..052a6a88a2 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -73,7 +73,7 @@ target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm) * machines set the Q bit from 0 to 1 without an exception, * so let this go without comment. */ - env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + cpu_hppa_put_psw(env, (psw & ~PSW_SM) | (nsm & PSW_SM)); return psw & PSW_SM; } @@ -88,7 +88,7 @@ void HELPER(rfi)(CPUHPPAState *env) * To recreate the space identifier, remove the offset bits. * For pa1.x, the mask reduces to no change to space. */ - mask = gva_offset_mask(env->psw); + mask = env->gva_offset_mask; env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7b9d3deb39..e9ef171418 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { /* IAOQ_Front at entry to TB. */ uint64_t iaoq_first; + uint64_t gva_offset_mask; DisasCond null_cond; TCGLabel *null_lab; @@ -1577,7 +1578,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, *pofs = ofs; *pgva = addr = tcg_temp_new_i64(); tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, - gva_offset_mask(ctx->tb_flags)); + ctx->gva_offset_mask); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); @@ -4615,6 +4616,12 @@ static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) nullify_over(ctx); tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, offsetof(CPUHPPAState, dr[a->dr])); + if (ctx->is_pa20 && (a->dr == 2)) { + /* Update gva_offset_mask from the new value of %dr2 */ + gen_helper_update_gva_offset_mask(tcg_env); + /* Exit to capture the new value for the next TB. */ + ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; + } return nullify_end(ctx); } @@ -4635,6 +4642,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); + ctx->gva_offset_mask = cpu_env(cs)->gva_offset_mask; #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER;