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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 01/14] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Date: Thu, 30 Jan 2025 18:22:56 +0000 Message-Id: <20250130182309.717346-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The access pseudocode for the CNTPS_TVAL_EL1, CNTPS_CTL_EL1 and CNTPS_CVAL_EL1 secure timer registers says that they are UNDEFINED from EL2 or NS EL1. We incorrectly return CP_ACCESS_TRAP from the access function in these cases, which means that we report the wrong syndrome value to the target EL. Use CP_ACCESS_TRAP_UNCATEGORIZED, which reports the correct syndrome value for an UNDEFINED instruction. Cc: qemu-stable@nongnu.org Fixes: b4d3978c2fd ("target-arm: Add the AArch64 view of the Secure physical timer") Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 40bdfc851a5..c5245a20aaf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2385,7 +2385,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, switch (arm_current_el(env)) { case 1: if (!arm_is_secure(env)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_UNCATEGORIZED; } if (!(env->cp15.scr_el3 & SCR_ST)) { return CP_ACCESS_TRAP_EL3; @@ -2393,7 +2393,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, return CP_ACCESS_OK; case 0: case 2: - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_UNCATEGORIZED; case 3: return CP_ACCESS_OK; default: From patchwork Thu Jan 30 18:22:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA0C3C0218A for ; Thu, 30 Jan 2025 18:24:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCE-0003ri-DH; Thu, 30 Jan 2025 13:23:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZC9-0003qO-Rj for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:18 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZC7-0000Tq-Vl for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:17 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385ef8b64b3so1069496f8f.0 for ; Thu, 30 Jan 2025 10:23:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261393; x=1738866193; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wlns9GOwYM2bjd4U7krW4vEiipIfGOqidyiNeaIvOXs=; b=EVTh20+C8LgriR1TaEM6c+RgLSLMhFHYtKSLu6k+G5b4Q/WspNkpXfL8r2WAvuRMEq EmrIMOLuAu+CxsND4ogv2frGW2e8xS75QeCwVOjHoKgtM0UEitlqIkNCkJRDiSgqL69C eco/BNgx2oKmqclPWrAUxNWm6pztpvL6XOeayVJNYva3MbtliRLxlQCuLhiQTeVga3pf f6TA+5wTc/Q3LZEVb5nzRb/t9E4sSlgzzBfHVcU6ZoiUiGWgLkm7SVCI7Lr/BjS/sAv+ PF6lLT6SLPuOmUyh+p8lKerdFwo2jJQFF0UB5OngA4HOzjr+xpSGR2GOHf4kTghOIDUb ATuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261393; x=1738866193; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wlns9GOwYM2bjd4U7krW4vEiipIfGOqidyiNeaIvOXs=; b=eBom7BFhkP3RhFqbg9AsfRzeWScx4RJ4dC6tGORTW3hqA883HpJIxJWqIInViy9Umd 5FsizDDROVSB9rfadefFfAIouLExEqNZ5MyYufRYHTN+KJLnbnx7sF9t4jcRc4PbGYQT MMjp9FGnqgeGTwQy5f7kza8rT/Rv7W1kM7r1hT/IEKLHeu+vKhnPAXfVhCmOSykwNMPS IF0FtSdstYRxmHm+5GNemKHSR81kSBoRGy0+GeUKP5KISM61iPIaSoIVnlIDxvF2Sg6L S9H68orMaXw4wGJEUNq8kJaPHt5YL8s7oxDIUsNOd1nlTjgurywVjW2M1bn8szrouJeX uHPQ== X-Forwarded-Encrypted: i=1; AJvYcCX29tvHuWcjgJyQNJ5sZ6GyDZKYboYvHsUy9tDlSlkEF3vo/rO/VrT439jF6nCTmmespexGqpsOgwle@nongnu.org X-Gm-Message-State: AOJu0Yx/aMXRCXEe6nsLUXUbNMH0X6NQwQR55GxWmqYsnfaArN0xJOGp 0tgh1dIWDV2mwDRynghy3lgyNnF7hdaTAW312c3FCMKlSpffQPSjaaXrBk4T5vA= X-Gm-Gg: ASbGncsUf5GGz8uuQ5u3D4FEXOim0ZtIXXfghkLSFlUQoIIylje6HCBGkwi+Jxq3XUi DcO9+/PNnEvpGHKsBYEweydXdAant7WGjRErYgJs3Yr2XApqaoURpegjvD+IkD5M9CtijSSHEpm 2hMW+YkV3bVMMpsbr1DxHLqTvUYtReOQnU+gBcq8cQz7IJQ/n88nkohNHt+ZAr3gN5zNFCBuciO yEcY3P70OtAPpNPT6HhVaBiciunOu4RvTK/6GUPu4dIb81X4Ueqvssr52Ct+S6SN2EEkXqHIxXc jNjqJf8I3GF7f5oPswkVmQ== X-Google-Smtp-Source: AGHT+IE2UbAKKT+ZDLAy0oJBJeXaNOHA7u6S1jdHO0APO9zbbJCdTYWh7roiFyRaiIozYNmO+XvbdQ== X-Received: by 2002:a05:6000:4023:b0:385:fa26:f0d9 with SMTP id ffacd0b85a97d-38c516583aamr7804506f8f.0.1738261393493; Thu, 30 Jan 2025 10:23:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:12 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 02/14] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Date: Thu, 30 Jan 2025 18:22:57 +0000 Message-Id: <20250130182309.717346-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org R_NYXTL says that these AT insns should be UNDEFINED if they would operate on an EL lower than EL3 and SCR_EL3.{NSE,NS} is set to the Reserved {1, 0}. We were incorrectly reporting them with the wrong syndrome; use CP_ACCESS_TRAP_UNCATEGORIZED so they are reported as UNDEFINED. Cc: qemu-stable@nongnu.org Fixes: 1acd00ef1410 ("target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions") Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c5245a20aaf..7ddeed0283f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3601,7 +3601,7 @@ static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, * scr_write() ensures that the NSE bit is not set otherwise. */ if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_UNCATEGORIZED; } return CP_ACCESS_OK; } From patchwork Thu Jan 30 18:22:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CB19C02193 for ; Thu, 30 Jan 2025 18:24:14 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCN-0003wW-GD; Thu, 30 Jan 2025 13:23:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCB-0003qk-2t for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:19 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZC8-0000U5-0w for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:18 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-436281c8a38so8512805e9.3 for ; Thu, 30 Jan 2025 10:23:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261394; x=1738866194; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2HabG4XQXFtTl/vZ0C82NDKUjYubip/tkWdtm1VvavA=; b=A7S4BPxHi0hL7F4tib8FPyP6ETLSvBBdg14iA1nsFaJ9qSEhWH2vmeg/rvTqHQMMn5 PS8dF+T1iypxancQY2Tn4HcZ0W7G39Qu/RaVuknWj9UK+gfTLpkt4Rva4hmAQRMstJEV xP4/L3gykq14K0/IeQYDaTjBKxOdmv48UC4nIDXfAOcjNHXNWMZsEJSXwmgJHi2pd9Qk MaEYVRmBhUJTO83W2rkd3eXOtCb/x/7KbN5UsDPmR+ZHQMp0SlXKhmcE0hVmrfcMfEdM y9IXWPzz4BjHNE92xQPnPm3KbNmA/h7exDwaLlzBXrYdRAzHlPwrrv6DZ42X0UK2SaK1 P+0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261394; x=1738866194; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2HabG4XQXFtTl/vZ0C82NDKUjYubip/tkWdtm1VvavA=; b=uBP0c2tkTxQR+cdmpOSBQzJNJTSlQNs5rvj/JIbchpsS8EVxhUvemWva9KaXPYVeIU ijMyw+W8FGAmyZEhr1COOMU89eFl9wH0CcuYEuTgb9rXhCsSJV4OsxQPKw/7IXGCi61U cJZM+iKLpNhRMfrQQNbDRcUTo6YgLFld87fKb3DC3iwXaAPcYdR6rc8mC+XNenz+80+e mAdHW5TmxLzxA6nIUV0Jj/qf7u2Jvsfcp5wH0tvO6e9qAuTzXxmqzMZDH9XLk22yb1B7 CJs1LP9yfb+f39VP2od8MxDqbJwvo76aT9lR5JRsnVDwvC7M7qggnbs7HNN3/BT84I9e RmWQ== X-Forwarded-Encrypted: i=1; AJvYcCUoDFZTh3IsFZxsxqLKUpSCPeAxlf7+WaWGjw+/CTgp8/VoMtrvW7MV0Axbc1DrKyGmcxo6Br2j1zNS@nongnu.org X-Gm-Message-State: AOJu0Yw5cC3BZ4ZqjTR6a7heL1bMjuxf8DxUZT9iGPK3XLL/Lb1SUBzs EoasrU1oJLXKieA8vEavw/IbvMn5KnlgDLJYzx584Zu0dFcdgbfroHdhJljWLqY= X-Gm-Gg: ASbGncuaQyYFp4GynEzrbwsFpv4n2b4VCkTA0yHl0ULin2UUMh2nt+sPaRNnwMAsSeo HVOuFlAshS0F4eZVf+3UDcmDDTpx4pZh86poq2YT3adLXJIujb8CSedsyDPfEKlVb1yk9TA87a/ tXkums7752S3qZgTGf5x4xXUv79EULSWSJdpt5kDg5rIXPU9H8+t7mjBvn/T30mGUXJRya1ycEi sejl6t/2B6tb3WkV3NmQBx4rNd6Rx0WJ2KLcd7yrDTc/mm9NgqQ61ZORT0s0kcV08kZ9FJBn3ey RK2ExCsALzixyN+2N3dptA== X-Google-Smtp-Source: AGHT+IGHWLRAr6UvyG5tkm3LNlD+rT9SlJQAJnIc0AxKJlDbszY93/3OUUNruL8dn9B3fuEhIAZdWA== X-Received: by 2002:a5d:6d86:0:b0:38b:ef22:d8c3 with SMTP id ffacd0b85a97d-38c5209395cmr9473926f8f.35.1738261394371; Thu, 30 Jan 2025 10:23:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:13 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 03/14] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Date: Thu, 30 Jan 2025 18:22:58 +0000 Message-Id: <20250130182309.717346-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The pseudocode for AT S1E2R and AT S1E2W says that they should be UNDEFINED if executed at EL3 when EL2 is not enabled. We were incorrectly using CP_ACCESS_TRAP and reporting the wrong exception syndrome as a result. Use CP_ACCESS_TRAP_UNCATEGORIZED. Cc: qemu-stable@nongnu.org Fixes: 2a47df953202e1 ("target-arm: Wire up AArch64 EL2 and EL3 address translation ops") Signed-off-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7ddeed0283f..74b556b6766 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3611,7 +3611,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, { if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_UNCATEGORIZED; } return at_e012_access(env, ri, isread); } From patchwork Thu Jan 30 18:22:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27575C0218A for ; Thu, 30 Jan 2025 18:25:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCQ-0003xI-EN; Thu, 30 Jan 2025 13:23:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCC-0003rV-7X for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:20 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZC8-0000UM-UM for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:19 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4368a293339so13216945e9.3 for ; Thu, 30 Jan 2025 10:23:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261395; x=1738866195; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9XVL1wlKsZQPV2VNsPNKghCDpbJZsLxmzWGbgwthcyk=; b=HWEY1YVP5vMFrNQ1SNjolJS2OFUUobKn2gJiUMxddHwEgLt4KdqfyxVbVDSdMnJoPX M3Od75YN9MZUhbTgB2Cbk0ZD4CYqr6/I8RLcxxkbD/n0QWoJYvNmO+oKSiweaVwUdJjl igic4PAl7wUrFDdDLUGOshVZMIk9MjITrZNQJSf6GYEE6mtsqLb0cReIh/bhX1IXwS4P qhVFdgCJAOt+LbzQompv7FLdv7timFEQfmxfkIANB/V43ebyU4ZYBWoRtX8V+YL4kwgq 0OOVnfiZ8qBjWUtk6F8eUebKV96wOyc89wPPNeUIuHPyTq2HnUeI41b2rc6izbr+iHpp laYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261395; x=1738866195; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9XVL1wlKsZQPV2VNsPNKghCDpbJZsLxmzWGbgwthcyk=; b=PaU2ujM/H3a+JsC44vlMq0YYIVlQiGXtlHPjXuUmPQZVNWsaFi0ldS3oSc466bkgWW U128Efl60RVwcChE2+RSn7peaCLfGsvPXQs1zgPPxoJFw4IflKEC/YL5ilMzhfSnV5cV JqR+laFPhltLug4hKOi0YTjnak0rOrbjpzfXCYXrk1R5B7D9nn06MD4/+gaYLGhjf0si xcnntjaFhDzAkeWzl+OJ2lV1N7gCs8gCqktwsKY7VHfslZkj9z1oIr+ulXVcmrW93UBl GCBaTcT7Q5qkCrdQiJwqsVZ6Mtjk0FdYSb+TQbJmzGm5MGRU0OsFylP8LTPJfqGHrvSI aPWw== X-Forwarded-Encrypted: i=1; AJvYcCX3jCvlFIMzknrC0pjliAPlN1Q1K5tNyMkQRUSJvSEbv1NDtS+1kd9UvUQSHWiH5hW12CT8S3mww0L0@nongnu.org X-Gm-Message-State: AOJu0YxTltDHXRI8DwFdgufYtJ0+mwBG8aAlO45fDfEg+yp58eHlt4j1 w3ooabMuR9EiGUJmrK+m/8JcxGuZmcEDBFiq+JiEtkMftE6Mlt8O3VFGeUV3amA= X-Gm-Gg: ASbGncu9MvbwiuLEPXlgkZQIjpA+EMGDWgtXVbJBLDkUwNIvWJX+IxDCEWVrM6oxpN/ lIWfAi4wDNUGa9l6gf9IauJFXz2j1DE9LGnhomOX0iDgZMppTGfGWcYIkuAcvm9qYeJhQi6AzHq IKXKdnftauSiLqyFD9jxLl8TRK7uTifmUqeu0nlDaRv5BMxiC/tX636JjjwqmOxRdPgRY0DVWB9 J9WUddo2nrH/gl8K+4OvufISdrq8pSwf+IYsnEsExuKF07NAG4G4aUCW1gtJRNwYii1XNO0l1li GXpwLznz6P/wFj4nYdenhA== X-Google-Smtp-Source: AGHT+IFEl4mBtaDwDRKh+R7ZNm0NJQGZd+X2Nd39Y7GBdCSES7z22sohAmIx6YE8+sjAuWJkmujg8g== X-Received: by 2002:a05:6000:1862:b0:38c:5d42:1528 with SMTP id ffacd0b85a97d-38c5d4218cemr2970194f8f.40.1738261395345; Thu, 30 Jan 2025 10:23:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:14 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 04/14] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Date: Thu, 30 Jan 2025 18:22:59 +0000 Message-Id: <20250130182309.717346-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The pseudocode for the accessors for the LOR sysregs says they are UNDEFINED if SCR_EL3.NS is 0. We were reporting the wrong syndrome value here; use CP_ACCESS_TRAP_UNCATEGORIZED. Cc: qemu-stable@nongnu.org Fixes: 2d7137c10faf ("target/arm: Implement the ARMv8.1-LOR extension") Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 74b556b6766..5d9eca35c04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6750,8 +6750,8 @@ static CPAccessResult access_lor_other(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { if (arm_is_secure_below_el3(env)) { - /* Access denied in secure mode. */ - return CP_ACCESS_TRAP; + /* UNDEF if SCR_EL3.NS == 0 */ + return CP_ACCESS_TRAP_UNCATEGORIZED; } return access_lor_ns(env, ri, isread); } From patchwork Thu Jan 30 18:23:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E06ACC02193 for ; Thu, 30 Jan 2025 18:25:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCS-0003yF-4o; Thu, 30 Jan 2025 13:23:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCE-0003sD-50 for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:22 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCA-0000Ua-Ab for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:20 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-38a8b35e168so719154f8f.1 for ; Thu, 30 Jan 2025 10:23:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261397; x=1738866197; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PQ3INqN7YHVgBd+O3rmiUMiDsje4n5n7QZ4vk3TY7Qg=; b=adPNNor4Zl2AIbZ0M3hbvRhjIJIKL/81vd7CL4Avcqu4lXaFKxVzKDlx8D7y/uEmnB PTv+31bPpd5eewclFdbrGCPpdSdAw0NezTPrh9T0+cSpuUoQGaFi3U/a4oRg/QjvVKaT sTxqU0R8Adnzx86PQ/xY/S2Vv68a3gCumb6j9DJxO0K1kRLCZ5KO/5iXmW4Mlatk/fZu vgemYuO0p+v3lCajnC7YOL8mba+dRHFSEf5MATNARx0qAAp84a52egRlYjBbUq/H8oUq US2gVbt1VXNT5A2mLb4O/igPn0NM8plGDwMcfsPqRykE04QwykAlYhnf8vK+eDVQliAs XTVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261397; x=1738866197; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQ3INqN7YHVgBd+O3rmiUMiDsje4n5n7QZ4vk3TY7Qg=; b=rpdLc56yXVotH0Vs8EyiBTN9GFD7hhOlsp/upIr3CxXhvRJ16HXsjLylX3ByTN17ZD 8YPKF5LB1Ebpr7hMIw2ACitxxVi6WMBj6yY5uyjefsLy0X6rjiG/ct56ijzod7kccAek Sn8sB4k4F+bgndOtdNZCRlSxiS5k6DBz+tQWaetT7xqDhz3eBYBV9N3dHiBdSDhnAcgg bQuhB1NTdRt7MFGCqA+4dxU/4TQWFsmU+bvfYDFvLnIzv299qWsEB1wmYljWo0Y4hoiu yTNADoeGoP0LQvA/eGCHQ4NbXNdo5c2KmECIyxCsr96fZUmMJpRNY93svW1fb5QMcNjw m91Q== X-Forwarded-Encrypted: i=1; AJvYcCV2iIt0UaTqeaUCgBwZ5+CtPgcLSHI1S4krZi+TL5ktIhbj402XsR6Fd3pobM2sBOJEBB4vUyU85hW2@nongnu.org X-Gm-Message-State: AOJu0YzoGCNtLBT82I+z4BsOKgo2NdIEh4Q8x3EWZLhXrAzs3VfJO3BO i2ULKC3hTVvICXesf3/pOJEoYv/Wl6vOWwr4V+PaUBazlgtsA5Mh6lAEL0ym5Mg= X-Gm-Gg: ASbGncuKewgSoGnpeI1yg6ps1BhX84Ewbjfk5dZdLn78MFg95gBDkewLdBD/etSTyx7 Afz1ex152mYOQoJlRkl2PX34LfdBbqHrNNas6QO5u4c43zviMzeB/Y/nL+4yaYij2S3fmCLPRWc 6+8hdZV0p0CofOpxJ6bBNDr+i3ytD7n7evXaZj0CfsjDWJY6YkWSnlsbgYIwytMHKWMJCNN2uOV 05bXyPZJk9pjtArmunse6vLjj+T5Cq6r8+3cQDdplUTYicMIx+xvne/PXzwFVaGc/dH6S05Fsg2 6AJtkZv7M3JYZ7sA06jwxA== X-Google-Smtp-Source: AGHT+IFk46o9MJfRxDQ5fp1zop2gX0pBdlLuXLQqomMqheDgghI/upyTVaZIVnOv9Ncrv7Wp4oLxvQ== X-Received: by 2002:a05:6000:1fae:b0:38a:a019:30dd with SMTP id ffacd0b85a97d-38c5a96f0b7mr3987385f8f.8.1738261396692; Thu, 30 Jan 2025 10:23:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:15 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 05/14] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Date: Thu, 30 Jan 2025 18:23:00 +0000 Message-Id: <20250130182309.717346-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In system register access pseudocode the common pattern for AArch32 registers with access traps to EL3 is: at EL1 and EL2: if HaveEL(EL3) && !ELUsingAArch32(EL3) && (SCR_EL3.TERR == 1) then AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && (SCR.TERR == 1) then AArch32.TakeMonitorTrapException(); at EL3: if (PSTATE.M != M32_Monitor) && (SCR.TERR == 1) then AArch32.TakeMonitorTrapException(); (taking as an example the ERRIDR access pseudocode). This implements the behaviour of (in this case) SCR.TERR that "Accesses to the specified registers from modes other than Monitor mode generate a Monitor Trap exception" and of SCR_EL3.TERR that "Accesses of the specified Error Record registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception". In QEMU we don't implement this pattern correctly in two ways: * in access_check_cp_reg() we turn the CP_ACCESS_TRAP_EL3 into an UNDEF, not a trap to Monitor mode * in the access functions, we check trap bits like SCR.TERR only when arm_current_el(env) < 3 -- this is correct for AArch64 EL3, but misses the "trap non-Monitor-mode execution at EL3 into Monitor mode" case for AArch32 EL3 In this commit we fix the first of these two issues, by making access_check_cp_reg() handle CP_ACCESS_TRAP_EL3 as a Monitor trap. This is a kind of exception that we haven't yet implemented(!), so we need a new EXCP_MON_TRAP for it. This diverges from the pseudocode approach, where every access check function explicitly checks for "if EL3 is AArch32" and takes a monitor trap; if we wanted to be closer to the pseudocode we could add a new CP_ACCESS_TRAP_MONITOR and make all the accessfns use it when appropriate. But because there are no non-standard cases in the pseudocode (i.e. where either it raises a Monitor trap that doesn't correspond to an AArch64 SystemAccessTrap or where it raises a SystemAccessTrap that doesn't correspond to a Monitor trap), handling this all in one place seems less likely to result in future bugs where we forgot again about this special case when writing an accessor. (The cc of stable here is because "hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3" which is also cc:stable will implicitly use the new EXCP_MON_TRAP code path.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.c | 11 +++++++++++ target/arm/tcg/op_helper.c | 13 ++++++++++++- 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2213c277348..4cb672c120b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -62,6 +62,7 @@ #define EXCP_NMI 26 #define EXCP_VINMI 27 #define EXCP_VFNMI 28 +#define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d9eca35c04..c5cd27b249f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9684,6 +9684,7 @@ void arm_log_exception(CPUState *cs) [EXCP_NMI] = "NMI", [EXCP_VINMI] = "Virtual IRQ NMI", [EXCP_VFNMI] = "Virtual FIQ NMI", + [EXCP_MON_TRAP] = "Monitor Trap", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { @@ -10250,6 +10251,16 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) mask = CPSR_A | CPSR_I | CPSR_F; offset = 0; break; + case EXCP_MON_TRAP: + new_mode = ARM_CPU_MODE_MON; + addr = 0x04; + mask = CPSR_A | CPSR_I | CPSR_F; + if (env->thumb) { + offset = 2; + } else { + offset = 4; + } + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 1161d301b71..1ba727e8e9f 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -758,6 +758,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); CPAccessResult res = CP_ACCESS_OK; int target_el; + uint32_t excp; assert(ri != NULL); @@ -851,8 +852,18 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, } fail: + excp = EXCP_UDEF; switch (res & ~CP_ACCESS_EL_MASK) { case CP_ACCESS_TRAP: + /* + * If EL3 is AArch32 then there's no syndrome register; the cases + * where we would raise a SystemAccessTrap to AArch64 EL3 all become + * raising a Monitor trap exception. (Because there's no visible + * syndrome it doesn't matter what we pass to raise_exception().) + */ + if ((res & CP_ACCESS_EL_MASK) == 3 && !arm_el_is_aa64(env, 3)) { + excp = EXCP_MON_TRAP; + } break; case CP_ACCESS_TRAP_UNCATEGORIZED: /* Only CP_ACCESS_TRAP traps are direct to a specified EL */ @@ -888,7 +899,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, g_assert_not_reached(); } - raise_exception(env, EXCP_UDEF, syndrome, target_el); + raise_exception(env, excp, syndrome, target_el); } const void *HELPER(lookup_cp_reg)(CPUARMState *env, uint32_t key) From patchwork Thu Jan 30 18:23:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D30E5C0218A for ; Thu, 30 Jan 2025 18:26:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCV-0003zv-5q; Thu, 30 Jan 2025 13:23:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCD-0003sC-Q9 for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:22 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCB-0000Ux-Hc for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:21 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-386329da1d9so599799f8f.1 for ; Thu, 30 Jan 2025 10:23:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261398; x=1738866198; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g/yslxnxwmm+HysZz/dpCshf9VmwSsaLGb2pE27kvDY=; b=a8OBTjezU7okXZvHSYcaB4Bkmw+FagzKHkAHWhxfuZEdJvjPJzacePdDe4G746ElNa cM0WtwHPU61gmngxWdmmWN7JxRNP879BfmH1K/ZDWhq7q/2fSVyLpDta8ZbEOYIo5izB O6orOVU/4FT9+7YFDPu6upufebfehxXl/rC2C9/ExKYNBD4Cg3jFMVl47UPLKd2IgCTh nGBqFzNKQLal8XMgMb6Szmtf8mtFLhdRTGH5rDKIQ5NF54H2YdH25v9xFWUySVQaizRL Hy0UwAvF3bDW364Y4APij/7xpBOBJYOmMJVn0tyf359GmiBwzWOYQnrXF+3/Bfh0at2Q sK4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261398; x=1738866198; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g/yslxnxwmm+HysZz/dpCshf9VmwSsaLGb2pE27kvDY=; b=uubVfGdDFu1u51YG5I3lejIi6XqFhckSDEjSIV6fnZ8DMdt+h/2N17Z/JnxE9QfcYr JQ1jdqqftxMYheg1+IVh0jqyWeK+USHlNZ3PUD5NMRBabbhhAY5QjBsvGAylymkglvm7 UaeKhQFNYC/4w+U7PUgkjgQuPkyCLMAueKDaiIe4ST9ZQOr2gEhK3U7WLCigLr+0jp/q nKKTJqSwduziDI7OthLeMM/Nh08AQ6uLnweMgRLvAGKaLZxRW17PUgsSjqrS5P3HzYfQ gVRAmVM+WkznYiNgHZcJlDS3ijsOAIPuFMpASGPoy8bfVzFVCF2dVSNzuHd3JDAAg21q GvgA== X-Forwarded-Encrypted: i=1; AJvYcCUjCT6XpNun2u4yj/B6MHrhWVl64ae/0aCANMgrnq5yWeJ+ZJRYd745XKeCD0GRZsQGlsFGZ++uiyi3@nongnu.org X-Gm-Message-State: AOJu0Yyzfj/3296b15HICBP3TbVkPrXZdLrDGzhOr98VGPoHTxrPs0Hi jtVnCZQXJxgNGd03r1jWmO+B/v0I9D++HSNHz7DHX+btLuhT6aQ8vfuk3Vaf4YA= X-Gm-Gg: ASbGnctDVR71DTcXBgVY4rw8MS9uihFNtXU536iZapXnqsx0yHpeRMukI6cwkKLgHkM lREnbZviIo+oCeKahVpAgdZBywaSYY1REwjRnu0NVeoJ+ZAYFZOOFm8ZJXRPzxnCUzRKnCO9TuY QygaIpLsupkQHATLXk4Apzr+slkznxTjNLJ/0x2ATYnoIbib//tmUX0IR7fK4X3PJo5DL7p/Cu6 CtWqth9lc/VXj1Vzc68ovlb18JE7TseSWNkSHcLEPUN3hFDWtxegJpWAHmLMeUEkmktktGxSc1i 1L1dWGNzeSLNoQ/4LZ0JcA== X-Google-Smtp-Source: AGHT+IH+I7yo4Js2hImL1H05KRHZE/gUC0mEnMK4BeWT4jXxKMiariAVI/m730Pzby6oKJBa9crVaA== X-Received: by 2002:a5d:5846:0:b0:385:f4db:e33b with SMTP id ffacd0b85a97d-38c51966b85mr8153358f8f.21.1738261397654; Thu, 30 Jan 2025 10:23:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:17 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 06/14] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Date: Thu, 30 Jan 2025 18:23:01 +0000 Message-Id: <20250130182309.717346-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not AArch64. This has been there since the GIC was first implemented, but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ then we definitely want to be going to EL3 (doing AArch32.TakeMonitorTrapException() in pseudocode terms). We might want to not take a trap at all, but we don't ever want to go to the default target EL, because that would mean, for instance, taking a trap to Hyp mode if the trapped access was made from Hyp mode. (This might have been an attempt to work around our failure to properly implement Monitor Traps.) Remove the bogus check. Cc: qemu-stable@nongnu.org Fixes: 359fbe65e01e ("hw/intc/arm_gicv3: Implement GICv3 CPU interface registers") Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 9cad8313a3a..8a715b3510b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2300,9 +2300,6 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, } } - if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { - r = CP_ACCESS_TRAP; - } return r; } @@ -2365,9 +2362,6 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env, } } - if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { - r = CP_ACCESS_TRAP; - } return r; } @@ -2404,9 +2398,6 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env, } } - if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) { - r = CP_ACCESS_TRAP; - } return r; } From patchwork Thu Jan 30 18:23:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7A80C02190 for ; Thu, 30 Jan 2025 18:25:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCT-0003zs-KR; Thu, 30 Jan 2025 13:23:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCF-0003ss-2m for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:24 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCC-0000Vr-Ip for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:22 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4363ae65100so13351805e9.0 for ; Thu, 30 Jan 2025 10:23:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261399; x=1738866199; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fMa5YuSy0NDTUYP5ui6N/RSQpdjoNfs7F2yE5YfgTb4=; b=QLyXT5avtYHv5+RnaydOyMFPb3tY6Bm6HiR/ActAnDiNW5sbqfSx6PdyT73xCIjTmQ +BP11bH6Sg+Yt2gYXF6pMZJgW31ThkuLdNiGmDHhhCYDgyMHaNqveWh0mlRR1ZZ5R29o YKEri0ZS7D/3VKkQ0LRikjIvFaH5kyMEk1UXRz76PhR0FXo0I/qt6Adtsb/UBWoK3DDZ A+eF1FYHvHZo6T3k2Ph9NUWcCz+VmwifteJQyD5WYPlcTtem4i85DPv4Wt9wMWNTkZOD I9BWzu5I1+z0aIRcpZkpJzfGWPW62MDDFZCjb5vgPhooXCbSEp/N35oMACguFUulBeHa POMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261399; x=1738866199; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fMa5YuSy0NDTUYP5ui6N/RSQpdjoNfs7F2yE5YfgTb4=; b=tpoI5q3wYQL3mjwl2iblT3jo1duZp9HglkF0GTcDXeLoINFjDXrH7IHdrOABW/3CEr 4FKQLDFEj1nAbDWAcqHjJe3JIiIQnLGifGkoU3Bh9pmZEKqY5Puf3Dyw96TEnl8/k15N Jc94ggRDD9J+IKDbA2Sogdsl8LMibBcXExIB8I0AY0XDr0vfHxJaki1fS8FdB6y9jk29 w/g9x4jv+15IorZQ8qBVrY9lll5diFpvR9tsWNHTbE9aRSaItSZRutrk/wYblPOwbTZe F5kO7dcRfGHYwyXa9YIH7NfVzGvKc1RSpZsYzBWnFN9CY8V2beErJaxiP3r+cCKvoCEs AKCw== X-Forwarded-Encrypted: i=1; AJvYcCVFe08sz41cVESBUleUjDIDXQfPTBYe1maWJijMAfgDqzWQ83nV+4pZIqOIBOhCRGcsbNXqXbxHh872@nongnu.org X-Gm-Message-State: AOJu0Yx3nlBPDFKDPRoZQNrsTEd3xCJMB9l9NAbfzuGgjjMOgGTuzuJ4 j/pQDEAsxJQ96n7uY2+nAwL8fs+uncs6l5fjz1CaGn05p3BYVVORAkvnpXzY9fVCQ+tn49vftZt U X-Gm-Gg: ASbGncsTl6fF7JxKsdZXV59+Rc1IBKrjnKj9wP5UgGsgqqRREYmAZA6QHwE+xByMIIM 4MSZdTda8yntlrm//yZWbM9HS/RlI2B52kBC1zn6eZvtt+8ik++BwiCuGHcSk89AXecqnjX/b9a 6OmH/+i8+Hy3J48x074T6QQo2hAFHm2n1kuKdmXTv1ZJc7vXV+3FGVlXUmvvYE5QRbpAER6KtiL yorlmMtRYQAWbaB1vifRxsvrdr/0cUVtWxlEG7GUVkw6kCj/ccS+R3nxHdmr01okOWPLP2siy2I UwI7wQv0dRJ0K28BmrAfiw== X-Google-Smtp-Source: AGHT+IFxjIh48WU/dSlOaoPrzaGSoSizC3MFT5Mm3SI1EOiyMrYEpqnqyWB8Fb2376SJHBAQgkzR3Q== X-Received: by 2002:a05:6000:1548:b0:38c:3f12:64be with SMTP id ffacd0b85a97d-38c51f8a3camr10044992f8f.35.1738261398740; Thu, 30 Jan 2025 10:23:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 07/14] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes Date: Thu, 30 Jan 2025 18:23:02 +0000 Message-Id: <20250130182309.717346-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There are not many traps in AArch32 which should trap to Monitor mode, but these trap bits should trap not just lower ELs to Monitor mode but also the non-Monitor modes running at EL3 (i.e. Secure System, Secure Undef, etc). We get this wrong because the relevant access functions implement the AArch64-style logic of if (el < 3 && trap_bit_set) { return CP_ACCESS_TRAP_EL3; } which won't trap the non-Monitor modes at EL3. Correct this error by using arm_is_el3_or_mon() instead, which returns true when the CPU is at AArch64 EL3 or AArch32 Monitor mode. (Since the new callsites are compiled also for the linux-user mode, we need to provide a dummy implementation for CONFIG_USER_ONLY.) This affects only: * trapping of ERRIDR via SCR.TERR * trapping of the debug channel registers via SDCR.TDCC * trapping of GICv3 registers via SCR.IRQ and SCR.FIQ (which we already used arm_is_el3_or_mon() for) This patch changes the handling of SCR.TERR and SDCR.TDCC. This patch only changes guest-visible behaviour for "-cpu max" on the qemu-system-arm binary, because SCR.TERR and SDCR.TDCC (and indeed the entire SDCR register) only arrived in Armv8, and the only guest CPU we support which has any v8 features and also starts in AArch32 EL3 is the 32-bit 'max'. Other uses of CP_ACCESS_TRAP_EL3 don't need changing: * uses in code paths that can't happen when EL3 is AArch32: access_trap_aa32s_el1, cpacr_access, cptr_access, nsacr_access * uses which are in accessfns for AArch64-only registers: gt_stimer_access, gt_cntpoff_access, access_hxen, access_tpidr2, access_smpri, access_smprimap, access_lor_ns, access_pauth, access_mte, access_tfsr_el2, access_scxtnum, access_fgt * trap bits which exist only in the AArch64 version of the trap register, not the AArch32 one: access_tpm, pmreg_access, access_dbgvcr32, access_tdra, access_tda, access_tdosa (TPM, TDA and TDOSA exist only in MDCR_EL3, not in SDCR, and we enforce this in sdcr_write()) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/debug_helper.c | 3 ++- target/arm/helper.c | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4cb672c120b..ae1e8b1c779 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2570,6 +2570,11 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) return false; } +static inline bool arm_is_el3_or_mon(CPUARMState *env) +{ + return false; +} + static inline ARMSecuritySpace arm_security_space(CPUARMState *env) { return ARMSS_NonSecure; diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2212ef4a3b9..c3c1eb5f628 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -880,7 +880,8 @@ static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri, if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) { return CP_ACCESS_TRAP_EL2; } - if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) { + if (!arm_is_el3_or_mon(env) && + ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) { return CP_ACCESS_TRAP_EL3; } return CP_ACCESS_OK; diff --git a/target/arm/helper.c b/target/arm/helper.c index c5cd27b249f..058a5af3aaf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6103,7 +6103,7 @@ static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { return CP_ACCESS_TRAP_EL2; } - if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + if (!arm_is_el3_or_mon(env) && (env->cp15.scr_el3 & SCR_TERR)) { return CP_ACCESS_TRAP_EL3; } return CP_ACCESS_OK; From patchwork Thu Jan 30 18:23:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFA79C0218A for ; Thu, 30 Jan 2025 18:25:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCS-0003yC-2Y; Thu, 30 Jan 2025 13:23:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCF-0003sy-B7 for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:19 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 08/14] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Date: Thu, 30 Jan 2025 18:23:03 +0000 Message-Id: <20250130182309.717346-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the gicv3_{irq,fiq,irqfiq}_access() functions, in the arm_current_el(env) == 3 case we do the following test: if (!is_a64(env) && !arm_is_el3_or_mon(env)) { r = CP_ACCESS_TRAP_EL3; } In this check, the "!is_a64(env)" is redundant, because if we are at EL3 and in AArch64 then arm_is_el3_or_mon() will return true and we will skip the if() body anyway. Remove the unnecessary tests. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8a715b3510b..7f1d071c198 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2291,7 +2291,7 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, r = CP_ACCESS_TRAP_EL3; break; case 3: - if (!is_a64(env) && !arm_is_el3_or_mon(env)) { + if (!arm_is_el3_or_mon(env)) { r = CP_ACCESS_TRAP_EL3; } break; @@ -2353,7 +2353,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env, r = CP_ACCESS_TRAP_EL3; break; case 3: - if (!is_a64(env) && !arm_is_el3_or_mon(env)) { + if (!arm_is_el3_or_mon(env)) { r = CP_ACCESS_TRAP_EL3; } break; @@ -2389,7 +2389,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env, r = CP_ACCESS_TRAP_EL3; break; case 3: - if (!is_a64(env) && !arm_is_el3_or_mon(env)) { + if (!arm_is_el3_or_mon(env)) { r = CP_ACCESS_TRAP_EL3; } break; From patchwork Thu Jan 30 18:23:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93C03C02194 for ; Thu, 30 Jan 2025 18:25:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCV-00041L-5p; Thu, 30 Jan 2025 13:23:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCG-0003to-Qi for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:25 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCE-0000Wj-QM for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:24 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3863c36a731so907438f8f.1 for ; Thu, 30 Jan 2025 10:23:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261401; x=1738866201; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yzUgHg6nqtrTZvIz3ixC5Nt4RQVPQXOj6ckfC4T6pic=; b=HwcyNL3oMwBo+d5Cx9dtQLo2wPmBss2ueuuURUumi+3Pi+v5TssmC3JjyxVNl6B+SL JUOCaDUqjzsg3/8laYZShSPnBQKoBOeDQkGXXsJlg03ipUHJbbjzGF0WvTWIsNVI+tJT Z8NEziDt7k4qPVkPPWykLfO2+yUqO/uJNe9hzj8C/+96Zw3ZLEs8mD8SKaRd8VHE+KIw pfSmKRd477kWuUOlhivJQExP+GMElIOK3zTLVVwL4QdGv59n4lubsa1DPQlWBWJsOxiy pccfSMK5IicD28ypFNrJu2nUotBUA0nH+MYBglhMFdlqDPBsdm+RFuJzjgj+Kie/k683 1VRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261401; x=1738866201; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yzUgHg6nqtrTZvIz3ixC5Nt4RQVPQXOj6ckfC4T6pic=; b=hHWBD8VRNMx7k3JSF2DJM9QkRxth+smVldhyP15wkopid/7DXl8oDK11QnU3ez4UqR X5ERbpi66I2K4w/A/PEcsjBP7+/UX/FBrXcDzdUQt2TCeeK9nngpX8bXOMGdiycikw0K VATCLzQT6q5sqSTFjR5hGfhMku4KnH/A1II72Gn8C15O96ghxPx1PW+GoR0SP5I9MCBT uzloTV35BfdbXWiRREuv3v7CueJs2gndTZ3LqAWjEKbAzFrQflDrdSTrbnZvA9gBfVUy GOncgwJuXO3ul7ORPPTSovxyPce1NFnyqdT2VoPQwTm7hFOgUKvE1LzTXcVyUa5XJcti FwoQ== X-Forwarded-Encrypted: i=1; AJvYcCXTzQcK1ymi4Qt7iaUFuHPxGo3Lv572g0L3XLEJyq4BXGDlcI5LZl+WRXoIN2ceV96SkYMCoFRcWuVH@nongnu.org X-Gm-Message-State: AOJu0YyCtvJIZRJ2ZAJ314pqx3Vq7AyBPiLxGhYznsetkU0iqfYDHQbk n/YY5UQpThWZkMwpUQx710HhsHqVfLmr1vt98w6VsM+pnbj9KBOn8xsgtjJWcCI= X-Gm-Gg: ASbGncvV4IcZFAUfRCg+mc1llUsGrf97rvLoc9CxaqXEut0lXJgfHICpN2P7oDw6xPq ObZr4H1wD/j5/vOef/RJ0DCnX6vRdve14kd+rhMWGOVc42ov7b58FTsXK0/1whd8CPAT+8vVqCe YYIB/kmXG7Z2GjpgZxPaS38zhRoIKEvgs33Xhk4fQ661Pc2+acBIZarZFafeTd75syoYvM0jwG6 ONMUT7QEJeskEke7yo9UYJ0AJTGMWtKC3LziiGkEIW6PRP9i2IG3q2P92lpA9N8n/YeZESEYn36 9qSflfn+nRCzVT6zfm1lRA== X-Google-Smtp-Source: AGHT+IE8KcPPbbX+/lcvomWZbLlt2xTmnRV4Djr3ywWNrv8azlYXfRd8F3odOCzEuERXlxchvO0xXQ== X-Received: by 2002:a5d:64a1:0:b0:385:f0dc:c9f4 with SMTP id ffacd0b85a97d-38c51967de4mr6882576f8f.20.1738261400830; Thu, 30 Jan 2025 10:23:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 09/14] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult Date: Thu, 30 Jan 2025 18:23:04 +0000 Message-Id: <20250130182309.717346-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the CPAccessResult enum, the CP_ACCESS_TRAP* values indicate the equivalent of the pseudocode AArch64.SystemAccessTrap(..., 0x18), causing a trap to a specified exception level with a syndrome value giving information about the failing instructions. In the pseudocode, such traps are always taken to a specified target EL. We support that for target EL of 2 or 3 via CP_ACCESS_TRAP_EL2 and CP_ACCESS_TRAP_EL3, but the only way to take the access trap to EL1 currently is to use CP_ACCESS_TRAP, which takes the trap to the "usual target EL" (EL1 if in EL0, otherwise to the current EL). Add CP_ACCESS_TRAP_EL1 so that access functions can follow the pseudocode more closely. (Note that for the common case in the pseudocode of "trap to EL2 if HCR_EL2.TGE is set, otherwise trap to EL1", we handle this in raise_exception(), so access functions don't need to special case it and can use CP_ACCESS_TRAP_EL1.) Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 1 + target/arm/tcg/op_helper.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1759d9defbe..fbf5798069d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -331,6 +331,7 @@ typedef enum CPAccessResult { * 0xc or 0x18). */ CP_ACCESS_TRAP = (1 << 2), + CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP | 1, CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2, CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3, diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 1ba727e8e9f..c427118655d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -781,7 +781,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, * the other trap takes priority. So we take the "check HSTR_EL2" path * for all of those cases.) */ - if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) && + if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) < 2) && arm_current_el(env) == 0) { goto fail; } @@ -887,6 +887,9 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, case 0: target_el = exception_target_el(env); break; + case 1: + assert(arm_current_el(env) < 2); + break; case 2: assert(arm_current_el(env) != 3); assert(arm_is_el2_enabled(env)); @@ -895,7 +898,6 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, assert(arm_feature(env, ARM_FEATURE_EL3)); break; default: - /* No "direct" traps to EL1 */ g_assert_not_reached(); } From patchwork Thu Jan 30 18:23:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBF29C0218A for ; Thu, 30 Jan 2025 18:26:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCW-000434-Ju; Thu, 30 Jan 2025 13:23:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCI-0003tw-LC for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:30 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCF-0000X5-SJ for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:26 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4362bae4d7dso8568725e9.1 for ; Thu, 30 Jan 2025 10:23:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261402; x=1738866202; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2CkHxBykkh+MkSMFpl2gMe093xK0SZ26idFhO7kRCAU=; b=NjIReg6bioSEKiNfHY+RDlSS6S3o6YdBfcUE2tVLvQcjed0Yw3IDQ3vaOGStnzLGRB vbpueu7j0FTwkNas8rHC5fnctrbqbohrKQpbB2BYyJ9D6tSJzjSPU0Kai9ODeZq5+zlF l/d0/1WLuyys0j13Nd8OO4aofSe0/IiExxMLG3cJogvtkvFYH9Rj3VOB8VthyFk2Vxrx do0RDAOreuytzvIwPcMkiV8gU1p528+OYAjDMKUWypOJFhKusMapgvPoILB0hrQx401d bM3qn1VAfcEyzhuuMT1S7jEvSwdFPaTLIj3U82UpEbvfvEALAXYjyQ3aU+hPZZo8P976 HzFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261402; x=1738866202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2CkHxBykkh+MkSMFpl2gMe093xK0SZ26idFhO7kRCAU=; b=BngZomyeZekgT8aDiecV4FtUaG4LGHV8iIjjj5IxwJRbXZ7jcWisL0qdPchXbGjv0B dZ9g2VxjRKKSfv/D58w7FOraZHOvZpbtyArOVCVMWwshGLfZkT7s5F2BkGCrJwoIP6jM SEIK1NKZZpcTFStiEnAtFu9KZyCCmwOdZWe93O17FbcjuGlfXv1QiQyGJpnRHG+YgRN5 lwIROjLwHSpSyxi/NXIJBzxnTOoIuMjbhH4nirQy1Hz7BAYvady+sSvQRRqeJdHGv7Oh Imd+FQ0IyZDKreAi7+vTAhu/SzGBFL1F+kiwzIPrfozCBOBbdryzIuvr45u5tFRs6Cby Flmw== X-Forwarded-Encrypted: i=1; AJvYcCXnf8+yD+nsnQFTXiDmgCMaJqudsiyvQ1sq+7BxijCI/epVQzERR9MaDSbKvPsPhXwuUXq0kxDALIkv@nongnu.org X-Gm-Message-State: AOJu0YwMXK46lodgI3Wjv2dTU0CEs0elWQgb5nvTi7ElkHHeEogLpWgL TL6eQvUQ8gAh5UqQcKYCvkZHu3OZqixidv+IvAYoVipsA0R8Q6+3WL5gd3nRnYY= X-Gm-Gg: ASbGnctj+8OX/pcBMSHmwfHp0d7C51xp4He6sWjA0iVLXDxzRrCOv7QauCjcPnn5u3W ZA81eicOb7+ZSYx6vwjB9dkHO10zBW0JPr9mkxmEd2pfsR0al92FJJK8/bwrzpko3idwfHzs8yM DyqBOGZwYrqHmVvo/mgpTess6w28qRDr1PJgey3JEIhKr9yZfbwBL6SHNz9H1Wjf8KopZnWPGoa OZwrlZHDOSEOgL4tRTjFDaPX5ZzvaDKn354jewgAXy/ubUxHXEm9dVBw8pTKFZBUHkq65GlJaRC O/8tyDL3hkiLUw73CWh+Aw== X-Google-Smtp-Source: AGHT+IEJ2ODNjHam3bz1ESlW1/hTzD8Wq66vV2VuMFkU5yxxcDllToWcDqGGfaoFfFhi5PcQTZHSpg== X-Received: by 2002:a05:600c:3155:b0:434:a5bc:70fc with SMTP id 5b1f17b1804b1-438dc3ae116mr78395615e9.8.1738261401931; Thu, 30 Jan 2025 10:23:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 10/14] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Date: Thu, 30 Jan 2025 18:23:05 +0000 Message-Id: <20250130182309.717346-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We currently use CP_ACCESS_TRAP in a number of access functions where we know we're currently at EL0; in this case the "usual target EL" is EL1, so CP_ACCESS_TRAP and CP_ACCESS_TRAP_EL1 behave the same. Use CP_ACCESS_TRAP_EL1 to more closely match the pseudocode for this sort of check. Note that in the case of the access functions foc cacheop to PoC or PoU, the code was correct but the comment was wrong: SCTLR_EL1.UCI traps for DC CVAC, DC CIVAC, DC CVAP, DC CVADP, DC CVAU and IC IVAU should be system access traps, not UNDEFs. Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 2 +- target/arm/helper.c | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index c3c1eb5f628..36bffde74e9 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -875,7 +875,7 @@ static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri, (env->cp15.mdcr_el3 & MDCR_TDCC); if (el < 1 && mdscr_el1_tdcc) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) { return CP_ACCESS_TRAP_EL2; diff --git a/target/arm/helper.c b/target/arm/helper.c index 058a5af3aaf..d1e26ec9d06 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -881,7 +881,7 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } if (el < 2 && (mdcr_el2 & MDCR_TPM)) { return CP_ACCESS_TRAP_EL2; @@ -2159,7 +2159,7 @@ static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { if (arm_current_el(env) == 0 && (env->teecr & 1)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } return teecr_access(env, ri, isread); } @@ -2239,7 +2239,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, cntkctl = env->cp15.c14_cntkctl; } if (!extract32(cntkctl, 0, 2)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } break; case 1: @@ -2278,7 +2278,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } /* fall through */ case 1: @@ -2319,7 +2319,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, * EL0 if EL0[PV]TEN is zero. */ if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } /* fall through */ @@ -4499,7 +4499,7 @@ static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } return CP_ACCESS_OK; } @@ -4589,9 +4589,9 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, /* Cache invalidate/clean to Point of Coherency or Persistence... */ switch (arm_current_el(env)) { case 0: - /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + /* ... EL0 must trap to EL1 unless SCTLR_EL1.UCI is set. */ if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } /* fall through */ case 1: @@ -4609,9 +4609,9 @@ static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags) /* Cache invalidate/clean to Point of Unification... */ switch (arm_current_el(env)) { case 0: - /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + /* ... EL0 must trap to EL1 unless SCTLR_EL1.UCI is set. */ if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } /* fall through */ case 1: @@ -4651,7 +4651,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, } } else { if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } if (hcr & HCR_TDZ) { return CP_ACCESS_TRAP_EL2; @@ -6073,7 +6073,7 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, } } else { if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } if (hcr & HCR_TID2) { return CP_ACCESS_TRAP_EL2; @@ -6372,7 +6372,7 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, if (el == 0) { uint64_t sctlr = arm_sctlr(env, el); if (!(sctlr & SCTLR_EnTP2)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } } /* TODO: FEAT_FGT */ @@ -7172,7 +7172,7 @@ static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, if (hcr & HCR_TGE) { return CP_ACCESS_TRAP_EL2; } - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { return CP_ACCESS_TRAP_EL2; @@ -7292,7 +7292,7 @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, if (el == 0) { uint64_t sctlr = arm_sctlr(env, el); if (!(sctlr & SCTLR_EnRCTX)) { - return CP_ACCESS_TRAP; + return CP_ACCESS_TRAP_EL1; } } else if (el == 1) { uint64_t hcr = arm_hcr_el2_eff(env); From patchwork Thu Jan 30 18:23:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47C30C02190 for ; Thu, 30 Jan 2025 18:26:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCR-0003y1-Cy; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 11/14] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Date: Thu, 30 Jan 2025 18:23:06 +0000 Message-Id: <20250130182309.717346-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On XScale CPUs, there is no EL2 or AArch64, so no syndrome register. These traps are just UNDEFs in the traditional AArch32 sense, so CP_ACCESS_TRAP_UNCATEGORIZED is more accurate than CP_ACCESS_TRAP. This has no visible behavioural change, because the guest doesn't have a way to see the syndrome value we generate. Signed-off-by: Peter Maydell --- target/arm/tcg/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c427118655d..c69d2ac643f 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -764,7 +764,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { - res = CP_ACCESS_TRAP; + res = CP_ACCESS_TRAP_UNCATEGORIZED; goto fail; } From patchwork Thu Jan 30 18:23:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4941EC0218A for ; Thu, 30 Jan 2025 18:25:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCT-0003zB-HO; Thu, 30 Jan 2025 13:23:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCK-0003u4-MZ for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:30 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCH-0000Xq-Kw for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:28 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4361dc6322fso8230115e9.3 for ; Thu, 30 Jan 2025 10:23:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261404; x=1738866204; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UzWUoCV36n6hAnw3YSCmnofxu0Xpqe1BV6caUwzw2Oc=; b=MVfEXVAmUTLMODntJQPY3PjKsyHzPn5QfOGEVpdLRQuORY9KLNgJHSbn4R4QGY2KOU AUDSAmYCPNpBUwJQYo7sLZMqxjyuHYB18PgFaW9PKdbaWy5UpdHaTQkTdwxStnLoOhel UW3/fynh7USZ8Dke5HCac+IRgJEJYAvrIGsWnHTRFktQo91VDCvKubcwsWqkzbPYt3fc TySpsl4fFgbJAdfShVBifII/EqqCQ7BAaYN+g861+fBwQxMHL8BBh1is53dzz7eqp5jZ 9TCc7fmCFCBPcCxzZcTEfiz3+2jQ68oCO1/ys9fP/C/Vjb3XT+o0mlmPig502ZjpKNIp OXqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261404; x=1738866204; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UzWUoCV36n6hAnw3YSCmnofxu0Xpqe1BV6caUwzw2Oc=; b=F/mZvh+2D93uxdlyJU9PRsblxt/cNDt8w32W2ycbJBeku0PrNbGP7nnnR5Eu3DOnmV 8x2aj9yeYtmtg58nL+rNVzgMaM5vFjfIQl/fzp59PwdR8s6MSLZ6xQi18ZAqHwBOaEk/ LqlYpMYpjZ03mg6e0O9zwrnM0kJ+TxvRKDIotsQkZzMAyRUywOKbgkkvXGfHBUIa3RcB uz5zMJNRCvwIosZx8vEGrjUNFkIdLHqDgLEK+/02Md+AGxc48npt9NbDi5Ui5OXn4zae GYvbdxSZImkYiLxp2ioGhd4L25yUMNBosWwQ7clTi6slvAktCSwN0qvC24qSs3CW3evk 18Qg== X-Forwarded-Encrypted: i=1; AJvYcCUUf6rw+KUL95v60ZEtk+cNtZ60/9Ed3ElACBkggOVgf1Wqb6dgErBjhrxGK6Qxj5wyolGXbK5CUJ0o@nongnu.org X-Gm-Message-State: AOJu0YyyTpNRXq3q94v4JzZItNXxCN4KgxAJB8lwqGlhSugTL1vGxWwN WEcXjurQjI+8yLmagvGmsBwREdvloEZ/cwd7CTXdeJs4Sw6o9ddf6wk2PtT+5HI= X-Gm-Gg: ASbGncv34XY0uiHV9/JqblhDvBcveYHl6LIQamkmUWrZ6i65dPIlx5I2ydH8zfbZK2Q +Gl2+GUaxga7rAHnv/+xx9aydjEKDjds60oqTP2EatR7hQTazlOeTpK5YQPGkvqgKcOHjVtoms9 emsDRerNC9dzUq2qXfyWBXXiY8ezD+M6XCmJjhpwGX3mD4vppFeRhVpQ+W2EGcoLHOF1ZMy3/Em sooONtabrwM7hpreLEGxOFZWmoYrWZeGn1msrcp8sk3AqILKke9XhE3z61RskhzN9C1m3dXVlwB 7FcWBiiD/+Mm9rPYH95OZA== X-Google-Smtp-Source: AGHT+IHv5gF70a4Mqx8gdcoaCrYuQ74X9HkaiJE7S7DYI8dtyyZsPjQ0YXE5YOYaMCY55s/ktOPz4w== X-Received: by 2002:a5d:64c3:0:b0:38a:a117:3da1 with SMTP id ffacd0b85a97d-38c51946048mr7119768f8f.5.1738261403930; Thu, 30 Jan 2025 10:23:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 12/14] target/arm: Remove CP_ACCESS_TRAP handling Date: Thu, 30 Jan 2025 18:23:07 +0000 Message-Id: <20250130182309.717346-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There are no longer any uses of CP_ACCESS_TRAP in access functions, because we have converted them all to use either CP_ACCESS_TRAP_EL1 or CP_ACCESS_TRAP_UNCATEGORIZED, as appropriate. Remove the handling of bare CP_ACCESS_TRAP from the access_check_cp_reg() helper, so that it now asserts if an access function returns it. Rename CP_ACCESS_TRAP to CP_ACCESS_TRAP_BIT, to make it clearer that this is an internal-only definition, not something that it makes sense to return from an access function. This should help to avoid future bugs where we return the wrong syndrome value by mistake. Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 11 ++++++----- target/arm/tcg/op_helper.c | 13 ++++++++----- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index fbf5798069d..fb3b84baa1e 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -328,12 +328,13 @@ typedef enum CPAccessResult { * Access fails due to a configurable trap or enable which would * result in a categorized exception syndrome giving information about * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). + * 0xc or 0x18). These traps are always to a specified target EL, + * never to the usual target EL. */ - CP_ACCESS_TRAP = (1 << 2), - CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP | 1, - CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2, - CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3, + CP_ACCESS_TRAP_BIT = (1 << 2), + CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP_BIT | 1, + CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP_BIT | 2, + CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3, /* * Access fails and results in an exception syndrome 0x0 ("uncategorized"). diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c69d2ac643f..fcee11e29ad 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -853,21 +853,24 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, fail: excp = EXCP_UDEF; - switch (res & ~CP_ACCESS_EL_MASK) { - case CP_ACCESS_TRAP: + switch (res) { + /* CP_ACCESS_TRAP* traps are always direct to a specified EL */ + case CP_ACCESS_TRAP_EL3: /* * If EL3 is AArch32 then there's no syndrome register; the cases * where we would raise a SystemAccessTrap to AArch64 EL3 all become * raising a Monitor trap exception. (Because there's no visible * syndrome it doesn't matter what we pass to raise_exception().) */ - if ((res & CP_ACCESS_EL_MASK) == 3 && !arm_el_is_aa64(env, 3)) { + if (!arm_el_is_aa64(env, 3)) { excp = EXCP_MON_TRAP; } break; + case CP_ACCESS_TRAP_EL2: + case CP_ACCESS_TRAP_EL1: + break; case CP_ACCESS_TRAP_UNCATEGORIZED: - /* Only CP_ACCESS_TRAP traps are direct to a specified EL */ - assert((res & CP_ACCESS_EL_MASK) == 0); + /* CP_ACCESS_TRAP_UNCATEGORIZED is never direct to a specified EL */ if (cpu_isar_feature(aa64_ids, cpu) && isread && arm_cpreg_in_idspace(ri)) { /* From patchwork Thu Jan 30 18:23:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13954816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C2BBC0218A for ; Thu, 30 Jan 2025 18:25:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdZCX-00043g-3g; Thu, 30 Jan 2025 13:23:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdZCS-0003yZ-JG for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:36 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tdZCI-0000YC-DG for qemu-devel@nongnu.org; Thu, 30 Jan 2025 13:23:36 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-38789e5b6a7so676214f8f.1 for ; Thu, 30 Jan 2025 10:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738261405; x=1738866205; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fT9psFAWJPNLFoqhflxpXdULv7n4FREA8vp9m2an3Sc=; b=ZVUW4awYt74Dr8dFQVE7VeDOXjgw8AJDP2P6432betuLUQUJ9ongNAJouUAYyRjOag 8SZaGVctMK+L1nS4901IcxnWSo347gmYPATjy3z6s1ePCC8OEIjGeyazwfDVj0aUPkq8 L4xXmgWyRvzZZo8oDfuMZaBbc4zmzXjAzDC+RP/1n9/QPJB6JCnxS7gdFuUmXK/Fwmdw urLB4R+Z3rRWIGEf+sfucAjEfX3Xse5mnQVa7H2vDEI9gqkBaVNz4sBMRsvwW0R1hm40 zpr3q0rneOdEs3q6u6s9czj12uXN3K6wBBmbk65/3LTGjuQFTRnKm5aLTlS2FwxdtSjo Gekw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738261405; x=1738866205; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fT9psFAWJPNLFoqhflxpXdULv7n4FREA8vp9m2an3Sc=; b=vqdIZHU+cVjp49bcqX4o3l82sWoMPbqXnCB/lJtmcYG+Z4hJ8YggAgJBaZa5aGW6bq 6anBLAzIHdif8gvwDspumuoC/g6fbL+IAARwQJpSMOkHLTIB2xiXcCm5hLy/ZNsW0CIT fpDpfRCe2GyDEP+7ju593c7AOccjy5dIb8w1uLNCRrgSK3/Ame9EgZm3dJeSHBY55jkA Vsr5djXv+eQ4+oFY3AyEjFg93znWLMkTtlHApTQQ9DNLI/bVORcQMe9QgJtLOWLUXm8h Y4/61+krxah5ZBFLLdr3STNK8MHtW01obr9am9+cOtKGO5AZZU1SCgrPAh5nOwB2y87s b5Rw== X-Forwarded-Encrypted: i=1; AJvYcCXh5atGkl8YpbVf/42dfYbpMj6l2Vvqxc9pB4KSS33hVdWtganEtiB8iYN5/lu3hI6cjYNsqCqbYrKV@nongnu.org X-Gm-Message-State: AOJu0YwbciKA8NFuw5Syh87dAx5VDIFKJn7BYIcbD8bCZXyWrO1RSP6a zja1LLgZE1vzgnb3hp0p8WGktEeNjhFUUoJRKmz9fOpSklHsaVpEonjhmD5Egnk= X-Gm-Gg: ASbGncvdqLmpAOnArFoOJo00Sj6uwdNFTckvDVK8IRBYrth8BxV9McJApodWuTY2XaC jd35hugxTz1dV2octjSvLTdBJMn4ymJXthTlanw+/qr/o8TjP3Lcq4L3ULAN12W8zSOCQHdcRcR eLU0wTKcChCDb7XR/DdSxuMeUQKgHe24z4LoCa9K8VwKB4mQiXl6Q0l5zm1T7Xjk5wN3EKg3tw9 ZVZWd1eLEislt+5vM6WzEL7gyYmt/ktfk+DFzS+f0Z0beZp+TTOGfX0qKk7yg8fxNJp5veBYh8j igR1kSmqofQTeM8u7hz7MQ== X-Google-Smtp-Source: AGHT+IHJ9OXse4dtVnUIniM47I4sjE8neBgEI/7d89xl0XSPiLCpUvOtYoeHha5fARQbxodmuAolDA== X-Received: by 2002:a5d:4348:0:b0:386:3e3c:ef1 with SMTP id ffacd0b85a97d-38c51e91b5emr7031841f8f.35.1738261404931; Thu, 30 Jan 2025 10:23:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 13/14] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Date: Thu, 30 Jan 2025 18:23:08 +0000 Message-Id: <20250130182309.717346-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CP_ACCESS_TRAP_UNCATEGORIZED is technically an accurate description of what this return value from a cpreg accessfn does, but it's liable to confusion because it doesn't match how the Arm ARM pseudocode indicates this case. What it does is an EXCP_UDEF with a zero ("uncategorized") syndrome value, which is what an UNDEFINED instruction does. The pseudocode uses "UNDEFINED" to show this; rename our constant to CP_ACCESS_UNDEFINED to make the parallel clearer. Commit created with sed -i -e 's/CP_ACCESS_TRAP_UNCATEGORIZED/CP_ACCESS_UNDEFINED/' $(git grep -l CP_ACCESS_TRAP_UNCATEGORIZED) plus manual editing of the comment. Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 5 +++-- target/arm/helper.c | 30 +++++++++++++++--------------- target/arm/tcg/op_helper.c | 6 +++--- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index fb3b84baa1e..52377c6eb50 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -337,13 +337,14 @@ typedef enum CPAccessResult { CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3, /* - * Access fails and results in an exception syndrome 0x0 ("uncategorized"). + * Access fails with UNDEFINED, i.e. an exception syndrome 0x0 + * ("uncategorized"), which is what an undefined insn produces. * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. * This trap is always to the usual target EL, never directly to a * specified target EL. */ - CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), + CP_ACCESS_UNDEFINED = (2 << 2), } CPAccessResult; /* Indexes into fgt_read[] */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d1e26ec9d06..1fee8fae127 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -285,7 +285,7 @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env, { if (!is_a64(env) && arm_current_el(env) == 3 && arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return CP_ACCESS_OK; } @@ -310,7 +310,7 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, return CP_ACCESS_TRAP_EL3; } /* This will be EL1 NS and EL2 NS, which just UNDEF */ - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } /* @@ -2246,7 +2246,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, if (!isread && ri->state == ARM_CP_STATE_AA32 && arm_is_secure_below_el3(env)) { /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } break; case 2: @@ -2255,7 +2255,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, } if (!isread && el < arm_highest_el(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return CP_ACCESS_OK; @@ -2385,7 +2385,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, switch (arm_current_el(env)) { case 1: if (!arm_is_secure(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } if (!(env->cp15.scr_el3 & SCR_ST)) { return CP_ACCESS_TRAP_EL3; @@ -2393,7 +2393,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env, return CP_ACCESS_OK; case 0: case 2: - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; case 3: return CP_ACCESS_OK; default: @@ -3304,7 +3304,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, } return CP_ACCESS_TRAP_EL3; } - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } } return CP_ACCESS_OK; @@ -3601,7 +3601,7 @@ static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, * scr_write() ensures that the NSE bit is not set otherwise. */ if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return CP_ACCESS_OK; } @@ -3611,7 +3611,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, { if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return at_e012_access(env, ri, isread); } @@ -4684,7 +4684,7 @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, * Access to SP_EL0 is undefined if it's being used as * the stack pointer. */ - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return CP_ACCESS_OK; } @@ -5674,7 +5674,7 @@ static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { return CP_ACCESS_OK; } - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } static const ARMCPRegInfo el2_sec_cp_reginfo[] = { @@ -5710,7 +5710,7 @@ static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, if (isread) { return CP_ACCESS_OK; } - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } static const ARMCPRegInfo el3_cp_reginfo[] = { @@ -5798,7 +5798,7 @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return CP_ACCESS_OK; } @@ -5896,7 +5896,7 @@ static CPAccessResult el2_e2h_e12_access(CPUARMState *env, } /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */ if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } if (ri->orig_accessfn) { return ri->orig_accessfn(env, ri->opaque, isread); @@ -6751,7 +6751,7 @@ static CPAccessResult access_lor_other(CPUARMState *env, { if (arm_is_secure_below_el3(env)) { /* UNDEF if SCR_EL3.NS == 0 */ - return CP_ACCESS_TRAP_UNCATEGORIZED; + return CP_ACCESS_UNDEFINED; } return access_lor_ns(env, ri, isread); } diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index fcee11e29ad..2230351a8f4 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -764,7 +764,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { - res = CP_ACCESS_TRAP_UNCATEGORIZED; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c5c101599sm2634426f8f.23.2025.01.30.10.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jan 2025 10:23:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 14/14] target/arm: Correct errors in WFI/WFE trapping Date: Thu, 30 Jan 2025 18:23:09 +0000 Message-Id: <20250130182309.717346-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130182309.717346-1-peter.maydell@linaro.org> References: <20250130182309.717346-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The code for WFI/WFE trapping has several errors: * it wasn't using arm_sctlr(), so it would look at SCTLR_EL1 even if the CPU was in the EL2&0 translation regime * it was raising UNDEF, not Monitor Trap, for traps to AArch32 EL3 because of SCR.{TWE,TWI} * it was not honouring SCR.{TWE,TWI} when running in AArch32 at EL3 not in Monitor mode * it checked SCR.{TWE,TWI} even on v7 CPUs which don't have those bits Fix these bugs. Cc: qemu-stable@nongnu.org Fixes: b1eced713d99 ("target-arm: Add WFx instruction trap support") Signed-off-by: Peter Maydell --- target/arm/tcg/op_helper.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 2230351a8f4..02c375d196d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -313,15 +313,19 @@ void HELPER(check_bxj_trap)(CPUARMState *env, uint32_t rm) } #ifndef CONFIG_USER_ONLY -/* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. +/* + * Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. * The function returns the target EL (1-3) if the instruction is to be trapped; * otherwise it returns 0 indicating it is not trapped. + * For a trap, *excp is updated with the EXCP_* trap type to use. */ -static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) +static inline int check_wfx_trap(CPUARMState *env, bool is_wfe, uint32_t *excp) { int cur_el = arm_current_el(env); uint64_t mask; + *excp = EXCP_UDEF; + if (arm_feature(env, ARM_FEATURE_M)) { /* M profile cores can never trap WFI/WFE. */ return 0; @@ -331,18 +335,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) * WFx instructions being trapped to EL1. These trap bits don't exist in v7. */ if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) { - int target_el; - mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI; - if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) { - /* Secure EL0 and Secure PL1 is at EL3 */ - target_el = 3; - } else { - target_el = 1; - } - - if (!(env->cp15.sctlr_el[target_el] & mask)) { - return target_el; + if (!(arm_sctlr(env, cur_el) & mask)) { + return exception_target_el(env); } } @@ -358,9 +353,12 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) } /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */ - if (cur_el < 3) { + if (arm_feature(env, ARM_FEATURE_V8) && !arm_is_el3_or_mon(env)) { mask = (is_wfe) ? SCR_TWE : SCR_TWI; if (env->cp15.scr_el3 & mask) { + if (!arm_el_is_aa64(env, 3)) { + *excp = EXCP_MON_TRAP; + } return 3; } } @@ -383,7 +381,8 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) return; #else CPUState *cs = env_cpu(env); - int target_el = check_wfx_trap(env, false); + uint32_t excp; + int target_el = check_wfx_trap(env, false, &excp); if (cpu_has_work(cs)) { /* Don't bother to go into our "low power state" if @@ -399,7 +398,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) env->regs[15] -= insn_len; } - raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2), + raise_exception(env, excp, syn_wfx(1, 0xe, 0, insn_len == 2), target_el); } @@ -424,7 +423,8 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) #else ARMCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); - int target_el = check_wfx_trap(env, false); + uint32_t excp; + int target_el = check_wfx_trap(env, false, &excp); /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */ uint64_t cntval = gt_get_countervalue(env); uint64_t offset = gt_virt_cnt_offset(env); @@ -441,8 +441,7 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) if (target_el) { env->pc -= 4; - raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, false), - target_el); + raise_exception(env, excp, syn_wfx(1, 0xe, 0, false), target_el); } if (uadd64_overflow(timeout, offset, &nexttick)) {