From patchwork Fri Jan 31 01:01:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13955037 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40C614409 for ; Fri, 31 Jan 2025 01:02:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738285335; cv=none; b=W0Vl5hoVj3/1Qj6+yx8ANsD7f2rF2ZE1iZYo8hkW8mP7CK3y7mlT/09mRXh6F6ZTSB2wLrsERGvZ6GHk++Bgrf7jmx8lX2XwgczmrDxGuL4K3XeDmHxhEwDvntl+1bAooNN41YMyHYa07CWUNuyhEVTrLnueu60deiHzmFTGUWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738285335; c=relaxed/simple; bh=KlcHGccGevK9NQFx61KDGxauWBmDVaGltURMM6rmh30=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AJl0EGQj01psASKaLJVwAq36YrNrFlcfi/xZu8fdvxoJNVEbyLhwwCsrlENWTl9Oavtsqtwbi7CzE+Rlw92S78GScwHfg+UONHjq08rdS/y2OSucpCK2FYdw2iTqaxoNVkvauwo04SgVkg92vx7psxSD3SaHKyoIXGvMgMsCz1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=oHqO6Af+; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="oHqO6Af+" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 595E42C019A; Fri, 31 Jan 2025 14:02:10 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738285330; bh=EdfF2PMQKfdZHx4FmLRkWBmB9Uv4yrzjsA4+2UFsnRA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oHqO6Af+g+KA39MpbhqcU+a/CauohUe6jaUnNHRQPXqW0u4WHRC7LtB9aGgUErQox zG6yoQh/qpGRsWu2GawdVEEs9DAORgsiZZNXzFbH0thr1lNU9yfHrUkqJtzHda3H3t W0p6Xyev987mjkfF1K/USJwzXf2ag22MrVMHoUzj+QQcRVBdvkoVMMkbKUcDymzt76 0i2tM1uuWwKFOkxjDHw4YDXNO0WDqUOkBBLrsyoqoE/XG1f44XcfLymf+Ed8T+Qy0A hk0d+PrRY21b3ZN8+jaUE8eb5ROyiXg9ODgpVi7+bopdoBVCnTUfcq01/mG4mclGhZ YMKy/+HqHAKpA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 31 Jan 2025 14:02:09 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id DEDF613EE2B; Fri, 31 Jan 2025 14:02:09 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id DDBA62809C0; Fri, 31 Jan 2025 14:02:09 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v5 1/4] dt-bindings: net: Add Realtek MDIO controller Date: Fri, 31 Jan 2025 14:01:48 +1300 Message-ID: <20250131010151.2527688-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> References: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=679c2111 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=VdSt8ZQiCzkA:10 a=gEfo2CItAAAA:8 a=uUkUPOp6VOHUeHtzUs0A:9 a=3ZKOabzyN94A:10 a=vS_ywuodlF3WoELfi4UP:22 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add dtschema for the MDIO controller found in the RTL9300 SoCs. The controller is slightly unusual in that direct MDIO communication is not possible. We model the MDIO controller with the MDIO buses as child nodes and the PHYs as children of the buses. Because we do need the switch port number to actually communicate over the MDIO bus this needs to be supplied via the "realtek,port" property. Signed-off-by: Chris Packham --- Notes: Changes in v5: - Add back reg property to mdio-controller node - Make unit address in the node name required - Andrew suggested perhaps doing away with the realtek,port property and providing the overall mapping via an array of phandles. I've explored this a little, it is doable but I'm not sure it actually makes things any clearer when the portmap has gaps so I haven't made this change. Changes in v4: - Model the MDIO controller with the buses as child nodes. We still need to deal with the switch port number so this is represented with the "realtek,port" property which needs to be added to the MDIO bus children (i.e. the PHYs) - Because the above is quite a departure from earlier I've dropped the r-by Changes in v3: - Add r-by from Connor Changes in v2: - None .../bindings/net/realtek,rtl9301-mdio.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml new file mode 100644 index 000000000000..80456dc791eb --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL9300 MDIO Controller + +maintainers: + - Chris Packham + +properties: + compatible: + oneOf: + - items: + - enum: + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - const: realtek,rtl9301-mdio + - const: realtek,rtl9301-mdio + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + '^mdio-bus@[0-4]$': + $ref: mdio.yaml# + + properties: + reg: + maxItems: 1 + + required: + - reg + + patternProperties: + '^ethernet-phy@[a-f0-9]+$': + type: object + $ref: ethernet-phy.yaml# + + properties: + realtek,port: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The MDIO communication on the RTL9300 is abstracted by the switch. At + the software level communication uses the switch port to address the + PHY with the actual MDIO bus and address having been setup via the + parent mdio-bus and reg property. + + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + realtek,port = <0>; + }; + }; + + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + realtek,port = <8>; + }; + }; + }; From patchwork Fri Jan 31 01:01:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13955038 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90BCF14AA9 for ; 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Fri, 31 Jan 2025 14:02:18 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 391B713EE2B; Fri, 31 Jan 2025 14:02:18 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 37BA72809C0; Fri, 31 Jan 2025 14:02:18 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v5 2/4] dt-bindings: mfd: Add MDIO interface to rtl9301-switch Date: Fri, 31 Jan 2025 14:01:49 +1300 Message-ID: <20250131010151.2527688-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> References: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=679c211a a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=VdSt8ZQiCzkA:10 a=5cQCLpD8v2SGHUEG_dEA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat The MDIO controller is part of the switch on the RTL9300 family of devices. Add a $ref to the mfd binding for these devices. Signed-off-by: Chris Packham --- Notes: This patch is dependent on "dt-bindings: net: Add Realtek MDIO controller" which adds the realtek,rtl9301-mdio.yaml binding. Changes in v5: - Note dependency on realtek,rtl9301-mdio.yaml patch - Add back reg property to the mdio-controller node. Changes in v4: - There is a single MDIO controller that has MDIO buses as children Changes in v3: - None Changes in v2: - None .../bindings/mfd/realtek,rtl9301-switch.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml index f053303ab1e6..89e10213a4ee 100644 --- a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml +++ b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml @@ -28,6 +28,9 @@ properties: reg: maxItems: 1 + mdio-controller: + $ref: /schemas/net/realtek,rtl9301-mdio.yaml# + '#address-cells': const: 1 @@ -41,6 +44,10 @@ patternProperties: 'i2c@[0-9a-f]+$': $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# + 'mdio-controller@[0-9a-f]+$': + $ref: /schemas/net/realtek,rtl9301-mdio.yaml# + + required: - compatible - reg @@ -110,5 +117,27 @@ examples: }; }; }; + + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + realtek,port = <1>; + }; + ethernet-phy@1 { + reg = <1>; + realtek,port = <0>; + }; + }; + }; }; From patchwork Fri Jan 31 01:01:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13955039 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B432FEED8 for ; Fri, 31 Jan 2025 01:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738285346; cv=none; b=ueR131sArVqPkwnTblmwGshneegJBwyO/u50yVJ5y8PSABDTJJqHBXCUBHZZpdWnkbFsmkPdla/1GxE2SET83aKr6Wi11WDm9TV2Q8AwfobayhPUj6ppPFNHyVfXWZsk0piLunoKwr6VNLNijBU+2wWEexI2m6CyKj4HHcUxvJo= ARC-Message-Signature: i=1; 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Fri, 31 Jan 2025 14:02:23 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738285343; bh=0s2xXq8yCjSIS4B0n1JfFfFBX2JwNCWqC8BfMIqxobM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZOQPZo/xnkaTtrzKBykLYvhdLzwc9CNs428GSGfN5M8RDExvcCj+ERTmmq7iaLtpt cYYNw8IZ0f68chAbld/B3skedRiPoiZYzpRqSr6F3+pm5Do86aydfoTj+yOcXJ3b0f WLFD2vSmRelwiu9qaYh55CaPXejwYSIBGFUTD+Xmi6DZjQgakRmoix7wEp3VDXii1D A3S1AoiNP3+zlqsVlIDJeku7KRT1bnBRUCF8ppPRd4dHJPwe4MhQgdvswLe/0eIdZZ 32zd5bIlS7/2YClDliFW1xInqvJR7NnXMWrvp3VwKfTmeGXGGHp/KMrCK1fQnMIWbm lXKeZQ0SCASoQ== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 31 Jan 2025 14:02:23 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 4B12D13EE2B; Fri, 31 Jan 2025 14:02:23 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 491AC2809C0; Fri, 31 Jan 2025 14:02:23 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v5 3/4] mips: dts: realtek: Add MDIO controller Date: Fri, 31 Jan 2025 14:01:50 +1300 Message-ID: <20250131010151.2527688-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> References: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=679c211f a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=VdSt8ZQiCzkA:10 a=Vd_wJYyKU8c0xNhbhIwA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add a device tree node for the MDIO controller on the RTL9300 chips. Signed-off-by: Chris Packham --- Notes: Changes in v5: - Add reg property to mdio-controller Changes in v4: - Have a single mdio-controller with the individual buses as child nodes Changes in v3: - None Changes in v2: - None arch/mips/boot/dts/realtek/rtl930x.dtsi | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index f2e57ea3a60c..101bab72a95f 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -69,6 +69,39 @@ i2c1: i2c@388 { #size-cells = <0>; status = "disabled"; }; + + mdio_controller: mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio0: mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio1: mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio2: mdio-bus@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio3: mdio-bus@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; soc: soc@18000000 { From patchwork Fri Jan 31 01:01:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13955040 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09D4D250F8 for ; Fri, 31 Jan 2025 01:02:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738285354; cv=none; b=Rx+DdS8KFpSyV3mZ2acbBQplpw9wYG7G4r7kC9AMQK4qefKolxf8fiP2cnEjxakBLwK4AJ8T9P4YTeIb76bLu2/6cOCMrlF5u+sVWfEQnJ8Whyp1vsDeKckQzGTphSUPEd7pFZGTI2DryzUmmnBC8AhMf6aR4fTdStJYem8FqWY= ARC-Message-Signature: i=1; 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Fri, 31 Jan 2025 14:02:30 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1738285350; bh=BjTHw9MdM9s5UjZintrwqlYxmBfW2wHuQ18gd2IymiQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N7hw4pZQdK3km4/h1ybtAQh31+r0KyfaFpo2LqlSNM3kIy7twEjbnsJPgarJ69cIZ 70CA3FrUe+LSROpXaEaS/+sUA0U8I5ky+HZtCFwbBQVMW3t9ZirI7NtDiRM7imUoSS QN8pxRnplUPT2FpmgQGMKIvSBp4rZfTwFUN37KkAsgJnupAq59hw8xws2pC7li5oGl jFKegjIES5W0nSlEMZbTuI0Ki0l1D3v19bOqDK16pYlhMohZs4vZeLFfZkDeGIPyCe Nve2+/jb4pVVpqzNMOwHGjlUXjIP32JwtBTqto1fkHvygc6OBBhG3/jXxPeeKANMx5 lgYPgDpxwl1hg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Fri, 31 Jan 2025 14:02:30 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 6451213EE2B; Fri, 31 Jan 2025 14:02:30 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 6284E2809C0; Fri, 31 Jan 2025 14:02:30 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, sander@svanheule.net, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v5 4/4] net: mdio: Add RTL9300 MDIO driver Date: Fri, 31 Jan 2025 14:01:51 +1300 Message-ID: <20250131010151.2527688-5-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> References: <20250131010151.2527688-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=QNvLRRLL c=1 sm=1 tr=0 ts=679c2126 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=VdSt8ZQiCzkA:10 a=lorn_ZLQiSlGyWFY7CwA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add a driver for the MDIO controller on the RTL9300 family of Ethernet switches with integrated SoC. There are 4 physical SMI interfaces on the RTL9300 however access is done using the switch ports. The driver takes the MDIO bus hierarchy from the DTS and uses this to configure the switch ports so they are associated with the correct PHY. This mapping is also used when dealing with software requests from phylib. Signed-off-by: Chris Packham --- Notes: Changes in v5: - Reword out of date comment - Use GENMASK/FIELD_PREP where appropriate - Introduce port validity bitmap. - Use more obvious names for PHY_CTRL_READ/WRITE and PHY_CTRL_TYPE_C45/C22 Changes in v4: - rename to realtek-rtl9300 - s/realtek_/rtl9300_/ - add locking to support concurrent access - The dtbinding now represents the MDIO bus hierarchy so we consume this information and use it to configure the switch port to MDIO bus+addr. Changes in v3: - Fix (another) off-by-one error Changes in v2: - Add clause 22 support - Remove commented out code - Formatting cleanup - Set MAX_PORTS correctly for MDIO interface - Fix off-by-one error in pn check drivers/net/mdio/Kconfig | 7 + drivers/net/mdio/Makefile | 1 + drivers/net/mdio/mdio-realtek-rtl9300.c | 436 ++++++++++++++++++++++++ 3 files changed, 444 insertions(+) create mode 100644 drivers/net/mdio/mdio-realtek-rtl9300.c diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig index 4a7a303be2f7..058fcdaf6c18 100644 --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig @@ -185,6 +185,13 @@ config MDIO_IPQ8064 This driver supports the MDIO interface found in the network interface units of the IPQ8064 SoC +config MDIO_REALTEK_RTL9300 + tristate "Realtek RTL9300 MDIO interface support" + depends on MACH_REALTEK_RTL || COMPILE_TEST + help + This driver supports the MDIO interface found in the Realtek + RTL9300 family of Ethernet switches with integrated SoC. + config MDIO_REGMAP tristate help diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile index 1015f0db4531..c23778e73890 100644 --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o +obj-$(CONFIG_MDIO_REALTEK_RTL9300) += mdio-realtek-rtl9300.o obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o diff --git a/drivers/net/mdio/mdio-realtek-rtl9300.c b/drivers/net/mdio/mdio-realtek-rtl9300.c new file mode 100644 index 000000000000..d2ee66890caf --- /dev/null +++ b/drivers/net/mdio/mdio-realtek-rtl9300.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MDIO controller for RTL9300 switches with integrated SoC. + * + * The MDIO communication is abstracted by the switch. At the software level + * communication uses the switch port to address the PHY. We work out the + * mapping based on the MDIO bus described in device tree and the realtek,port + * property. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMI_GLB_CTRL 0xca00 +#define GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf)) +#define SMI_PORT0_15_POLLING_SEL 0xca08 +#define SMI_POLL_CTRL 0xca90 +#define SMI_ACCESS_PHY_CTRL_0 0xcb70 +#define SMI_ACCESS_PHY_CTRL_1 0xcb74 +#define PHY_CTRL_WRITE BIT(2) +#define PHY_CTRL_READ 0 +#define PHY_CTRL_TYPE_C45 BIT(1) +#define PHY_CTRL_TYPE_C22 0 +#define PHY_CTRL_CMD BIT(0) +#define PHY_CTRL_FAIL BIT(25) +#define SMI_ACCESS_PHY_CTRL_2 0xcb78 +#define SMI_ACCESS_PHY_CTRL_3 0xcb7c +#define SMI_PORT0_5_ADDR_CTRL 0xcb80 + +#define MAX_PORTS 28 +#define MAX_SMI_BUSSES 4 +#define MAX_SMI_ADDR 0x1f + +struct rtl9300_mdio_priv { + struct regmap *regmap; + struct mutex lock; /* protect HW access */ + DECLARE_BITMAP(valid_ports, MAX_PORTS); + u8 smi_bus[MAX_PORTS]; + u8 smi_addr[MAX_PORTS]; + bool smi_bus_is_c45[MAX_SMI_BUSSES]; + struct mii_bus *bus[MAX_SMI_BUSSES]; +}; + +struct rtl9300_mdio_chan { + struct rtl9300_mdio_priv *priv; + u8 mdio_bus; +}; + +static int rtl9300_mdio_phy_to_port(struct mii_bus *bus, int phy_id) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + int i; + + for (i = find_first_bit(priv->valid_ports, MAX_PORTS); + i < MAX_PORTS; + i = find_next_bit(priv->valid_ports, MAX_PORTS, i + 1)) + if (priv->smi_bus[i] == chan->mdio_bus && + priv->smi_addr[i] == phy_id) + return i; + + return -ENOENT; +} + +static int rtl9300_mdio_wait_ready(struct rtl9300_mdio_priv *priv) +{ + struct regmap *regmap = priv->regmap; + u32 val; + + lockdep_assert_held(&priv->lock); + + return regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 1000); +} + +static int rtl9300_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, port << 16); + if (err) + return err; + + val = FIELD_PREP(GENMASK(24, 20), regnum) | + FIELD_PREP(GENMASK(19, 15), 0x1f) | + FIELD_PREP(GENMASK(14, 3), 0xfff) | + PHY_CTRL_READ | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD; + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val); + if (err) + return err; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return FIELD_GET(GENMASK(15, 0), val); +} + +static int rtl9300_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port)); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, value << 16); + if (err) + return err; + + val = FIELD_PREP(GENMASK(24, 20), regnum) | + FIELD_PREP(GENMASK(19, 15), 0x1f) | + FIELD_PREP(GENMASK(14, 3), 0xfff) | + PHY_CTRL_WRITE | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD; + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val); + if (err) + return err; + + err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int rtl9300_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + val = FIELD_PREP(GENMASK(31, 16), port); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val); + if (err) + return err; + + val = FIELD_PREP(GENMASK(20, 16), dev_addr) | + FIELD_PREP(GENMASK(15, 0), regnum); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_READ | PHY_CTRL_TYPE_C45 | PHY_CTRL_CMD); + if (err) + return err; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return FIELD_GET(GENMASK(15, 0), val); +} + +static int rtl9300_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, + int regnum, u16 value) +{ + struct rtl9300_mdio_chan *chan = bus->priv; + struct rtl9300_mdio_priv *priv = chan->priv; + struct regmap *regmap = priv->regmap; + int port; + u32 val; + int err; + + guard(mutex)(&priv->lock); + + port = rtl9300_mdio_phy_to_port(bus, phy_id); + if (port < 0) + return port; + + err = rtl9300_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port)); + if (err) + return err; + + val = FIELD_PREP(GENMASK(31, 16), value); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val); + if (err) + return err; + + val = FIELD_PREP(GENMASK(20, 16), dev_addr) | + FIELD_PREP(GENMASK(15, 0), regnum); + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val); + if (err) + return err; + + err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_TYPE_C45 | PHY_CTRL_WRITE | PHY_CTRL_CMD); + if (err) + return err; + + err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int rtl9300_mdiobus_init(struct rtl9300_mdio_priv *priv) +{ + u32 glb_ctrl_mask = 0, glb_ctrl_val = 0; + struct regmap *regmap = priv->regmap; + u32 port_addr[5] = { 0 }; + u32 poll_sel[2] = { 0 }; + int i, err; + + /* Associate the port with the SMI interface and PHY */ + for (i = find_first_bit(priv->valid_ports, MAX_PORTS); + i < MAX_PORTS; + i = find_next_bit(priv->valid_ports, MAX_PORTS, i + 1)) { + int pos; + + pos = (i % 6) * 5; + port_addr[i / 6] |= (priv->smi_addr[i] & 0x1f) << pos; + + pos = (i % 16) * 2; + poll_sel[i / 16] |= (priv->smi_bus[i] & 0x3) << pos; + } + + /* Stop the PPU from interfering */ + err = regmap_update_bits(regmap, SMI_POLL_CTRL, priv->valid_ports, 0); + if (err) + return err; + + /* Put the interfaces into C45 mode if required */ + glb_ctrl_mask = GENMASK(19, 16); + for (i = 0; i < MAX_SMI_BUSSES; i++) + if (priv->smi_bus_is_c45[i]) + glb_ctrl_val |= GLB_CTRL_INTF_SEL(i); + + err = regmap_bulk_write(regmap, SMI_PORT0_5_ADDR_CTRL, + port_addr, 5); + if (err) + return err; + + err = regmap_bulk_write(regmap, SMI_PORT0_15_POLLING_SEL, + poll_sel, 2); + if (err) + return err; + + err = regmap_update_bits(regmap, SMI_GLB_CTRL, + glb_ctrl_mask, glb_ctrl_val); + if (err) + return err; + + return 0; +} + +static int rtl9300_mdiobus_probe_one(struct device *dev, struct rtl9300_mdio_priv *priv, + struct fwnode_handle *node) +{ + struct rtl9300_mdio_chan *chan; + struct fwnode_handle *child; + struct mii_bus *bus; + u32 mdio_bus; + int err; + + err = fwnode_property_read_u32(node, "reg", &mdio_bus); + if (err) + return err; + + if (mdio_bus >= MAX_SMI_BUSSES) + return dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", mdio_bus); + + fwnode_for_each_child_node(node, child) { + u32 addr; + u32 pn; + + err = fwnode_property_read_u32(child, "reg", &addr); + if (err) + return err; + + err = fwnode_property_read_u32(child, "realtek,port", &pn); + if (err) + return err; + + if (pn >= MAX_PORTS) + return dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn); + + if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45")) + priv->smi_bus_is_c45[mdio_bus] = true; + + bitmap_set(priv->valid_ports, pn, 1); + priv->smi_bus[pn] = mdio_bus; + priv->smi_addr[pn] = addr; + } + + bus = devm_mdiobus_alloc_size(dev, sizeof(*chan)); + if (!bus) + return -ENOMEM; + + bus->name = "Reaktek Switch MDIO Bus"; + bus->read = rtl9300_mdio_read_c22; + bus->write = rtl9300_mdio_write_c22; + bus->read_c45 = rtl9300_mdio_read_c45; + bus->write_c45 = rtl9300_mdio_write_c45; + bus->parent = dev; + chan = bus->priv; + chan->mdio_bus = mdio_bus; + chan->priv = priv; + + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus); + + err = devm_of_mdiobus_register(dev, bus, to_of_node(node)); + if (err) + return dev_err_probe(dev, err, "cannot register MDIO bus\n"); + + return 0; +} + +static int rtl9300_mdiobus_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rtl9300_mdio_priv *priv; + struct fwnode_handle *child; + int err; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + err = devm_mutex_init(dev, &priv->lock); + if (err) + return err; + + priv->regmap = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + platform_set_drvdata(pdev, priv); + + device_for_each_child_node(dev, child) { + err = rtl9300_mdiobus_probe_one(dev, priv, child); + if (err) + return err; + } + + err = rtl9300_mdiobus_init(priv); + if (err) + return dev_err_probe(dev, err, "failed to initialise MDIO bus controller\n"); + + return 0; +} + +static const struct of_device_id rtl9300_mdio_ids[] = { + { .compatible = "realtek,rtl9301-mdio" }, + {} +}; +MODULE_DEVICE_TABLE(of, rtl9300_mdio_ids); + +static struct platform_driver rtl9300_mdio_driver = { + .probe = rtl9300_mdiobus_probe, + .driver = { + .name = "mdio-rtl9300", + .of_match_table = rtl9300_mdio_ids, + }, +}; + +module_platform_driver(rtl9300_mdio_driver); + +MODULE_DESCRIPTION("RTL9300 MDIO driver"); +MODULE_LICENSE("GPL");