From patchwork Fri Jan 31 09:22:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B2A4C0218D for ; Fri, 31 Jan 2025 09:24:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEX-0008GB-8Y; Fri, 31 Jan 2025 04:22:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEU-0008FJ-Rh for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:38 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnET-0004DE-D5 for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:38 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 854FE5C5CD4; Fri, 31 Jan 2025 09:21:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1425DC4CEE2; Fri, 31 Jan 2025 09:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315354; bh=kFS5JPLZ6Yq0LhIiT+AHVHk3BwDkleBFMtJ92/ovT10=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mQKh1IkpLJcp3Ef5EuOEKI9SRvRTqp3kJnD9xDVrX14rENwlNQNs5cmAuXIz0ivXc a1IoyhIhBw12+K5Y1ui3Cdczs23jRojnZDahIFqFdeq0XiTAIsJ+16mK9bKEzaVhsr ggM06A0age1u+KyfLdyJ88pR+2P/9ChaGd1HWxKIhmxERCoP0bcpq9mAxkilQ11heT v1BfPax/ijZNL4qJzVqK/BzbUK4DCvVULMBY7pLRN1il/5qwU5AItBs/J1VSzRsXVt BzUs+/qXXMx7+uzIFXLfBWjghLcFERbP5/W1RRgsPv504HpCuHJPQUPxK8bctjk8Tx F2CzD/n2stlRg== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 1/9] MAINTAINERS: Add myself as HPPA maintainer Date: Fri, 31 Jan 2025 10:22:21 +0100 Message-ID: <20250131092229.38232-2-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Since I contribute quite some code to hppa, I'd like to step up and become the secondary maintainer for HPPA beside Richard. Additionally change status of hppa machines to maintained as I will take care of them. Signed-off-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7be3d8f431..dbf39cfbb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -251,6 +251,7 @@ F: target/hexagon/gen_idef_parser_funcs.py HPPA (PA-RISC) TCG CPUs M: Richard Henderson +M: Helge Deller S: Maintained F: target/hppa/ F: disas/hppa.c @@ -1188,8 +1189,8 @@ HP-PARISC Machines ------------------ HP B160L, HP C3700 M: Richard Henderson -R: Helge Deller -S: Odd Fixes +M: Helge Deller +S: Maintained F: configs/devices/hppa-softmmu/default.mak F: hw/display/artist.c F: hw/hppa/ From patchwork Fri Jan 31 09:22:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32337C0218F for ; Fri, 31 Jan 2025 09:24:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEX-0008GX-Q6; Fri, 31 Jan 2025 04:22:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEV-0008FQ-4Z for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:39 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnET-0004DD-HK for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:38 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 26B325C5D60; Fri, 31 Jan 2025 09:21:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8DC8C4CED1; Fri, 31 Jan 2025 09:22:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315355; bh=JbHKUaoOT21JZo4ZqtXrin1/f4CIQEzf3APbV087HeE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fbz8aamCJdN9ybvtox5PpXO39XTdnRSHiqTeTRr5Jy7rx+6OktptMx/o5aYK1haDj 90s4UAdmw10vn9Tyqq1LYQdtyvKeXlG7SJsQfGWaqSG4IHY329Qw/0AP8r6Qpjw2Pm Koa8Oc/AbmdoQI70PnCY5tp3tlK0OjioEofIkXdMxG6yaiYHwyEb5tChZqGXq17QY8 a4FLKR2BQL6LYsQTqbxm+NOaIMhUH0IQbRf3pJsViKQbA7/z3RtlLP7n+8JM5ZjyN8 MfVjba7RcEYNJoxAZ47jpRGWlNQwUW19x/gFP0NjUxW9TD5f0eS26fI5PwIGYKjdde 65PW5s0S0Arug== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 2/9] hppa: Sync contents of hppa_hardware.h header file with SeaBIOS-hppa Date: Fri, 31 Jan 2025 10:22:22 +0100 Message-ID: <20250131092229.38232-3-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -83 X-Spam_score: -8.4 X-Spam_bar: -------- X-Spam_report: (-8.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The hppa_hardware.h header file holds many constants for addresses and offsets which are needed while building the firmware (SeaBIOS-hppa) and while setting up the virtual machine in QEMU. This patch brings it in sync between both source code repositories. Signed-off-by: Helge Deller Acked-by: Richard Henderson --- hw/hppa/hppa_hardware.h | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h index a276240967..21c777cba6 100644 --- a/hw/hppa/hppa_hardware.h +++ b/hw/hppa/hppa_hardware.h @@ -6,6 +6,11 @@ #define FIRMWARE_START 0xf0000000 #define FIRMWARE_END 0xf0800000 +#define FIRMWARE_HIGH 0xfffffff0 /* upper 32-bits of 64-bit firmware address */ + +#define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ + +#define MEM_PDC_ENTRY 0x4800 /* PDC entry address */ #define DEVICE_HPA_LEN 0x00100000 @@ -18,6 +23,7 @@ #define LASI_UART_HPA 0xffd05000 #define LASI_SCSI_HPA 0xffd06000 #define LASI_LAN_HPA 0xffd07000 +#define LASI_RTC_HPA 0xffd09000 #define LASI_LPT_HPA 0xffd02000 #define LASI_AUDIO_HPA 0xffd04000 #define LASI_PS2KBD_HPA 0xffd08000 @@ -27,16 +33,23 @@ #define CPU_HPA 0xfffb0000 #define MEMORY_HPA 0xfffff000 -#define PCI_HPA DINO_HPA /* PCI bus */ #define IDE_HPA 0xf9000000 /* Boot disc controller */ +#define ASTRO_HPA 0xfed00000 +#define ELROY0_HPA 0xfed30000 +#define ELROY2_HPA 0xfed32000 +#define ELROY8_HPA 0xfed38000 +#define ELROYc_HPA 0xfed3c000 +#define ASTRO_MEMORY_HPA 0xfed10200 + +#define SCSI_HPA 0xf1040000 /* emulated SCSI, needs to be in f region */ /* offsets to DINO HPA: */ #define DINO_PCI_ADDR 0x064 #define DINO_CONFIG_DATA 0x068 #define DINO_IO_DATA 0x06c -#define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) -#define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) +#define PORT_PCI_CMD hppa_port_pci_cmd +#define PORT_PCI_DATA hppa_port_pci_data #define FW_CFG_IO_BASE 0xfffa0000 @@ -46,9 +59,24 @@ #define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */ #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ +#define CR_PSW_DEFAULT 6 /* used by SeaBIOS & QEMU for default PSW */ #define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */ #define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */ -#define RAM_MAP_HIGH 0x0100000000 /* memory above 3.75 GB is mapped here */ +#define ASTRO_BUS_MODULE 0x0a /* C3700: 0x0a, others maybe 0 ? */ + +/* ASTRO Memory and I/O regions */ +#define ASTRO_BASE_HPA 0xfffed00000 +#define ELROY0_BASE_HPA 0xfffed30000 /* ELROY0_HPA */ + +#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ + +#define LMMIO_DIRECT0_BASE 0x300 +#define LMMIO_DIRECT0_MASK 0x308 +#define LMMIO_DIRECT0_ROUTE 0x310 + +/* space register hashing */ +#define HPPA64_DIAG_SPHASH_ENABLE 0x200 /* DIAG_SPHASH_ENAB (bit 54) */ +#define HPPA64_PDC_CACHE_RET_SPID_VAL 0xfe0 /* PDC return value on 64-bit CPU */ #endif From patchwork Fri Jan 31 09:22:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D42BC0218F for ; Fri, 31 Jan 2025 09:23:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEY-0008Gi-GH; Fri, 31 Jan 2025 04:22:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEW-0008G2-Fu for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:40 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEU-0004DR-SN for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:40 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id BB4325C5D61; Fri, 31 Jan 2025 09:21:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49DAFC4CED1; Fri, 31 Jan 2025 09:22:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315357; bh=8JVAwIADkG+JebhPJNIZp30+tTso8du5rqRv5ZLqBuI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FH7VA9l0HCjjfwi9FUD2zyFUl/LzHhaaAwR8xhK7gayTdncx/Dl3qdcZbtLd76JYA JiE0VK84BEk51HIpUwZE0bPV8eKmGvVCXyYYdvrL7dxJGlaLpCUsxkj3zQ0iV5rF02 z25TwYZ+4F63lCLLwN+RVWzi3riYvjP16p2xTmDvRm1YvqdBt7uYym9Wjf/KJBk8Lw gFVMqqOUbxEhuVxdCkR4wjvojVmmq/RDIQAXIFDcOdLhKrJ3cIAr7IJfI+Lju62G1k LEFFwUHm9LHwThlYPvSwiygBki+Aiam2DHiCOjMNYfVNUKA96MQ/Dch6fj8k5aMSvZ qsHF5eGBW+mVw== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 3/9] disas/hppa: implement mfdiag/mtdiag disassembly Date: Fri, 31 Jan 2025 10:22:23 +0100 Message-ID: <20250131092229.38232-4-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The various PA-RISC CPUs implement different CPU-specific diag instructions (mfdiag, mtdiag, mfcpu, mtcpu, ...) to access CPU-internal diagnose/configuration registers, e.g. for cache control, managing space register hashing, control front panel LEDs and read status of the hardware reset button. Those instructions are mostly undocumented, but are used by ODE, HP-UX and Linux. This patch adds some neccessary instructions for PCXL and PCXU CPUs. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- disas/hppa.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/disas/hppa.c b/disas/hppa.c index 49e2231ae6..2b58434966 100644 --- a/disas/hppa.c +++ b/disas/hppa.c @@ -606,7 +606,7 @@ struct pa_opcode In the args field, the following characters are unused: - ' " - / 34 6789:; ' + ' " - / 34 678 :; ' '@ C M [\] ' '` e g } ' @@ -650,6 +650,7 @@ Also these: | 6 bit field length at 19,27:31 (fixed extract/deposit) A 13 bit immediate at 18 (to support the BREAK instruction) ^ like b, but describes a control register + 9 like b, but describes a diagnose register ! sar (cr11) register D 26 bit immediate at 31 (to support the DIAG instruction) $ 9 bit immediate at 28 (to support POPBTS) @@ -1322,13 +1323,19 @@ static const struct pa_opcode pa_opcodes[] = { "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +/* completely undocumented, but used by ODE, HP-UX and Linux: */ +{ "mfcpu_pcxu", 0x140008a0, 0xfc9fffe0, "9,t", pa20, 0}, /* PCXU: mfdiag */ +{ "mtcpu_pcxu", 0x14001840, 0xfc00ffff, "x,9", pa20, 0}, + /* These may be specific to certain versions of the PA. Joel claimed they were 72000 (7200?) specific. However, I'm almost certain the mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mfcpu_c", 0x14000600, 0xfc00ffff, "9,x", pa10, 0}, /* PCXL: for dr0 and dr8 only */ +{ "mfcpu_t", 0x14001400, 0xfc9fffe0, "9,t", pa10, 0}, /* PCXL: all dr except dr0 and dr8 */ +{ "mtcpu_pcxl", 0x14000240, 0xfc00ffff, "x,9", pa11, 0}, /* PCXL: mtcpu for dr0 and dr8 */ { "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, { "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, @@ -1336,6 +1343,9 @@ static const struct pa_opcode pa_opcodes[] = { "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, { "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, +/* instead of showing D only, show all other registers too */ +{ "diag", 0x14000000, 0xfc000000, "D x,9,t", pa10, 0}, + /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ { "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, @@ -1801,6 +1811,12 @@ fput_creg (unsigned reg, disassemble_info *info) (*info->fprintf_func) (info->stream, "%s", control_reg[reg]); } +static void +fput_dreg (unsigned reg, disassemble_info *info) +{ + (*info->fprintf_func) (info->stream, "dr%d", reg); +} + /* Print constants with sign. */ static void @@ -2007,6 +2023,9 @@ print_insn_hppa (bfd_vma memaddr, disassemble_info *info) case '^': fput_creg (GET_FIELD (insn, 6, 10), info); break; + case '9': + fput_dreg (GET_FIELD (insn, 6, 10), info); + break; case 't': fput_reg (GET_FIELD (insn, 27, 31), info); break; From patchwork Fri Jan 31 09:22:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955153 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C4B2C0218D for ; Fri, 31 Jan 2025 09:24:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEZ-0008H1-Je; Fri, 31 Jan 2025 04:22:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEX-0008GY-R5 for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:41 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEW-0004Di-ES for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:41 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 5BBA15C5CD4; Fri, 31 Jan 2025 09:21:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DEE64C4CED1; Fri, 31 Jan 2025 09:22:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315359; bh=wtPYEkp/rYjrO4/L11LpwqkfMFGmuvFU+26iDChJ36Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eQBn0m2RQDo8qX+waoiybpG1odLY5VB/hgtsJLb0J8b70ZRh6zee6WyYb4cuF7HEF +brNDB2XeBnzoG7egd22D77a+PdPMGCR3vP7rmnPNFkj8/GlP0KsQ9Ywn3+94ovadZ 1OyfrCr8KEIKbBB1+PzTTGzm957kvg3NbaVc12A2qx7kXms9nhjXgD9csNRiT9KMY7 Xb66h3z18IUUoHjdBDsqx6IMtf4ZyUS5v0E6crFW5sO4yVCW4gH0t+WC/bbg0m1RYA EQBQqZZHo9ADMgHmbP310FLi2So/QxyiS/4te+nfweJDmHidvb87enJ3FOJVJrV/J8 DlYdKtNvCXUoQ== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 4/9] target/hppa: Add CPU diagnose registers Date: Fri, 31 Jan 2025 10:22:24 +0100 Message-ID: <20250131092229.38232-5-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -83 X-Spam_score: -8.4 X-Spam_bar: -------- X-Spam_report: (-8.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Add the diagnose registers (%dr) to the CPUArchState. Those are mostly undocumented and control cache behaviour, memory behaviour, reset button management and many other related internal CPU things. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/machine.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index beea42d105..b858986c41 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -232,6 +232,7 @@ typedef struct CPUArchState { target_ulong cr[32]; /* control registers */ target_ulong cr_back[2]; /* back of cr17/cr18 */ target_ulong shadow[7]; /* shadow registers */ + target_ulong dr[32]; /* diagnose registers */ /* * During unwind of a memory insn, the base register of the address. diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 211bfcf640..bb47a2e689 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -198,6 +198,7 @@ static const VMStateField vmstate_env_fields[] = { VMSTATE_UINT64(iasq_b, CPUHPPAState), VMSTATE_UINT32(fr0_shadow, CPUHPPAState), + VMSTATE_UINT64_ARRAY(dr, CPUHPPAState, 32), VMSTATE_END_OF_LIST() }; @@ -208,8 +209,8 @@ static const VMStateDescription * const vmstate_env_subsections[] = { static const VMStateDescription vmstate_env = { .name = "env", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .fields = vmstate_env_fields, .subsections = vmstate_env_subsections, }; From patchwork Fri Jan 31 09:22:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47F5CC0218F for ; Fri, 31 Jan 2025 09:24:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEa-0008HN-Mm; Fri, 31 Jan 2025 04:22:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEZ-0008Gy-Fx for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:43 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEX-0004Du-QE for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:43 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id EFB495C5D60; Fri, 31 Jan 2025 09:22:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F7CBC4CEE1; Fri, 31 Jan 2025 09:22:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315360; bh=EdUmbIHS6wsR+QKUpjXCHpozaxkbBLR0Vx1ZIKvUOQA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HOvOXkecpRaa47P+RjpFqXS8ZIVrDDqxSjx2HXoTdNMONKgpep0PK+w2rOMuj3tno 5hEX2OJ7fc1qyhSaX3KQBcWcf9TeMSqk+BV+slHHWlxLpnNx+ClLgzKbSamTZubDUD P/3i8Snkajpusr8kBH5nkaxouROxAElJIf9YnKt7EkkEjtkJ4joRY0ZunSesQP91Nh 0BJVNLOxlReKkj8LfpoqlppxAqaqwr1P6p0fdWhQ16Br2vcNv3naxSFj0O8JfrwN0C izjq63rfadUR03EntwMCC+Dz0aqw/zjVRARL5fk98c/8lXzOy5hgci1MwM/Aoo0lxw DmUVMErKnZcXA== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 5/9] target/hppa: Drop diag_getshadowregs_pa2 and diag_putshadowregs_pa2 Date: Fri, 31 Jan 2025 10:22:25 +0100 Message-ID: <20250131092229.38232-6-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in commit 3bdf20819e68 based on some analysis of ODE code, but now they conflict with the generic mfdiag/mtdiag instructions. I believe the former analysis was wrong, so remove them again. Note that all diag instructions are badly documented, so most things are based on reverse engineering and thus may be wrong. Signed-off-by: Helge Deller Fixes: 3bdf20819e68 ("target/hppa: Add diag instructions to set/restore shadow registers") Reviewed-by: Richard Henderson --- target/hppa/insns.decode | 2 -- target/hppa/translate.c | 10 ---------- 2 files changed, 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 71074a64c1..527c453443 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -646,8 +646,6 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 # For 64-bit PA8700 (PCX-W2) - diag_getshadowregs_pa2 000101 00 0111 1000 0001 1000 0100 0000 - diag_putshadowregs_pa2 000101 00 0111 0000 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dc04f9f3c0..30fba5297a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4593,21 +4593,11 @@ static bool trans_diag_getshadowregs_pa1(DisasContext *ctx, arg_empty *a) return !ctx->is_pa20 && do_getshadowregs(ctx); } -static bool trans_diag_getshadowregs_pa2(DisasContext *ctx, arg_empty *a) -{ - return ctx->is_pa20 && do_getshadowregs(ctx); -} - static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) { return !ctx->is_pa20 && do_putshadowregs(ctx); } -static bool trans_diag_putshadowregs_pa2(DisasContext *ctx, arg_empty *a) -{ - return ctx->is_pa20 && do_putshadowregs(ctx); -} - static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); From patchwork Fri Jan 31 09:22:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E17AC0218F for ; Fri, 31 Jan 2025 09:23:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEc-0008Hs-8C; Fri, 31 Jan 2025 04:22:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEa-0008HM-Jx for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:44 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEZ-0004E5-8s for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:44 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 03411A41ACF; Fri, 31 Jan 2025 09:20:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 200EAC4CEE2; Fri, 31 Jan 2025 09:22:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315362; bh=TTZQ3gdFh6H6hJ0o3arXtbhMAP/Olm8bzx/GKUy+TWI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LYRglHM+qHo4ZR9Cqky6KVVOesKzXlu3rtLRDTMTTI4j0sVJ8Tzftvm8qmbCjrTvI egpCH5vtOT2WhubQX3w6rDlnHvNEeBSjCjO7ge+07Ebp23oGRLgO9ZsGz5nphgynON DWj4knFNEOoIhD4YGoouls1LC9fJ4tMT72oavB5jEbBo9FuljAZN/eD63AYGVInWey gABcbjqO3YOlCkQuBbMBmWvSCHoO1zDrMtvLCNxrAQBYXGW8w0pQ5GslhArQGlL0hz Fmu2KeoxgeabAhghYt3huD1Py2LytLS/DabCFMDvz+LRMkrGMyk2UuATsS+lygqIcv 6cMVXtjFnKTzg== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 6/9] target/hppa: Add instruction decoding for mfdiag and mtdiag Date: Fri, 31 Jan 2025 10:22:26 +0100 Message-ID: <20250131092229.38232-7-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag instructions which modify the diagnose registers. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/insns.decode | 4 ++++ target/hppa/translate.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 527c453443..4eaac750ea 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -644,8 +644,12 @@ xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 # For 32-bit PA-7300LC (PCX-L2) diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 + diag_mfdiag 000101 dr:5 rt:5 0000 0110 0000 0000 + diag_mtdiag 000101 dr:5 r1:5 0001 0110 0000 0000 # For 64-bit PA8700 (PCX-W2) + diag_mfdiag 000101 dr:5 0 0000 0000 1000 101 rt:5 + diag_mtdiag 000101 dr:5 r1:5 0001 1000 0100 0000 ] diag_unimp 000101 i:26 } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 30fba5297a..7b9d3deb39 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4598,6 +4598,26 @@ static bool trans_diag_putshadowregs_pa1(DisasContext *ctx, arg_empty *a) return !ctx->is_pa20 && do_putshadowregs(ctx); } +static bool trans_diag_mfdiag(DisasContext *ctx, arg_diag_mfdiag *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + TCGv_i64 dest = dest_gpr(ctx, a->rt); + tcg_gen_ld_i64(dest, tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + save_gpr(ctx, a->rt, dest); + return nullify_end(ctx); +} + +static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, + offsetof(CPUHPPAState, dr[a->dr])); + return nullify_end(ctx); +} + static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); From patchwork Fri Jan 31 09:22:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955152 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73657C02193 for ; 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d=kernel.org; s=k20201202; t=1738315363; bh=UThlWjqG888IPofGfuoGum5DaEYXPS/+ciipEBddP2Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eQl+7EZC60mCeqYPKIiDY3KrP2yt4h9cyeDdoNLlumepRL8ogx2PQOFxDWWDWL47W qM0utC5D8t+uPq1SX2CCQHR3nFzcYM5yW5Sqv1QNuC0VOuk9GizRBd+wP2gQM1G9FE RCe6+WjDnLv0F1JWqCpfGBiysssaq8KQFTZuXyJxUSnoEw9qpT4R06JUrFAb2xYd3G Wo404HlsmGNvjce7QLHUMHBYUh4sSHLQC7gZ0ef3X1LmknhnCwglY3AgF5wll00tI8 ZlWy1y/vWNTUvWA8z7uBubnMWntx+a1RGnpHc71pMDihZfLWGDuw9QgPRnxhJkaD0x QsNzjxaLWzugg== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 7/9] target/hppa: 64-bit CPUs start with space register hashing enabled Date: Fri, 31 Jan 2025 10:22:27 +0100 Message-ID: <20250131092229.38232-8-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=139.178.84.217; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -83 X-Spam_score: -8.4 X-Spam_bar: -------- X-Spam_report: (-8.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller Turn on space register hashing for 64-bit CPUs when reset. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b0bc9d35e4..c86f9190d2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,6 +28,7 @@ #include "exec/translation-block.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" +#include "hw/hppa/hppa_hardware.h" static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -217,6 +218,10 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType type) memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); cpu_hppa_loaded_fr0(env); + + /* 64-bit machines start with space-register hashing enabled in %dr2 */ + env->dr[2] = hppa_is_pa20(env) ? HPPA64_DIAG_SPHASH_ENABLE : 0; + cpu_hppa_put_psw(env, PSW_M); } From patchwork Fri Jan 31 09:22:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Helge Deller X-Patchwork-Id: 13955150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1FBAC02193 for ; Fri, 31 Jan 2025 09:23:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tdnEg-0008Im-PG; Fri, 31 Jan 2025 04:22:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEe-0008IL-El for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:48 -0500 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tdnEc-0004Ed-ES for qemu-devel@nongnu.org; Fri, 31 Jan 2025 04:22:48 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 39C33A41A13; Fri, 31 Jan 2025 09:20:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56BB6C4CED1; Fri, 31 Jan 2025 09:22:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738315365; bh=irFb0ydrt6N4q0n5j4pBmrMloyIWuDDsLdKUN8Uyg9A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d/PYz1gnn/pg61qKZCJ95LrCRjdDCBCxgIikv/5QgseFM5akdTM8zStB+dHUMLMLs KGGkXrWxr2k4K17fSct7rB8LpZxAoc8eP7sc9XBJMa/jO6dRzVKlBvA/bmA5UKs6M4 Bs3c51sgYFT5x+P87OdWTAWYTlZVqqSZLKvqxjdPKnRlk6NL5DJdcptGw8qPPQ1oD3 9ZMZ6KWjswIax7eR4z9U2WGDkBwIHszFoPbR1F8uC0khbbl6Y0qDg3ycJOepHTla2p C/iQKsM0LoOhEdc5pwi5Jrs2VtTj8OSzWRci71Zp+3EZLznmP/HihICSXLASmU5Lwb tlX5RNf9y+R1A== From: deller@kernel.org To: Richard Henderson , Stefan Hajnoczi , qemu-devel@nongnu.org, Peter Maydell Cc: deller@gmx.de Subject: [PULL v2 8/9] target/hppa: Implement space register hashing for 64-bit HP-UX Date: Fri, 31 Jan 2025 10:22:28 +0100 Message-ID: <20250131092229.38232-9-deller@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250131092229.38232-1-deller@kernel.org> References: <20250131092229.38232-1-deller@kernel.org> MIME-Version: 1.0 Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -56 X-Spam_score: -5.7 X-Spam_bar: ----- X-Spam_report: (-5.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.3, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Helge Deller The Linux kernel turns space-register hashing off unconditionally at bootup. That code was provided by HP at the beginning of the PA-RISC Linux porting effort, and I don't know why it was decided then why Linux should not use space register hashing. 32-bit HP-UX versions seem to not use space register hashing either. But for 64-bit HP-UX versions, Sven Schnelle noticed that space register hashing needs to be enabled and is required, otherwise the HP-UX kernel will crash badly. On 64-bit CPUs space register hashing is controlled by a bit in diagnose register %dr2. Since we want to support Linux and 32- and 64-bit HP-UX, we need to fully emulate the diagnose registers and handle specifically the bit in %dr2. This patch adds the code to calculate the gva memory mask based on the space-register hashing bit in %dr2 and the PSW_W (64-bit) flag. The value is cached in the gva_offset_mask variable in CPUArchState and recalculated at every modification of the CPU PSW or %dr2. Signed-off-by: Helge Deller Suggested-by: Sven Schnelle Suggested-by: Richard Henderson Reviewed-by: Richard Henderson --- target/hppa/cpu.c | 9 +++++++-- target/hppa/cpu.h | 20 ++++++++------------ target/hppa/helper.c | 25 +++++++++++++++++++++++-- target/hppa/helper.h | 1 + target/hppa/int_helper.c | 10 ++++++---- target/hppa/mem_helper.c | 5 +++++ target/hppa/sys_helper.c | 4 ++-- target/hppa/translate.c | 12 +++++++++++- 8 files changed, 63 insertions(+), 23 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c86f9190d2..5655677431 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -45,8 +45,9 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) { CPUHPPAState *env = cpu_env(cs); - return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); + return hppa_form_gva_mask(env->gva_offset_mask, + (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, @@ -91,6 +92,10 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, & (env->sr[4] == env->sr[7])) { flags |= TB_FLAG_SR_SAME; } + if ((env->psw & PSW_W) && + (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE)) { + flags |= TB_FLAG_SPHASH; + } #endif *pcsbase = cs_base; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index b858986c41..7be4a1d380 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -223,6 +223,7 @@ typedef struct CPUArchState { target_ulong psw_cb; /* in least significant bit of next nibble */ target_ulong psw_cb_msb; /* boolean */ + uint64_t gva_offset_mask; /* cached address mask based on PSW and %dr2 */ uint64_t iasq_f; uint64_t iasq_b; @@ -320,27 +321,20 @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb, #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU -static inline uint64_t gva_offset_mask(target_ulong psw) -{ - return (psw & PSW_W - ? MAKE_64BIT_MASK(0, 62) - : MAKE_64BIT_MASK(0, 32)); -} - -static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, - target_ulong off) +static inline target_ulong hppa_form_gva_mask(uint64_t gva_offset_mask, + uint64_t spc, target_ulong off) { #ifdef CONFIG_USER_ONLY - return off & gva_offset_mask(psw); + return off & gva_offset_mask; #else - return spc | (off & gva_offset_mask(psw)); + return spc | (off & gva_offset_mask); #endif } static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, target_ulong off) { - return hppa_form_gva_psw(env->psw, spc, off); + return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); @@ -354,6 +348,7 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 +#define TB_FLAG_SPHASH 0x800 #define CS_BASE_DIFFPAGE (1 << 12) #define CS_BASE_DIFFSPACE (1 << 13) @@ -362,6 +357,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); +void update_gva_offset_mask(CPUHPPAState *env); void cpu_hppa_loaded_fr0(CPUHPPAState *env); #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/helper.c b/target/hppa/helper.c index d4b1a3cd5a..ac7f58f0af 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" +#include "hw/hppa/hppa_hardware.h" target_ulong cpu_hppa_get_psw(CPUHPPAState *env) { @@ -59,6 +60,22 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) return psw; } +void update_gva_offset_mask(CPUHPPAState *env) +{ + uint64_t gom; + + if (env->psw & PSW_W) { + gom = (env->dr[2] & HPPA64_DIAG_SPHASH_ENABLE) + ? MAKE_64BIT_MASK(0, 62) & + ~((uint64_t)HPPA64_PDC_CACHE_RET_SPID_VAL << 48) + : MAKE_64BIT_MASK(0, 62); + } else { + gom = MAKE_64BIT_MASK(0, 32); + } + + env->gva_offset_mask = gom; +} + void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { uint64_t reserved; @@ -98,6 +115,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) cb |= ((psw >> 9) & 1) << 8; cb |= ((psw >> 8) & 1) << 4; env->psw_cb = cb; + + update_gva_offset_mask(env); } void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) @@ -133,9 +152,11 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", env->iasq_f >> 32, w, m & env->iaoq_f, - hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), + hppa_form_gva_mask(env->gva_offset_mask, env->iasq_f, + env->iaoq_f), env->iasq_b >> 32, w, m & env->iaoq_b, - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); + hppa_form_gva_mask(env->gva_offset_mask, env->iasq_b, + env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); diff --git a/target/hppa/helper.h b/target/hppa/helper.h index de411923d9..8369855d78 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -99,6 +99,7 @@ DEF_HELPER_FLAGS_2(ptlb_l, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tl, env, tl) DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_1(update_gva_offset_mask, TCG_CALL_NO_RWG, void, env) DEF_HELPER_1(diag_btlb, void, env) DEF_HELPER_1(diag_console_output, void, env) #endif diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 58695def82..7d48643bb6 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -94,11 +94,12 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; int i = cs->exception_index; - uint64_t old_psw; + uint64_t old_psw, old_gva_offset_mask; /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); + old_gva_offset_mask = env->gva_offset_mask; /* step 2 -- Note PSW_W is masked out again for pa1.x */ cpu_hppa_put_psw(env, @@ -112,9 +113,9 @@ void hppa_cpu_do_interrupt(CPUState *cs) */ if (old_psw & PSW_C) { env->cr[CR_IIASQ] = - hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32; + hppa_form_gva_mask(old_gva_offset_mask, env->iasq_f, env->iaoq_f) >> 32; env->cr_back[0] = - hppa_form_gva_psw(old_psw, env->iasq_b, env->iaoq_b) >> 32; + hppa_form_gva_mask(old_gva_offset_mask, env->iasq_b, env->iaoq_b) >> 32; } else { env->cr[CR_IIASQ] = 0; env->cr_back[0] = 0; @@ -165,7 +166,8 @@ void hppa_cpu_do_interrupt(CPUState *cs) if (old_psw & PSW_C) { int prot, t; - vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); + vaddr = hppa_form_gva_mask(old_gva_offset_mask, + env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, 0, 0, &paddr, &prot); if (t >= 0) { diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b8c3e55170..304f0b61e2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -824,3 +824,8 @@ uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f) } return iaoq_f; } + +void HELPER(update_gva_offset_mask)(CPUHPPAState *env) +{ + update_gva_offset_mask(env); +} diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index da5b569de8..052a6a88a2 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -73,7 +73,7 @@ target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm) * machines set the Q bit from 0 to 1 without an exception, * so let this go without comment. */ - env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + cpu_hppa_put_psw(env, (psw & ~PSW_SM) | (nsm & PSW_SM)); return psw & PSW_SM; } @@ -88,7 +88,7 @@ void HELPER(rfi)(CPUHPPAState *env) * To recreate the space identifier, remove the offset bits. * For pa1.x, the mask reduces to no change to space. */ - mask = gva_offset_mask(env->psw); + mask = env->gva_offset_mask; env->iaoq_f = env->cr[CR_IIAOQ]; env->iaoq_b = env->cr_back[1]; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7b9d3deb39..0d0d1bc99b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { /* IAOQ_Front at entry to TB. */ uint64_t iaoq_first; + uint64_t gva_offset_mask; DisasCond null_cond; TCGLabel *null_lab; @@ -1577,7 +1578,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, *pofs = ofs; *pgva = addr = tcg_temp_new_i64(); tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, - gva_offset_mask(ctx->tb_flags)); + ctx->gva_offset_mask); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); @@ -4615,6 +4616,14 @@ static bool trans_diag_mtdiag(DisasContext *ctx, arg_diag_mtdiag *a) nullify_over(ctx); tcg_gen_st_i64(load_gpr(ctx, a->r1), tcg_env, offsetof(CPUHPPAState, dr[a->dr])); +#ifndef CONFIG_USER_ONLY + if (ctx->is_pa20 && (a->dr == 2)) { + /* Update gva_offset_mask from the new value of %dr2 */ + gen_helper_update_gva_offset_mask(tcg_env); + /* Exit to capture the new value for the next TB. */ + ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT; + } +#endif return nullify_end(ctx); } @@ -4635,6 +4644,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); + ctx->gva_offset_mask = cpu_env(cs)->gva_offset_mask; #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER;