From patchwork Mon Feb 3 20:40:12 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaustabh Chakraborty X-Patchwork-Id: 13958230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5107C02192 for ; Mon, 3 Feb 2025 21:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=WnQ/Yw9u8lHA5/KIL39alLrkEPe/ZW45qmvWWCAF8t4=; b=GBueLPRZAPD3XxkCDblTPfQth2 pfZyQB4IA9oAYH5cUjyAw5LoWOzFtdkCqu1qfKH0DU0XoctfCRkSG0R519mvPJdO36ffozlEtNFkS qz6RBiBR+iIHN3gyFhMO5oaFEm4IGGPnWj0ogyykGOzJqUHfEn0OfgwInVy2P6017m9RKceb4oTRM REGkUkQYs2MX69LSNEefOAbpOfHbLK2BRXoU+0C2/cqPY5Z8DT2QOS+CtS7K9+NJFRGmehDz5HLMt wXhak+Rb6Wb+0e4fyMcKOrNK1DdS1eQUgcLePCwfcBWBNwkt3XwesVntGlS73W6puzN26f0ux4bSU 6gKHvKeg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tf3hi-0000000GcO1-38td; Mon, 03 Feb 2025 21:10:02 +0000 Received: from layka.disroot.org ([178.21.23.139]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tf3FL-0000000GYr5-1L3I; Mon, 03 Feb 2025 20:40:44 +0000 Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 2991F25C5C; Mon, 3 Feb 2025 21:40:42 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id qq7L7MlcKT6L; Mon, 3 Feb 2025 21:40:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1738615241; bh=pror0XWyyGe/mjoG6mkYXCLKXmddXdbejFXeV//EYQ8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=UJk4oZnQGFCOjinrOxl5zEpg30LKkWUeRJRDRBv05H0/aMXjHGo0j1X1ceh0ooVQ2 Jj/qonuF4R9hfpilOulkAkpjsT27yBYlSPCybc1ExWGiaY5Io4cm9OObRWEi+ojJrn Ue3Q/9+PbvlWcolexR49ve3nMROQ0DYKWKHew18BwgI2uFgZbs0gKKTylXvGOgZXYs 8rBIPUuuHhaXE9FQarN+JYvquCcvgLzPpNrp4IW6FyiFpeXHbFKVkYCa6lhYpWbPEO fcVBPpRysNhO3V//3Swvwr8CYedriPsfVRiGqz+el2beOU00/bTmdl0psoWTuSIOgg J3ELPqGbAFD5w== From: Kaustabh Chakraborty Date: Tue, 04 Feb 2025 02:10:12 +0530 Subject: [PATCH 1/4] phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk MIME-Version: 1.0 Message-Id: <20250204-exynos7870-usbphy-v1-1-f30a9857efeb@disroot.org> References: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> In-Reply-To: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Vivek Gautam , Rob Herring , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki Cc: Sergey Lisov , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kaustabh Chakraborty X-Developer-Signature: v=1; a=ed25519-sha256; t=1738615219; l=1704; i=kauschluss@disroot.org; s=20250202; h=from:subject:message-id; bh=pror0XWyyGe/mjoG6mkYXCLKXmddXdbejFXeV//EYQ8=; b=D6jFW4npMZfbRijNOv1ltq1eV8zqSQ3LrZ0t3CAVb0kFz0l72lXaMnqN+kDvOIy698yLVJLkb JBjXiN3AXZZDssTe761EKpqlAigR1r86/7UstWp3h5tVT6WALuhdtrl X-Developer-Key: i=kauschluss@disroot.org; a=ed25519; pk=h2xeR+V2I1+GrfDPAhZa3M+NWA0Cnbdkkq1bH3ct1hE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250203_124043_497342_FE526E74 X-CRM114-Status: UNSURE ( 8.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not inverted when applied to the register values. Fix it. Fixes: 59025887fb08 ("phy: Add new Exynos5 USB 3.0 PHY driver") Signed-off-by: Kaustabh Chakraborty --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index c421b495eb0fe4396d76f8c9d7c198ad7cd08869..4a108fdab118c0edd76bd88dc9dbf6a498e064b3 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -488,9 +488,9 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst) reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; /* FSEL settings corresponding to reference clock */ - reg &= ~PHYCLKRST_FSEL_PIPE_MASK | - PHYCLKRST_MPLL_MULTIPLIER_MASK | - PHYCLKRST_SSC_REFCLKSEL_MASK; + reg &= ~(PHYCLKRST_FSEL_PIPE_MASK | + PHYCLKRST_MPLL_MULTIPLIER_MASK | + PHYCLKRST_SSC_REFCLKSEL_MASK); switch (phy_drd->extrefclk) { case EXYNOS5_FSEL_50MHZ: reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | @@ -532,9 +532,9 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst) reg &= ~PHYCLKRST_REFCLKSEL_MASK; reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; - reg &= ~PHYCLKRST_FSEL_UTMI_MASK | - PHYCLKRST_MPLL_MULTIPLIER_MASK | - PHYCLKRST_SSC_REFCLKSEL_MASK; + reg &= ~(PHYCLKRST_FSEL_UTMI_MASK | + PHYCLKRST_MPLL_MULTIPLIER_MASK | + PHYCLKRST_SSC_REFCLKSEL_MASK); reg |= PHYCLKRST_FSEL(phy_drd->extrefclk); return reg; From patchwork Mon Feb 3 20:40:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaustabh Chakraborty X-Patchwork-Id: 13958231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A620AC02193 for ; Mon, 3 Feb 2025 21:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Mon, 03 Feb 2025 20:40:56 +0000 Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 03CC725C59; Mon, 3 Feb 2025 21:40:54 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 3blw3TwI0hZa; Mon, 3 Feb 2025 21:40:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1738615252; bh=wt2GHvwQc8oyS/a94zlZqsI73cR1u9EzFQZlaA/5+ZU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Zg/jxgRznMkz2a2RdPlY5Lo0N6vCZuL3AC4b3Kl/oWwzGfnGcUSlPUrJ7B2vFYm8Z C6S5GNRWMqY9KiBw9yK8C+pylfgIotqkSN4rjKDZCPlBUJpcQOrYdoC45YiauFAibb jrfUpoDLdQxLVsvWiAa6Gpw2705qnCC7OVXLuYSlg79unG16X8o9Q9Xsu8eTz265Wf n+ZTqCuUscAq/4D61IdwYGQ+zcav//hr6dzTQSxvnQufT4pgqGNdeJ2IpIjgMjZis6 cWzD9wd8LmKeQtCmnFNstioo2BPy1E11GkOdJ7PRRzb6L3XFeAXeADlKGYYLfjHg5r SiVl9RH5SQ7Ag== From: Kaustabh Chakraborty Date: Tue, 04 Feb 2025 02:10:13 +0530 Subject: [PATCH 2/4] phy: exynos5-usbdrd: use GENMASK and FIELD_PREP for Exynos5 PHY registers MIME-Version: 1.0 Message-Id: <20250204-exynos7870-usbphy-v1-2-f30a9857efeb@disroot.org> References: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> In-Reply-To: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Vivek Gautam , Rob Herring , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki Cc: Sergey Lisov , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kaustabh Chakraborty X-Developer-Signature: v=1; a=ed25519-sha256; t=1738615219; l=12277; i=kauschluss@disroot.org; s=20250202; h=from:subject:message-id; bh=wt2GHvwQc8oyS/a94zlZqsI73cR1u9EzFQZlaA/5+ZU=; b=iia+uq4EAucOrUu4rUoWAsax86cUgcZKLtoZCcDA0W4GLOeOa4EHPXvxHCh634NZ/QhiQJNQD 9mSrHGApBhKCUnj+yFtms7Twka906ct+HyVIB5uOWE5mysd/8bXn9ut X-Developer-Key: i=kauschluss@disroot.org; a=ed25519; pk=h2xeR+V2I1+GrfDPAhZa3M+NWA0Cnbdkkq1bH3ct1hE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250203_124055_506251_825803F6 X-CRM114-Status: GOOD ( 12.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Most Exynos850 and Exynos9 (GS101) DRD PHY registers use GENMASK for masks and FIELD_PREP for writing values to registers. Rewrite the register definitions which don't follow this approach to follow it as much as possible. This patch doesn't introduce any fixes or functional changes, it's merely an attempt to introduce some uniformity and consistency in the driver code. The CRPORT SuperSpeed control registers have been exempted from this change. Since the writing of register values do not require any masking operations, implementing it would unnecessarily complicate things. Signed-off-by: Kaustabh Chakraborty --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 147 ++++++++++++++++--------------- 1 file changed, 75 insertions(+), 72 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 4a108fdab118c0edd76bd88dc9dbf6a498e064b3..b2194134193984392c8b48bac249591a92eaa924 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -37,8 +37,7 @@ /* Exynos5: USB 3.0 DRD PHY registers */ #define EXYNOS5_DRD_LINKSYSTEM 0x04 #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) -#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) -#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_FLADJ GENMASK(6, 1) #define EXYNOS5_DRD_PHYUTMI 0x08 #define PHYUTMI_OTGDISABLE BIT(6) @@ -49,30 +48,27 @@ #define EXYNOS5_DRD_PHYCLKRST 0x10 #define PHYCLKRST_EN_UTMISUSPEND BIT(31) -#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) -#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) -#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) -#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) +#define PHYCLKRST_SSC_REFCLKSEL GENMASK(30, 23) +#define PHYCLKRST_SSC_RANGE GENMASK(22, 21) #define PHYCLKRST_SSC_EN BIT(20) #define PHYCLKRST_REF_SSP_EN BIT(19) #define PHYCLKRST_REF_CLKDIV2 BIT(18) -#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) -#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) -#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8) -#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) -#define PHYCLKRST_FSEL(_x) ((_x) << 5) -#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) -#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) -#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) -#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) +#define PHYCLKRST_MPLL_MULTIPLIER GENMASK(17, 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF 0x19 +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF 0x32 +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF 0x68 +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF 0x7d +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF 0x02 +#define PHYCLKRST_FSEL_PIPE GENMASK(10, 8) +#define PHYCLKRST_FSEL_UTMI GENMASK(7, 5) +#define PHYCLKRST_FSEL_PAD_100MHZ 0x27 +#define PHYCLKRST_FSEL_PAD_24MHZ 0x2a +#define PHYCLKRST_FSEL_PAD_20MHZ 0x31 +#define PHYCLKRST_FSEL_PAD_19_2MHZ 0x38 #define PHYCLKRST_RETENABLEN BIT(4) -#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) -#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) -#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) +#define PHYCLKRST_REFCLKSEL GENMASK(3, 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK 0x2 +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK 0x3 #define PHYCLKRST_PORTRESET BIT(1) #define PHYCLKRST_COMMONONN BIT(0) @@ -81,22 +77,22 @@ #define PHYREG0_SSC_RANGE BIT(20) #define PHYREG0_CR_WRITE BIT(19) #define PHYREG0_CR_READ BIT(18) -#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2) +#define PHYREG0_CR_DATA_IN GENMASK(17, 2) #define PHYREG0_CR_CAP_DATA BIT(1) #define PHYREG0_CR_CAP_ADDR BIT(0) #define EXYNOS5_DRD_PHYREG1 0x18 -#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1) +#define PHYREG0_CR_DATA_OUT GENMASK(16, 1) #define PHYREG1_CR_ACK BIT(0) #define EXYNOS5_DRD_PHYPARAM0 0x1c #define PHYPARAM0_REF_USE_PAD BIT(31) -#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) -#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) +#define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26) +#define PHYPARAM0_REF_LOSLEVEL_VAL 0x9 #define EXYNOS5_DRD_PHYPARAM1 0x20 -#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) -#define PHYPARAM1_PCS_TXDEEMPH (0x1c) +#define PHYPARAM1_PCS_TXDEEMPH GENMASK(4, 0) +#define PHYPARAM1_PCS_TXDEEMPH_VAL 0x1c #define EXYNOS5_DRD_PHYTERM 0x24 @@ -138,7 +134,7 @@ #define LINKCTRL_FORCE_PHYSTATUS BIT(17) #define LINKCTRL_FORCE_PIPE_EN BIT(16) #define LINKCTRL_FORCE_QACT BIT(8) -#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4) +#define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4) #define EXYNOS850_DRD_LINKPORT 0x08 #define LINKPORT_HOST_NUM_U3 GENMASK(19, 16) @@ -484,29 +480,34 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst) reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); /* Use EXTREFCLK as ref clock */ - reg &= ~PHYCLKRST_REFCLKSEL_MASK; - reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; + reg &= ~PHYCLKRST_REFCLKSEL; + reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, + PHYCLKRST_REFCLKSEL_EXT_REFCLK); /* FSEL settings corresponding to reference clock */ - reg &= ~(PHYCLKRST_FSEL_PIPE_MASK | - PHYCLKRST_MPLL_MULTIPLIER_MASK | - PHYCLKRST_SSC_REFCLKSEL_MASK); + reg &= ~(PHYCLKRST_FSEL_PIPE | + PHYCLKRST_MPLL_MULTIPLIER | + PHYCLKRST_SSC_REFCLKSEL); switch (phy_drd->extrefclk) { case EXYNOS5_FSEL_50MHZ: - reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | - PHYCLKRST_SSC_REFCLKSEL(0x00)); + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); break; case EXYNOS5_FSEL_24MHZ: - reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | - PHYCLKRST_SSC_REFCLKSEL(0x88)); + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); break; case EXYNOS5_FSEL_20MHZ: - reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF | - PHYCLKRST_SSC_REFCLKSEL(0x00)); + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); break; case EXYNOS5_FSEL_19MHZ2: - reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF | - PHYCLKRST_SSC_REFCLKSEL(0x88)); + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, + PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); break; default: dev_dbg(phy_drd->dev, "unsupported ref clk\n"); @@ -529,13 +530,14 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst) /* restore any previous reference clock settings */ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); - reg &= ~PHYCLKRST_REFCLKSEL_MASK; - reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; + reg &= ~PHYCLKRST_REFCLKSEL; + reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, + PHYCLKRST_REFCLKSEL_EXT_REFCLK); - reg &= ~(PHYCLKRST_FSEL_UTMI_MASK | - PHYCLKRST_MPLL_MULTIPLIER_MASK | - PHYCLKRST_SSC_REFCLKSEL_MASK); - reg |= PHYCLKRST_FSEL(phy_drd->extrefclk); + reg &= ~(PHYCLKRST_FSEL_UTMI | + PHYCLKRST_MPLL_MULTIPLIER | + PHYCLKRST_SSC_REFCLKSEL); + reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); return reg; } @@ -585,8 +587,9 @@ static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); /* Set Tx De-Emphasis level */ - reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; - reg |= PHYPARAM1_PCS_TXDEEMPH; + reg &= ~PHYPARAM1_PCS_TXDEEMPH; + reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, + PHYPARAM1_PCS_TXDEEMPH_VAL); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); @@ -607,7 +610,7 @@ exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd) reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); reg &= ~SECPMACTL_PMA_REF_FREQ_SEL; - reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1); + reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1); /* SFR reset */ reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST); reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL | @@ -723,14 +726,16 @@ static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); /* Set Loss-of-Signal Detector sensitivity */ - reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK; - reg |= PHYPARAM0_REF_LOSLEVEL; + reg &= ~PHYPARAM0_REF_LOSLEVEL; + reg |= FIELD_PREP_CONST(PHYPARAM0_REF_LOSLEVEL, + PHYPARAM0_REF_LOSLEVEL_VAL); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); /* Set Tx De-Emphasis level */ - reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; - reg |= PHYPARAM1_PCS_TXDEEMPH; + reg &= ~PHYPARAM1_PCS_TXDEEMPH; + reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, + PHYPARAM1_PCS_TXDEEMPH_VAL); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); /* UTMI Power Control */ @@ -761,7 +766,7 @@ static int exynos5_usbdrd_phy_init(struct phy *phy) * See xHCI 1.0 spec, 5.2.4 */ reg = LINKSYSTEM_XHCI_VERSION_CONTROL | - LINKSYSTEM_FLADJ(0x20); + FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); @@ -920,26 +925,24 @@ static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd, static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd, u32 addr, u32 data) { + u32 val; int ret; /* Write Address */ - writel(PHYREG0_CR_DATA_IN(addr), - phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); - ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr), - PHYREG0_CR_CAP_ADDR); + val = FIELD_PREP(PHYREG0_CR_DATA_IN, addr); + writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + ret = crport_handshake(phy_drd, val, PHYREG0_CR_CAP_ADDR); if (ret) return ret; /* Write Data */ - writel(PHYREG0_CR_DATA_IN(data), - phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); - ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), - PHYREG0_CR_CAP_DATA); + val = FIELD_PREP(PHYREG0_CR_DATA_IN, data); + writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + ret = crport_handshake(phy_drd, val, PHYREG0_CR_CAP_DATA); if (ret) return ret; - ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), - PHYREG0_CR_WRITE); + ret = crport_handshake(phy_drd, val, PHYREG0_CR_WRITE); return ret; } @@ -1108,7 +1111,7 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); - reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf); + reg |= FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); reg = readl(regs_base + EXYNOS850_DRD_UTMI); @@ -1123,19 +1126,19 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) reg &= ~SSPPLLCTL_FSEL; switch (phy_drd->extrefclk) { case EXYNOS5_FSEL_50MHZ: - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7); + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); break; case EXYNOS5_FSEL_26MHZ: - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6); + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); break; case EXYNOS5_FSEL_24MHZ: - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2); + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); break; case EXYNOS5_FSEL_20MHZ: - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1); + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); break; case EXYNOS5_FSEL_19MHZ2: - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); break; default: dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", From patchwork Mon Feb 3 20:40:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaustabh Chakraborty X-Patchwork-Id: 13958232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8017DC02192 for ; Mon, 3 Feb 2025 21:12:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Mon, 03 Feb 2025 20:41:05 +0000 Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 65EA925888; Mon, 3 Feb 2025 21:41:03 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id UT50sK67Dgox; Mon, 3 Feb 2025 21:41:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1738615262; bh=21d+Jc9d+gADlgNHYfQOcBVdXDZGzdPTgv991qDeWLc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Iy8uyQW2ecHHSezrfBWohAKMPT86crMNu0Wy2hsDziRO4MYK1C4vhlcm2kAEIrhce dvvWMf6lL1mySTW1vlp0mfZDvKnA1pEfT7Dk9aHyGonSC2fdX5Ut9UcKhc0f8GLLWC i8zl6GhkP/GTJxt8ELePkZ5Yxpet8RQ3zAU5+2YC/eIwxGYjqs4WDmbU/kxBd9R/hZ XaQM1ND8tbrTyz7Sq9qcJg2jGnb9Pz9mrtM/9EgqYlDaIyWhaQJDIj4qehy631JBLF 4Fr83K3v1PBBLec58jGCpFXOMeJDXoSo8l59BpSm9vPKDUegkX48ksNFBpm8VS9JlY qaQyl4CM+9C6A== From: Kaustabh Chakraborty Date: Tue, 04 Feb 2025 02:10:14 +0530 Subject: [PATCH 3/4] dt-bindings: phy: samsung,usb3-drd-phy: add exynos7870-usbdrd-phy compatible MIME-Version: 1.0 Message-Id: <20250204-exynos7870-usbphy-v1-3-f30a9857efeb@disroot.org> References: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> In-Reply-To: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Vivek Gautam , Rob Herring , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki Cc: Sergey Lisov , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kaustabh Chakraborty X-Developer-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the compatible string "samsung,exynos7870-usbdrd-phy" to the documentation. The devicetree node requires two clocks, named "phy" and "ref" (same as clocks required by Exynos5). Signed-off-by: Kaustabh Chakraborty --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd4919cd00228c35e3c1676e7954077591..3b5881e7e5bc403ef2b379668584a8379effc256 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -30,6 +30,7 @@ properties: - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy - samsung,exynos7-usbdrd-phy + - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy clocks: @@ -168,6 +169,7 @@ allOf: enum: - samsung,exynos5250-usbdrd-phy - samsung,exynos5420-usbdrd-phy + - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy then: properties: From patchwork Mon Feb 3 20:40:15 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaustabh Chakraborty X-Patchwork-Id: 13958233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E5E5C02192 for ; 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Mon, 03 Feb 2025 21:14:05 +0000 Received: from layka.disroot.org ([178.21.23.139]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tf3Fu-0000000GZ3K-0Da8; Mon, 03 Feb 2025 20:41:19 +0000 Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id A8CEB25BC9; Mon, 3 Feb 2025 21:41:16 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id jnQ_KJNVvoAL; Mon, 3 Feb 2025 21:41:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1738615272; bh=rWj06FvYIxT7vbEmJHdYsqQCLp8XJbN54JJ1bJmwGx4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=mZTTGcddpINkDrE7Asn8ecdiHwl7akVgIeiDNvCndz77BcerGxfhizLTnerU8x0sk S3EMr4AxuKYY48nDeevkcCi8AUVwIHbBHx/9ddboKBl083g1Z8Wn8HCdGS5I2y8n7I A719R7aLOFJyoDv7h6OLGMxiC8kQud4ybnGeA8tto3UWKFnibGN6Gpcb9MNpIuDIU5 jbSNOXwHMSA5g0tuztRCi16AlraImINaHnuLSKyNaU+Fql3hVmO1EtYWexPuZhf1nU NxR3Xa3j7cKFS8rvaodfJdHSswJFcO2aNpZHH4Ipxv0zaybQdDcWSDUvlsq/9EP3Re GTn8f2p2whWwg== From: Kaustabh Chakraborty Date: Tue, 04 Feb 2025 02:10:15 +0530 Subject: [PATCH 4/4] phy: exynos5-usbdrd: add exynos7870 USBDRD support MIME-Version: 1.0 Message-Id: <20250204-exynos7870-usbphy-v1-4-f30a9857efeb@disroot.org> References: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> In-Reply-To: <20250204-exynos7870-usbphy-v1-0-f30a9857efeb@disroot.org> To: Vinod Koul , Kishon Vijay Abraham I , Krzysztof Kozlowski , Alim Akhtar , Vivek Gautam , Rob Herring , Conor Dooley , Marek Szyprowski , Sylwester Nawrocki Cc: Sergey Lisov , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kaustabh Chakraborty X-Developer-Signature: v=1; a=ed25519-sha256; t=1738615219; l=13362; i=kauschluss@disroot.org; s=20250202; h=from:subject:message-id; bh=GTcOGWDNKNMwP6Bju0nlY+mIa3II8IQPsqSfD64jlOQ=; b=kc3inyHZ9+1OYVD7j0ft3nrBTG4B2+VqMqwUH72egkSS5e1QxDEyu8NP2lfQDNujyLk0slKqC LLlNQmjDSD4D+dDlhBQbu76yUlQG4mCTzOe8z6qHO43hCvjc+pcpg/Y X-Developer-Key: i=kauschluss@disroot.org; a=ed25519; pk=h2xeR+V2I1+GrfDPAhZa3M+NWA0Cnbdkkq1bH3ct1hE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250203_124118_366237_EC14223C X-CRM114-Status: GOOD ( 19.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Sergey Lisov Implement support for Exynos7870 USB DRD on top of the existing exynos5-usbdrd driver. Exynos7870 has a single USB 2.0 DRD PHY controller and no 3.0 PHYs. Thus, it only supports the UTMI interface. Moreover, the PMU register offset for enabling the PHY controller is different for SoCs such as Exynos7870, where BIT(0) is for the 3.0 PHY and BIT(1) is for the 2.0 PHY. The phy_isol function for Exynos7870 uses the appropriate register offsets. Signed-off-by: Sergey Lisov Co-developed-by: Kaustabh Chakraborty Signed-off-by: Kaustabh Chakraborty --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 260 ++++++++++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 262 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index b2194134193984392c8b48bac249591a92eaa924..4fe926483343ee2edf15b53e35f83a721f5cedab 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -37,10 +37,22 @@ /* Exynos5: USB 3.0 DRD PHY registers */ #define EXYNOS5_DRD_LINKSYSTEM 0x04 #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) +#define LINKSYSTEM_FORCE_VBUSVALID BIT(8) +#define LINKSYSTEM_FORCE_BVALID BIT(7) #define LINKSYSTEM_FLADJ GENMASK(6, 1) #define EXYNOS5_DRD_PHYUTMI 0x08 +#define PHYUTMI_UTMI_SUSPEND_COM_N BIT(12) +#define PHYUTMI_UTMI_L1_SUSPEND_COM_N BIT(11) +#define PHYUTMI_VBUSVLDEXTSEL BIT(10) +#define PHYUTMI_VBUSVLDEXT BIT(9) +#define PHYUTMI_TXBITSTUFFENH BIT(8) +#define PHYUTMI_TXBITSTUFFEN BIT(7) #define PHYUTMI_OTGDISABLE BIT(6) +#define PHYUTMI_IDPULLUP BIT(5) +#define PHYUTMI_DRVVBUS BIT(4) +#define PHYUTMI_DPPULLDOWN BIT(3) +#define PHYUTMI_DMPULLDOWN BIT(2) #define PHYUTMI_FORCESUSPEND BIT(1) #define PHYUTMI_FORCESLEEP BIT(0) @@ -89,6 +101,16 @@ #define PHYPARAM0_REF_USE_PAD BIT(31) #define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26) #define PHYPARAM0_REF_LOSLEVEL_VAL 0x9 +#define PHYPARAM0_TXVREFTUNE GENMASK(25, 22) +#define PHYPARAM0_TXRISETUNE GENMASK(21, 20) +#define PHYPARAM0_TXRESTUNE GENMASK(19, 18) +#define PHYPARAM0_TXPREEMPPULSETUNE BIT(17) +#define PHYPARAM0_TXPREEMPAMPTUNE GENMASK(16, 15) +#define PHYPARAM0_TXHSXVTUNE GENMASK(14, 13) +#define PHYPARAM0_TXFSLSTUNE GENMASK(12, 9) +#define PHYPARAM0_SQRXTUNE GENMASK(8, 6) +#define PHYPARAM0_OTGTUNE GENMASK(5, 3) +#define PHYPARAM0_COMPDISTUNE GENMASK(2, 0) #define EXYNOS5_DRD_PHYPARAM1 0x20 #define PHYPARAM1_PCS_TXDEEMPH GENMASK(4, 0) @@ -108,6 +130,12 @@ #define EXYNOS5_DRD_PHYRESUME 0x34 #define EXYNOS5_DRD_LINKPORT 0x44 +#define LINKPORT_HOST_U3_PORT_DISABLE BIT(8) +#define LINKPORT_HOST_U2_PORT_DISABLE BIT(7) +#define LINKPORT_HOST_PORT_OVCR_U3 BIT(5) +#define LINKPORT_HOST_PORT_OVCR_U2 BIT(4) +#define LINKPORT_HOST_PORT_OVCR_U3_SEL BIT(3) +#define LINKPORT_HOST_PORT_OVCR_U2_SEL BIT(2) /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */ #define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15) @@ -128,6 +156,24 @@ #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4) #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4) +/* Exynos7870: USB DRD PHY registers */ +#define EXYNOS7870_DRD_PHYPCSVAL 0x3C +#define PHYPCSVAL_PCS_RX_LOS_MASK GENMASK(9, 0) + +#define EXYNOS7870_DRD_PHYPARAM2 0x50 +#define PHYPARAM2_TX_VBOOST_LVL GENMASK(6, 4) +#define PHYPARAM2_LOS_BIAS GENMASK(2, 0) + +#define EXYNOS7870_DRD_HSPHYCTRL 0x54 +#define HSPHYCTRL_PHYSWRSTALL BIT(31) +#define HSPHYCTRL_SIDDQ BIT(6) +#define HSPHYCTRL_PHYSWRST BIT(0) + +#define EXYNOS7870_DRD_HSPHYPLLTUNE 0x70 +#define HSPHYPLLTUNE_PLL_B_TUNE BIT(6) +#define HSPHYPLLTUNE_PLL_I_TUNE GENMASK(5, 4) +#define HSPHYPLLTUNE_PLL_P_TUNE GENMASK(3, 0) + /* Exynos850: USB DRD PHY registers */ #define EXYNOS850_DRD_LINKCTRL 0x04 #define LINKCTRL_FORCE_RXELECIDLE BIT(18) @@ -1052,6 +1098,172 @@ static const struct phy_ops exynos5_usbdrd_phy_ops = { .owner = THIS_MODULE, }; +static void exynos7870_usbdrd_phy_isol(struct phy_usb_instance *inst, + bool isolate) +{ + unsigned int val; + + if (!inst->reg_pmu) + return; + + val = isolate ? 0 : EXYNOS7870_USB2PHY_ENABLE; + + regmap_update_bits(inst->reg_pmu, inst->pmu_offset, + EXYNOS7870_USB2PHY_ENABLE, val); +} + +static void exynos7870_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) +{ + u32 reg; + + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); + /* Use PADREFCLK as ref clock */ + reg &= ~PHYCLKRST_REFCLKSEL; + reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, + PHYCLKRST_REFCLKSEL_PAD_REFCLK); + /* Select ref clock rate */ + reg &= ~PHYCLKRST_FSEL_UTMI; + reg &= ~PHYCLKRST_FSEL_PIPE; + reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); + /* Enable suspend and reset the port */ + reg |= PHYCLKRST_EN_UTMISUSPEND; + reg |= PHYCLKRST_COMMONONN; + reg |= PHYCLKRST_PORTRESET; + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); + udelay(10); + + /* Clear the port reset bit */ + reg &= ~PHYCLKRST_PORTRESET; + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); + + /* Change PHY PLL tune value */ + reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); + if (phy_drd->extrefclk == EXYNOS5_FSEL_24MHZ) + reg |= HSPHYPLLTUNE_PLL_B_TUNE; + else + reg &= ~HSPHYPLLTUNE_PLL_B_TUNE; + reg &= ~HSPHYPLLTUNE_PLL_P_TUNE; + reg |= FIELD_PREP_CONST(HSPHYPLLTUNE_PLL_P_TUNE, 14); + writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); + + /* High-Speed PHY control */ + reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + reg &= ~HSPHYCTRL_SIDDQ; + reg &= ~HSPHYCTRL_PHYSWRST; + reg &= ~HSPHYCTRL_PHYSWRSTALL; + writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + udelay(500); + + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); + /* + * Setting the Frame length Adj value[6:1] to default 0x20 + * See xHCI 1.0 spec, 5.2.4 + */ + reg |= LINKSYSTEM_XHCI_VERSION_CONTROL; + reg |= FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); + /* Set VBUSVALID signal as the VBUS pad is not used */ + reg |= LINKSYSTEM_FORCE_BVALID; + reg |= LINKSYSTEM_FORCE_VBUSVALID; + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); + + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); + /* Release force_sleep & force_suspend */ + reg &= ~PHYUTMI_FORCESLEEP; + reg &= ~PHYUTMI_FORCESUSPEND; + /* DP/DM pull down control */ + reg &= ~PHYUTMI_DMPULLDOWN; + reg &= ~PHYUTMI_DPPULLDOWN; + reg &= ~PHYUTMI_DRVVBUS; + /* Set DP-pull up as the VBUS pad is not used */ + reg |= PHYUTMI_VBUSVLDEXTSEL; + reg |= PHYUTMI_VBUSVLDEXT; + /* Disable OTG block and VBUS valid comparator */ + reg |= PHYUTMI_OTGDISABLE; + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); + + /* Configure OVC IO usage */ + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT); + reg |= LINKPORT_HOST_PORT_OVCR_U3_SEL | LINKPORT_HOST_PORT_OVCR_U2_SEL; + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT); + + /* High-Speed PHY swrst */ + reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + reg |= HSPHYCTRL_PHYSWRST; + writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + udelay(20); + + /* Clear the PHY swrst bit */ + reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + reg &= ~HSPHYCTRL_PHYSWRST; + writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + + if (phy_drd->drv_data->phy_tunes) + exynos5_usbdrd_apply_phy_tunes(phy_drd, + PTS_UTMI_POSTINIT); +} + +static int exynos7870_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + int ret; + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynos7870_usbdrd_phy_exit(struct phy *phy) +{ + int ret; + u32 reg; + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + + ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + /* + * Disable the VBUS signal and the ID pull-up resistor. + * Enable force-suspend and force-sleep modes. + */ + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); + reg &= ~(PHYUTMI_DRVVBUS | PHYUTMI_VBUSVLDEXT | PHYUTMI_VBUSVLDEXTSEL); + reg &= ~PHYUTMI_IDPULLUP; + reg |= PHYUTMI_FORCESUSPEND | PHYUTMI_FORCESLEEP; + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); + + /* Power down PHY analog blocks */ + reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + reg |= HSPHYCTRL_SIDDQ; + writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); + + /* Clear VBUSVALID signal as the VBUS pad is not used */ + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); + reg &= ~(LINKSYSTEM_FORCE_BVALID | LINKSYSTEM_FORCE_VBUSVALID); + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static const struct phy_ops exynos7870_usbdrd_phy_ops = { + .init = exynos7870_usbdrd_phy_init, + .exit = exynos7870_usbdrd_phy_exit, + .power_on = exynos5_usbdrd_phy_power_on, + .power_off = exynos5_usbdrd_phy_power_off, + .owner = THIS_MODULE, +}; + static void exynos5_usbdrd_usb_v3p1_pipe_override(struct exynos5_usbdrd_phy *phy_drd) { @@ -1389,6 +1601,14 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { }, }; +static const struct exynos5_usbdrd_phy_config phy_cfg_exynos7870[] = { + { + .id = EXYNOS5_DRDPHY_UTMI, + .phy_isol = exynos7870_usbdrd_phy_isol, + .phy_init = exynos7870_usbdrd_utmi_init, + }, +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = { { .id = EXYNOS5_DRDPHY_UTMI, @@ -1397,6 +1617,30 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = { }, }; +static +const struct exynos5_usbdrd_phy_tuning exynos7870_tunes_utmi_postinit[] = { + PHY_TUNING_ENTRY_PHY(EXYNOS5_DRD_PHYPARAM0, + (PHYPARAM0_TXVREFTUNE | PHYPARAM0_TXRISETUNE | + PHYPARAM0_TXRESTUNE | PHYPARAM0_TXPREEMPPULSETUNE | + PHYPARAM0_TXPREEMPAMPTUNE | PHYPARAM0_TXHSXVTUNE | + PHYPARAM0_TXFSLSTUNE | PHYPARAM0_SQRXTUNE | + PHYPARAM0_OTGTUNE | PHYPARAM0_COMPDISTUNE), + (FIELD_PREP_CONST(PHYPARAM0_TXVREFTUNE, 14) | + FIELD_PREP_CONST(PHYPARAM0_TXRISETUNE, 1) | + FIELD_PREP_CONST(PHYPARAM0_TXRESTUNE, 3) | + FIELD_PREP_CONST(PHYPARAM0_TXPREEMPAMPTUNE, 0) | + FIELD_PREP_CONST(PHYPARAM0_TXHSXVTUNE, 0) | + FIELD_PREP_CONST(PHYPARAM0_TXFSLSTUNE, 3) | + FIELD_PREP_CONST(PHYPARAM0_SQRXTUNE, 6) | + FIELD_PREP_CONST(PHYPARAM0_OTGTUNE, 2) | + FIELD_PREP_CONST(PHYPARAM0_COMPDISTUNE, 3))), + PHY_TUNING_ENTRY_LAST +}; + +static const struct exynos5_usbdrd_phy_tuning *exynos7870_tunes[PTS_MAX] = { + [PTS_UTMI_POSTINIT] = exynos7870_tunes_utmi_postinit, +}; + static const char * const exynos5_clk_names[] = { "phy", }; @@ -1463,6 +1707,19 @@ static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = { .n_regulators = ARRAY_SIZE(exynos5_regulator_names), }; +static const struct exynos5_usbdrd_phy_drvdata exynos7870_usbdrd_phy = { + .phy_cfg = phy_cfg_exynos7870, + .phy_tunes = exynos7870_tunes, + .phy_ops = &exynos7870_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, + .clk_names = exynos5_clk_names, + .n_clks = ARRAY_SIZE(exynos5_clk_names), + .core_clk_names = exynos5_core_clk_names, + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names = exynos5_regulator_names, + .n_regulators = ARRAY_SIZE(exynos5_regulator_names), +}; + static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { .phy_cfg = phy_cfg_exynos850, .phy_ops = &exynos850_usbdrd_phy_ops, @@ -1666,6 +1923,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynos7-usbdrd-phy", .data = &exynos7_usbdrd_phy + }, { + .compatible = "samsung,exynos7870-usbdrd-phy", + .data = &exynos7870_usbdrd_phy }, { .compatible = "samsung,exynos850-usbdrd-phy", .data = &exynos850_usbdrd_phy diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index ce1a3790d6fb0400021f5cc22394afedfb742152..cde299a85384a70d04dae49ee9a4e2daa88fbbf6 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -55,6 +55,8 @@ #define EXYNOS4_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS4_MIPI_PHY_MRESETN (1 << 2) #define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1) +/* USB PHY enable bit, valid for Exynos7870 */ +#define EXYNOS7870_USB2PHY_ENABLE (1 << 1) #define S5P_INFORM0 0x0800 #define S5P_INFORM1 0x0804