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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dcae80dsm26339635e9.22.2025.02.06.10.18.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address Date: Thu, 6 Feb 2025 19:18:21 +0100 Message-ID: <20250206181827.41557-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Alistair's email is typed differently, so the get_maintainer.pl script add it twice :) Unify to reduce traffic. $ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u M: Alistair Francis M: Alistair Francis M: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 0cf37fce7b5..b7ac1519ee3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -318,7 +318,7 @@ F: tests/functional/test_ppc_74xx.py RISC-V TCG CPUs M: Palmer Dabbelt -M: Alistair Francis +M: alistair.francis M: Bin Meng R: Weiwei Li R: Daniel Henrique Barboza @@ -753,7 +753,7 @@ F: docs/system/arm/digic.rst Goldfish RTC M: Anup Patel -M: Alistair Francis +M: alistair.francis L: qemu-riscv@nongnu.org S: Maintained F: hw/rtc/goldfish_rtc.c @@ -1009,7 +1009,7 @@ F: tests/functional/test_arm_tuxrun.py Xilinx Zynq M: Edgar E. Iglesias -M: Alistair Francis +M: alistair.francis M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained @@ -1593,7 +1593,7 @@ F: pc-bios/vof* RISC-V Machines --------------- OpenTitan -M: Alistair Francis +M: Alistair Francis L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c @@ -1628,7 +1628,7 @@ F: include/hw/riscv/shakti_c.h F: include/hw/char/shakti_uart.h SiFive Machines -M: Alistair Francis +M: Alistair Francis M: Bin Meng M: Palmer Dabbelt L: qemu-riscv@nongnu.org @@ -3842,7 +3842,7 @@ F: tcg/ppc/ RISC-V TCG target M: Palmer Dabbelt -M: Alistair Francis +M: Alistair Francis L: qemu-riscv@nongnu.org S: Maintained F: tcg/riscv/ From patchwork Thu Feb 6 18:18:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13963510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DDCBC02194 for ; Thu, 6 Feb 2025 18:20:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg6Sg-0007e2-9a; Thu, 06 Feb 2025 13:18:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg6Sb-0007bx-Ez for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:18:45 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg6SZ-0006oX-9C for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:18:45 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-436249df846so8657445e9.3 for ; Thu, 06 Feb 2025 10:18:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738865921; x=1739470721; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJl7/XCq/mOYxrX7g6HKZEwMAdetJgh4DocsCwIosNE=; b=lAde4DnB0uWJJXxZfn03EkrEA80KRWSlSVEr6cFP9UPJ024TjzCEc7GmAbTIUng1Np C1E20ILsmX6iKkNZGatVhBfkpsMst/nQa3eAK5Ie8ZOg3r7GEGTApL2sJ/7aMuHjk+Ir pQf21fmsn24lQxdYlh6mH6qGcmeYL+1idf5A4/ZWt6KAXlypCdqlwXxnOKxc/IZK/9hT J9VfJ4YGLhccyAF+fGKAfxYviGNFp+4n2fFSSJIedm5ddlhA0GOPi1RwFRqCNVOvqFqk Ls08RG30/n5p28AzmnRBl5Er5GTGe/7PHVeMQ4Iun4LLMppt5vs46zMdwj+c9YKfi4kC pXAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738865921; x=1739470721; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJl7/XCq/mOYxrX7g6HKZEwMAdetJgh4DocsCwIosNE=; b=ljIKkg/t679Qo0Y5WntrvQrUAcGCEpf7PwodlGW40Sxx+Vt8Mdj6FL+afl5xp392Td VHAbUIDYZzGFM2KcxqcwHpQrecVlu1oIKQC2uvkLZ7tLjvXa4K15DKxjByh8TH5bb6ru Uf4tR6KR+H/6wEMcKmchlr8ZRQVOG/Od2R2XVU4E6jgbNP/FKWnEGOhz4qsT3M9nKtIA u+HU6MsiFjUbkMR1zJpy6XMZ97w8Npp3G2Jl1+/G6olyI62JXcPdOgI2D7TSTZ4W66ds PmoTgArts5jYkygOTxIynIxDO++0xkwjnkWo+sBtd6SjTjmpWrMAo07zX3iqNxSPocpH slNw== X-Gm-Message-State: AOJu0YyL63hD9tMC87xxabp/zT5nTgIXYnBtaF7JMIdD3AC/II6Jsaa0 hV+vnULLTpkaUMq9IQqSHG7Q4l8QFntJq4ZzBaDhrbxuVCIu0gSp6NdhrVa59tDdurLHXZBDICG oIHU= X-Gm-Gg: ASbGncuWHPFRhnR938OLoneeGYDaupVWP1C7+kp7PkPm8hcIMrliAxAeLOQWseBuEIB YKbAjRNJSFpsfWavaNXQ1VFp6WrRkXCWInqZJpw9V0rHe6bNvgOz28PnL+2zrCSo+eKD5o4L6xh jWNG3n8EIDezFTATv1Biu7K4i+ZOmP5eEBC0IORf+CzqUannlbqg8p+w+CDGF264p/TsgFpOtX+ z3eucREy6dLPypnvhY7F7cyQkKByKe8O16W48pOsJdqcThP0f14eN3bdLwv/q1Geb9TcWVtg37b T5H+5lMBYYrQ/ntDqpQVKv2K0nslfTn9ahI4OebuP7oEKDzUmfWBV0wxeEej5AtHLg== X-Google-Smtp-Source: AGHT+IHG7C2tyyfiGwe2p+xdnPWu21qDsS92W896e/2VOWr+1H/9f9iYFPgUHovHTeAn5h1rVy4ZOQ== X-Received: by 2002:a05:600c:1e28:b0:437:c3a1:5fe7 with SMTP id 5b1f17b1804b1-439249abd7amr3524595e9.20.1738865919619; Thu, 06 Feb 2025 10:18:39 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390db11200sm61574155e9.38.2025.02.06.10.18.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h' Date: Thu, 6 Feb 2025 19:18:22 +0100 Message-ID: <20250206181827.41557-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "cpu.h" is target-specific. Definitions which can be used by hw/ code when building QOM blocks can be in "cpu-qom.h", which is target-agnostic. Move the MISA bits (removing the pointless target_ulong cast) and the IRQ index definitions. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu-qom.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 24 ------------------------ target/riscv/cpu_bits.h | 15 --------------- 3 files changed, 40 insertions(+), 39 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index d56b067bf24..6028aa38fb2 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -55,4 +55,44 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) +/* Interrupt causes */ +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define RV(x) (1UL << (x - 'A')) + +/* + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] + * when adding new MISA bits here. + */ +#define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ +#define RVM RV('M') +#define RVA RV('A') +#define RVF RV('F') +#define RVD RV('D') +#define RVV RV('V') +#define RVC RV('C') +#define RVS RV('S') +#define RVU RV('U') +#define RVH RV('H') +#define RVG RV('G') +#define RVB RV('B') + +extern const uint32_t misa_bits[]; +const char *riscv_get_misa_ext_name(uint32_t bit); +const char *riscv_get_misa_ext_description(uint32_t bit); + #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cbe..4e681ad3917 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -54,30 +54,6 @@ typedef struct CPUArchState CPURISCVState; */ #define RISCV_UW2_ALWAYS_STORE_AMO 1 -#define RV(x) ((target_ulong)1 << (x - 'A')) - -/* - * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] - * when adding new MISA bits here. - */ -#define RVI RV('I') -#define RVE RV('E') /* E and I are mutually exclusive */ -#define RVM RV('M') -#define RVA RV('A') -#define RVF RV('F') -#define RVD RV('D') -#define RVV RV('V') -#define RVC RV('C') -#define RVS RV('S') -#define RVU RV('U') -#define RVH RV('H') -#define RVG RV('G') -#define RVB RV('B') - -extern const uint32_t misa_bits[]; -const char *riscv_get_misa_ext_name(uint32_t bit); -const char *riscv_get_misa_ext_description(uint32_t bit); - #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) typedef struct riscv_cpu_profile { diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f97c48a3943..80701bc77fe 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -720,21 +720,6 @@ typedef enum RISCVException { #define RISCV_EXCP_INT_FLAG 0x80000000 #define RISCV_EXCP_INT_MASK 0x7fffffff -/* Interrupt causes */ -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 64 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) From patchwork Thu Feb 6 18:18:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13963507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30560C0219B for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dc9ffcdsm26115595e9.15.2025.02.06.10.18.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header Date: Thu, 6 Feb 2025 19:18:23 +0100 Message-ID: <20250206181827.41557-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org opentitan_machine_init() calls get_system_memory(), which is declared in "exec/address-spaces.h". Include it in order to avoid when refactoring unrelated headers: hw/riscv/opentitan.c:83:29: error: call to undeclared function 'get_system_memory' 83 | MemoryRegion *sys_mem = get_system_memory(); | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- hw/riscv/opentitan.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index b9e56235d87..98a67fe52a8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -28,6 +28,7 @@ #include "hw/riscv/boot.h" #include "qemu/units.h" #include "system/system.h" +#include "exec/address-spaces.h" /* * This version of the OpenTitan machine currently supports From patchwork Thu Feb 6 18:18:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13963508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08326C02199 for ; Thu, 6 Feb 2025 18:20:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg6Sl-0007lI-8k; Thu, 06 Feb 2025 13:18:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg6Sj-0007hb-Ez for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:18:53 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg6Sh-0006pc-Jx for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:18:53 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-43634b570c1so8950705e9.0 for ; Thu, 06 Feb 2025 10:18:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738865929; x=1739470729; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nF0gOL375kOEqgBWe6BH6Zaiz34mrVikUB/O+vzSeyU=; b=lJyTZgulPhZDU/yoF6OKY0U02otJMjDLM53Tc7ch0Qx6ett9hVidjMEYrNrg7J6JUw Xs0YSBXvtAsGs4Jvu6XC/LdwrSA+OMpwsHlMf8ho3lUr1b2P2vgElCfMIRNYmDWmkROY Lreu1NhSqSjZsI1kq93q/KXm2iwdyOWIIJ580UFvbpJJhn9086uMljg9zFBOMM3ReEGA pm+YAG7OFMMBzTISb4pJSpLHC+MQU4wKLH3JeLu6AXBF2Sb4FtVuO0qIqxNpR+npLl0b L5aqSYg9XxQsieILhGj8+Tl3QshJueoUMDfpdAA2Daxez2ccwNiLIqbEFFqEfkAiCDkD hfpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738865929; x=1739470729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nF0gOL375kOEqgBWe6BH6Zaiz34mrVikUB/O+vzSeyU=; b=dv0Gq0CtXWXbXdbncLUZVaVvkTpTAsNhPGRAEEgnnSOteC3TJIWXxnugbjJHzxpR6e IPEcvNkk4rByl2wicTLJ6ForENjRAwUzC8dlIG7pO7ogrZa+GVTPDTThuSOTnbVbSR4Z AZnkQMUYTSfxDaZhkQ2MR0c75A1S8k364h2OHuqo4vH6xPtauwV1pKPCOK4O2NYcNtee DafcJE+XOmFvW8DXh/9DZzFD54+6xxx7szj67Ye3M8l2+Km4tPT1Gp1DiArEr0B4tv6G 43TNpyWlRqTU/ko6zgMWX3HrHNOS/cuSp9JIkWl84NPLiAhwChf+pvHT8x5QA2/dflx3 dnnw== X-Gm-Message-State: AOJu0Ywdt6ScsTujgsfZcsNQGIVWoeSHDLkLKIBw8Ou/XSDq9tDTa2zo qSQazsi6DGZqtCck2tSKeRfBgSTEanimSgCRg508tuiut0ixc3uZPjIVo9fbxSCerf9uxUfx1fB MgwE= X-Gm-Gg: ASbGncsAQdxeuDq9yG9iM+HKswwvOV1u9H5//YtGJ0lor5hgJnjf9Nif45+nyUM1gTd 5FZn/Sn5xGYs+nzNJ/i8gU5kkd1+QuORb0C71VLjibO2bWuJwJhJOEQMmRFINyHj59MEACafPh6 fcL2RQ84C77OlLax6zgUfQSFTcIalIsyKrFkNmQ4EygvaC4QtafCfq9y6V0v9eq6tKBq/0OtuP7 pkLxFS9tQ0vEIj9k18/MIxOle8iUNVVKoCzjCWwDF71ovCvY/0O1NOnLzliz2vIrG/jt5MeblZ1 7RhMe5kYp9blapUjjm328Gr5E4AF0SST+0xhSBv3fNoFWwNtIE0QbF6I9mS8SHg72A== X-Google-Smtp-Source: AGHT+IEr6mKVF/5i7XI9bPvijw6JSF2ZIebTXVKbzR1YpFeo3XtTLng05fB/qgrsOlZD9l4eG5PdLQ== X-Received: by 2002:a05:600c:1c0e:b0:434:fdf3:2c26 with SMTP id 5b1f17b1804b1-439249a8b60mr3401665e9.19.1738865929487; Thu, 06 Feb 2025 10:18:49 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d40csm62272665e9.9.2025.02.06.10.18.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/7] hw/riscv/boot: Use 'hwaddr' type for firmware addresses Date: Thu, 6 Feb 2025 19:18:24 +0100 Message-ID: <20250206181827.41557-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some places already use the hwaddr type. Use it all over the API allows it to be target agnostic. Use cpu_env() in riscv_plic_hart_config_string() to shorten the access. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/boot.h | 21 ++++++++++----------- include/hw/riscv/boot_opensbi.h | 14 +++++++------- hw/riscv/boot.c | 28 ++++++++++++++-------------- 3 files changed, 31 insertions(+), 32 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7d59b2e6c63..1f66432eaed 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -20,7 +20,6 @@ #ifndef RISCV_BOOT_H #define RISCV_BOOT_H -#include "exec/cpu-defs.h" #include "hw/loader.h" #include "hw/riscv/riscv_hart.h" @@ -43,21 +42,21 @@ bool riscv_is_32bit(RISCVHartArrayState *harts); char *riscv_plic_hart_config_string(int hart_count); void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr); -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firmware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr); +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); const char *riscv_default_firmware_name(RISCVHartArrayState *harts); char *riscv_find_firmware(const char *firmware_filename, const char *default_machine_firmware); -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb); +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb); void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, - target_ulong kernel_start_addr, + hwaddr kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h index 18664a174b5..e6998c668ad 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -8,7 +8,7 @@ #ifndef RISCV_BOOT_OPENSBI_H #define RISCV_BOOT_OPENSBI_H -#include "exec/cpu-defs.h" +#include "exec/hwaddr.h" /** Expected value of info magic ('OSBI' ascii string in hex) */ #define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f @@ -31,15 +31,15 @@ enum sbi_scratch_options { /** Representation dynamic info passed by previous booting stage */ struct fw_dynamic_info { /** Info magic */ - target_long magic; + hwaddr magic; /** Info version */ - target_long version; + hwaddr version; /** Next booting stage address */ - target_long next_addr; + hwaddr next_addr; /** Next booting stage mode */ - target_long next_mode; + hwaddr next_mode; /** Options for OpenSBI library */ - target_long options; + hwaddr options; /** * Preferred boot HART id * @@ -55,7 +55,7 @@ struct fw_dynamic_info { * stage can set it to -1UL which will force the FW_DYNAMIC firmware * to use the relocation lottery mechanism. */ - target_long boot_hart; + hwaddr boot_hart; }; /** Representation dynamic info passed by previous booting stage */ diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c309441b7d8..acc0d221fce 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -21,7 +21,6 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/error-report.h" -#include "exec/cpu-defs.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/riscv/boot.h" @@ -31,6 +30,7 @@ #include "system/qtest.h" #include "system/kvm.h" #include "system/reset.h" +#include "target/riscv/cpu.h" #include @@ -51,7 +51,7 @@ char *riscv_plic_hart_config_string(int hart_count) for (i = 0; i < hart_count; i++) { CPUState *cs = qemu_get_cpu(i); - CPURISCVState *env = &RISCV_CPU(cs)->env; + CPURISCVState *env = cpu_env(cs); if (kvm_enabled()) { vals[i] = "S"; @@ -74,8 +74,8 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) info->is_32bit = riscv_is_32bit(harts); } -target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, - target_ulong firmware_end_addr) { +hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, + hwaddr firmware_end_addr) { if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { @@ -133,13 +133,13 @@ char *riscv_find_firmware(const char *firmware_filename, return filename; } -target_ulong riscv_find_and_load_firmware(MachineState *machine, - const char *default_machine_firmware, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_find_and_load_firmware(MachineState *machine, + const char *default_machine_firmware, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { char *firmware_filename; - target_ulong firmware_end_addr = *firmware_load_addr; + hwaddr firmware_end_addr = *firmware_load_addr; firmware_filename = riscv_find_firmware(machine->firmware, default_machine_firmware); @@ -154,11 +154,11 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine, return firmware_end_addr; } -target_ulong riscv_load_firmware(const char *firmware_filename, - hwaddr *firmware_load_addr, - symbol_fn_t sym_cb) +hwaddr riscv_load_firmware(const char *firmware_filename, + hwaddr *firmware_load_addr, + symbol_fn_t sym_cb) { - uint64_t firmware_entry, firmware_end; + hwaddr firmware_entry, firmware_end; ssize_t firmware_size; g_assert(firmware_filename != NULL); @@ -227,7 +227,7 @@ static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) void riscv_load_kernel(MachineState *machine, RISCVBootInfo *info, - target_ulong kernel_start_addr, + hwaddr kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb) { From patchwork Thu Feb 6 18:18:25 2025 Content-Type: text/plain; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43907f16ffasm58795995e9.1.2025.02.06.10.18.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code Date: Thu, 6 Feb 2025 19:18:25 +0100 Message-ID: <20250206181827.41557-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Use the qemu_target_page_size() runtime function instead of the TARGET_PAGE_SIZE definition, remove unnecessary "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/riscv-iommu-pci.c | 5 +++-- hw/riscv/riscv-iommu-sys.c | 1 - hw/riscv/riscv-iommu.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index 12451869e41..d8779481421 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -22,13 +22,13 @@ #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" +#include "exec/target_page.h" #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/host-utils.h" #include "qom/object.h" -#include "cpu_bits.h" #include "riscv-iommu.h" #include "riscv-iommu-bits.h" #include "trace.h" @@ -102,7 +102,8 @@ static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) qdev_realize(DEVICE(iommu), NULL, errp); memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", - QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); + QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), + qemu_target_page_size())); memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); pcie_endpoint_cap_init(dev, 0); diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c index 65b24fb07de..bbe839ed241 100644 --- a/hw/riscv/riscv-iommu-sys.c +++ b/hw/riscv/riscv-iommu-sys.c @@ -26,7 +26,6 @@ #include "qemu/host-utils.h" #include "qemu/module.h" #include "qom/object.h" -#include "exec/exec-all.h" #include "trace.h" #include "riscv-iommu.h" diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index e7568ca227a..fb763e6e69d 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/timer.h" +#include "target/riscv/cpu.h" #include "cpu_bits.h" #include "riscv-iommu.h" #include "riscv-iommu-bits.h" From patchwork Thu Feb 6 18:18:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13963511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A063C02194 for ; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94d802sm65995685e9.12.2025.02.06.10.18.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:18:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 6/7] hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic Date: Thu, 6 Feb 2025 19:18:26 +0100 Message-ID: <20250206181827.41557-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hardware code using HART rarely needs to knows its internals. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/riscv_hart.h | 4 ++-- hw/riscv/virt-acpi-build.c | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index a6ed73a1956..a2ca455d8b1 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -22,7 +22,7 @@ #define HW_RISCV_HART_H #include "hw/sysbus.h" -#include "target/riscv/cpu.h" +#include "target/riscv/cpu-qom.h" #include "qom/object.h" #define TYPE_RISCV_HART_ARRAY "riscv.hart_array" @@ -42,7 +42,7 @@ struct RISCVHartArrayState { uint64_t *rnmi_irqvec; uint32_t num_rnmi_excpvec; uint64_t *rnmi_excpvec; - RISCVCPU *harts; + ArchCPU *harts; }; #endif diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 1ad68005085..0030c21bc41 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -39,6 +39,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "system/reset.h" +#include "target/riscv/cpu.h" #define ACPI_BUILD_TABLE_SIZE 0x20000 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) From patchwork Thu Feb 6 18:18:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13963509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9582C0219B for ; Thu, 6 Feb 2025 18:20:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tg6T7-0008Ni-0y; Thu, 06 Feb 2025 13:19:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tg6T5-0008Jd-CO for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:19:15 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tg6T1-0006sJ-AU for qemu-devel@nongnu.org; Thu, 06 Feb 2025 13:19:15 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-38daf156e97so692341f8f.0 for ; Thu, 06 Feb 2025 10:19:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1738865945; x=1739470745; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cvk5XVWM6B/U3edLFXPiRke7Pe808hVHpTM0rnQwgtQ=; b=SVIQACkHxIxHQXcjc1ksIuC4CypjMF+czbB9r4LmfXrZNM1d+hCDdgrzgZMSgtN/1/ jjWPWNFTzb/YWWv3ts5ruL80JDW9XgCFF/hPnX1ub8ycVwoYLv89B8fTyheym9KnWuPm uWJk3h+Fj86prAJeHuh2dNPoY+x0s2cOcZNIdwKYEc/fBHlPUPmXnPcigbS/6PrhogLh 8RVXXaBoa8t0wJRSe5IOMTvsBG8fQkDYnXOFvAxX/WR5fV3hGbSdMdX7IhYZ1IqeroNx ELuC8MIvwzY2ym+T/Qo559luruWDRnwY4RWdc/IvU4r3yevVEzqlFDWAlXHjyiKA5bd3 a33g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738865945; x=1739470745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cvk5XVWM6B/U3edLFXPiRke7Pe808hVHpTM0rnQwgtQ=; b=tXG47fvlC8/BYjcM+LhaEDV+7AK7fXoTsl9J5UtByeUkDokh8o3QeLe8Izkg+iQTEv f7+BApPPWYFk4x2btv2+KszPsSNYrKV5hZVofuaCKKbhbCrseNdUps3qYA1XUGdoX4zQ Itz4lmsh1bunvFnFL0UIOQWbou12BdZvgB2gxbojntrAlVnSIyi3Mry9aH9A8O/pSblQ KMSWgl/UHuCyb1plm0RkOqjic7Jl67YV1BRrYLlUsEFljBbxhcO+dXXwCxbCiOJHDNzl GzQIo38asw1tswj04FRqfKFo9b4ksnszoiqKC2oWVsteDvUz2WHfcim2cmwcfqSagnFP Yxjg== X-Gm-Message-State: AOJu0Yzf/CxA0leVaQEAV4XQlwrjQRZeox1frOxJ+spEdzsgygmbW8rF uISKWYADXeuOfZy0qDYwRcvsiRxEVZZgNTfRQwMB6J8VtJikuayc72SOb4qXe5D2mlxqpYR3qqF 0xTo= X-Gm-Gg: ASbGncuqqySk/Bd7NhUlhb20UPC9tjKEApQUKIeU4KuEoqcy57YhDeY3TwICTcT5V9O c6uskgeI7nt5s9Q7FEdaYmd4/vLW5k4xF97kUjP5SUPtGOgk9Gq2pGSmhepfC4bA/fDWp8J7nV/ CK4PsRkU8pLPM6EP6y+g0ROfuM4jJji9sKTM5Pr3cYMkmL1L07yyiAr/sqHr+jg6n6Qi08kYS9b e1RYkAiyBy146Mf9/5V0pyjrZcSNhMTAtZewjF8UmCAK3+aLuWcZtIa31Q8tisb9YHk4QNbDX2Z 6vapRnzYFUHK4kcfWU2t7j9sHXVHYJ43q0BGJzyQsbH9g1zYWnrnaPO2pldgde/9XQ== X-Google-Smtp-Source: AGHT+IEISMzuba5y5/a/hV1oFvHOX1dJCnIqiaCa55m0+aDk27ImuF5o9z6OsKXLJ5E4PHf3A2yCLA== X-Received: by 2002:adf:e30e:0:b0:38d:c85c:f917 with SMTP id ffacd0b85a97d-38dc85cf9f1mr99566f8f.55.1738865945467; Thu, 06 Feb 2025 10:19:05 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd1c151sm2310535f8f.7.2025.02.06.10.19.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 10:19:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, Alistair Francis , Daniel Henrique Barboza , Bin Meng , Weiwei Li , Sunil V L , Liu Zhiwei , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 7/7] hw/riscv: Move few objects to common_ss[] to build them once Date: Thu, 6 Feb 2025 19:18:27 +0100 Message-ID: <20250206181827.41557-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206181827.41557-1-philmd@linaro.org> References: <20250206181827.41557-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org opentitan.c, riscv-iommu-pci.c, riscv-iommu-sys.c don't depend on target-specific knowledge. Move them to common_ss[] to build them once. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/meson.build | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 3c7e083aca1..ff578a2e01a 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -2,7 +2,7 @@ riscv_ss = ss.source_set() riscv_ss.add(files('boot.c')) riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) riscv_ss.add(files('riscv_hart.c')) -riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) +common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) @@ -10,7 +10,8 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c')) +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c')) +common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu-pci.c', 'riscv-iommu-sys.c')) riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c')) hw_arch += {'riscv': riscv_ss}