From patchwork Thu Feb 6 18:55:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2519EC0219C for ; Thu, 6 Feb 2025 18:55:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC1DD10E310; Thu, 6 Feb 2025 18:55:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JfZBqcdH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id F3A3910E310; Thu, 6 Feb 2025 18:55:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738868140; x=1770404140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KhGKm2kkbs68HGctwgtBF+G44HsqW0F8x2qWNXzIPYE=; b=JfZBqcdH1rawFKDwmYyep17dLWhTey+OIqH5mDBfLgMloW6zpLs0P6lt NN5xoxoG7iENe4Wh3VdSr7sV5v1enJtUYYUM/H+eaCJzDdXuIttLhjps/ NIUwhFElxMTfH3W2HlHO6YBv2i/goZnLdD27etKkKkT0FXLG+2ihydwpX xR6JfEIVI/Kao7Pe8LoluEumlrLz3ePVtlXt7IQE+9SL/j+Myjo2XDNFu /MwFKTO3M18DSjoyMV+MVteF3VsrZ5CHksWxfgrTE069UT8EWknF9UV3V Ec2lxsfQfPWLj4SKpHcm3iHMfG9uKk2NQhsPQ9e8jGE85rWpI+XNgQi0c A==; X-CSE-ConnectionGUID: bbpxWhmeSTaQoXT95hLHUw== X-CSE-MsgGUID: HDak/NGHQpK0jujtHZbfeA== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395037" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395037" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:55:39 -0800 X-CSE-ConnectionGUID: /MWY9CRpRdSZcdR4wGqiXw== X-CSE-MsgGUID: yG7AofNwRPWUFEMpEXtuKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499536" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:37 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:36 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 01/12] drm/i915: Pass intel_display to intel_scanout_needs_vtd_wa() Date: Thu, 6 Feb 2025 20:55:22 +0200 Message-ID: <20250206185533.32306-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that intel_scanout_needs_vtd_wa() is no longer used from the gem code we can convert it to take struct intel_display. which will help with converting the low level plane code over as well. Cc: Jani Nikula Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_cursor.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 10 +++++----- drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 ++- 6 files changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index bd3f8db13700..110ad49884be 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -780,13 +780,13 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); if (intel_plane_can_async_flip(plane, fb->modifier)) return 256 * 1024; /* FIXME undocumented so not sure what's actually needed */ - if (intel_scanout_needs_vtd_wa(i915)) + if (intel_scanout_needs_vtd_wa(display)) return 256 * 1024; switch (fb->modifier) { @@ -804,12 +804,12 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); if (intel_plane_can_async_flip(plane, fb->modifier)) return 256 * 1024; - if (intel_scanout_needs_vtd_wa(i915)) + if (intel_scanout_needs_vtd_wa(display)) return 256 * 1024; switch (fb->modifier) { @@ -865,6 +865,7 @@ static const struct drm_plane_funcs i8xx_plane_funcs = { struct intel_plane * intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; unsigned int supported_rotations; @@ -959,7 +960,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->min_alignment = i9xx_plane_min_alignment; /* FIXME undocumented for VLV/CHV so not sure what's actually needed */ - if (intel_scanout_needs_vtd_wa(dev_priv)) + if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 128; if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 6a1035a22b0a..791557b99d94 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -372,9 +372,9 @@ static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); - if (intel_scanout_needs_vtd_wa(i915)) + if (intel_scanout_needs_vtd_wa(display)) return 64 * 1024; return 4 * 1024; /* physical for i915/i945 */ @@ -989,6 +989,7 @@ struct intel_plane * intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; struct intel_plane *cursor; int ret, zpos; u64 *modifiers; @@ -1019,7 +1020,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, else cursor->min_alignment = i9xx_cursor_min_alignment; - if (intel_scanout_needs_vtd_wa(dev_priv)) + if (intel_scanout_needs_vtd_wa(display)) cursor->vtd_guard = 2; cursor->update_arm = i9xx_cursor_update_arm; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a6383ddde871..0f4d4a86cb98 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8782,7 +8782,9 @@ void intel_hpd_poll_fini(struct drm_i915_private *i915) drm_connector_list_iter_end(&conn_iter); } -bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) +bool intel_scanout_needs_vtd_wa(struct intel_display *display) { - return IS_DISPLAY_VER(i915, 6, 11) && i915_vtd_active(i915); + struct drm_i915_private *i915 = to_i915(display->drm); + + return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 49a246feb1ae..793c9d30c582 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -596,7 +596,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port); unlikely(__ret_warn_on); \ }) -bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); +bool intel_scanout_needs_vtd_wa(struct intel_display *display); int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state); #endif diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index a6b27798fdc3..d873c3ea5fa6 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -980,9 +980,9 @@ static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); - if (intel_scanout_needs_vtd_wa(i915)) + if (intel_scanout_needs_vtd_wa(display)) return 128 * 1024; return 4 * 1024; @@ -1610,7 +1610,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_cdclk = vlv_plane_min_cdclk; /* FIXME undocumented for VLV/CHV so not sure what's actually needed */ - if (intel_scanout_needs_vtd_wa(dev_priv)) + if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 128; if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { @@ -1639,7 +1639,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_alignment = g4x_sprite_min_alignment; - if (intel_scanout_needs_vtd_wa(dev_priv)) + if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 64; formats = snb_sprite_formats; @@ -1656,7 +1656,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_alignment = g4x_sprite_min_alignment; plane->min_cdclk = g4x_sprite_min_cdclk; - if (intel_scanout_needs_vtd_wa(dev_priv)) + if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 64; if (IS_SANDYBRIDGE(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ee93361bba09..e166e1915afa 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2697,6 +2697,7 @@ struct intel_plane * skl_universal_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, enum plane_id plane_id) { + struct intel_display *display = &dev_priv->display; const struct drm_plane_funcs *plane_funcs; struct intel_plane *plane; enum drm_plane_type plane_type; @@ -2750,7 +2751,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane->min_alignment = skl_plane_min_alignment; - if (intel_scanout_needs_vtd_wa(dev_priv)) + if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = DISPLAY_VER(dev_priv) >= 10 ? 168 : 136; if (DISPLAY_VER(dev_priv) >= 11) { From patchwork Thu Feb 6 18:55:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C95CBC02199 for ; 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X-CSE-ConnectionGUID: SZMAk07MTc6FhELV7K1rlQ== X-CSE-MsgGUID: 3DHZo0hdTvazLOdfpyNUyg== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395040" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395040" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:55:43 -0800 X-CSE-ConnectionGUID: WHNBZ2gPQ0O4LvccOK5KdA== X-CSE-MsgGUID: ZuLpZEqyTCaMNMeQfuRrRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499541" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:41 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:39 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 02/12] drm/i915: Decouple i915_gem_dumb_create() from the display a bit Date: Thu, 6 Feb 2025 20:55:23 +0200 Message-ID: <20250206185533.32306-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pass the device argument as drm_device to intel_plane_fb_max_stride() to decouple i915_gem_dumb_create() vs. the display code a bit. xe currently doesn't even call this, but it probably should... v2: s/dev/drm/ (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 4 ++-- drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0f4d4a86cb98..a04eeaf6f819 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -713,13 +713,15 @@ void intel_add_fb_offsets(int *x, int *y, *y += state->view.color_plane[color_plane].y; } -u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, +u32 intel_plane_fb_max_stride(struct drm_device *drm, u32 pixel_format, u64 modifier) { + struct intel_display *display = to_intel_display(drm); + struct drm_i915_private *dev_priv = to_i915(drm); struct intel_crtc *crtc; struct intel_plane *plane; - if (!HAS_DISPLAY(dev_priv)) + if (!HAS_DISPLAY(display)) return 0; /* diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 793c9d30c582..e594492bade7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -421,7 +421,7 @@ void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, int bw_overhead, struct intel_link_m_n *m_n); -u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, +u32 intel_plane_fb_max_stride(struct drm_device *drm, u32 pixel_format, u64 modifier); enum drm_mode_status intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index d9328877cc6d..42c46376daae 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1895,7 +1895,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, */ if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) || intel_fb_modifier_uses_dpt(dev_priv, modifier)) - return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); + return intel_plane_fb_max_stride(&dev_priv->drm, pixel_format, modifier); else if (DISPLAY_VER(dev_priv) >= 7) return 256 * 1024; else @@ -1909,7 +1909,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) unsigned int tile_width; if (is_surface_linear(fb, color_plane)) { - unsigned int max_stride = intel_plane_fb_max_stride(dev_priv, + unsigned int max_stride = intel_plane_fb_max_stride(&dev_priv->drm, fb->format->format, fb->modifier); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 19156ba4b9ef..c3e6a325872d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -193,7 +193,7 @@ i915_gem_dumb_create(struct drm_file *file, args->pitch = ALIGN(args->width * cpp, 64); /* align stride to page size so that we can remap */ - if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format, + if (args->pitch > intel_plane_fb_max_stride(dev, format, DRM_FORMAT_MOD_LINEAR)) args->pitch = ALIGN(args->pitch, 4096); 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06 Feb 2025 10:55:46 -0800 X-CSE-ConnectionGUID: s9/vp8oLRIKOebjbWwltBw== X-CSE-MsgGUID: EygLZls8SHWXyMnG25gD4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499545" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:44 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:43 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 03/12] drm/i915: Decouple intel_fb_bo.h interfaces from driver specific types Date: Thu, 6 Feb 2025 20:55:24 +0200 Message-ID: <20250206185533.32306-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Make the intel_fb_bo.h interfaces operated purely in base drm_ types so that each driver (i915 and xe) doesn't have to know about each other, or the display stuff. v2: s/dev/drm/ (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 5 ++--- drivers/gpu/drm/i915/display/intel_fb_bo.c | 5 +++-- drivers/gpu/drm/i915/display/intel_fb_bo.h | 8 ++++---- drivers/gpu/drm/xe/display/intel_fb_bo.c | 7 ++++--- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 42c46376daae..872c3fd62846 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -2126,7 +2126,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, int ret = -EINVAL; int i; - ret = intel_fb_bo_framebuffer_init(intel_fb, obj, mode_cmd); + ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd); if (ret) return ret; @@ -2242,9 +2242,8 @@ intel_user_framebuffer_create(struct drm_device *dev, struct drm_framebuffer *fb; struct drm_gem_object *obj; struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; - struct drm_i915_private *i915 = to_i915(dev); - obj = intel_fb_bo_lookup_valid_bo(i915, filp, &mode_cmd); + obj = intel_fb_bo_lookup_valid_bo(dev, filp, &mode_cmd); if (IS_ERR(obj)) return ERR_CAST(obj); diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.c b/drivers/gpu/drm/i915/display/intel_fb_bo.c index 810ca6ff8640..ecc95beaf6df 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_bo.c +++ b/drivers/gpu/drm/i915/display/intel_fb_bo.c @@ -16,7 +16,7 @@ void intel_fb_bo_framebuffer_fini(struct drm_gem_object *obj) /* Nothing to do for i915 */ } -int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, +int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, struct drm_gem_object *_obj, struct drm_mode_fb_cmd2 *mode_cmd) { @@ -76,10 +76,11 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, } struct drm_gem_object * -intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915, +intel_fb_bo_lookup_valid_bo(struct drm_device *drm, struct drm_file *filp, const struct drm_mode_fb_cmd2 *mode_cmd) { + struct drm_i915_private *i915 = to_i915(drm); struct drm_i915_gem_object *obj; obj = i915_gem_object_lookup(filp, mode_cmd->handles[0]); diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.h b/drivers/gpu/drm/i915/display/intel_fb_bo.h index e71acd1bcb24..eefcb05a99f0 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_bo.h +++ b/drivers/gpu/drm/i915/display/intel_fb_bo.h @@ -6,20 +6,20 @@ #ifndef __INTEL_FB_BO_H__ #define __INTEL_FB_BO_H__ +struct drm_device; struct drm_file; +struct drm_framebuffer; struct drm_gem_object; -struct drm_i915_private; struct drm_mode_fb_cmd2; -struct intel_framebuffer; void intel_fb_bo_framebuffer_fini(struct drm_gem_object *obj); -int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, +int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd); struct drm_gem_object * -intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915, +intel_fb_bo_lookup_valid_bo(struct drm_device *drm, struct drm_file *filp, const struct drm_mode_fb_cmd2 *user_mode_cmd); diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c b/drivers/gpu/drm/xe/display/intel_fb_bo.c index 4d209ebc26c2..3f8e8d31e800 100644 --- a/drivers/gpu/drm/xe/display/intel_fb_bo.c +++ b/drivers/gpu/drm/xe/display/intel_fb_bo.c @@ -24,7 +24,7 @@ void intel_fb_bo_framebuffer_fini(struct drm_gem_object *obj) xe_bo_put(bo); } -int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, +int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd) { @@ -68,10 +68,11 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, return ret; } -struct drm_gem_object *intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915, +struct drm_gem_object *intel_fb_bo_lookup_valid_bo(struct drm_device *drm, struct drm_file *filp, const struct drm_mode_fb_cmd2 *mode_cmd) { + struct xe_device *xe = to_xe_device(drm); struct xe_bo *bo; struct drm_gem_object *gem = drm_gem_object_lookup(filp, mode_cmd->handles[0]); @@ -80,7 +81,7 @@ struct drm_gem_object *intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915 bo = gem_to_xe_bo(gem); /* Require vram placement or dma-buf import */ - if (IS_DGFX(i915) && + if (IS_DGFX(xe) && !xe_bo_can_migrate(bo, XE_PL_VRAM0) && bo->ttm.type != ttm_bo_type_sg) { drm_gem_object_put(gem); From patchwork Thu Feb 6 18:55:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D933AC0219B for ; Thu, 6 Feb 2025 18:55:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C28010E15E; Thu, 6 Feb 2025 18:55:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="39395045" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395045" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:55:50 -0800 X-CSE-ConnectionGUID: P4NaU6R9SP2FXbracCNJhw== X-CSE-MsgGUID: /R1aOztXTOONRJfVkJE8pA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499549" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:47 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:46 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 04/12] drm/i915: Convert intel_crtc.c to struct intel_display Date: Thu, 6 Feb 2025 20:55:25 +0200 Message-ID: <20250206185533.32306-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert intel_crtc.c code to use it. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +- drivers/gpu/drm/i915/display/intel_audio.c | 3 +- drivers/gpu/drm/i915/display/intel_crtc.c | 57 ++++++++++--------- drivers/gpu/drm/i915/display/intel_crtc.h | 7 +-- drivers/gpu/drm/i915/display/intel_display.c | 3 +- .../drm/i915/display/intel_display_driver.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 3 +- 8 files changed, 42 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 56353377466c..434de337814c 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -224,7 +224,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, * 2. Program DP PLL enable */ if (IS_IRONLAKE(dev_priv)) - intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); + intel_wait_for_vblank_if_active(display, !crtc->pipe); intel_dp->DP |= DP_PLL_ENABLE; @@ -471,7 +471,7 @@ intel_dp_link_down(struct intel_encoder *encoder, intel_de_write(display, intel_dp->output_reg, intel_dp->DP); intel_de_posting_read(display, intel_dp->output_reg); - intel_wait_for_vblank_if_active(dev_priv, PIPE_A); + intel_wait_for_vblank_if_active(display, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 98e6a931042f..3aaa7f9e9210 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -384,6 +384,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); @@ -426,7 +427,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); - intel_wait_for_vblank_if_active(dev_priv, PIPE_A); + intel_wait_for_vblank_if_active(display, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 113d763e6ef3..f145f83346ca 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -954,13 +954,12 @@ static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, static void glk_force_audio_cdclk(struct intel_display *display, bool enable) { - struct drm_i915_private *i915 = to_i915(display->drm); struct drm_modeset_acquire_ctx ctx; struct drm_atomic_state *state; struct intel_crtc *crtc; int ret; - crtc = intel_first_crtc(i915); + crtc = intel_first_crtc(display); if (!crtc) return; diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index e69b28779ac5..da2d6aeb2072 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -45,9 +45,9 @@ static void assert_vblank_disabled(struct drm_crtc *crtc) drm_crtc_vblank_put(crtc); } -struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915) +struct intel_crtc *intel_first_crtc(struct intel_display *display) { - return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0)); + return to_intel_crtc(drm_crtc_from_index(display->drm, 0)); } struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display, @@ -68,10 +68,9 @@ void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc) drm_crtc_wait_one_vblank(&crtc->base); } -void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, +void intel_wait_for_vblank_if_active(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &i915->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); if (crtc->active) @@ -93,7 +92,7 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); /* * From Gen 11, in case of dsi cmd mode, frame counter wouldn't @@ -109,13 +108,13 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) * On i965gm the hardware frame counter reads * zero when the TV encoder is enabled :( */ - if (IS_I965GM(dev_priv) && + if (display->platform.i965gm && (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) return 0; - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return 0xffffffff; /* full 32 bit counter */ - else if (DISPLAY_VER(dev_priv) >= 3) + else if (DISPLAY_VER(display) >= 3) return 0xffffff; /* only 24 bits of frame count */ else return 0; /* Gen2 doesn't have a hardware frame counter */ @@ -142,8 +141,8 @@ void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_display *display = to_intel_display(crtc); /* * Should really happen exactly when we disable the pipe @@ -304,8 +303,9 @@ static const struct drm_crtc_funcs i8xx_crtc_funcs = { .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; -int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) +int intel_crtc_init(struct intel_display *display, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_plane *primary, *cursor; const struct drm_crtc_funcs *funcs; struct intel_crtc *crtc; @@ -316,9 +316,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) return PTR_ERR(crtc); crtc->pipe = pipe; - crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe]; + crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe]; - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1); else primary = intel_primary_plane_create(dev_priv, pipe); @@ -330,7 +330,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) intel_init_fifo_underrun_reporting(dev_priv, crtc, false); - for_each_sprite(dev_priv, pipe, sprite) { + for_each_sprite(display, pipe, sprite) { struct intel_plane *plane; if (DISPLAY_VER(dev_priv) >= 9) @@ -351,32 +351,34 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) } crtc->plane_ids_mask |= BIT(cursor->id); - if (HAS_GMCH(dev_priv)) { - if (IS_CHERRYVIEW(dev_priv) || - IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) + if (HAS_GMCH(display)) { + if (display->platform.cherryview || + display->platform.valleyview || + display->platform.g4x) funcs = &g4x_crtc_funcs; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(display) == 4) funcs = &i965_crtc_funcs; - else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) + else if (display->platform.i945gm || + display->platform.i915gm) funcs = &i915gm_crtc_funcs; - else if (DISPLAY_VER(dev_priv) == 3) + else if (DISPLAY_VER(display) == 3) funcs = &i915_crtc_funcs; else funcs = &i8xx_crtc_funcs; } else { - if (DISPLAY_VER(dev_priv) >= 8) + if (DISPLAY_VER(display) >= 8) funcs = &bdw_crtc_funcs; else funcs = &ilk_crtc_funcs; } - ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, + ret = drm_crtc_init_with_planes(display->drm, &crtc->base, &primary->base, &cursor->base, funcs, "pipe %c", pipe_name(pipe)); if (ret) goto fail; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) drm_crtc_create_scaling_filter_property(&crtc->base, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); @@ -387,7 +389,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE); - drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe); return 0; @@ -512,7 +514,7 @@ int intel_scanlines_to_usecs(const struct drm_display_mode *adjusted_mode, void intel_pipe_update_start(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = @@ -546,7 +548,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state, intel_vblank_evade_init(old_crtc_state, new_crtc_state, &evade); - if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base))) + if (drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) goto irq_disable; /* @@ -649,6 +651,7 @@ void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state, void intel_pipe_update_end(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; @@ -666,7 +669,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state, * Incase of mipi dsi command mode, we need to set frame update * request for every commit. */ - if (DISPLAY_VER(dev_priv) >= 11 && + if (DISPLAY_VER(display) >= 11 && intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) icl_dsi_frame_update(new_crtc_state); @@ -723,7 +726,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state, if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", pipe_name(pipe), crtc->debug.start_vbl_count, end_vbl_count, diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index de54ae1deedf..8c14ff8b391e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -13,7 +13,6 @@ enum pipe; struct drm_device; struct drm_display_mode; struct drm_file; -struct drm_i915_private; struct drm_pending_vblank_event; struct intel_atomic_state; struct intel_crtc; @@ -38,7 +37,7 @@ void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state); void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state, struct drm_pending_vblank_event **event); u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state); -int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe); +int intel_crtc_init(struct intel_display *display, enum pipe pipe); int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); @@ -52,10 +51,10 @@ void intel_pipe_update_start(struct intel_atomic_state *state, void intel_pipe_update_end(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_wait_for_vblank_workers(struct intel_atomic_state *state); -struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915); +struct intel_crtc *intel_first_crtc(struct intel_display *display); struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display, enum pipe pipe); -void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, +void intel_wait_for_vblank_if_active(struct intel_display *display, enum pipe pipe); void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a04eeaf6f819..e3e96613470b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -717,7 +717,6 @@ u32 intel_plane_fb_max_stride(struct drm_device *drm, u32 pixel_format, u64 modifier) { struct intel_display *display = to_intel_display(drm); - struct drm_i915_private *dev_priv = to_i915(drm); struct intel_crtc *crtc; struct intel_plane *plane; @@ -729,7 +728,7 @@ u32 intel_plane_fb_max_stride(struct drm_device *drm, * the highest stride limits of them all, * if in case pipe A is disabled, use the first pipe from pipe_mask. */ - crtc = intel_first_crtc(dev_priv); + crtc = intel_first_crtc(display); if (!crtc) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index c4120a834698..d448672fdfa4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -442,7 +442,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) INTEL_NUM_PIPES(display) > 1 ? "s" : ""); for_each_pipe(display, pipe) { - ret = intel_crtc_init(i915, pipe); + ret = intel_crtc_init(display, pipe); if (ret) goto err_mode_config; } diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index ca8aeb17c909..6ebd099d8861 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -1838,6 +1838,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); @@ -1873,7 +1874,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, temp &= ~SDVO_ENABLE; intel_sdvo_write_sdvox(intel_sdvo, temp); - intel_wait_for_vblank_if_active(dev_priv, PIPE_A); + intel_wait_for_vblank_if_active(display, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } From patchwork Thu Feb 6 18:55:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 015F9C02199 for ; Thu, 6 Feb 2025 18:55:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E06A10E921; Thu, 6 Feb 2025 18:55:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="evoGO4UK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id F345910E91C; Thu, 6 Feb 2025 18:55:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738868154; x=1770404154; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=50MSKjSiyHOVRvm7CD0LBbZWqkOze6pxcQttGBl7Y+s=; b=evoGO4UKlc0rElvPKawxZdjMUZPqjWj3xluNca2InSO8j2XSj3duwsRL 5mPpnOUxy6amu0TjOzM2PlLivKUkESrLBh3Yysi2ocOUpbvIMYxuOEkOM aDqHRT4Gb4XkDUPytSF71wEwRehby8EgPvPMtHUy+tWW1UPGN1WQebok1 /AmMztVsB+IlITotEmX+fTQMl0vGqHPlhf/xFFJskyjLFZmO01R+m+AlR 1Ldx0w9+GNrte0KBHUHAxmgbjSVb03N7NNt1N3cAOGTry+vKPFiwEahgS T5Cni6+IfNMFdHhAg2ebtlQLg96MQOPa4o+GkGC/B2U9RFmg+LNXi3x8U w==; X-CSE-ConnectionGUID: mY4xVcboRp+hsVxE0f3GmA== X-CSE-MsgGUID: p7Z/DE/XR+SsnJwJ+Z6POg== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395051" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395051" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:55:53 -0800 X-CSE-ConnectionGUID: /ZFBHUiGTR+Up/BnbtVgRg== X-CSE-MsgGUID: N5igfPovRdChPFrfmcDWFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499555" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:51 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:50 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 05/12] drm/i915: Convert intel_fb.c to struct intel_display Date: Thu, 6 Feb 2025 20:55:26 +0200 Message-ID: <20250206185533.32306-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the fb code to use it. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 250 +++++++++--------- drivers/gpu/drm/i915/display/intel_fb.h | 11 +- drivers/gpu/drm/i915/display/intel_fb_bo.c | 13 +- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- .../drm/i915/display/skl_universal_plane.c | 4 +- 7 files changed, 146 insertions(+), 138 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 110ad49884be..5c4652f662cb 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -998,7 +998,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) } } - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); + modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 791557b99d94..9c9cded729af 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -1035,7 +1035,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) cursor->cursor.size = ~0; - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); + modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE); ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 0, &intel_cursor_plane_funcs, diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 872c3fd62846..5af93235057c 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -20,7 +20,7 @@ #include "intel_fb_bo.h" #include "intel_frontbuffer.h" -#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) +#define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) /* * From the Sky Lake PRM: @@ -539,11 +539,13 @@ static bool check_modifier_display_ver_range(const struct intel_modifier_desc *m display_ver_from <= md->display_ver.until; } -static bool plane_has_modifier(struct drm_i915_private *i915, +static bool plane_has_modifier(struct intel_display *display, u8 plane_caps, const struct intel_modifier_desc *md) { - if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) + struct drm_i915_private *i915 = to_i915(display->drm); + + if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) return false; if (!plane_caps_contain_all(plane_caps, md->plane_caps)) @@ -570,14 +572,14 @@ static bool plane_has_modifier(struct drm_i915_private *i915, /** * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities - * @i915: i915 device instance + * @display: display instance * @plane_caps: capabilities for the plane the modifiers are queried for * * Returns: - * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. + * Returns the list of modifiers allowed by the @display platform and @plane_caps. * The caller must free the returned buffer. */ -u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, +u64 *intel_fb_plane_get_modifiers(struct intel_display *display, u8 plane_caps) { u64 *list, *p; @@ -585,17 +587,17 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, int i; for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { - if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) count++; } list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); - if (drm_WARN_ON(&i915->drm, !list)) + if (drm_WARN_ON(display->drm, !list)) return NULL; p = list; for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { - if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) *p++ = intel_modifiers[i].modifier; } *p++ = DRM_FORMAT_MOD_INVALID; @@ -751,33 +753,34 @@ static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_p int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) { const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) return main_to_ccs_plane(fb, main_plane); - else if (DISPLAY_VER(i915) < 11 && + else if (DISPLAY_VER(display) < 11 && format_is_yuv_semiplanar(md, fb->format)) return 1; else return 0; } -unsigned int intel_tile_size(const struct drm_i915_private *i915) +unsigned int intel_tile_size(struct intel_display *display) { - return DISPLAY_VER(i915) == 2 ? 2048 : 4096; + return DISPLAY_VER(display) == 2 ? 2048 : 4096; } unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *dev_priv = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); + struct drm_i915_private *i915 = to_i915(display->drm); unsigned int cpp = fb->format->cpp[color_plane]; switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: - return intel_tile_size(dev_priv); + return intel_tile_size(display); case I915_FORMAT_MOD_X_TILED: - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(display) == 2) return 128; else return 512; @@ -807,7 +810,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 64; fallthrough; case I915_FORMAT_MOD_Y_TILED: - if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)) + if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915)) return 128; else return 512; @@ -838,7 +841,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) { - return intel_tile_size(to_i915(fb->dev)) / + struct intel_display *display = to_intel_display(fb->dev); + + return intel_tile_size(display) / intel_tile_width_bytes(fb, color_plane); } @@ -890,15 +895,17 @@ intel_fb_align_height(const struct drm_framebuffer *fb, return ALIGN(height, tile_height); } -bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier) +bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier) { - return HAS_DPT(i915) && modifier != DRM_FORMAT_MOD_LINEAR; + return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR; } bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) { - return to_i915(fb->dev)->display.params.enable_dpt && - intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); + struct intel_display *display = to_intel_display(fb->dev); + + return display->params.enable_dpt && + intel_fb_modifier_uses_dpt(display, fb->modifier); } void intel_fb_plane_get_subsampling(int *hsub, int *vsub, @@ -1007,16 +1014,16 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, unsigned int pitch, u32 old_offset, u32 new_offset) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); unsigned int cpp = fb->format->cpp[color_plane]; - drm_WARN_ON(&i915->drm, new_offset > old_offset); + drm_WARN_ON(display->drm, new_offset > old_offset); if (!is_surface_linear(fb, color_plane)) { unsigned int tile_size, tile_width, tile_height; unsigned int pitch_tiles; - tile_size = intel_tile_size(i915); + tile_size = intel_tile_size(display); intel_tile_dims(fb, color_plane, &tile_width, &tile_height); if (drm_rotation_90_or_270(rotation)) { @@ -1066,7 +1073,7 @@ u32 intel_plane_adjust_aligned_offset(int *x, int *y, * used. This is why the user has to pass in the pitch since it * is specified in the rotated orientation. */ -static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, +static u32 intel_compute_aligned_offset(struct intel_display *display, int *x, int *y, const struct drm_framebuffer *fb, int color_plane, @@ -1081,7 +1088,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, unsigned int tile_size, tile_width, tile_height; unsigned int tile_rows, tiles, pitch_tiles; - tile_size = intel_tile_size(i915); + tile_size = intel_tile_size(display); intel_tile_dims(fb, color_plane, &tile_width, &tile_height); if (drm_rotation_90_or_270(rotation)) { @@ -1125,14 +1132,14 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y, const struct intel_plane_state *state, int color_plane) { + struct intel_display *display = to_intel_display(state); struct intel_plane *plane = to_intel_plane(state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = state->hw.fb; unsigned int rotation = state->hw.rotation; unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; unsigned int alignment = plane->min_alignment(plane, fb, color_plane); - return intel_compute_aligned_offset(i915, x, y, fb, color_plane, + return intel_compute_aligned_offset(display, x, y, fb, color_plane, pitch, rotation, alignment); } @@ -1141,16 +1148,16 @@ static int intel_fb_offset_to_xy(int *x, int *y, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); unsigned int height, alignment, unused; if (fb->modifier != DRM_FORMAT_MOD_LINEAR) - alignment = intel_tile_size(i915); + alignment = intel_tile_size(display); else alignment = 0; if (alignment != 0 && fb->offsets[color_plane] % alignment) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Misaligned offset 0x%08x for color plane %d\n", fb->offsets[color_plane], color_plane); return -EINVAL; @@ -1162,7 +1169,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, /* Catch potential overflows early */ if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), fb->offsets[color_plane], &unused)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Bad offset 0x%08x or pitch %d for color plane %d\n", fb->offsets[color_plane], fb->pitches[color_plane], color_plane); @@ -1182,7 +1189,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); int main_plane; int hsub, vsub; @@ -1216,13 +1223,12 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane * x/y offsets must match between CCS and the main surface. */ if (main_x != ccs_x || main_y != ccs_y) { - drm_dbg_kms(&i915->drm, - "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", - main_x, main_y, - ccs_x, ccs_y, - intel_fb->normal_view.color_plane[main_plane].x, - intel_fb->normal_view.color_plane[main_plane].y, - x, y); + drm_dbg_kms(display->drm, + "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", + main_x, main_y, ccs_x, ccs_y, + intel_fb->normal_view.color_plane[main_plane].x, + intel_fb->normal_view.color_plane[main_plane].y, + x, y); return -EINVAL; } @@ -1231,8 +1237,8 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int i; @@ -1246,7 +1252,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) * Would also need to deal with the fence POT alignment * and gen2 2KiB GTT tile size. */ - if (DISPLAY_VER(i915) < 4) + if (DISPLAY_VER(display) < 4) return false; /* @@ -1258,7 +1264,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) /* Linear needs a page aligned stride for remapping */ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { - unsigned int alignment = intel_tile_size(i915) - 1; + unsigned int alignment = intel_tile_size(display) - 1; for (i = 0; i < fb->format->num_planes; i++) { if (fb->pitches[i] & alignment) @@ -1271,9 +1277,9 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); - return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && + return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && intel_fb_uses_dpt(&fb->base); } @@ -1318,12 +1324,13 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, int plane_width, int *x, int *y) { + struct intel_display *display = to_intel_display(fb->base.dev); struct drm_gem_object *obj = intel_fb_bo(&fb->base); int ret; ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); if (ret) { - drm_dbg_kms(fb->base.dev, + drm_dbg_kms(display->drm, "bad fb plane %d offset: 0x%x\n", color_plane, fb->base.offsets[color_plane]); return ret; @@ -1344,7 +1351,7 @@ static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int co */ if (color_plane == 0 && intel_bo_is_tiled(obj) && (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { - drm_dbg_kms(fb->base.dev, + drm_dbg_kms(display->drm, "bad fb plane %d offset: 0x%x\n", color_plane, fb->base.offsets[color_plane]); return -EINVAL; @@ -1355,11 +1362,11 @@ static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int co static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); - unsigned int tile_size = intel_tile_size(i915); + struct intel_display *display = to_intel_display(fb->base.dev); + unsigned int tile_size = intel_tile_size(display); u32 offset; - offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane, + offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane, fb->base.pitches[color_plane], DRM_MODE_ROTATE_0, tile_size); @@ -1410,10 +1417,10 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, unsigned int tile_width, unsigned int src_stride_tiles, unsigned int dst_stride_tiles) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); unsigned int stride_tiles; - if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && + if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && src_stride_tiles < dst_stride_tiles) stride_tiles = src_stride_tiles; else @@ -1443,23 +1450,23 @@ plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, const struct fb_plane_view_dims *dims, int x, int y) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); unsigned int size; size = (y + dims->height) * fb->base.pitches[color_plane] + x * fb->base.format->cpp[color_plane]; - return DIV_ROUND_UP(size, intel_tile_size(i915)); + return DIV_ROUND_UP(size, intel_tile_size(display)); } -#define assign_chk_ovf(i915, var, val) ({ \ - drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \ +#define assign_chk_ovf(display, var, val) ({ \ + drm_WARN_ON((display)->drm, overflows_type(val, var)); \ (var) = (val); \ }) -#define assign_bfld_chk_ovf(i915, var, val) ({ \ +#define assign_bfld_chk_ovf(display, var, val) ({ \ (var) = (val); \ - drm_WARN_ON(&(i915)->drm, (var) != (val)); \ + drm_WARN_ON((display)->drm, (var) != (val)); \ (var); \ }) @@ -1468,38 +1475,38 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p u32 obj_offset, u32 gtt_offset, int x, int y, struct intel_fb_view *view) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; unsigned int tile_width = dims->tile_width; unsigned int tile_height = dims->tile_height; - unsigned int tile_size = intel_tile_size(i915); + unsigned int tile_size = intel_tile_size(display); struct drm_rect r; u32 size = 0; - assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset); + assign_bfld_chk_ovf(display, remap_info->offset, obj_offset); if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { remap_info->linear = 1; - assign_chk_ovf(i915, remap_info->size, + assign_chk_ovf(display, remap_info->size, plane_view_linear_tiles(fb, color_plane, dims, x, y)); } else { remap_info->linear = 0; - assign_chk_ovf(i915, remap_info->src_stride, + assign_chk_ovf(display, remap_info->src_stride, plane_view_src_stride_tiles(fb, color_plane, dims)); - assign_chk_ovf(i915, remap_info->width, + assign_chk_ovf(display, remap_info->width, plane_view_width_tiles(fb, color_plane, dims, x)); - assign_chk_ovf(i915, remap_info->height, + assign_chk_ovf(display, remap_info->height, plane_view_height_tiles(fb, color_plane, dims, y)); } if (view->gtt.type == I915_GTT_VIEW_ROTATED) { - drm_WARN_ON(&i915->drm, remap_info->linear); - check_array_bounds(i915, view->gtt.rotated.plane, color_plane); + drm_WARN_ON(display->drm, remap_info->linear); + check_array_bounds(display, view->gtt.rotated.plane, color_plane); - assign_chk_ovf(i915, remap_info->dst_stride, + assign_chk_ovf(display, remap_info->dst_stride, plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); /* rotate the x/y offsets to match the GTT view */ @@ -1520,9 +1527,9 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p /* rotate the tile dimensions to match the GTT view */ swap(tile_width, tile_height); } else { - drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); + drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); - check_array_bounds(i915, view->gtt.remapped.plane, color_plane); + check_array_bounds(display, view->gtt.remapped.plane, color_plane); if (view->gtt.remapped.plane_alignment) { u32 aligned_offset = ALIGN(gtt_offset, @@ -1556,7 +1563,7 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); - assign_chk_ovf(i915, remap_info->dst_stride, dst_stride); + assign_chk_ovf(display, remap_info->dst_stride, dst_stride); color_plane_info->mapping_stride = dst_stride * tile_width * fb->base.format->cpp[color_plane]; @@ -1614,20 +1621,23 @@ calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, return tiles; } -static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view, +static void intel_fb_view_init(struct intel_display *display, + struct intel_fb_view *view, enum i915_gtt_view_type view_type) { memset(view, 0, sizeof(*view)); view->gtt.type = view_type; if (view_type == I915_GTT_VIEW_REMAPPED && - (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)) + (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; } bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) { - if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13) + struct intel_display *display = to_intel_display(fb->base.dev); + + if (DISPLAY_VER(display) >= 13) return false; return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || @@ -1636,11 +1646,11 @@ bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); struct intel_plane *plane; unsigned int min_alignment = 0; - for_each_intel_plane(&i915->drm, plane) { + for_each_intel_plane(display->drm, plane) { unsigned int plane_min_alignment; if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) @@ -1648,7 +1658,7 @@ static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) plane_min_alignment = plane->min_alignment(plane, fb, 0); - drm_WARN_ON(&i915->drm, plane_min_alignment && + drm_WARN_ON(display->drm, plane_min_alignment && !is_power_of_2(plane_min_alignment)); if (intel_plane_needs_physical(plane)) @@ -1662,11 +1672,11 @@ static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); struct intel_plane *plane; unsigned int vtd_guard = 0; - for_each_intel_plane(&i915->drm, plane) { + for_each_intel_plane(display->drm, plane) { if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) continue; @@ -1676,25 +1686,25 @@ static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) return vtd_guard; } -int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) +int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb) { struct drm_gem_object *obj = intel_fb_bo(&fb->base); u32 gtt_offset_rotated = 0; u32 gtt_offset_remapped = 0; unsigned int max_size = 0; int i, num_planes = fb->base.format->num_planes; - unsigned int tile_size = intel_tile_size(i915); + unsigned int tile_size = intel_tile_size(display); - intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL); + intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL); - drm_WARN_ON(&i915->drm, + drm_WARN_ON(display->drm, intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb)); if (intel_fb_supports_90_270_rotation(fb)) - intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED); + intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED); if (intel_fb_needs_pot_stride_remap(fb)) - intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); + intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); for (i = 0; i < num_planes; i++) { struct fb_plane_view_dims view_dims; @@ -1713,14 +1723,14 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * unsigned int end; if (!IS_ALIGNED(fb->base.offsets[i], 64)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb misaligned clear color plane %d offset (0x%x)\n", i, fb->base.offsets[i]); return -EINVAL; } if (check_add_overflow(fb->base.offsets[i], 64, &end)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb bad clear color plane %d offset (0x%x)\n", i, fb->base.offsets[i]); return -EINVAL; @@ -1766,7 +1776,7 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * } if (mul_u32_u32(max_size, tile_size) > obj->size) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb too big for bo (need %llu bytes, have %zu bytes)\n", mul_u32_u32(max_size, tile_size), obj->size); return -EINVAL; @@ -1811,8 +1821,7 @@ unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); struct drm_framebuffer *fb = plane_state->hw.fb; struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); unsigned int rotation = plane_state->hw.rotation; @@ -1821,7 +1830,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) unsigned int src_w, src_h; u32 gtt_offset = 0; - intel_fb_view_init(i915, &plane_state->view, + intel_fb_view_init(display, &plane_state->view, drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : I915_GTT_VIEW_REMAPPED); @@ -1830,7 +1839,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) src_w = drm_rect_width(&plane_state->uapi.src) >> 16; src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier)); + drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier)); /* Make src coordinates relative to the viewport */ drm_rect_translate(&plane_state->uapi.src, @@ -1884,7 +1893,7 @@ void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotatio } static -u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, +u32 intel_fb_max_stride(struct intel_display *display, u32 pixel_format, u64 modifier) { /* @@ -1893,10 +1902,10 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, * * The new CCS hash mode makes remapping impossible */ - if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) || - intel_fb_modifier_uses_dpt(dev_priv, modifier)) - return intel_plane_fb_max_stride(&dev_priv->drm, pixel_format, modifier); - else if (DISPLAY_VER(dev_priv) >= 7) + if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) || + intel_fb_modifier_uses_dpt(display, modifier)) + return intel_plane_fb_max_stride(display->drm, pixel_format, modifier); + else if (DISPLAY_VER(display) >= 7) return 256 * 1024; else return 128 * 1024; @@ -1905,11 +1914,11 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, static unsigned int intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *dev_priv = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); unsigned int tile_width; if (is_surface_linear(fb, color_plane)) { - unsigned int max_stride = intel_plane_fb_max_stride(&dev_priv->drm, + unsigned int max_stride = intel_plane_fb_max_stride(display->drm, fb->format->format, fb->modifier); @@ -1919,7 +1928,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) */ if (fb->pitches[color_plane] > max_stride && !intel_fb_is_ccs_modifier(fb->modifier)) - return intel_tile_size(dev_priv); + return intel_tile_size(display); else return 64; } @@ -1930,7 +1939,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * On TGL the surface stride must be 4 tile aligned, mapped by * one 64 byte cacheline on the CCS AUX surface. */ - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) tile_width *= 4; /* * Display WA #0531: skl,bxt,kbl,glk @@ -1941,7 +1950,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && + else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) && color_plane == 0 && fb->width > 3840) tile_width *= 4; } @@ -1950,6 +1959,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) static int intel_plane_check_stride(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; @@ -1971,7 +1981,7 @@ static int intel_plane_check_stride(const struct intel_plane_state *plane_state) fb->modifier, rotation); if (stride > max_stride) { - drm_dbg_kms(plane->base.dev, + drm_dbg_kms(display->drm, "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", fb->base.id, stride, plane->base.base.id, plane->base.name, max_stride); @@ -2120,7 +2130,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd) { - struct drm_i915_private *dev_priv = to_i915(obj->dev); + struct intel_display *display = to_intel_display(obj->dev); struct drm_framebuffer *fb = &intel_fb->base; u32 max_stride; int ret = -EINVAL; @@ -2137,19 +2147,19 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } ret = -EINVAL; - if (!drm_any_plane_has_format(&dev_priv->drm, + if (!drm_any_plane_has_format(display->drm, mode_cmd->pixel_format, mode_cmd->modifier[0])) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "unsupported pixel format %p4cc / modifier 0x%llx\n", &mode_cmd->pixel_format, mode_cmd->modifier[0]); goto err_frontbuffer_put; } - max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, + max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format, mode_cmd->modifier[0]); if (mode_cmd->pitches[0] > max_stride) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "%s pitch (%u) must be at most %d\n", mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? "tiled" : "linear", @@ -2159,26 +2169,25 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ if (mode_cmd->offsets[0] != 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "plane 0 offset (0x%08x) must be 0\n", mode_cmd->offsets[0]); goto err_frontbuffer_put; } - drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(display->drm, fb, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) { unsigned int stride_alignment; if (mode_cmd->handles[i] != mode_cmd->handles[0]) { - drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", - i); + drm_dbg_kms(display->drm, "bad plane %d handle\n", i); goto err_frontbuffer_put; } stride_alignment = intel_fb_stride_alignment(fb, i); if (fb->pitches[i] & (stride_alignment - 1)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "plane %d pitch (%d) must be at least %u byte aligned\n", i, fb->pitches[i], stride_alignment); goto err_frontbuffer_put; @@ -2188,10 +2197,9 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); if (fb->pitches[i] != ccs_aux_stride) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "ccs aux plane %d pitch (%d) must be %d\n", - i, - fb->pitches[i], ccs_aux_stride); + i, fb->pitches[i], ccs_aux_stride); goto err_frontbuffer_put; } } @@ -2199,7 +2207,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, fb->obj[i] = obj; } - ret = intel_fill_fb_info(dev_priv, intel_fb); + ret = intel_fill_fb_info(display, intel_fb); if (ret) goto err_frontbuffer_put; @@ -2208,7 +2216,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, vm = intel_dpt_create(intel_fb); if (IS_ERR(vm)) { - drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n"); + drm_dbg_kms(display->drm, "failed to create DPT\n"); ret = PTR_ERR(vm); goto err_frontbuffer_put; } @@ -2216,9 +2224,9 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, intel_fb->dpt_vm = vm; } - ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); + ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs); if (ret) { - drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); + drm_err(display->drm, "framebuffer init failed %d\n", ret); goto err_free_dpt; } diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 026e9f7f98f7..e6ef1783e351 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -13,9 +13,8 @@ struct drm_device; struct drm_file; struct drm_framebuffer; struct drm_gem_object; -struct drm_i915_gem_object; -struct drm_i915_private; struct drm_mode_fb_cmd2; +struct intel_display; struct intel_fb_view; struct intel_framebuffer; struct intel_plane; @@ -41,7 +40,7 @@ bool intel_fb_is_tile4_modifier(u64 modifier); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); -u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, +u64 *intel_fb_plane_get_modifiers(struct intel_display *display, u8 plane_caps); bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); @@ -58,7 +57,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane); int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); -unsigned int intel_tile_size(const struct drm_i915_private *i915); +unsigned int intel_tile_size(struct intel_display *display); unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); @@ -80,7 +79,7 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y, bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb); bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb); -int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb); +int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb); void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, struct intel_fb_view *view); unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, @@ -99,7 +98,7 @@ intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, const struct drm_mode_fb_cmd2 *user_mode_cmd); -bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier); +bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier); bool intel_fb_uses_dpt(const struct drm_framebuffer *fb); unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier); diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.c b/drivers/gpu/drm/i915/display/intel_fb_bo.c index ecc95beaf6df..3d338a728354 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_bo.c +++ b/drivers/gpu/drm/i915/display/intel_fb_bo.c @@ -8,6 +8,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_bo.h" @@ -21,7 +22,7 @@ int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_i915_gem_object *obj = to_intel_bo(_obj); - struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct intel_display *display = to_intel_display(obj->base.dev); unsigned int tiling, stride; i915_gem_object_lock(obj, NULL); @@ -36,7 +37,7 @@ int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, */ if (tiling != I915_TILING_NONE && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "tiling_mode doesn't match fb modifier\n"); return -EINVAL; } @@ -44,7 +45,7 @@ int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, if (tiling == I915_TILING_X) { mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; } else if (tiling == I915_TILING_Y) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "No Y tiling for legacy addfb\n"); return -EINVAL; } @@ -54,9 +55,9 @@ int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, * gen2/3 display engine uses the fence if present, * so the tiling mode must match the fb modifier exactly. */ - if (DISPLAY_VER(i915) < 4 && + if (DISPLAY_VER(display) < 4 && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "tiling_mode must match fb modifier exactly on gen2/3\n"); return -EINVAL; } @@ -66,7 +67,7 @@ int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, * the fb pitch and fence stride match. */ if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "pitch (%d) must match tiling stride (%d)\n", mode_cmd->pitches[0], stride); return -EINVAL; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index d873c3ea5fa6..ee7839eb4099 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1685,7 +1685,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->id = PLANE_SPRITE0 + sprite; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); + modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index e166e1915afa..a871450150d9 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2817,7 +2817,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, INTEL_PLANE_CAP_CCS_RC_CC | INTEL_PLANE_CAP_CCS_MC); - modifiers = intel_fb_plane_get_modifiers(dev_priv, caps); + modifiers = intel_fb_plane_get_modifiers(display, caps); ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, @@ -2994,7 +2994,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, } if (!dev_priv->display.params.enable_dpt && - intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { + intel_fb_modifier_uses_dpt(display, fb->modifier)) { drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); goto error; } From patchwork Thu Feb 6 18:55:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3192EC02194 for ; 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X-CSE-ConnectionGUID: YRywWotyR+GDXZhxmHx5fg== X-CSE-MsgGUID: awVZDfqmSxmYVQ7WPROtDQ== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395057" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395057" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:55:57 -0800 X-CSE-ConnectionGUID: i4F3wScPS+G90mYU3CappQ== X-CSE-MsgGUID: A9YCTYshQSCYJOZ3HKGjrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499562" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:54 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:53 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 06/12] drm/i915: Convert intel_display_power_{get, put}*() to intel_display Date: Thu, 6 Feb 2025 20:55:27 +0200 Message-ID: <20250206185533.32306-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pass intel_display to the display power stuff. These are spread all over the place so tend to hinder clean conversions of whole files. TODO: The gt part/unpark power domain shenanigans need some kind of more abstract interface... v2: Deal with cmtg Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/g4x_dp.c | 5 +- drivers/gpu/drm/i915/display/g4x_hdmi.c | 5 +- drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +- drivers/gpu/drm/i915/display/icl_dsi.c | 11 +-- drivers/gpu/drm/i915/display/intel_audio.c | 6 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 8 +- drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +- drivers/gpu/drm/i915/display/intel_crt.c | 16 ++-- drivers/gpu/drm/i915/display/intel_cursor.c | 10 ++- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 13 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 63 ++++++++------ drivers/gpu/drm/i915/display/intel_display.c | 53 +++++++----- .../drm/i915/display/intel_display_debugfs.c | 5 +- .../gpu/drm/i915/display/intel_display_irq.c | 10 +-- .../drm/i915/display/intel_display_power.c | 85 +++++++++---------- .../drm/i915/display/intel_display_power.h | 54 ++++++------ drivers/gpu/drm/i915/display/intel_dmc.c | 7 +- drivers/gpu/drm/i915/display/intel_dp.c | 7 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 5 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 55 +++++++----- drivers/gpu/drm/i915/display/intel_gmbus.c | 10 +-- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +-- drivers/gpu/drm/i915/display/intel_hotplug.c | 5 +- drivers/gpu/drm/i915/display/intel_lvds.c | 5 +- .../drm/i915/display/intel_modeset_setup.c | 6 +- drivers/gpu/drm/i915/display/intel_pipe_crc.c | 5 +- drivers/gpu/drm/i915/display/intel_pps.c | 18 ++-- drivers/gpu/drm/i915/display/intel_sprite.c | 17 ++-- drivers/gpu/drm/i915/display/intel_tc.c | 78 +++++++++-------- drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +- drivers/gpu/drm/i915/display/intel_vga.c | 5 +- .../drm/i915/display/skl_universal_plane.c | 5 +- drivers/gpu/drm/i915/display/skl_watermark.c | 5 +- drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +- 35 files changed, 312 insertions(+), 298 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 434de337814c..7eb5b4915f2c 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -305,12 +305,13 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, static bool intel_dp_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -318,7 +319,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, encoder->port, pipe); - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 3aaa7f9e9210..7f13cf9b1a2e 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -66,19 +66,20 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 5c4652f662cb..72699944768e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -681,6 +681,7 @@ static bool i9xx_plane_can_async_flip(u64 modifier) static bool i9xx_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { + struct intel_display *display = to_intel_display(plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; @@ -694,7 +695,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, * display power wells. */ power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -707,7 +708,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, else *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ee1c3fb500a7..0f2a19690c18 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -387,13 +387,12 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) { struct intel_display *display = to_intel_display(&intel_dsi->base); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum port port; for_each_dsi_port(port, intel_dsi->ports) { drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); intel_dsi->io_wakeref[port] = - intel_display_power_get(dev_priv, + intel_display_power_get(display, port == PORT_A ? POWER_DOMAIN_PORT_DDI_IO_A : POWER_DOMAIN_PORT_DDI_IO_B); @@ -1385,7 +1384,6 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; @@ -1393,7 +1391,7 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) intel_wakeref_t wakeref; wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); - intel_display_power_put(dev_priv, + intel_display_power_put(display, port == PORT_A ? POWER_DOMAIN_PORT_DDI_IO_A : POWER_DOMAIN_PORT_DDI_IO_B, @@ -1697,7 +1695,6 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum transcoder dsi_trans; intel_wakeref_t wakeref; @@ -1705,7 +1702,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, bool ret = false; u32 tmp; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -1736,7 +1733,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, ret = tmp & TRANSCONF_ENABLE; } out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index f145f83346ca..aaba438ab41e 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -1037,13 +1037,12 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) static unsigned long intel_audio_component_get_power(struct device *kdev) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; /* Catch potential impedance mismatches before they occur! */ BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); - wakeref = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); + wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); if (display->audio.power_refcount++ == 0) { if (DISPLAY_VER(display) >= 9) { @@ -1070,7 +1069,6 @@ static void intel_audio_component_put_power(struct device *kdev, unsigned long cookie) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref = (intel_wakeref_t)cookie; /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ @@ -1078,7 +1076,7 @@ static void intel_audio_component_put_power(struct device *kdev, if (display->platform.geminilake) glk_force_audio_cdclk(display, false); - intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); + intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); } static void intel_audio_component_codec_wake_override(struct device *kdev, diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 753ba3e3a0b7..c6cfc57a0346 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -656,7 +656,7 @@ static void vlv_set_cdclk(struct intel_display *display, * a system suspend. So grab the display core domain, which covers * the HW blocks needed for the following programming. */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_CCK) | @@ -716,7 +716,7 @@ static void vlv_set_cdclk(struct intel_display *display, vlv_program_pfi_credits(display); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); } static void chv_set_cdclk(struct intel_display *display, @@ -745,7 +745,7 @@ static void chv_set_cdclk(struct intel_display *display, * a system suspend. So grab the display core domain, which covers * the HW blocks needed for the following programming. */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); vlv_punit_get(dev_priv); val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); @@ -765,7 +765,7 @@ static void chv_set_cdclk(struct intel_display *display, vlv_program_pfi_credits(display); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); } static int bdw_calc_cdclk(int min_cdclk) diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c index 6b6fb82009f5..07d7f4e8f60f 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.c +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -85,7 +85,6 @@ static void intel_cmtg_dump_config(struct intel_display *display, static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display, enum transcoder trans) { - struct drm_i915_private *i915 = to_i915(display->drm); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; u32 val = 0; @@ -95,7 +94,7 @@ static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display, power_domain = POWER_DOMAIN_TRANSCODER(trans); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) + with_intel_display_power_if_enabled(display, power_domain, wakeref) val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); return val & CMTG_SECONDARY_MODE; diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index b5367e059ee3..aa46c14ce225 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -108,19 +108,18 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crt *crt = intel_encoder_to_crt(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -858,7 +857,6 @@ intel_crt_detect(struct drm_connector *connector, bool force) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); struct intel_encoder *encoder = &crt->base; struct drm_atomic_state *state; @@ -876,7 +874,7 @@ intel_crt_detect(struct drm_connector *connector, return connector->status; if (display->params.load_detect_test) { - wakeref = intel_display_power_get(dev_priv, encoder->power_domain); + wakeref = intel_display_power_get(display, encoder->power_domain); goto load_detect; } @@ -884,7 +882,7 @@ intel_crt_detect(struct drm_connector *connector, if (dmi_check_system(intel_spurious_crt_detect)) return connector_status_disconnected; - wakeref = intel_display_power_get(dev_priv, encoder->power_domain); + wakeref = intel_display_power_get(display, encoder->power_domain); if (I915_HAS_HOTPLUG(display)) { /* We can not rely on the HPD pin always being correctly wired @@ -941,7 +939,7 @@ intel_crt_detect(struct drm_connector *connector, } out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return status; } @@ -959,7 +957,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) if (!intel_display_driver_check_access(display)) return drm_edid_connector_add_modes(connector); - wakeref = intel_display_power_get(dev_priv, encoder->power_domain); + wakeref = intel_display_power_get(display, encoder->power_domain); ret = intel_crt_ddc_get_modes(connector, connector->ddc); if (ret || !IS_G4X(dev_priv)) @@ -970,7 +968,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) ret = intel_crt_ddc_get_modes(connector, ddc); out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 9c9cded729af..6a0d563174cf 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -326,13 +326,14 @@ static void i845_cursor_disable_arm(struct intel_dsb *dsb, static bool i845_cursor_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { + struct intel_display *display = to_intel_display(plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(PIPE_A); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -340,7 +341,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane, *pipe = PIPE_A; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -733,6 +734,7 @@ static void i9xx_cursor_disable_arm(struct intel_dsb *dsb, static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { + struct intel_display *display = to_intel_display(plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; @@ -745,7 +747,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, * display power wells. */ power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -758,7 +760,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, else *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 0ff76ef10d4b..4121d0d759bf 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -73,10 +73,9 @@ static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder) static void assert_dc_off(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); bool enabled; - enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF); + enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); drm_WARN_ON(display->drm, !enabled); } @@ -103,12 +102,12 @@ static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder) */ static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) { - intel_wakeref_t wakeref; - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_wakeref_t wakeref; intel_psr_pause(intel_dp); - wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); intel_cx0_program_msgbus_timer(encoder); return wakeref; @@ -116,11 +115,11 @@ static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *enc static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_psr_resume(intel_dp); - intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref); } static void intel_clear_response_ready_flag(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index db3c2d85c57b..6e09dfcbaa7d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -705,19 +705,20 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, enum transcoder cpu_transcoder, bool enable, u32 hdcp_mask) { + struct intel_display *display = to_intel_display(intel_encoder); struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); intel_wakeref_t wakeref; int ret = 0; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, intel_encoder->power_domain); if (drm_WARN_ON(dev, !wakeref)) return -ENXIO; intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), hdcp_mask, enable ? hdcp_mask : 0); - intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); + intel_display_power_put(display, intel_encoder->power_domain, wakeref); return ret; } @@ -734,7 +735,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) u32 ddi_mode; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -775,7 +776,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) } out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -794,7 +795,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, *pipe_mask = 0; *is_dp_mst = false; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return; @@ -831,7 +832,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, u32 port_mask, ddi_select, ddi_mode; intel_wakeref_t trans_wakeref; - trans_wakeref = intel_display_power_get_if_enabled(dev_priv, + trans_wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder)); if (!trans_wakeref) continue; @@ -846,7 +847,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); - intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), + intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), trans_wakeref); if ((tmp & port_mask) != ddi_select) @@ -911,7 +912,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name, tmp); } - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); } bool intel_ddi_get_hw_state(struct intel_encoder *encoder, @@ -963,23 +964,23 @@ static void main_link_aux_power_domain_get(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); enum intel_display_power_domain domain = intel_ddi_main_link_aux_domain(dig_port, crtc_state); - drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); + drm_WARN_ON(display->drm, dig_port->aux_wakeref); if (domain == POWER_DOMAIN_INVALID) return; - dig_port->aux_wakeref = intel_display_power_get(i915, domain); + dig_port->aux_wakeref = intel_display_power_get(display, domain); } static void main_link_aux_power_domain_put(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); enum intel_display_power_domain domain = intel_ddi_main_link_aux_domain(dig_port, crtc_state); intel_wakeref_t wf; @@ -988,13 +989,13 @@ main_link_aux_power_domain_put(struct intel_digital_port *dig_port, if (!wf) return; - intel_display_power_put(i915, domain, wf); + intel_display_power_put(display, domain, wf); } static void intel_ddi_get_power_domains(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port; /* @@ -1002,15 +1003,15 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, * happen since fake-MST encoders don't set their get_power_domains() * hook. */ - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) return; dig_port = enc_to_dig_port(encoder); if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2725,6 +2726,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -2771,7 +2773,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2872,6 +2874,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; @@ -2900,7 +2903,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2967,6 +2970,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2975,7 +2979,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, intel_ddi_enable_clock(encoder, crtc_state); drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); icl_program_mg_dp_mode(dig_port, crtc_state); @@ -3134,6 +3138,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &dig_port->dp; @@ -3185,7 +3190,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); if (wakeref) - intel_display_power_put(dev_priv, + intel_display_power_put(display, dig_port->ddi_io_power_domain, wakeref); @@ -3202,6 +3207,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; @@ -3220,7 +3226,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); if (wakeref) - intel_display_power_put(dev_priv, + intel_display_power_put(display, dig_port->ddi_io_power_domain, wakeref); @@ -3897,10 +3903,12 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { + struct intel_display *display = &dev_priv->display; + if (cpu_transcoder == TRANSCODER_EDP) return false; - if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) + if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) return false; return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & @@ -3976,6 +3984,7 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); @@ -3989,7 +3998,7 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) intel_wakeref_t trans_wakeref; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - trans_wakeref = intel_display_power_get_if_enabled(dev_priv, + trans_wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!trans_wakeref) @@ -3999,7 +4008,7 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) crtc_state->cpu_transcoder) crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); - intel_display_power_put(dev_priv, power_domain, trans_wakeref); + intel_display_power_put(display, power_domain, trans_wakeref); } drm_WARN_ON(&dev_priv->drm, @@ -4614,13 +4623,13 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->dev); + struct intel_display *display = to_intel_display(encoder->dev); struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); intel_dp_encoder_flush_work(encoder); if (intel_encoder_is_tc(&dig_port->base)) intel_tc_port_cleanup(dig_port); - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); drm_encoder_cleanup(encoder); kfree(dig_port->hdcp_port_data.streams); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e3e96613470b..83bc3cf1cf97 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -432,13 +432,13 @@ void assert_transcoder(struct drm_i915_private *dev_priv, state = true; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (wakeref) { u32 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); cur_state = !!(val & TRANSCONF_ENABLE); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); } else { cur_state = false; } @@ -2160,8 +2160,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *old_domains) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum intel_display_power_domain domain; struct intel_power_domain_mask domains, new_domains; @@ -2177,7 +2177,7 @@ void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, POWER_DOMAIN_NUM); for_each_power_domain(domain, &new_domains) - intel_display_power_get_in_set(dev_priv, + intel_display_power_get_in_set(display, &crtc->enabled_power_domains, domain); } @@ -2185,7 +2185,9 @@ void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, struct intel_power_domain_mask *domains) { - intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), + struct intel_display *display = to_intel_display(crtc); + + intel_display_power_put_mask_in_set(display, &crtc->enabled_power_domains, domains); } @@ -3221,6 +3223,7 @@ bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; @@ -3228,7 +3231,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, bool ret; power_domain = POWER_DOMAIN_PIPE(crtc->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -3322,7 +3325,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, ret = true; out: - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -3603,6 +3606,7 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) static bool ilk_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(crtc); struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum intel_display_power_domain power_domain; @@ -3611,7 +3615,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, bool ret; power_domain = POWER_DOMAIN_PIPE(crtc->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -3676,7 +3680,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, ret = true; out: - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -3698,13 +3702,14 @@ static u8 joiner_pipes(struct drm_i915_private *i915) static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { + struct intel_display *display = &dev_priv->display; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; u32 tmp = 0; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) + with_intel_display_power_if_enabled(display, power_domain, wakeref) tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); @@ -3730,7 +3735,7 @@ static void enabled_uncompressed_joiner_pipes(struct intel_display *display, intel_wakeref_t wakeref; power_domain = POWER_DOMAIN_PIPE(pipe); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain, wakeref) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (tmp & UNCOMPRESSED_JOINER_PRIMARY) @@ -3760,7 +3765,7 @@ static void enabled_bigjoiner_pipes(struct intel_display *display, intel_wakeref_t wakeref; power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain, wakeref) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (!(tmp & BIG_JOINER_ENABLE)) @@ -3831,7 +3836,7 @@ static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915, intel_wakeref_t wakeref; power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain, wakeref) { u32 tmp = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); if (!(tmp & ULTRA_JOINER_ENABLE)) @@ -3977,6 +3982,7 @@ static u8 hsw_panel_transcoders(struct drm_i915_private *i915) static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); @@ -3996,7 +4002,7 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) u32 tmp = 0; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) + with_intel_display_power_if_enabled(display, power_domain, wakeref) tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); @@ -4081,6 +4087,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) { + struct intel_display *display = to_intel_display(crtc); struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); unsigned long enabled_transcoders; @@ -4099,7 +4106,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, */ pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; - if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, + if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) return false; @@ -4133,7 +4140,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, else cpu_transcoder = TRANSCODER_DSI_C; - if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, + if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, POWER_DOMAIN_TRANSCODER(cpu_transcoder))) continue; @@ -4186,7 +4193,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, bool active; u32 tmp; - if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, + if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, POWER_DOMAIN_PIPE(crtc->pipe))) return false; @@ -4238,7 +4245,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, pipe_config->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); - if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, + if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { if (DISPLAY_VER(dev_priv) >= 9) skl_scaler_get_config(pipe_config); @@ -4267,7 +4274,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, } out: - intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); + intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); return active; } @@ -7199,6 +7206,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state, static void intel_pre_update_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -7233,7 +7241,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_fbc_update(state, crtc); - drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); + drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); if (!modeset && intel_crtc_needs_color_update(new_crtc_state) && @@ -7754,6 +7762,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, static void intel_atomic_commit_tail(struct intel_atomic_state *state) { + struct intel_display *display = to_intel_display(state); struct drm_device *dev = state->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc_state *new_crtc_state, *old_crtc_state; @@ -7805,7 +7814,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * the CSC latched register values with the readout (see * skl_read_csc() and skl_color_commit_noarm()). */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -7963,7 +7972,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * Delay re-enabling DC states by 17 ms to avoid the off->on->off * toggling overhead at and above 60 FPS. */ - intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17); + intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); /* diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 926f09c35084..feecabd81274 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -86,10 +86,11 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) static int i915_sr_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = &dev_priv->display; intel_wakeref_t wakeref; bool sr_enabled = false; - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); if (DISPLAY_VER(dev_priv) >= 9) /* no global SR status; inspect per-plane WM */; @@ -105,7 +106,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; - intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d9734fcd0d45..0f68b0a34ca9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1617,7 +1617,7 @@ void gen8_display_irq_reset(struct drm_i915_private *dev_priv) intel_de_write(display, EDP_PSR_IIR, 0xffffffff); for_each_pipe(dev_priv, pipe) - if (intel_display_power_is_enabled(dev_priv, + if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); @@ -1644,7 +1644,7 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) enum intel_display_power_domain domain; domain = POWER_DOMAIN_TRANSCODER(trans); - if (!intel_display_power_is_enabled(dev_priv, domain)) + if (!intel_display_power_is_enabled(display, domain)) continue; intel_de_write(display, @@ -1660,7 +1660,7 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) } for_each_pipe(dev_priv, pipe) - if (intel_display_power_is_enabled(dev_priv, + if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); @@ -1887,7 +1887,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) enum intel_display_power_domain domain; domain = POWER_DOMAIN_TRANSCODER(trans); - if (!intel_display_power_is_enabled(dev_priv, domain)) + if (!intel_display_power_is_enabled(display, domain)) continue; intel_display_irq_regs_assert_irr_is_zero(display, @@ -1900,7 +1900,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) for_each_pipe(dev_priv, pipe) { dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; - if (intel_display_power_is_enabled(dev_priv, + if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), dev_priv->display.irq.de_irq_mask[pipe], diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 14ae60749f02..cfc5c0b4f907 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -224,7 +224,7 @@ static bool __intel_display_power_is_enabled(struct intel_display *display, /** * intel_display_power_is_enabled - check for a power domain - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to check * * This function can be used to check the hw power domain state. It is mostly @@ -239,10 +239,9 @@ static bool __intel_display_power_is_enabled(struct intel_display *display, * Returns: * True when the power domain is enabled, false otherwise. */ -bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, +bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; struct i915_power_domains *power_domains = &display->power.domains; bool ret; @@ -500,7 +499,7 @@ __intel_display_power_get_domain(struct intel_display *display, /** * intel_display_power_get - grab a power domain reference - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * * This function grabs a power domain reference for @domain and ensures that the @@ -510,10 +509,10 @@ __intel_display_power_get_domain(struct intel_display *display, * Any power domain reference obtained by this function must have a symmetric * call to intel_display_power_put() to release the reference again. */ -intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, +intel_wakeref_t intel_display_power_get(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); @@ -526,7 +525,7 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, /** * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * * This function grabs a power domain reference for @domain and ensures that the @@ -537,10 +536,10 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, * call to intel_display_power_put() to release the reference again. */ intel_wakeref_t -intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, +intel_display_power_get_if_enabled(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref; bool is_enabled; @@ -696,7 +695,7 @@ intel_display_power_put_async_work(struct work_struct *work) /** * __intel_display_power_put_async - release a power domain reference asynchronously - * @i915: i915 device instance + * @display: display device instance * @domain: power domain to reference * @wakeref: wakeref acquired for the reference that is being released * @delay_ms: delay of powering down the power domain @@ -707,12 +706,12 @@ intel_display_power_put_async_work(struct work_struct *work) * The power down is delayed by @delay_ms if this is >= 0, or by a default * 100 ms otherwise. */ -void __intel_display_power_put_async(struct drm_i915_private *i915, +void __intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_runtime_pm *rpm = &i915->runtime_pm; intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); @@ -754,7 +753,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915, /** * intel_display_power_flush_work - flushes the async display power disabling work - * @i915: i915 device instance + * @display: display device instance * * Flushes any pending work that was scheduled by a preceding * intel_display_power_put_async() call, completing the disabling of the @@ -764,9 +763,9 @@ void __intel_display_power_put_async(struct drm_i915_private *i915, * function returns; to ensure that the work handler isn't running use * intel_display_power_flush_work_sync() instead. */ -void intel_display_power_flush_work(struct drm_i915_private *i915) +void intel_display_power_flush_work(struct intel_display *display) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_power_domain_mask async_put_mask; intel_wakeref_t work_wakeref; @@ -800,10 +799,9 @@ void intel_display_power_flush_work(struct drm_i915_private *i915) static void intel_display_power_flush_work_sync(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); cancel_async_put_work(power_domains, true); verify_async_put_domains_state(power_domains); @@ -814,7 +812,7 @@ intel_display_power_flush_work_sync(struct intel_display *display) #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) /** * intel_display_power_put - release a power domain reference - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * @wakeref: wakeref acquired for the reference that is being released * @@ -822,11 +820,11 @@ intel_display_power_flush_work_sync(struct intel_display *display) * intel_display_power_get() and might power down the corresponding hardware * block right away if this is the last reference. */ -void intel_display_power_put(struct drm_i915_private *dev_priv, +void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); __intel_display_power_put(display, domain); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); @@ -834,7 +832,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, #else /** * intel_display_power_put_unchecked - release an unchecked power domain reference - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * * This function drops the power domain reference obtained by @@ -845,10 +843,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, * tracking when the corresponding debug kconfig option is disabled, should not * be used otherwise. */ -void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, +void intel_display_power_put_unchecked(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); __intel_display_power_put(display, domain); intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); @@ -856,16 +854,15 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, #endif void -intel_display_power_get_in_set(struct drm_i915_private *i915, +intel_display_power_get_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain) { - struct intel_display *display = &i915->display; intel_wakeref_t __maybe_unused wf; drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); - wf = intel_display_power_get(i915, domain); + wf = intel_display_power_get(display, domain); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) power_domain_set->wakerefs[domain] = wf; #endif @@ -873,16 +870,15 @@ intel_display_power_get_in_set(struct drm_i915_private *i915, } bool -intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, +intel_display_power_get_in_set_if_enabled(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain) { - struct intel_display *display = &i915->display; intel_wakeref_t wf; drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); - wf = intel_display_power_get_if_enabled(i915, domain); + wf = intel_display_power_get_if_enabled(display, domain); if (!wf) return false; @@ -895,11 +891,10 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, } void -intel_display_power_put_mask_in_set(struct drm_i915_private *i915, +intel_display_power_put_mask_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, struct intel_power_domain_mask *mask) { - struct intel_display *display = &i915->display; enum intel_display_power_domain domain; drm_WARN_ON(display->drm, @@ -911,7 +906,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); #endif - intel_display_power_put(i915, domain, wf); + intel_display_power_put(display, domain, wf); clear_bit(domain, power_domain_set->mask.bits); } } @@ -999,7 +994,7 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) * intel_power_domains_init - initializes the power domain structures * @display: display device instance * - * Initializes the power domain structures for @dev_priv depending upon the + * Initializes the power domain structures for @display depending upon the * supported platform. */ int intel_power_domains_init(struct intel_display *display) @@ -1963,12 +1958,12 @@ void intel_power_domains_init_hw(struct intel_display *display, bool resume) */ drm_WARN_ON(display->drm, power_domains->init_wakeref); power_domains->init_wakeref = - intel_display_power_get(i915, POWER_DOMAIN_INIT); + intel_display_power_get(display, POWER_DOMAIN_INIT); /* Disable power support if the user asked so. */ if (!display->params.disable_power_well) { drm_WARN_ON(display->drm, power_domains->disable_wakeref); - display->power.domains.disable_wakeref = intel_display_power_get(i915, + display->power.domains.disable_wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); } intel_power_domains_sync_hw(display); @@ -1995,7 +1990,7 @@ void intel_power_domains_driver_remove(struct intel_display *display) /* Remove the refcount we took to keep power well support disabled. */ if (!display->params.disable_power_well) - intel_display_power_put(i915, POWER_DOMAIN_INIT, + intel_display_power_put(display, POWER_DOMAIN_INIT, fetch_and_zero(&display->power.domains.disable_wakeref)); intel_display_power_flush_work_sync(display); @@ -2051,11 +2046,10 @@ void intel_power_domains_sanitize_state(struct intel_display *display) */ void intel_power_domains_enable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&display->power.domains.init_wakeref); - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); intel_power_domains_verify_state(display); } @@ -2068,12 +2062,11 @@ void intel_power_domains_enable(struct intel_display *display) */ void intel_power_domains_disable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; drm_WARN_ON(display->drm, power_domains->init_wakeref); power_domains->init_wakeref = - intel_display_power_get(i915, POWER_DOMAIN_INIT); + intel_display_power_get(display, POWER_DOMAIN_INIT); intel_power_domains_verify_state(display); } @@ -2091,12 +2084,11 @@ void intel_power_domains_disable(struct intel_display *display) */ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&power_domains->init_wakeref); - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); /* * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 @@ -2107,7 +2099,7 @@ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) */ if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && intel_dmc_has_payload(display)) { - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); intel_power_domains_verify_state(display); return; } @@ -2117,10 +2109,10 @@ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) * power wells if power domains must be deinitialized for suspend. */ if (!display->params.disable_power_well) - intel_display_power_put(i915, POWER_DOMAIN_INIT, + intel_display_power_put(display, POWER_DOMAIN_INIT, fetch_and_zero(&display->power.domains.disable_wakeref)); - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); intel_power_domains_verify_state(display); if (DISPLAY_VER(display) >= 11) @@ -2145,7 +2137,6 @@ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) */ void intel_power_domains_resume(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; if (power_domains->display_core_suspended) { @@ -2154,7 +2145,7 @@ void intel_power_domains_resume(struct intel_display *display) } else { drm_WARN_ON(display->drm, power_domains->init_wakeref); power_domains->init_wakeref = - intel_display_power_get(i915, POWER_DOMAIN_INIT); + intel_display_power_get(display, POWER_DOMAIN_INIT); } intel_power_domains_verify_state(display); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 7b294eec4431..b5d67b6c73cf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -184,88 +184,88 @@ void intel_display_power_resume(struct intel_display *display); void intel_display_power_set_target_dc_state(struct intel_display *display, u32 state); -bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, +bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain); -intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, +intel_wakeref_t intel_display_power_get(struct intel_display *display, enum intel_display_power_domain domain); intel_wakeref_t -intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, +intel_display_power_get_if_enabled(struct intel_display *display, enum intel_display_power_domain domain); -void __intel_display_power_put_async(struct drm_i915_private *i915, +void __intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms); -void intel_display_power_flush_work(struct drm_i915_private *i915); +void intel_display_power_flush_work(struct intel_display *display); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) -void intel_display_power_put(struct drm_i915_private *dev_priv, +void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref); static inline void -intel_display_power_put_async(struct drm_i915_private *i915, +intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - __intel_display_power_put_async(i915, domain, wakeref, -1); + __intel_display_power_put_async(display, domain, wakeref, -1); } static inline void -intel_display_power_put_async_delay(struct drm_i915_private *i915, +intel_display_power_put_async_delay(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms) { - __intel_display_power_put_async(i915, domain, wakeref, delay_ms); + __intel_display_power_put_async(display, domain, wakeref, delay_ms); } #else void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, enum intel_display_power_domain domain); static inline void -intel_display_power_put(struct drm_i915_private *i915, +intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - intel_display_power_put_unchecked(i915, domain); + intel_display_power_put_unchecked(display, domain); } static inline void -intel_display_power_put_async(struct drm_i915_private *i915, +intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, -1); + __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1); } static inline void -intel_display_power_put_async_delay(struct drm_i915_private *i915, +intel_display_power_put_async_delay(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms) { - __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, delay_ms); + __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms); } #endif void -intel_display_power_get_in_set(struct drm_i915_private *i915, +intel_display_power_get_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain); bool -intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, +intel_display_power_get_in_set_if_enabled(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain); void -intel_display_power_put_mask_in_set(struct drm_i915_private *i915, +intel_display_power_put_mask_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, struct intel_power_domain_mask *mask); static inline void -intel_display_power_put_all_in_set(struct drm_i915_private *i915, +intel_display_power_put_all_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set) { - intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask); + intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask); } void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); @@ -296,12 +296,12 @@ enum dbuf_slice { void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices); -#define with_intel_display_power(i915, domain, wf) \ - for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ - intel_display_power_put_async((i915), (domain), (wf)), (wf) = NULL) +#define with_intel_display_power(display, domain, wf) \ + for ((wf) = intel_display_power_get((display), (domain)); (wf); \ + intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) -#define with_intel_display_power_if_enabled(i915, domain, wf) \ - for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ - intel_display_power_put_async((i915), (domain), (wf)), (wf) = NULL) +#define with_intel_display_power_if_enabled(display, domain, wf) \ + for ((wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ + intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) #endif /* __INTEL_DISPLAY_POWER_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 221d3abda791..fa6944e55d95 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -992,19 +992,16 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) static void intel_dmc_runtime_pm_get(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - drm_WARN_ON(display->drm, display->dmc.wakeref); - display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); + display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); } static void intel_dmc_runtime_pm_put(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&display->dmc.wakeref); - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); } static const char *dmc_fallback_path(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cd53070d7ea2..1c6f65493928 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5470,13 +5470,13 @@ void intel_digital_port_unlock(struct intel_encoder *encoder) */ bool intel_digital_port_connected_locked(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); bool is_connected = false; intel_wakeref_t wakeref; - with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); do { @@ -6523,7 +6523,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_dp *intel_dp = &dig_port->dp; struct intel_encoder *encoder = &dig_port->base; struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); enum port port = encoder->port; int type; @@ -6623,7 +6622,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, return true; fail: - intel_display_power_flush_work(dev_priv); + intel_display_power_flush_work(display); drm_connector_cleanup(&connector->base); return false; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 40c697476b72..ec27bbd70bcf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -243,7 +243,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); i915_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; enum intel_display_power_domain aux_domain; @@ -272,7 +271,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, aux_domain = intel_aux_power_domain(dig_port); - aux_wakeref = intel_display_power_get(i915, aux_domain); + aux_wakeref = intel_display_power_get(display, aux_domain); pps_wakeref = intel_pps_lock(intel_dp); /* @@ -432,7 +431,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, intel_pps_vdd_off_unlocked(intel_dp, false); intel_pps_unlock(intel_dp, pps_wakeref); - intel_display_power_put_async(i915, aux_domain, aux_wakeref); + intel_display_power_put_async(display, aux_domain, aux_wakeref); out_unlock: intel_digital_port_unlock(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b8fa04d3cd5c..cb2ef317d219 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -228,8 +228,10 @@ intel_tc_pll_enable_reg(struct drm_i915_private *i915, static void _intel_enable_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { + struct intel_display *display = &i915->display; + if (pll->info->power_domain) - pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); + pll->wakeref = intel_display_power_get(display, pll->info->power_domain); pll->info->funcs->enable(i915, pll, &pll->state.hw_state); pll->on = true; @@ -238,11 +240,13 @@ static void _intel_enable_shared_dpll(struct drm_i915_private *i915, static void _intel_disable_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { + struct intel_display *display = &i915->display; + pll->info->funcs->disable(i915, pll); pll->on = false; if (pll->info->power_domain) - intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); + intel_display_power_put(display, pll->info->power_domain, pll->wakeref); } /** @@ -525,12 +529,13 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; const enum intel_dpll_id id = pll->info->id; intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -540,7 +545,7 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & DPLL_VCO_ENABLE; } @@ -747,12 +752,13 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; const enum intel_dpll_id id = pll->info->id; intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -760,7 +766,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, val = intel_de_read(i915, WRPLL_CTL(id)); hw_state->wrpll = val; - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & WRPLL_PLL_ENABLE; } @@ -769,11 +775,12 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -781,7 +788,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, val = intel_de_read(i915, SPLL_CTL); hw_state->spll = val; - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & SPLL_PLL_ENABLE; } @@ -1425,6 +1432,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; @@ -1432,7 +1440,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, bool ret; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -1454,7 +1462,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -1463,6 +1471,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; @@ -1470,7 +1479,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, u32 val; bool ret; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -1488,7 +1497,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -2172,7 +2181,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, bxt_port_to_phy_channel(display, port, &phy, &ch); - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -2234,7 +2243,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -3541,6 +3550,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); @@ -3550,7 +3560,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915, i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -3600,7 +3610,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -3608,6 +3618,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { + struct intel_display *display = &i915->display; struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); @@ -3615,7 +3626,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -3672,7 +3683,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -3681,13 +3692,14 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_dpll_hw_state *dpll_hw_state, i915_reg_t enable_reg) { + struct intel_display *display = &i915->display; struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; intel_wakeref_t wakeref; bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -3733,7 +3745,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -4508,12 +4520,13 @@ bool intel_dpll_get_hw_state(struct drm_i915_private *i915, static void readout_dpll_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll) { + struct intel_display *display = &i915->display; struct intel_crtc *crtc; pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); if (pll->on && pll->info->power_domain) - pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); + pll->wakeref = intel_display_power_get(display, pll->info->power_domain); pll->state.pipe_mask = 0; for_each_intel_crtc(&i915->drm, crtc) { diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 807cf606e7a8..abf457e68ee9 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -761,11 +761,10 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; int ret; - wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); if (bus->force_bit) { ret = i2c_bit_algo.master_xfer(adapter, msgs, num); @@ -777,7 +776,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) bus->force_bit |= GMBUS_FORCE_BIT_RETRY; } - intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); return ret; } @@ -786,7 +785,6 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); u8 cmd = DRM_HDCP_DDC_AKSV; u8 buf[DRM_HDCP_KSV_LEN] = {}; struct i2c_msg msgs[] = { @@ -806,7 +804,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) intel_wakeref_t wakeref; int ret; - wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); mutex_lock(&display->gmbus.mutex); /* @@ -817,7 +815,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); mutex_unlock(&display->gmbus.mutex); - intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 3b51238022f4..015110fc57a2 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2491,14 +2491,13 @@ static bool intel_hdmi_set_edid(struct drm_connector *connector) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); struct i2c_adapter *ddc = connector->ddc; intel_wakeref_t wakeref; const struct drm_edid *drm_edid; bool connected = false; - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); drm_edid = drm_edid_read_ddc(connector, ddc); @@ -2521,7 +2520,7 @@ intel_hdmi_set_edid(struct drm_connector *connector) connected = true; } - intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, connector->display_info.source_physical_address); @@ -2534,7 +2533,6 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) { struct intel_display *display = to_intel_display(connector->dev); enum drm_connector_status status = connector_status_disconnected; - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; intel_wakeref_t wakeref; @@ -2548,7 +2546,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) if (!intel_display_driver_check_access(display)) return connector->status; - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); if (DISPLAY_VER(display) >= 11 && !intel_digital_port_connected(encoder)) @@ -2560,7 +2558,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) status = connector_status_connected; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); if (status != connector_status_connected) cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index c0d48f651dab..d2e0002c5dc3 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -732,6 +732,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) struct drm_i915_private *dev_priv = container_of(work, struct drm_i915_private, display.hotplug.poll_init_work); + struct intel_display *display = &dev_priv->display; struct drm_connector_list_iter conn_iter; struct intel_connector *connector; intel_wakeref_t wakeref; @@ -747,7 +748,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) * and so risk an endless loop of this same sequence. */ if (!enabled) { - wakeref = intel_display_power_get(dev_priv, + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); drm_WARN_ON(&dev_priv->drm, READ_ONCE(dev_priv->display.hotplug.poll_enabled)); @@ -789,7 +790,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) if (!enabled) { i915_hpd_poll_detect_connectors(dev_priv); - intel_display_power_put(dev_priv, + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); } diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 4b0dce169d4e..e86b3a86db82 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -102,18 +102,19 @@ bool intel_lvds_port_enabled(struct drm_i915_private *i915, static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); - intel_display_power_put(i915, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 10cdfdad82e4..69373031c557 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -177,7 +177,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) intel_fbc_disable(crtc); intel_update_watermarks(i915); - intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); + intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains); cdclk_state->min_cdclk[pipe] = 0; cdclk_state->min_voltage_level[pipe] = 0; @@ -969,7 +969,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, struct intel_crtc *crtc; intel_wakeref_t wakeref; - wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); + wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); intel_early_display_was(i915); intel_modeset_readout_hw_state(i915); @@ -1028,7 +1028,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, intel_modeset_put_crtc_power_domains(crtc, &put_domains); } - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); intel_power_domains_sanitize_state(display); } diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 90efc6f64e52..10e26c3db946 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -582,6 +582,7 @@ int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) { struct intel_crtc *crtc = to_intel_crtc(_crtc); + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; enum intel_display_power_domain power_domain; @@ -598,7 +599,7 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) } power_domain = POWER_DOMAIN_PIPE(pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) { drm_dbg_kms(&dev_priv->drm, "Trying to capture CRC while pipe is off\n"); @@ -628,7 +629,7 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) if (!enable) intel_crtc_crc_setup_workarounds(crtc, false); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index c0f65749a3f6..ef6effaf82e0 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -65,13 +65,12 @@ static const char *pps_name(struct intel_dp *intel_dp) intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); intel_wakeref_t wakeref; /* * See vlv_pps_reset_all() why we need a power domain reference here. */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); mutex_lock(&display->pps.mutex); return wakeref; @@ -81,10 +80,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); mutex_unlock(&display->pps.mutex); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return NULL; } @@ -741,7 +739,6 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; @@ -759,7 +756,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) return need_to_disable; drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); - intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, + intel_dp->pps.vdd_wakeref = intel_display_power_get(display, intel_aux_power_domain(dig_port)); pp_stat_reg = _pp_stat_reg(intel_dp); @@ -825,7 +822,6 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp) static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; @@ -863,7 +859,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) intel_dp_invalidate_source_oui(intel_dp); } - intel_display_power_put(dev_priv, + intel_display_power_put(display, intel_aux_power_domain(dig_port), fetch_and_zero(&intel_dp->pps.vdd_wakeref)); } @@ -1036,7 +1032,6 @@ void intel_pps_on(struct intel_dp *intel_dp) void intel_pps_off_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_ctrl_reg; @@ -1074,7 +1069,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) intel_dp_invalidate_source_oui(intel_dp); /* We got a reference when we enabled the VDD. */ - intel_display_power_put(dev_priv, + intel_display_power_put(display, intel_aux_power_domain(dig_port), fetch_and_zero(&intel_dp->pps.vdd_wakeref)); } @@ -1338,7 +1333,6 @@ void vlv_pps_port_disable(struct intel_encoder *encoder, static void pps_vdd_init(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); lockdep_assert_held(&display->pps.mutex); @@ -1357,7 +1351,7 @@ static void pps_vdd_init(struct intel_dp *intel_dp) dig_port->base.base.base.id, dig_port->base.base.name, pps_name(intel_dp)); drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); - intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, + intel_dp->pps.vdd_wakeref = intel_display_power_get(display, intel_aux_power_domain(dig_port)); } diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index ee7839eb4099..d1b4b20af4a0 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -452,15 +452,14 @@ static bool vlv_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; enum plane_id plane_id = plane->id; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -468,7 +467,7 @@ vlv_sprite_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -884,13 +883,12 @@ ivb_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -898,7 +896,7 @@ ivb_sprite_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -1222,13 +1220,12 @@ g4x_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -1236,7 +1233,7 @@ g4x_sprite_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 13811244c82b..e9e9ee5d345a 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -187,11 +187,11 @@ bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port) static intel_wakeref_t __tc_cold_block(struct intel_tc_port *tc, enum intel_display_power_domain *domain) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); *domain = tc_phy_cold_off_domain(tc); - return intel_display_power_get(i915, *domain); + return intel_display_power_get(display, *domain); } static intel_wakeref_t @@ -211,9 +211,9 @@ static void __tc_cold_unblock(struct intel_tc_port *tc, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); - intel_display_power_put(i915, domain, wakeref); + intel_display_power_put(display, domain, wakeref); } static void @@ -230,21 +230,21 @@ tc_cold_unblock(struct intel_tc_port *tc, intel_wakeref_t wakeref) static void assert_display_core_power_enabled(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); - drm_WARN_ON(&i915->drm, - !intel_display_power_is_enabled(i915, POWER_DOMAIN_DISPLAY_CORE)); + drm_WARN_ON(display->drm, + !intel_display_power_is_enabled(display, POWER_DOMAIN_DISPLAY_CORE)); } static void assert_tc_cold_blocked(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); bool enabled; - enabled = intel_display_power_is_enabled(i915, + enabled = intel_display_power_is_enabled(display, tc_phy_cold_off_domain(tc)); - drm_WARN_ON(&i915->drm, !enabled); + drm_WARN_ON(display->drm, !enabled); } static enum intel_display_power_domain @@ -258,10 +258,10 @@ tc_port_power_domain(struct intel_tc_port *tc) static void assert_tc_port_power_enabled(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); - drm_WARN_ON(&i915->drm, - !intel_display_power_is_enabled(i915, tc_port_power_domain(tc))); + drm_WARN_ON(display->drm, + !intel_display_power_is_enabled(display, tc_port_power_domain(tc))); } static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) @@ -296,12 +296,13 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { + struct intel_display *display = to_intel_display(dig_port); struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); intel_wakeref_t wakeref; u32 val, pin_assignment; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); pin_assignment = @@ -321,11 +322,11 @@ static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); intel_wakeref_t wakeref; u32 pin_mask; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); switch (pin_mask) { @@ -342,11 +343,11 @@ static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); intel_wakeref_t wakeref; u32 lane_mask = 0; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) lane_mask = intel_tc_port_get_lane_mask(dig_port); switch (lane_mask) { @@ -488,6 +489,7 @@ icl_tc_phy_cold_off_domain(struct intel_tc_port *tc) static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); struct intel_digital_port *dig_port = tc->dig_port; u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; @@ -496,7 +498,7 @@ static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc) u32 pch_isr; u32 mask = 0; - with_intel_display_power(i915, tc_phy_cold_off_domain(tc), wakeref) { + with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) { fia_isr = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); pch_isr = intel_de_read(i915, SDEISR); } @@ -730,11 +732,12 @@ tgl_tc_phy_cold_off_domain(struct intel_tc_port *tc) static void tgl_tc_phy_init(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); intel_wakeref_t wakeref; u32 val; - with_intel_display_power(i915, tc_phy_cold_off_domain(tc), wakeref) + with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1)); drm_WARN_ON(&i915->drm, val == 0xffffffff); @@ -771,6 +774,7 @@ adlp_tc_phy_cold_off_domain(struct intel_tc_port *tc) static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); struct intel_digital_port *dig_port = tc->dig_port; enum hpd_pin hpd_pin = dig_port->base.hpd_pin; @@ -781,7 +785,7 @@ static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc) u32 pch_isr; u32 mask = 0; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR); pch_isr = intel_de_read(i915, SDEISR); } @@ -851,22 +855,23 @@ static bool adlp_tc_phy_is_owned(struct intel_tc_port *tc) static void adlp_tc_phy_get_hw_state(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); intel_wakeref_t port_wakeref; - port_wakeref = intel_display_power_get(i915, port_power_domain); + port_wakeref = intel_display_power_get(display, port_power_domain); tc->mode = tc_phy_get_current_mode(tc); if (tc->mode != TC_PORT_DISCONNECTED) tc->lock_wakeref = tc_cold_block(tc); - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); } static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); @@ -877,7 +882,7 @@ static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) return true; } - port_wakeref = intel_display_power_get(i915, port_power_domain); + port_wakeref = intel_display_power_get(display, port_power_domain); if (!adlp_tc_phy_take_ownership(tc, true) && !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) { @@ -898,7 +903,7 @@ static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes)) goto out_unblock_tc_cold; - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); return true; @@ -907,19 +912,19 @@ static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) out_release_phy: adlp_tc_phy_take_ownership(tc, false); out_put_port_power: - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); return false; } static void adlp_tc_phy_disconnect(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); intel_wakeref_t port_wakeref; - port_wakeref = intel_display_power_get(i915, port_power_domain); + port_wakeref = intel_display_power_get(display, port_power_domain); tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref)); @@ -934,7 +939,7 @@ static void adlp_tc_phy_disconnect(struct intel_tc_port *tc) MISSING_CASE(tc->mode); } - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); } static void adlp_tc_phy_init(struct intel_tc_port *tc) @@ -959,6 +964,7 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = { */ static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); struct intel_digital_port *dig_port = tc->dig_port; enum hpd_pin hpd_pin = dig_port->base.hpd_pin; @@ -969,7 +975,7 @@ static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc) u32 pch_isr; u32 mask = 0; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR); pch_isr = intel_de_read(i915, SDEISR); } @@ -1436,25 +1442,25 @@ static void tc_phy_init(struct intel_tc_port *tc) static void intel_tc_port_reset_mode(struct intel_tc_port *tc, int required_lanes, bool force_disconnect) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); struct intel_digital_port *dig_port = tc->dig_port; enum tc_port_mode old_tc_mode = tc->mode; - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); if (!intel_tc_cold_requires_aux_pw(dig_port)) { enum intel_display_power_domain aux_domain; bool aux_powered; aux_domain = intel_aux_power_domain(dig_port); - aux_powered = intel_display_power_is_enabled(i915, aux_domain); - drm_WARN_ON(&i915->drm, aux_powered); + aux_powered = intel_display_power_is_enabled(display, aux_domain); + drm_WARN_ON(display->drm, aux_powered); } tc_phy_disconnect(tc); if (!force_disconnect) tc_phy_connect(tc, required_lanes); - drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n", + drm_dbg_kms(display->drm, "Port %s: TC port mode reset (%s -> %s)\n", tc->port_name, tc_port_mode_name(old_tc_mode), tc_port_mode_name(tc->mode)); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 932435a7f88d..6e7151346382 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -962,6 +962,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) void intel_dsc_get_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -974,7 +975,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return; @@ -994,7 +995,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) intel_dsc_get_pps_config(crtc_state); out: - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); } static void intel_vdsc_dump_state(struct drm_printer *p, int indent, diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index fd18dd07ae49..684b5d1bc87c 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -59,7 +59,6 @@ void intel_vga_redisable_power_on(struct intel_display *display) void intel_vga_redisable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; /* @@ -71,13 +70,13 @@ void intel_vga_redisable(struct intel_display *display) * follow the "don't touch the power well if we don't need it" policy * the rest of the driver uses. */ - wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_VGA); + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_VGA); if (!wakeref) return; intel_vga_redisable_power_on(display); - intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref); + intel_display_power_put(display, POWER_DOMAIN_VGA, wakeref); } void intel_vga_reset_io_mem(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index a871450150d9..3a60d6d49662 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -922,6 +922,7 @@ static bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { + struct intel_display *display = to_intel_display(plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; enum plane_id plane_id = plane->id; @@ -929,7 +930,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -937,7 +938,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 45fe4aaeb450..1c4510d520e8 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -836,6 +836,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb_y, u16 *min_ddb, u16 *interim_ddb) { + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; @@ -843,7 +844,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, enum plane_id plane_id; power_domain = POWER_DOMAIN_PIPE(pipe); - wakeref = intel_display_power_get_if_enabled(i915, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return; @@ -855,7 +856,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, &min_ddb[plane_id], &interim_ddb[plane_id]); - intel_display_power_put(i915, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); } struct dbuf_slice_conf_entry { diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 14973e9cb899..f6be1cd5d270 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -947,7 +947,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, drm_dbg_kms(display->drm, "\n"); - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -1007,7 +1007,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, } out_put_power: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return active; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index c08fdb65cc69..175fa2db0551 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -70,6 +70,7 @@ static int __gt_unpark(struct intel_wakeref *wf) { struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; GT_TRACE(gt, "\n"); @@ -84,7 +85,7 @@ static int __gt_unpark(struct intel_wakeref *wf) * Work around it by grabbing a GT IRQ power domain whilst there is any * GT activity, preventing any DC state transitions. */ - gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); + gt->awake = intel_display_power_get(display, POWER_DOMAIN_GT_IRQ); GEM_BUG_ON(!gt->awake); intel_rc6_unpark(>->rc6); @@ -103,6 +104,7 @@ static int __gt_park(struct intel_wakeref *wf) struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); intel_wakeref_t wakeref = fetch_and_zero(>->awake); struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; GT_TRACE(gt, "\n"); @@ -120,7 +122,7 @@ static int __gt_park(struct intel_wakeref *wf) /* Defer dropping the display power well for 100ms, it's slow! */ GEM_BUG_ON(!wakeref); - intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); + intel_display_power_put_async(display, POWER_DOMAIN_GT_IRQ, wakeref); return 0; } From patchwork Thu Feb 6 18:55:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CA65C0219D for ; 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X-CSE-ConnectionGUID: ML7kGlw7R5G24q1spze4QQ== X-CSE-MsgGUID: YAeNOistSYi10MI18emXNw== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395060" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395060" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:56:00 -0800 X-CSE-ConnectionGUID: J01qksz3QiKjqFyexKWEOA== X-CSE-MsgGUID: 6l/mjTe+Tky5lXV2QMka9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499568" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:55:58 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:55:57 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 07/12] drm/i915: Convert i9xx_plane.c to struct intel_display Date: Thu, 6 Feb 2025 20:55:28 +0200 Message-ID: <20250206185533.32306-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the pre-skl primary plane code to use it. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 240 +++++++++++----------- drivers/gpu/drm/i915/display/i9xx_plane.h | 6 +- drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- 3 files changed, 122 insertions(+), 126 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 72699944768e..c3ed903d5582 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -109,42 +109,42 @@ static bool i965_plane_format_mod_supported(struct drm_plane *_plane, } } -static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, +static bool i9xx_plane_has_fbc(struct intel_display *display, enum i9xx_plane_id i9xx_plane) { - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(display)) return false; - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + if (display->platform.broadwell || display->platform.haswell) return i9xx_plane == PLANE_A; /* tied to pipe A */ - else if (IS_IVYBRIDGE(dev_priv)) + else if (display->platform.ivybridge) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || i9xx_plane == PLANE_C; - else if (DISPLAY_VER(dev_priv) >= 4) + else if (DISPLAY_VER(display) >= 4) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; else return i9xx_plane == PLANE_A; } -static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, +static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, enum i9xx_plane_id i9xx_plane) { - if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) - return dev_priv->display.fbc[INTEL_FBC_A]; + if (i9xx_plane_has_fbc(display, i9xx_plane)) + return display->fbc[INTEL_FBC_A]; else return NULL; } static bool i9xx_plane_has_windowing(struct intel_plane *plane) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) return i9xx_plane == PLANE_B; - else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return false; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(display) == 4) return i9xx_plane == PLANE_C; else return i9xx_plane == PLANE_B || @@ -154,16 +154,15 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; u32 dspcntr; dspcntr = DISP_ENABLE; - if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || - IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (display->platform.g4x || display->platform.ironlake || + display->platform.sandybridge || display->platform.ivybridge) dspcntr |= DISP_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -211,7 +210,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, return 0; } - if (DISPLAY_VER(dev_priv) >= 4 && + if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) dspcntr |= DISP_TILED; @@ -226,8 +225,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, int i9xx_check_plane_surface(struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int src_x, src_y, src_w; u32 offset; @@ -245,12 +244,12 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) src_y = plane_state->uapi.src.y1 >> 16; /* Undocumented hardware limit on i965/g4x/vlv/chv */ - if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) + if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) return -EINVAL; intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) offset = intel_plane_compute_aligned_offset(&src_x, &src_y, plane_state, 0); else @@ -267,13 +266,13 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) * Linear surfaces seem to work just fine, even on hsw/bdw * despite them not using the linear offset anymore. */ - if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { + if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { unsigned int alignment = plane->min_alignment(plane, fb, 0); int cpp = fb->format->cpp[0]; while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { if (offset == 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unable to find suitable display surface offset due to X-tiling\n"); return -EINVAL; } @@ -291,7 +290,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) src_x << 16, src_y << 16); /* HSW/BDW do this automagically in hardware */ - if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { + if (!display->platform.haswell && !display->platform.broadwell) { unsigned int rotation = plane_state->hw.rotation; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; @@ -304,11 +303,11 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) } } - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); - } else if (DISPLAY_VER(dev_priv) >= 4 && + if (display->platform.haswell || display->platform.broadwell) { + drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095); + } else if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { - drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); + drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095); } plane_state->view.color_plane[0].offset = offset; @@ -354,8 +353,8 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dspcntr = 0; if (crtc_state->gamma_enable) @@ -364,7 +363,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) if (crtc_state->csc_enable) dspcntr |= DISP_PIPE_CSC_ENABLE; - if (DISPLAY_VER(dev_priv) < 5) + if (DISPLAY_VER(display) < 5) dspcntr |= DISP_PIPE_SEL(crtc->pipe); return dspcntr; @@ -422,13 +421,13 @@ static void i9xx_plane_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane), plane_state->view.color_plane[0].mapping_stride); - if (DISPLAY_VER(dev_priv) < 4) { + if (DISPLAY_VER(display) < 4) { int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); @@ -439,9 +438,9 @@ static void i9xx_plane_update_noarm(struct intel_dsb *dsb, * generator but let's assume we still need to * program whatever is there. */ - intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPPOS(display, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPSIZE(display, i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); } } @@ -451,7 +450,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; int x = plane_state->view.color_plane[0].x; int y = plane_state->view.color_plane[0].y; @@ -466,32 +465,32 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) dspaddr_offset = plane_state->view.color_plane[0].offset; else dspaddr_offset = linear_offset; - if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { + if (display->platform.cherryview && i9xx_plane == PLANE_B) { int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); int crtc_h = drm_rect_height(&plane_state->uapi.dst); - intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), + intel_de_write_fw(display, PRIMPOS(display, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), + intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); - intel_de_write_fw(dev_priv, - PRIMCNSTALPHA(dev_priv, i9xx_plane), 0); + intel_de_write_fw(display, + PRIMCNSTALPHA(display, i9xx_plane), 0); } - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane), + if (display->platform.haswell || display->platform.broadwell) { + intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); - } else if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), + } else if (DISPLAY_VER(display) >= 4) { + intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane), linear_offset); - intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } @@ -500,13 +499,13 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), + if (DISPLAY_VER(display) >= 4) + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -529,7 +528,7 @@ static void i9xx_plane_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; u32 dspcntr; @@ -545,12 +544,12 @@ static void i9xx_plane_disable_arm(struct intel_dsb *dsb, */ dspcntr = i9xx_plane_ctl_crtc(crtc_state); - intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0); + if (DISPLAY_VER(display) >= 4) + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0); else - intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0); } static void @@ -560,7 +559,7 @@ g4x_primary_async_flip(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, bool async_flip) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; @@ -568,9 +567,9 @@ g4x_primary_async_flip(struct intel_dsb *dsb, if (async_flip) dspcntr |= DISP_ASYNC_FLIP; - intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -581,11 +580,11 @@ vlv_primary_async_flip(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, bool async_flip) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -682,7 +681,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; intel_wakeref_t wakeref; @@ -699,11 +697,11 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); + val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); ret = val & DISP_ENABLE; - if (DISPLAY_VER(dev_priv) >= 5) + if (DISPLAY_VER(display) >= 5) *pipe = plane->pipe; else *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); @@ -864,9 +862,8 @@ static const struct drm_plane_funcs i8xx_plane_funcs = { }; struct intel_plane * -intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) +intel_primary_plane_create(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; unsigned int supported_rotations; @@ -884,20 +881,20 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS * port is hooked to pipe B. Hence we want plane A feeding pipe B. */ - if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 && - INTEL_NUM_PIPES(dev_priv) == 2) + if (HAS_FBC(display) && DISPLAY_VER(display) < 4 && + INTEL_NUM_PIPES(display) == 2) plane->i9xx_plane = (enum i9xx_plane_id) !pipe; else plane->i9xx_plane = (enum i9xx_plane_id) pipe; plane->id = PLANE_PRIMARY; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); + intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { formats = vlv_primary_formats; num_formats = ARRAY_SIZE(vlv_primary_formats); - } else if (DISPLAY_VER(dev_priv) >= 4) { + } else if (DISPLAY_VER(display) >= 4) { /* * WaFP16GammaEnabling:ivb * "Workaround : When using the 64-bit format, the plane @@ -911,7 +908,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * planes, so we choose not to expose fp16 on IVB primary * planes. HSW primary planes no longer have this problem. */ - if (IS_IVYBRIDGE(dev_priv)) { + if (display->platform.ivybridge) { formats = ivb_primary_formats; num_formats = ARRAY_SIZE(ivb_primary_formats); } else { @@ -923,39 +920,39 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) num_formats = ARRAY_SIZE(i8xx_primary_formats); } - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) plane_funcs = &i965_plane_funcs; else plane_funcs = &i8xx_plane_funcs; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) plane->min_cdclk = vlv_plane_min_cdclk; - else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + else if (display->platform.broadwell || display->platform.haswell) plane->min_cdclk = hsw_plane_min_cdclk; - else if (IS_IVYBRIDGE(dev_priv)) + else if (display->platform.ivybridge) plane->min_cdclk = ivb_plane_min_cdclk; else plane->min_cdclk = i9xx_plane_min_cdclk; - if (HAS_GMCH(dev_priv)) { - if (DISPLAY_VER(dev_priv) >= 4) + if (HAS_GMCH(display)) { + if (DISPLAY_VER(display) >= 4) plane->max_stride = i965_plane_max_stride; - else if (DISPLAY_VER(dev_priv) == 3) + else if (DISPLAY_VER(display) == 3) plane->max_stride = i915_plane_max_stride; else plane->max_stride = i8xx_plane_max_stride; } else { - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + if (display->platform.broadwell || display->platform.haswell) plane->max_stride = hsw_primary_max_stride; else plane->max_stride = ilk_primary_max_stride; } - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) plane->min_alignment = vlv_plane_min_alignment; - else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) plane->min_alignment = g4x_primary_min_alignment; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(display) == 4) plane->min_alignment = i965_plane_min_alignment; else plane->min_alignment = i9xx_plane_min_alignment; @@ -964,7 +961,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 128; - if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { + if (display->platform.i830 || display->platform.i845g) { plane->update_arm = i830_plane_update_arm; } else { plane->update_noarm = i9xx_plane_update_noarm; @@ -974,24 +971,24 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->get_hw_state = i9xx_plane_get_hw_state; plane->check_plane = i9xx_plane_check; - if (HAS_ASYNC_FLIPS(dev_priv)) { - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (HAS_ASYNC_FLIPS(display)) { + if (display->platform.valleyview || display->platform.cherryview) { plane->async_flip = vlv_primary_async_flip; plane->enable_flip_done = vlv_primary_enable_flip_done; plane->disable_flip_done = vlv_primary_disable_flip_done; plane->can_async_flip = i9xx_plane_can_async_flip; - } else if (IS_BROADWELL(dev_priv)) { + } else if (display->platform.broadwell) { plane->need_async_flip_toggle_wa = true; plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = bdw_primary_enable_flip_done; plane->disable_flip_done = bdw_primary_disable_flip_done; plane->can_async_flip = i9xx_plane_can_async_flip; - } else if (DISPLAY_VER(dev_priv) >= 7) { + } else if (DISPLAY_VER(display) >= 7) { plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = ivb_primary_enable_flip_done; plane->disable_flip_done = ivb_primary_disable_flip_done; plane->can_async_flip = i9xx_plane_can_async_flip; - } else if (DISPLAY_VER(dev_priv) >= 5) { + } else if (DISPLAY_VER(display) >= 5) { plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = ilk_primary_enable_flip_done; plane->disable_flip_done = ilk_primary_disable_flip_done; @@ -1001,15 +998,15 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) + ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, + ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, @@ -1022,18 +1019,18 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) if (ret) goto fail; - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + if (display->platform.cherryview && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X; - } else if (DISPLAY_VER(dev_priv) >= 4) { + } else if (DISPLAY_VER(display) >= 4) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; } else { supported_rotations = DRM_MODE_ROTATE_0; } - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, supported_rotations); @@ -1088,8 +1085,7 @@ void i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane = to_intel_plane(crtc->base.primary); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; enum pipe pipe; @@ -1102,21 +1098,21 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - drm_WARN_ON(dev, pipe != crtc->pipe); + drm_WARN_ON(display->drm, pipe != crtc->pipe); intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { - drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); + drm_dbg_kms(display->drm, "failed to alloc fb\n"); return; } fb = &intel_fb->base; - fb->dev = dev; + fb->dev = display->drm; - val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); + val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { if (val & DISP_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier = I915_FORMAT_MOD_X_TILED; @@ -1126,46 +1122,46 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, plane_config->rotation = DRM_MODE_ROTATE_180; } - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && - val & DISP_MIRROR) + if (display->platform.cherryview && + pipe == PIPE_B && val & DISP_MIRROR) plane_config->rotation |= DRM_MODE_REFLECT_X; pixel_format = val & DISP_FORMAT_MASK; fourcc = i9xx_format_to_fourcc(pixel_format); fb->format = drm_format_info(fourcc); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = intel_de_read(dev_priv, - DSPOFFSET(dev_priv, i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; - } else if (DISPLAY_VER(dev_priv) >= 4) { + if (display->platform.haswell || display->platform.broadwell) { + offset = intel_de_read(display, + DSPOFFSET(display, i9xx_plane)); + base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; + } else if (DISPLAY_VER(display) >= 4) { if (plane_config->tiling) - offset = intel_de_read(dev_priv, - DSPTILEOFF(dev_priv, i9xx_plane)); + offset = intel_de_read(display, + DSPTILEOFF(display, i9xx_plane)); else - offset = intel_de_read(dev_priv, - DSPLINOFF(dev_priv, i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; + offset = intel_de_read(display, + DSPLINOFF(display, i9xx_plane)); + base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; - base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); + base = intel_de_read(display, DSPADDR(display, i9xx_plane)); } plane_config->base = base; - drm_WARN_ON(&dev_priv->drm, offset != 0); + drm_WARN_ON(display->drm, offset != 0); - val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe)); + val = intel_de_read(display, PIPESRC(display, pipe)); fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; - val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane)); + val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); plane_config->size = fb->pitches[0] * aligned_height; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", crtc->base.name, plane->base.name, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], @@ -1177,7 +1173,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, const struct intel_initial_plane_config *plane_config) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -1196,10 +1192,10 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, if (plane_config->base == base) return false; - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base); + if (DISPLAY_VER(display) >= 4) + intel_de_write(display, DSPSURF(display, i9xx_plane), base); else - intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); + intel_de_write(display, DSPADDR(display, i9xx_plane), base); return true; } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h index 457f4bccf106..d90546d60855 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h @@ -10,8 +10,8 @@ enum pipe; struct drm_framebuffer; -struct drm_i915_private; struct intel_crtc; +struct intel_display; struct intel_initial_plane_config; struct intel_plane; struct intel_plane_state; @@ -26,7 +26,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, int i9xx_check_plane_surface(struct intel_plane_state *plane_state); struct intel_plane * -intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe); +intel_primary_plane_create(struct intel_display *display, enum pipe pipe); void i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config); @@ -44,7 +44,7 @@ static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state return 0; } static inline struct intel_plane * -intel_primary_plane_create(struct drm_i915_private *dev_priv, int pipe) +intel_primary_plane_create(struct intel_display *display, int pipe) { return NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index da2d6aeb2072..15e81f901aa1 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -321,7 +321,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) if (DISPLAY_VER(display) >= 9) primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1); else - primary = intel_primary_plane_create(dev_priv, pipe); + primary = intel_primary_plane_create(display, pipe); if (IS_ERR(primary)) { ret = PTR_ERR(primary); goto fail; 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06 Feb 2025 10:56:04 -0800 X-CSE-ConnectionGUID: BWA7szqdQWSJFBuD9GPgOg== X-CSE-MsgGUID: uLAxxW2WR12JNZslG/qlpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499610" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:56:01 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:56:00 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 08/12] drm/i915: Finish intel_sprite.c struct intel_display conversion Date: Thu, 6 Feb 2025 20:55:29 +0200 Message-ID: <20250206185533.32306-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä intel_sprite.c was partially converted to struct intel_display. Finish the job now that we can deal with the platform checks as well. And while at it we also move the 'display' variable declaration to be the first thing in most functions, consistency. We can actually do that now since intel_display() accepts the intel_plane and intel_plane_state types. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 91 +++++++++------------ drivers/gpu/drm/i915/display/intel_sprite.h | 6 +- 3 files changed, 43 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 15e81f901aa1..7279e064a565 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -336,7 +336,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) if (DISPLAY_VER(dev_priv) >= 9) plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite); else - plane = intel_sprite_plane_create(dev_priv, pipe, sprite); + plane = intel_sprite_plane_create(display, pipe, sprite); if (IS_ERR(plane)) { ret = PTR_ERR(plane); goto fail; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index d1b4b20af4a0..ab5bc8a08f0f 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -66,8 +66,8 @@ static void i9xx_plane_linear_gamma(u16 gamma[8]) static void chv_sprite_update_csc(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum plane_id plane_id = plane->id; /* @@ -138,8 +138,8 @@ chv_sprite_update_csc(const struct intel_plane_state *plane_state) static void vlv_sprite_update_clrc(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -341,8 +341,8 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -368,7 +368,7 @@ vlv_sprite_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; int crtc_x = plane_state->uapi.dst.x1; @@ -390,8 +390,7 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -404,7 +403,7 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) + if (display->platform.cherryview && pipe == PIPE_B) chv_sprite_update_csc(plane_state); if (key->flags) { @@ -440,7 +439,7 @@ vlv_sprite_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -645,19 +644,17 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; return fb->format->cpp[0] == 8 && - (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); + (display->platform.ivybridge || display->platform.haswell); } static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -665,7 +662,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, sprctl = SPRITE_ENABLE; - if (IS_IVYBRIDGE(dev_priv)) + if (display->platform.ivybridge) sprctl |= SPRITE_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -754,8 +751,8 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); enum pipe pipe = plane->pipe; u16 gamma[18]; int i; @@ -787,8 +784,7 @@ ivb_sprite_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -809,7 +805,7 @@ ivb_sprite_update_noarm(struct intel_dsb *dsb, SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x)); intel_de_write_fw(display, SPRSIZE(pipe), SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1)); - if (IS_IVYBRIDGE(dev_priv)) + if (display->platform.ivybridge) intel_de_write_fw(display, SPRSCALE(pipe), sprscale); } @@ -819,8 +815,7 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 sprsurf_offset = plane_state->view.color_plane[0].offset; @@ -841,7 +836,7 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + if (display->platform.haswell || display->platform.broadwell) { intel_de_write_fw(display, SPROFFSET(pipe), SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); } else { @@ -867,13 +862,12 @@ ivb_sprite_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; intel_de_write_fw(display, SPRCTL(pipe), 0); /* Disable the scaler */ - if (IS_IVYBRIDGE(dev_priv)) + if (display->platform.ivybridge) intel_de_write_fw(display, SPRSCALE(pipe), 0); intel_de_write_fw(display, SPRSURF(pipe), 0); } @@ -882,7 +876,7 @@ static bool ivb_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; @@ -1002,8 +996,7 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -1011,7 +1004,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, dvscntr = DVS_ENABLE; - if (IS_SANDYBRIDGE(dev_priv)) + if (display->platform.sandybridge) dvscntr |= DVS_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -1072,8 +1065,8 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; u16 gamma[8]; @@ -1102,8 +1095,8 @@ static void ilk_sprite_linear_gamma(u16 gamma[17]) static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; u16 gamma[17]; @@ -1132,7 +1125,7 @@ g4x_sprite_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -1162,8 +1155,7 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 dvssurf_offset = plane_state->view.color_plane[0].offset; @@ -1195,7 +1187,7 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DVSSURF(pipe), intel_plane_ggtt_offset(plane_state) + dvssurf_offset); - if (IS_G4X(dev_priv)) + if (display->platform.g4x) g4x_sprite_update_gamma(plane_state); else ilk_sprite_update_gamma(plane_state); @@ -1206,7 +1198,7 @@ g4x_sprite_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; intel_de_write_fw(display, DVSCNTR(pipe), 0); @@ -1219,7 +1211,7 @@ static bool g4x_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; @@ -1259,7 +1251,7 @@ static int g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(crtc_state); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; const struct drm_rect *src = &plane_state->uapi.src; const struct drm_rect *dst = &plane_state->uapi.dst; @@ -1325,9 +1317,7 @@ static int g4x_sprite_check(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(crtc_state); - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); int min_scale = DRM_PLANE_NO_SCALING; int max_scale = DRM_PLANE_NO_SCALING; int ret; @@ -1336,7 +1326,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, if (DISPLAY_VER(display) < 7) { min_scale = 1; max_scale = 16 << 16; - } else if (IS_IVYBRIDGE(dev_priv)) { + } else if (display->platform.ivybridge) { min_scale = 1; max_scale = 2 << 16; } @@ -1372,13 +1362,11 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, int chv_plane_check_rotation(const struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int rotation = plane_state->hw.rotation; /* CHV ignores the mirror bit when the rotate bit is set :( */ - if (IS_CHERRYVIEW(dev_priv) && + if (display->platform.cherryview && rotation & DRM_MODE_ROTATE_180 && rotation & DRM_MODE_REFLECT_X) { drm_dbg_kms(display->drm, @@ -1580,10 +1568,9 @@ static const struct drm_plane_funcs vlv_sprite_funcs = { }; struct intel_plane * -intel_sprite_plane_create(struct drm_i915_private *dev_priv, +intel_sprite_plane_create(struct intel_display *display, enum pipe pipe, int sprite) { - struct intel_display *display = &dev_priv->display; struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; unsigned int supported_rotations; @@ -1596,7 +1583,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (IS_ERR(plane)) return plane; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { plane->update_noarm = vlv_sprite_update_noarm; plane->update_arm = vlv_sprite_update_arm; plane->disable_arm = vlv_sprite_disable_arm; @@ -1610,7 +1597,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 128; - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + if (display->platform.cherryview && pipe == PIPE_B) { formats = chv_pipe_b_sprite_formats; num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); } else { @@ -1626,7 +1613,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = ivb_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (display->platform.broadwell || display->platform.haswell) { plane->max_stride = hsw_sprite_max_stride; plane->min_cdclk = hsw_plane_min_cdclk; } else { @@ -1656,7 +1643,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (intel_scanout_needs_vtd_wa(display)) plane->vtd_guard = 64; - if (IS_SANDYBRIDGE(dev_priv)) { + if (display->platform.sandybridge) { formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); @@ -1669,7 +1656,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } } - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + if (display->platform.cherryview && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h index 531079979c05..c33a2808da8c 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.h +++ b/drivers/gpu/drm/i915/display/intel_sprite.h @@ -8,13 +8,13 @@ #include -struct drm_i915_private; struct intel_crtc_state; +struct intel_display; struct intel_plane_state; enum pipe; #ifdef I915 -struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, +struct intel_plane *intel_sprite_plane_create(struct intel_display *display, enum pipe pipe, int plane); int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state); int chv_plane_check_rotation(const struct intel_plane_state *plane_state); @@ -26,7 +26,7 @@ int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); #else -static inline struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, +static inline struct intel_plane *intel_sprite_plane_create(struct intel_display *display, int pipe, int plane) { return NULL; From patchwork Thu Feb 6 18:55:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DD30C02199 for ; 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X-CSE-ConnectionGUID: QEW/eDCkTiqwf9AnEextJQ== X-CSE-MsgGUID: jVWFEyvWThaz4D9k7eIPdg== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395066" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395066" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:56:07 -0800 X-CSE-ConnectionGUID: AnHpFdxhSx64ZeuDMvchGQ== X-CSE-MsgGUID: 1L+hd+AQR4mQHLvNi/12nQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499618" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:56:04 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:56:04 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 09/12] drm/i915: Convert intel_cursor.c to struct intel_display Date: Thu, 6 Feb 2025 20:55:30 +0200 Message-ID: <20250206185533.32306-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the cursor code to use it. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 136 +++++++++----------- drivers/gpu/drm/i915/display/intel_cursor.h | 4 +- 3 files changed, 66 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 7279e064a565..2dc495659563 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -344,7 +344,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) crtc->plane_ids_mask |= BIT(plane->id); } - cursor = intel_cursor_plane_create(dev_priv, pipe); + cursor = intel_cursor_plane_create(display, pipe); if (IS_ERR(cursor)) { ret = PTR_ERR(cursor); goto fail; diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 6a0d563174cf..4cd48d54164d 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -35,11 +35,10 @@ static const u32 intel_cursor_formats[] = { static u32 intel_cursor_base(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); u32 base; - if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) + if (DISPLAY_INFO(display)->cursor_needs_physical) base = plane_state->phys_dma_addr; else base = intel_plane_ggtt_offset(plane_state); @@ -92,8 +91,7 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) static int intel_cursor_check_surface(struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int rotation = plane_state->hw.rotation; int src_x, src_y; u32 offset; @@ -114,7 +112,7 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) plane_state, 0); if (src_x != 0 || src_y != 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Arbitrary cursor panning not supported\n"); return -EINVAL; } @@ -127,7 +125,7 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) src_x << 16, src_y << 16); /* ILK+ do this automagically in hardware */ - if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { + if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) { const struct drm_framebuffer *fb = plane_state->hw.fb; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; @@ -145,14 +143,14 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) static int intel_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_rect src = plane_state->uapi.src; const struct drm_rect dst = plane_state->uapi.dst; int ret; if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { - drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); + drm_dbg_kms(display->drm, "cursor cannot be tiled\n"); return -EINVAL; } @@ -233,8 +231,8 @@ static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) static int i845_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); int ret; ret = intel_check_cursor(crtc_state, plane_state); @@ -247,14 +245,14 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i845_cursor_size_ok(plane_state)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Cursor dimension %dx%d not supported\n", drm_rect_width(&plane_state->uapi.dst), drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } - drm_WARN_ON(&i915->drm, plane_state->uapi.visible && + drm_WARN_ON(display->drm, plane_state->uapi.visible && plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); switch (fb->pitches[0]) { @@ -264,7 +262,7 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, case 2048: break; default: - drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", + drm_dbg_kms(display->drm, "Invalid cursor stride (%u)\n", fb->pitches[0]); return -EINVAL; } @@ -280,7 +278,7 @@ static void i845_cursor_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 cntl = 0, base = 0, pos = 0, size = 0; if (plane_state && plane_state->uapi.visible) { @@ -302,17 +300,17 @@ static void i845_cursor_update_arm(struct intel_dsb *dsb, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); - intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); - intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size); - intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); - intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); + intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); + intel_de_write_fw(display, CURBASE(display, PIPE_A), base); + intel_de_write_fw(display, CURSIZE(display, PIPE_A), size); + intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); + intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); + intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); } } @@ -327,7 +325,6 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; @@ -337,7 +334,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE; + ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; *pipe = PIPE_A; @@ -383,11 +380,11 @@ static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 cntl = 0; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) return cntl; if (crtc_state->gamma_enable) @@ -396,7 +393,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) if (crtc_state->csc_enable) cntl |= MCURSOR_PIPE_CSC_ENABLE; - if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (DISPLAY_VER(display) < 5 && !display->platform.g4x) cntl |= MCURSOR_PIPE_SEL(crtc->pipe); return cntl; @@ -405,11 +402,10 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); u32 cntl = 0; - if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (display->platform.sandybridge || display->platform.ivybridge) cntl |= MCURSOR_TRICKLE_FEED_DISABLE; switch (drm_rect_width(&plane_state->uapi.dst)) { @@ -431,7 +427,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, cntl |= MCURSOR_ROTATE_180; /* Wa_22012358565:adl-p */ - if (DISPLAY_VER(dev_priv) == 13) + if (DISPLAY_VER(display) == 13) cntl |= MCURSOR_ARB_SLOTS(1); return cntl; @@ -439,8 +435,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); int width = drm_rect_width(&plane_state->uapi.dst); int height = drm_rect_height(&plane_state->uapi.dst); @@ -463,7 +458,7 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) * cursor is not rotated. Everything else requires square * cursors. */ - if (HAS_CUR_FBC(dev_priv) && + if (HAS_CUR_FBC(display) && plane_state->hw.rotation & DRM_MODE_ROTATE_0) { if (height < 8 || height > width) return false; @@ -478,8 +473,8 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; int ret; @@ -494,19 +489,19 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i9xx_cursor_size_ok(plane_state)) { - drm_dbg(&dev_priv->drm, + drm_dbg(display->drm, "Cursor dimension %dx%d not supported\n", drm_rect_width(&plane_state->uapi.dst), drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } - drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && + drm_WARN_ON(display->drm, plane_state->uapi.visible && plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); if (fb->pitches[0] != drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Invalid cursor stride (%u) (cursor width %d)\n", fb->pitches[0], drm_rect_width(&plane_state->uapi.dst)); @@ -523,9 +518,9 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, * display power well must be turned off and on again. * Refuse the put the cursor into that compromised position. */ - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && + if (display->platform.cherryview && pipe == PIPE_C && plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "CHV cursor C not allowed to straddle the left screen edge\n"); return -EINVAL; } @@ -539,7 +534,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -553,8 +548,7 @@ static void wa_16021440873(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 ctl = plane_state->ctl; int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1; enum pipe pipe = plane->pipe; @@ -564,7 +558,7 @@ static void wa_16021440873(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl); - intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), + intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), CURSOR_POS_Y(et_y_position)); } @@ -573,8 +567,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -585,7 +578,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb, u32 val = intel_cursor_position(crtc_state, plane_state, true); - intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), val); + intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val); } intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl); @@ -659,8 +652,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; @@ -698,7 +690,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, * the CURCNTR write arms the update. */ - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) skl_write_cursor_wm(dsb, plane, crtc_state); if (plane_state) @@ -709,18 +701,18 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, if (plane->cursor.base != base || plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { - if (HAS_CUR_FBC(dev_priv)) - intel_de_write_dsb(display, dsb, CUR_FBC_CTL(dev_priv, pipe), fbc_ctl); - intel_de_write_dsb(display, dsb, CURCNTR(dev_priv, pipe), cntl); - intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos); - intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base); + if (HAS_CUR_FBC(display)) + intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl); + intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl); + intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); + intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos); - intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base); + intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); + intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); } } @@ -735,7 +727,6 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; @@ -751,11 +742,11 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe)); + val = intel_de_read(display, CURCNTR(display, plane->pipe)); ret = val & MCURSOR_MODE_MASK; - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) *pipe = plane->pipe; else *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); @@ -797,7 +788,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane, { struct intel_plane *plane = to_intel_plane(_plane); struct intel_crtc *crtc = to_intel_crtc(_crtc); - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); struct intel_plane_state *old_plane_state = to_intel_plane_state(plane->base.state); struct intel_plane_state *new_plane_state; @@ -901,7 +892,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane, intel_psr_lock(crtc_state); - if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) { + if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) { /* * TODO: maybe check if we're still in PSR * and skip the vblank evasion entirely? @@ -967,8 +958,8 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = { static void intel_cursor_add_size_hints_property(struct intel_plane *plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); - const struct drm_mode_config *config = &i915->drm.mode_config; + struct intel_display *display = to_intel_display(plane); + const struct drm_mode_config *config = &display->drm->mode_config; struct drm_plane_size_hint hints[4]; int size, max_size, num_hints = 0; @@ -976,7 +967,7 @@ static void intel_cursor_add_size_hints_property(struct intel_plane *plane) /* for simplicity only enumerate the supported square+POT sizes */ for (size = 64; size <= max_size; size *= 2) { - if (drm_WARN_ON(&i915->drm, num_hints >= ARRAY_SIZE(hints))) + if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints))) break; hints[num_hints].width = size; @@ -988,10 +979,9 @@ static void intel_cursor_add_size_hints_property(struct intel_plane *plane) } struct intel_plane * -intel_cursor_plane_create(struct drm_i915_private *dev_priv, +intel_cursor_plane_create(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; struct intel_plane *cursor; int ret, zpos; u64 *modifiers; @@ -1005,7 +995,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, cursor->id = PLANE_CURSOR; cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); - if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { + if (display->platform.i845g || display->platform.i865g) { cursor->max_stride = i845_cursor_max_stride; cursor->min_alignment = i845_cursor_min_alignment; cursor->update_arm = i845_cursor_update_arm; @@ -1015,9 +1005,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, } else { cursor->max_stride = i9xx_cursor_max_stride; - if (IS_I830(dev_priv)) + if (display->platform.i830) cursor->min_alignment = i830_cursor_min_alignment; - else if (IS_I85X(dev_priv)) + else if (display->platform.i85x) cursor->min_alignment = i85x_cursor_min_alignment; else cursor->min_alignment = i9xx_cursor_min_alignment; @@ -1034,12 +1024,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; - if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) + if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display)) cursor->cursor.size = ~0; modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE); - ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, + ret = drm_universal_plane_init(display->drm, &cursor->base, 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), @@ -1052,7 +1042,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (ret) goto fail; - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) drm_plane_create_rotation_property(&cursor->base, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | @@ -1060,10 +1050,10 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, intel_cursor_add_size_hints_property(cursor); - zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; + zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1; drm_plane_create_zpos_immutable_property(&cursor->base, zpos); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) drm_plane_enable_fb_damage_clips(&cursor->base); intel_plane_helper_add(cursor); diff --git a/drivers/gpu/drm/i915/display/intel_cursor.h b/drivers/gpu/drm/i915/display/intel_cursor.h index e2d9ec710a86..65a9e7eb88c2 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.h +++ b/drivers/gpu/drm/i915/display/intel_cursor.h @@ -7,12 +7,12 @@ #define _INTEL_CURSOR_H_ enum pipe; -struct drm_i915_private; +struct intel_display; struct intel_plane; struct kthread_work; struct intel_plane * -intel_cursor_plane_create(struct drm_i915_private *dev_priv, +intel_cursor_plane_create(struct intel_display *display, enum pipe pipe); void intel_cursor_unpin_work(struct kthread_work *base); From patchwork Thu Feb 6 18:55:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41A3EC02194 for ; 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X-CSE-ConnectionGUID: lJcje0+ERgyukODjpLme+w== X-CSE-MsgGUID: QajApJGETkS63FCtr+FDIA== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395069" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395069" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:56:11 -0800 X-CSE-ConnectionGUID: OeqGnUklQWGhL0zu+ghGcw== X-CSE-MsgGUID: JASkm/3bT6OjR6boCVt4Aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499628" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:56:08 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:56:07 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 10/12] drm/i915: Convert skl_univeral_plane.c to struct intel_display Date: Thu, 6 Feb 2025 20:55:31 +0200 Message-ID: <20250206185533.32306-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the skl+ universal plane code to use it. Note that we still have two straggles in the form on HAS_FLAT_CCS() and the pxp stuff. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 5 +- drivers/gpu/drm/i915/display/skl_scaler.c | 13 +- .../drm/i915/display/skl_universal_plane.c | 360 +++++++++--------- .../drm/i915/display/skl_universal_plane.h | 8 +- 5 files changed, 189 insertions(+), 201 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 2dc495659563..89785da93603 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -319,7 +319,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe]; if (DISPLAY_VER(display) >= 9) - primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1); + primary = skl_universal_plane_create(display, pipe, PLANE_1); else primary = intel_primary_plane_create(display, pipe); if (IS_ERR(primary)) { @@ -334,7 +334,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) struct intel_plane *plane; if (DISPLAY_VER(dev_priv) >= 9) - plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite); + plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite); else plane = intel_sprite_plane_create(display, pipe, sprite); if (IS_ERR(plane)) { diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 83bc3cf1cf97..a451c46d3795 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4438,6 +4438,7 @@ static int icl_add_linked_planes(struct intel_atomic_state *state) static int icl_check_nv12_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -4479,7 +4480,7 @@ static int icl_check_nv12_planes(struct intel_atomic_state *state, continue; for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { - if (!icl_is_nv12_y_plane(dev_priv, linked->id)) + if (!icl_is_nv12_y_plane(display, linked->id)) continue; if (crtc_state->active_planes & BIT(linked->id)) @@ -4524,7 +4525,7 @@ static int icl_check_nv12_planes(struct intel_atomic_state *state, linked_state->uapi.src = plane_state->uapi.src; linked_state->uapi.dst = plane_state->uapi.dst; - if (icl_is_hdr_plane(dev_priv, plane->id)) { + if (icl_is_hdr_plane(display, plane->id)) { if (linked->id == PLANE_7) plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; else if (linked->id == PLANE_6) diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index c8bf6fd92ce8..3d24fa773094 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -279,14 +279,14 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); struct drm_framebuffer *fb = plane_state->hw.fb; bool force_detach = !fb || !plane_state->uapi.visible; bool need_scaler = false; /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ - if (!icl_is_hdr_plane(dev_priv, plane->id) && + if (!icl_is_hdr_plane(display, plane->id) && fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) need_scaler = true; @@ -364,9 +364,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, int *scaler_id) { struct intel_display *display = to_intel_display(crtc); - struct intel_crtc_scaler_state *scaler_state = - &crtc_state->scaler_state; - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; u32 mode; int hscale = 0; int vscale = 0; @@ -386,7 +384,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, if (DISPLAY_VER(display) == 9) { mode = SKL_PS_SCALER_MODE_NV12; - } else if (icl_is_hdr_plane(dev_priv, plane->id)) { + } else if (icl_is_hdr_plane(display, plane->id)) { /* * On gen11+'s HDR planes we only use the scaler for * scaling. They have a dedicated chroma upsampler, so @@ -782,7 +780,6 @@ skl_program_plane_scaler(struct intel_plane *plane, const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; int scaler_id = plane_state->scaler_id; @@ -806,7 +803,7 @@ skl_program_plane_scaler(struct intel_plane *plane, /* TODO: handle sub-pixel coordinates */ if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - !icl_is_hdr_plane(dev_priv, plane->id)) { + !icl_is_hdr_plane(display, plane->id)) { y_hphase = skl_scaler_calc_phase(1, hscale, false); y_vphase = skl_scaler_calc_phase(1, vscale, false); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 3a60d6d49662..f8d3a79a96ff 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -233,21 +233,19 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) } } -static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) +static u8 icl_nv12_y_plane_mask(struct intel_display *display) { - struct intel_display *display = &i915->display; - if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) return BIT(PLANE_4) | BIT(PLANE_5); else return BIT(PLANE_6) | BIT(PLANE_7); } -bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, +bool icl_is_nv12_y_plane(struct intel_display *display, enum plane_id plane_id) { - return DISPLAY_VER(dev_priv) >= 11 && - icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); + return DISPLAY_VER(display) >= 11 && + icl_nv12_y_plane_mask(display) & BIT(plane_id); } u8 icl_hdr_plane_mask(void) @@ -255,9 +253,9 @@ u8 icl_hdr_plane_mask(void) return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3); } -bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) +bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id) { - return DISPLAY_VER(dev_priv) >= 11 && + return DISPLAY_VER(display) >= 11 && icl_hdr_plane_mask() & BIT(plane_id); } @@ -589,7 +587,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); /* PLANE_SURF GGTT -> DPT alignment */ int mult = intel_fb_uses_dpt(fb) ? 512 : 1; @@ -602,7 +600,7 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, * flips unless we align to 16k at least. * Figure out what's going on here... */ - if (IS_ALDERLAKE_P(i915) && + if (display->platform.alderlake_p && intel_plane_can_async_flip(plane, fb->modifier)) return mult * 16 * 1024; @@ -684,7 +682,7 @@ icl_program_input_csc(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -829,7 +827,7 @@ static void skl_write_plane_wm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; @@ -875,7 +873,7 @@ skl_plane_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; @@ -889,7 +887,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -903,12 +901,11 @@ icl_plane_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - if (icl_is_hdr_plane(dev_priv, plane_id)) + if (icl_is_hdr_plane(display, plane_id)) intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0); skl_write_plane_wm(dsb, plane, crtc_state); @@ -923,7 +920,6 @@ skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum intel_display_power_domain power_domain; enum plane_id plane_id = plane->id; intel_wakeref_t wakeref; @@ -934,7 +930,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; + ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; *pipe = plane->pipe; @@ -1155,10 +1151,10 @@ static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); u32 plane_ctl = 0; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) return plane_ctl; if (crtc_state->gamma_enable) @@ -1173,8 +1169,7 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -1182,7 +1177,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl = PLANE_CTL_ENABLE; - if (DISPLAY_VER(dev_priv) < 10) { + if (DISPLAY_VER(display) < 10) { plane_ctl |= skl_plane_ctl_alpha(plane_state); plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; @@ -1197,7 +1192,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= skl_plane_ctl_tiling(fb->modifier); plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) plane_ctl |= icl_plane_ctl_flip(rotation & DRM_MODE_REFLECT_MASK); @@ -1207,7 +1202,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; /* Wa_22012358565:adl-p */ - if (DISPLAY_VER(dev_priv) == 13) + if (DISPLAY_VER(display) == 13) plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); return plane_ctl; @@ -1215,10 +1210,10 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); u32 plane_color_ctl = 0; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) return plane_color_ctl; if (crtc_state->gamma_enable) @@ -1233,8 +1228,7 @@ static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); u32 plane_color_ctl = 0; @@ -1242,7 +1236,7 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); - if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { + if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) { switch (plane_state->hw.color_encoding) { case DRM_COLOR_YCBCR_BT709: plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; @@ -1272,7 +1266,7 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, static u32 skl_surf_address(const struct intel_plane_state *plane_state, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; u32 offset = plane_state->view.color_plane[color_plane].offset; @@ -1281,12 +1275,12 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state, * The DPT object contains only one vma, so the VMA's offset * within the DPT is always 0. */ - drm_WARN_ON(&i915->drm, plane_state->dpt_vma && + drm_WARN_ON(display->drm, plane_state->dpt_vma && intel_dpt_offset(plane_state->dpt_vma)); - drm_WARN_ON(&i915->drm, offset & 0x1fffff); + drm_WARN_ON(display->drm, offset & 0x1fffff); return offset >> 9; } else { - drm_WARN_ON(&i915->drm, offset & 0xfff); + drm_WARN_ON(display->drm, offset & 0xfff); return offset; } } @@ -1308,7 +1302,7 @@ static u32 skl_plane_surf(const struct intel_plane_state *plane_state, u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_plane = skl_main_to_aux_plane(fb, color_plane); u32 aux_dist; @@ -1319,7 +1313,7 @@ u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, aux_dist = skl_surf_address(plane_state, aux_plane) - skl_surf_address(plane_state, color_plane); - if (DISPLAY_VER(i915) < 12) + if (DISPLAY_VER(display) < 12) aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); return aux_dist; @@ -1357,7 +1351,7 @@ static void icl_plane_csc_load_black(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; @@ -1394,7 +1388,7 @@ skl_plane_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; u32 stride = skl_plane_stride(plane_state, 0); @@ -1425,8 +1419,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; u32 x = plane_state->view.color_plane[0].x; @@ -1441,7 +1434,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, crtc_state->async_flip_planes & BIT(plane->id)) plane_ctl |= PLANE_CTL_ASYNC_FLIP; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) plane_color_ctl = plane_state->color_ctl | glk_plane_color_ctl_crtc(crtc_state); @@ -1462,7 +1455,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); @@ -1493,7 +1486,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, int color_plane) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_rect *clip; u32 val; @@ -1539,8 +1532,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; int color_plane = icl_plane_color_plane(plane_state); @@ -1588,18 +1580,18 @@ icl_plane_update_noarm(struct intel_dsb *dsb, } /* FLAT CCS doesn't need to program AUX_DIST */ - if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20) + if (!HAS_FLAT_CCS(to_i915(display->drm)) && DISPLAY_VER(display) < 20) intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id), skl_plane_aux_dist(plane_state, color_plane)); - if (icl_is_hdr_plane(dev_priv, plane_id)) + if (icl_is_hdr_plane(display, plane_id)) intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); - if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) + if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id)) icl_program_input_csc(dsb, plane, plane_state); skl_write_plane_wm(dsb, plane, crtc_state); @@ -1619,7 +1611,7 @@ static void icl_plane_update_sel_fetch_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -1638,7 +1630,7 @@ icl_plane_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; int color_plane = icl_plane_color_plane(plane_state); @@ -1677,7 +1669,7 @@ skl_plane_async_flip(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, bool async_flip) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; u32 plane_ctl = plane_state->ctl, plane_surf; @@ -1713,8 +1705,7 @@ static bool intel_format_is_p01x(u32 format) static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; @@ -1723,7 +1714,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && intel_fb_is_ccs_modifier(fb->modifier)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "RC support only with 0/180 degree rotation (%x)\n", rotation); return -EINVAL; @@ -1731,7 +1722,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, if (rotation & DRM_MODE_REFLECT_X && fb->modifier == DRM_FORMAT_MOD_LINEAR) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "horizontal flip is not supported with linear surface formats\n"); return -EINVAL; } @@ -1741,15 +1732,15 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, */ if (rotation & DRM_MODE_REFLECT_X && intel_fb_is_tile4_modifier(fb->modifier) && - DISPLAY_VER(dev_priv) >= 20) { - drm_dbg_kms(&dev_priv->drm, + DISPLAY_VER(display) >= 20) { + drm_dbg_kms(display->drm, "horizontal flip is not supported with tile4 surface formats\n"); return -EINVAL; } if (drm_rotation_90_or_270(rotation)) { if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Y/Yf tiling required for 90/270!\n"); return -EINVAL; } @@ -1760,7 +1751,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, */ switch (fb->format->format) { case DRM_FORMAT_RGB565: - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) break; fallthrough; case DRM_FORMAT_C8: @@ -1773,7 +1764,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_Y216: case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unsupported pixel format %p4cc for 90/270!\n", &fb->format->format); return -EINVAL; @@ -1787,16 +1778,16 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && fb->modifier != DRM_FORMAT_MOD_LINEAR && fb->modifier != I915_FORMAT_MOD_X_TILED) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Y/Yf tiling not supported in IF-ID mode\n"); return -EINVAL; } /* Wa_1606054188:tgl,adl-s */ - if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && + if ((display->platform.alderlake_s || display->platform.tigerlake) && plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && intel_format_is_p01x(fb->format->format)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Source color keying not supported with P01x formats\n"); return -EINVAL; } @@ -1807,8 +1798,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); int crtc_x = plane_state->uapi.dst.x1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); @@ -1822,9 +1812,9 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s * than the cursor ending less than 4 pixels from the left edge of the * screen may cause FIFO underflow and display corruption. */ - if (DISPLAY_VER(dev_priv) == 10 && + if (DISPLAY_VER(display) == 10 && (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "requested plane X %s position %d invalid (valid range %d-%d)\n", crtc_x + crtc_w < 4 ? "end" : "start", crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, @@ -1837,7 +1827,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; @@ -1847,14 +1837,14 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s src_w & 3 && (rotation == DRM_MODE_ROTATE_270 || rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { - drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); + drm_dbg_kms(display->drm, "src width must be multiple of 4 for rotated planar YUV\n"); return -EINVAL; } return 0; } -static int skl_plane_max_scale(struct drm_i915_private *dev_priv, +static int skl_plane_max_scale(struct intel_display *display, const struct drm_framebuffer *fb) { /* @@ -1863,7 +1853,7 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv, * the best case. * FIXME need to properly check this later. */ - if (DISPLAY_VER(dev_priv) >= 10 || + if (DISPLAY_VER(display) >= 10 || !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) return 0x30000 - 1; else @@ -1952,8 +1942,8 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, int *x, int *y, u32 *offset) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_plane = skl_main_to_aux_plane(fb, 0); u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; @@ -1962,7 +1952,7 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, intel_add_fb_offsets(x, y, plane_state, 0); *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); - if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(display->drm, alignment && !is_power_of_2(alignment))) return -EINVAL; /* @@ -1986,7 +1976,7 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { if (*offset == 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unable to find suitable display surface offset due to X-tiling\n"); return -EINVAL; } @@ -2002,8 +1992,8 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, static int skl_check_main_surface(struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int x = plane_state->uapi.src.x1 >> 16; @@ -2019,7 +2009,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int ret; if (w > max_width || w < min_width || h > max_height || h < 1) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", w, h, min_width, max_width, max_height); return -EINVAL; @@ -2046,16 +2036,16 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) if (x != plane_state->view.color_plane[aux_plane].x || y != plane_state->view.color_plane[aux_plane].y) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unable to find suitable display surface offset due to CCS\n"); return -EINVAL; } } - if (DISPLAY_VER(dev_priv) >= 13) - drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); + if (DISPLAY_VER(display) >= 13) + drm_WARN_ON(display->drm, x > 65535 || y > 65535); else - drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); + drm_WARN_ON(display->drm, x > 8191 || y > 8191); plane_state->view.color_plane[0].offset = offset; plane_state->view.color_plane[0].x = x; @@ -2073,8 +2063,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int uv_plane = 1; @@ -2090,7 +2080,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) /* FIXME not quite sure how/if these apply to the chroma plane */ if (w > max_width || h > max_height) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "CbCr source size %dx%d too big (limit %dx%d)\n", w, h, max_width, max_height); return -EINVAL; @@ -2124,16 +2114,16 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (x != plane_state->view.color_plane[ccs_plane].x || y != plane_state->view.color_plane[ccs_plane].y) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Unable to find suitable display surface offset due to CCS\n"); return -EINVAL; } } - if (DISPLAY_VER(i915) >= 13) - drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); + if (DISPLAY_VER(display) >= 13) + drm_WARN_ON(display->drm, x > 65535 || y > 65535); else - drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); + drm_WARN_ON(display->drm, x > 8191 || y > 8191); plane_state->view.color_plane[uv_plane].offset = offset; plane_state->view.color_plane[uv_plane].x = x; @@ -2219,9 +2209,13 @@ static int skl_check_plane_surface(struct intel_plane_state *plane_state) static bool skl_fb_scalable(const struct drm_framebuffer *fb) { + struct intel_display *display; + if (!fb) return false; + display = to_intel_display(fb->dev); + switch (fb->format->format) { case DRM_FORMAT_C8: return false; @@ -2229,7 +2223,7 @@ static bool skl_fb_scalable(const struct drm_framebuffer *fb) case DRM_FORMAT_ARGB16161616F: case DRM_FORMAT_XBGR16161616F: case DRM_FORMAT_ABGR16161616F: - return DISPLAY_VER(to_i915(fb->dev)) >= 11; + return DISPLAY_VER(display) >= 11; default: return true; } @@ -2237,12 +2231,12 @@ static bool skl_fb_scalable(const struct drm_framebuffer *fb) static void check_protection(struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); + struct drm_i915_private *i915 = to_i915(display->drm); const struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_gem_object *obj = intel_fb_bo(fb); - if (DISPLAY_VER(i915) < 11) + if (DISPLAY_VER(display) < 11) return; plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0; @@ -2253,8 +2247,8 @@ static void check_protection(struct intel_plane_state *plane_state) static int skl_plane_check(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int min_scale = DRM_PLANE_NO_SCALING; int max_scale = DRM_PLANE_NO_SCALING; @@ -2267,7 +2261,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, /* use scaler when colorkey is not required */ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { min_scale = 1; - max_scale = skl_plane_max_scale(dev_priv, fb); + max_scale = skl_plane_max_scale(display, fb); } ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, @@ -2302,12 +2296,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) plane_state->color_ctl = glk_plane_color_ctl(crtc_state, plane_state); if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - icl_is_hdr_plane(dev_priv, plane->id)) + icl_is_hdr_plane(display, plane->id)) /* Enable and use MPEG-2 chroma siting */ plane_state->cus_ctl = PLANE_CUS_ENABLE | PLANE_CUS_HPHASE_0 | @@ -2323,37 +2317,37 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) return pipe - PIPE_A + INTEL_FBC_A; } -static bool skl_plane_has_fbc(struct drm_i915_private *i915, +static bool skl_plane_has_fbc(struct intel_display *display, enum intel_fbc_id fbc_id, enum plane_id plane_id) { - if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) + if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0) return false; - if (DISPLAY_VER(i915) >= 20) - return icl_is_hdr_plane(i915, plane_id); + if (DISPLAY_VER(display) >= 20) + return icl_is_hdr_plane(display, plane_id); else return plane_id == PLANE_1; } -static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, +static struct intel_fbc *skl_plane_fbc(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); - if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) - return dev_priv->display.fbc[fbc_id]; + if (skl_plane_has_fbc(display, fbc_id, plane_id)) + return display->fbc[fbc_id]; else return NULL; } -static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, +static bool skl_plane_has_planar(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { /* Display WA #0870: skl, bxt */ - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.skylake || display->platform.broxton) return false; - if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) + if (DISPLAY_VER(display) == 9 && pipe == PIPE_C) return false; if (plane_id != PLANE_1 && plane_id != PLANE_2) @@ -2362,11 +2356,11 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, return true; } -static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, +static const u32 *skl_get_plane_formats(struct intel_display *display, enum pipe pipe, enum plane_id plane_id, int *num_formats) { - if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { + if (skl_plane_has_planar(display, pipe, plane_id)) { *num_formats = ARRAY_SIZE(skl_planar_formats); return skl_planar_formats; } else { @@ -2375,11 +2369,11 @@ static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, } } -static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, +static const u32 *glk_get_plane_formats(struct intel_display *display, enum pipe pipe, enum plane_id plane_id, int *num_formats) { - if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { + if (skl_plane_has_planar(display, pipe, plane_id)) { *num_formats = ARRAY_SIZE(glk_planar_formats); return glk_planar_formats; } else { @@ -2388,14 +2382,14 @@ static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, } } -static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, +static const u32 *icl_get_plane_formats(struct intel_display *display, enum pipe pipe, enum plane_id plane_id, int *num_formats) { - if (icl_is_hdr_plane(dev_priv, plane_id)) { + if (icl_is_hdr_plane(display, plane_id)) { *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); return icl_hdr_plane_formats; - } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { + } else if (icl_is_nv12_y_plane(display, plane_id)) { *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); return icl_sdr_y_plane_formats; } else { @@ -2613,46 +2607,46 @@ skl_plane_disable_flip_done(struct intel_plane *plane) spin_unlock_irq(&i915->irq_lock); } -static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, +static bool skl_plane_has_rc_ccs(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { return pipe != PIPE_C && (plane_id == PLANE_1 || plane_id == PLANE_2); } -static u8 skl_plane_caps(struct drm_i915_private *i915, +static u8 skl_plane_caps(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { u8 caps = INTEL_PLANE_CAP_TILING_X | INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_TILING_Yf; - if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) + if (skl_plane_has_rc_ccs(display, pipe, plane_id)) caps |= INTEL_PLANE_CAP_CCS_RC; return caps; } -static bool glk_plane_has_rc_ccs(struct drm_i915_private *i915, +static bool glk_plane_has_rc_ccs(struct intel_display *display, enum pipe pipe) { return pipe != PIPE_C; } -static u8 glk_plane_caps(struct drm_i915_private *i915, +static u8 glk_plane_caps(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { u8 caps = INTEL_PLANE_CAP_TILING_X | INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_TILING_Yf; - if (glk_plane_has_rc_ccs(i915, pipe)) + if (glk_plane_has_rc_ccs(display, pipe)) caps |= INTEL_PLANE_CAP_CCS_RC; return caps; } -static u8 icl_plane_caps(struct drm_i915_private *i915, +static u8 icl_plane_caps(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { return INTEL_PLANE_CAP_TILING_X | @@ -2661,21 +2655,20 @@ static u8 icl_plane_caps(struct drm_i915_private *i915, INTEL_PLANE_CAP_CCS_RC; } -static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915, +static bool tgl_plane_has_mc_ccs(struct intel_display *display, enum plane_id plane_id) { /* Wa_14010477008 */ - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || - (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) + if (display->platform.dg1 || display->platform.rocketlake || + (display->platform.tigerlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_D0))) return false; return plane_id < PLANE_6; } -static u8 tgl_plane_caps(struct drm_i915_private *i915, +static u8 tgl_plane_caps(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { - struct intel_display *display = &i915->display; u8 caps = INTEL_PLANE_CAP_TILING_X | INTEL_PLANE_CAP_CCS_RC | INTEL_PLANE_CAP_CCS_RC_CC; @@ -2685,7 +2678,7 @@ static u8 tgl_plane_caps(struct drm_i915_private *i915, else caps |= INTEL_PLANE_CAP_TILING_Y; - if (tgl_plane_has_mc_ccs(i915, plane_id)) + if (tgl_plane_has_mc_ccs(display, plane_id)) caps |= INTEL_PLANE_CAP_CCS_MC; if (DISPLAY_VER(display) >= 14 && display->platform.dgfx) @@ -2695,10 +2688,9 @@ static u8 tgl_plane_caps(struct drm_i915_private *i915, } struct intel_plane * -skl_universal_plane_create(struct drm_i915_private *dev_priv, +skl_universal_plane_create(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { - struct intel_display *display = &dev_priv->display; const struct drm_plane_funcs *plane_funcs; struct intel_plane *plane; enum drm_plane_type plane_type; @@ -2718,21 +2710,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->id = plane_id; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); - intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); + intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane); - if (DISPLAY_VER(dev_priv) >= 30) { + if (DISPLAY_VER(display) >= 30) { plane->max_width = xe3_plane_max_width; plane->max_height = icl_plane_max_height; plane->min_cdclk = icl_plane_min_cdclk; - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { plane->min_width = icl_plane_min_width; - if (icl_is_hdr_plane(dev_priv, plane_id)) + if (icl_is_hdr_plane(display, plane_id)) plane->max_width = icl_hdr_plane_max_width; else plane->max_width = icl_sdr_plane_max_width; plane->max_height = icl_plane_max_height; plane->min_cdclk = icl_plane_min_cdclk; - } else if (DISPLAY_VER(dev_priv) >= 10) { + } else if (DISPLAY_VER(display) >= 10) { plane->max_width = glk_plane_max_width; plane->max_height = skl_plane_max_height; plane->min_cdclk = glk_plane_min_cdclk; @@ -2742,20 +2734,20 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->min_cdclk = skl_plane_min_cdclk; } - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) plane->max_stride = adl_plane_max_stride; else plane->max_stride = skl_plane_max_stride; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) plane->min_alignment = tgl_plane_min_alignment; else plane->min_alignment = skl_plane_min_alignment; if (intel_scanout_needs_vtd_wa(display)) - plane->vtd_guard = DISPLAY_VER(dev_priv) >= 10 ? 168 : 136; + plane->vtd_guard = DISPLAY_VER(display) >= 10 ? 168 : 136; - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(display) >= 11) { plane->update_noarm = icl_plane_update_noarm; plane->update_arm = icl_plane_update_arm; plane->disable_arm = icl_plane_disable_arm; @@ -2767,33 +2759,33 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; - if (HAS_ASYNC_FLIPS(dev_priv) && plane_id == PLANE_1) { - plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); + if (HAS_ASYNC_FLIPS(display) && plane_id == PLANE_1) { + plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(display, 9, 10); plane->async_flip = skl_plane_async_flip; plane->enable_flip_done = skl_plane_enable_flip_done; plane->disable_flip_done = skl_plane_disable_flip_done; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) plane->can_async_flip = tgl_plane_can_async_flip; - else if (DISPLAY_VER(dev_priv) == 11) + else if (DISPLAY_VER(display) == 11) plane->can_async_flip = icl_plane_can_async_flip; else plane->can_async_flip = skl_plane_can_async_flip; } - if (DISPLAY_VER(dev_priv) >= 11) - formats = icl_get_plane_formats(dev_priv, pipe, + if (DISPLAY_VER(display) >= 11) + formats = icl_get_plane_formats(display, pipe, plane_id, &num_formats); - else if (DISPLAY_VER(dev_priv) >= 10) - formats = glk_get_plane_formats(dev_priv, pipe, + else if (DISPLAY_VER(display) >= 10) + formats = glk_get_plane_formats(display, pipe, plane_id, &num_formats); else - formats = skl_get_plane_formats(dev_priv, pipe, + formats = skl_get_plane_formats(display, pipe, plane_id, &num_formats); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) plane_funcs = &tgl_plane_funcs; - else if (DISPLAY_VER(dev_priv) == 11) + else if (DISPLAY_VER(display) == 11) plane_funcs = &icl_plane_funcs; else plane_funcs = &skl_plane_funcs; @@ -2803,24 +2795,24 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_type = DRM_PLANE_TYPE_OVERLAY; - if (DISPLAY_VER(dev_priv) >= 12) - caps = tgl_plane_caps(dev_priv, pipe, plane_id); - else if (DISPLAY_VER(dev_priv) == 11) - caps = icl_plane_caps(dev_priv, pipe, plane_id); - else if (DISPLAY_VER(dev_priv) == 10) - caps = glk_plane_caps(dev_priv, pipe, plane_id); + if (DISPLAY_VER(display) >= 12) + caps = tgl_plane_caps(display, pipe, plane_id); + else if (DISPLAY_VER(display) == 11) + caps = icl_plane_caps(display, pipe, plane_id); + else if (DISPLAY_VER(display) == 10) + caps = glk_plane_caps(display, pipe, plane_id); else - caps = skl_plane_caps(dev_priv, pipe, plane_id); + caps = skl_plane_caps(display, pipe, plane_id); /* FIXME: xe has problems with AUX */ - if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(dev_priv)) + if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(to_i915(display->drm))) caps &= ~(INTEL_PLANE_CAP_CCS_RC | INTEL_PLANE_CAP_CCS_RC_CC | INTEL_PLANE_CAP_CCS_MC); modifiers = intel_fb_plane_get_modifiers(display, caps); - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, + ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, plane_type, @@ -2832,14 +2824,14 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, if (ret) goto fail; - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; else supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) supported_rotations |= DRM_MODE_REFLECT_X; drm_plane_create_rotation_property(&plane->base, @@ -2848,7 +2840,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); drm_plane_create_color_properties(&plane->base, @@ -2866,10 +2858,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, drm_plane_create_zpos_immutable_property(&plane->base, plane_id); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) drm_plane_enable_fb_damage_clips(&plane->base); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) drm_plane_create_scaling_filter_property(&plane->base, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); @@ -2890,8 +2882,6 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); enum plane_id plane_id = plane->id; enum pipe pipe; @@ -2905,35 +2895,35 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - drm_WARN_ON(dev, pipe != crtc->pipe); + drm_WARN_ON(display->drm, pipe != crtc->pipe); if (crtc_state->joiner_pipes) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Unsupported joiner configuration for initial FB\n"); return; } intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { - drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); + drm_dbg_kms(display->drm, "failed to alloc fb\n"); return; } fb = &intel_fb->base; - fb->dev = dev; + fb->dev = display->drm; - val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); + val = intel_de_read(display, PLANE_CTL(pipe, plane_id)); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; else pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; - if (DISPLAY_VER(dev_priv) >= 10) { + if (DISPLAY_VER(display) >= 10) { u32 color_ctl; - color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); + color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id)); alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); } else { alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); @@ -2955,14 +2945,14 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, case PLANE_CTL_TILED_Y: plane_config->tiling = I915_TILING_Y; if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(display) >= 12) fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; else fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; else fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; @@ -2994,9 +2984,9 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, goto error; } - if (!dev_priv->display.params.enable_dpt && + if (!display->params.enable_dpt && intel_fb_modifier_uses_dpt(display, fb->modifier)) { - drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); + drm_dbg_kms(display->drm, "DPT disabled, skipping initial FB\n"); goto error; } @@ -3019,24 +3009,24 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, break; } - if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) + if (DISPLAY_VER(display) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) plane_config->rotation |= DRM_MODE_REFLECT_X; /* 90/270 degree rotation would require extra work */ if (drm_rotation_90_or_270(plane_config->rotation)) goto error; - base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; + base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; plane_config->base = base; - offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); - drm_WARN_ON(&dev_priv->drm, offset != 0); + offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id)); + drm_WARN_ON(display->drm, offset != 0); - val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); + val = intel_de_read(display, PLANE_SIZE(pipe, plane_id)); fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; - val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); + val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id)); stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; @@ -3045,7 +3035,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, plane_config->size = fb->pitches[0] * aligned_height; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", crtc->base.name, plane->base.name, fb->width, fb->height, fb->format->cpp[0] * 8, base, fb->pitches[0], @@ -3061,7 +3051,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, const struct intel_initial_plane_config *plane_config) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -3081,7 +3071,7 @@ bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, if (plane_config->base == base) return false; - intel_de_write(i915, PLANE_SURF(pipe, plane_id), base); + intel_de_write(display, PLANE_SURF(pipe, plane_id), base); return true; } diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h index 18b41d13f0bd..0ce240e9ca5a 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h @@ -8,8 +8,8 @@ #include -struct drm_i915_private; struct intel_crtc; +struct intel_display; struct intel_initial_plane_config; struct intel_plane_state; struct skl_ddb_entry; @@ -19,7 +19,7 @@ enum pipe; enum plane_id; struct intel_plane * -skl_universal_plane_create(struct drm_i915_private *dev_priv, +skl_universal_plane_create(struct intel_display *display, enum pipe pipe, enum plane_id plane_id); void skl_get_initial_plane_config(struct intel_crtc *crtc, @@ -32,10 +32,10 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, int *x, int *y, u32 *offset); -bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, +bool icl_is_nv12_y_plane(struct intel_display *display, enum plane_id plane_id); u8 icl_hdr_plane_mask(void); -bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id); +bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id); u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, int color_plane); From patchwork Thu Feb 6 18:55:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3A81C0219C for ; Thu, 6 Feb 2025 18:56:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 698C610E92C; Thu, 6 Feb 2025 18:56:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RkGOixgE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78A8310E92B; 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06 Feb 2025 10:56:14 -0800 X-CSE-ConnectionGUID: kNul86A1TEaCbAI81rl9gg== X-CSE-MsgGUID: VoQLouv0TJW4zUQquf/PqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499639" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:56:11 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:56:10 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 11/12] drm/i915: Use DRM_RECT_FMT & co. for plane debugs Date: Thu, 6 Feb 2025 20:55:32 +0200 Message-ID: <20250206185533.32306-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Switch the plane debugs to use DRM_RECT_FMT & co. instead of drm_rect_debug_print() so that the debugs go on the same line. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 651f81ed85ab..3a474652abaa 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -944,9 +944,9 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); if (hscale < 0 || vscale < 0) { - drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n"); - drm_rect_debug_print("src: ", src, true); - drm_rect_debug_print("dst: ", dst, false); + drm_dbg_kms(&i915->drm, + "Invalid scaling of plane " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n", + DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst)); return -ERANGE; } @@ -960,9 +960,8 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, if (!can_position && plane_state->uapi.visible && !drm_rect_equals(dst, clip)) { - drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n"); - drm_rect_debug_print("dst: ", dst, false); - drm_rect_debug_print("clip: ", clip, false); + drm_dbg_kms(&i915->drm, "Plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n", + DRM_RECT_ARG(dst), DRM_RECT_ARG(clip)); return -EINVAL; } From patchwork Thu Feb 6 18:55:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13963589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 223A5C02194 for ; Thu, 6 Feb 2025 18:56:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCB1110E922; Thu, 6 Feb 2025 18:56:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NoLRzmKV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 00E9410E922; Thu, 6 Feb 2025 18:56:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738868178; x=1770404178; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZHGP81+WNZ8vV0wPVOEp1Nlx0rbng3kHd2Vb6RHedHU=; b=NoLRzmKVYGfhMQ1lgeuSscuiUvl+0g3trEvaHfItHdsOkhcmK0v3Y9zv X1RBrAp+aglIMmMnfDP9Zp89BOUFLDS6yNWEc7CB/6YO6AtekkuJcvXEE u6wguYSWy8Z6w+FhGCqdt4jbyRQXwOTWE4VD354jr7O5WsB2ibOP/Mw1j u7tpm4fHqLhQ/q8gRjJ9LYbS88mZESMYaJCWWS+PtFnyMdEzZBOqsKOD8 e4/TUasNRVtl26t4d0/UNWTgJQpheuW8sGLj6sshJIdMD3Aui7IE8+RCo m+kIi5j4mmGZ1wVaZ6dQ7roh+lnUhTQqGN5h5zx4YrVL2rmOgBM6wH6RN A==; X-CSE-ConnectionGUID: TIRhGglhS7u81jq4x4Skeg== X-CSE-MsgGUID: h/7P4yb4SSmbjbQ/zQk2pg== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39395074" X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="39395074" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2025 10:56:17 -0800 X-CSE-ConnectionGUID: cWQw2H7QQCau3ibhzgbj+g== X-CSE-MsgGUID: a9PnmZmGQSOmvC6ZP+62cA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,265,1732608000"; d="scan'208";a="111499647" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Feb 2025 10:56:15 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 06 Feb 2025 20:56:14 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Chaitanya Kumar Borah , Jani Nikula Subject: [PATCH v2 12/12] drm/i915: Pimp plane debugs Date: Thu, 6 Feb 2025 20:55:33 +0200 Message-ID: <20250206185533.32306-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250206185533.32306-1-ville.syrjala@linux.intel.com> References: <20250206185533.32306-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Include the standard "[PLANE:%d:s]" stuff in all plane debugs (or rather all I was able to find), to provide better information on which plane we're actually talking about. There are a few spots where we care about the CRTC as well, so include that where appropriate. Reviewed-by: Chaitanya Kumar Borah Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 18 ++++-- .../gpu/drm/i915/display/intel_atomic_plane.c | 17 ++++-- drivers/gpu/drm/i915/display/intel_cursor.c | 33 ++++++---- drivers/gpu/drm/i915/display/intel_display.c | 9 +-- .../drm/i915/display/skl_universal_plane.c | 60 ++++++++++++------- 5 files changed, 90 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index c3ed903d5582..aef8d8b7ea85 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -244,8 +244,12 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) src_y = plane_state->uapi.src.y1 >> 16; /* Undocumented hardware limit on i965/g4x/vlv/chv */ - if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) + if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) { + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] plane too wide (%d) for 64bpp\n", + plane->base.base.id, plane->base.name, src_w); return -EINVAL; + } intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); @@ -273,7 +277,8 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { if (offset == 0) { drm_dbg_kms(display->drm, - "Unable to find suitable display surface offset due to X-tiling\n"); + "[PLANE:%d:%s] unable to find suitable display surface offset due to X-tiling\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1162,10 +1167,11 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, plane_config->size = fb->pitches[0] * aligned_height; drm_dbg_kms(display->drm, - "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); + "[CRTC:%d:%s][PLANE:%d:%s] with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + fb->width, fb->height, fb->format->cpp[0] * 8, + base, fb->pitches[0], plane_config->size); plane_config->fb = intel_fb; } diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 3a474652abaa..8a49d87d9bd9 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -926,6 +926,7 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, bool can_position) { struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_rect *src = &plane_state->uapi.src; struct drm_rect *dst = &plane_state->uapi.dst; @@ -945,7 +946,8 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); if (hscale < 0 || vscale < 0) { drm_dbg_kms(&i915->drm, - "Invalid scaling of plane " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n", + "[PLANE:%d:%s] invalid scaling "DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n", + plane->base.base.id, plane->base.name, DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst)); return -ERANGE; } @@ -960,7 +962,9 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, if (!can_position && plane_state->uapi.visible && !drm_rect_equals(dst, clip)) { - drm_dbg_kms(&i915->drm, "Plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n", + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n", + plane->base.base.id, plane->base.name, DRM_RECT_ARG(dst), DRM_RECT_ARG(clip)); return -EINVAL; } @@ -974,6 +978,7 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) { struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_rect *src = &plane_state->uapi.src; u32 src_x, src_y, src_w, src_h, hsub, vsub; @@ -1029,13 +1034,17 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) hsub = vsub = max(hsub, vsub); if (src_x % hsub || src_w % hsub) { - drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n", + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n", + plane->base.base.id, plane->base.name, src_x, src_w, hsub, str_yes_no(rotated)); return -EINVAL; } if (src_y % vsub || src_h % vsub) { - drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n", + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n", + plane->base.base.id, plane->base.name, src_y, src_h, vsub, str_yes_no(rotated)); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 4cd48d54164d..f31efac89e95 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -92,6 +92,7 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) static int intel_cursor_check_surface(struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); unsigned int rotation = plane_state->hw.rotation; int src_x, src_y; u32 offset; @@ -113,7 +114,8 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) if (src_x != 0 || src_y != 0) { drm_dbg_kms(display->drm, - "Arbitrary cursor panning not supported\n"); + "[PLANE:%d:%s] arbitrary cursor panning not supported\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -144,13 +146,15 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; const struct drm_rect src = plane_state->uapi.src; const struct drm_rect dst = plane_state->uapi.dst; int ret; if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { - drm_dbg_kms(display->drm, "cursor cannot be tiled\n"); + drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -232,6 +236,7 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; int ret; @@ -246,7 +251,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i845_cursor_size_ok(plane_state)) { drm_dbg_kms(display->drm, - "Cursor dimension %dx%d not supported\n", + "[PLANE:%d:%s] cursor dimension %dx%d not supported\n", + plane->base.base.id, plane->base.name, drm_rect_width(&plane_state->uapi.dst), drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; @@ -262,7 +268,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, case 2048: break; default: - drm_dbg_kms(display->drm, "Invalid cursor stride (%u)\n", + drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n", + plane->base.base.id, plane->base.name, fb->pitches[0]); return -EINVAL; } @@ -489,10 +496,11 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i9xx_cursor_size_ok(plane_state)) { - drm_dbg(display->drm, - "Cursor dimension %dx%d not supported\n", - drm_rect_width(&plane_state->uapi.dst), - drm_rect_height(&plane_state->uapi.dst)); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] cursor dimension %dx%d not supported\n", + plane->base.base.id, plane->base.name, + drm_rect_width(&plane_state->uapi.dst), + drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } @@ -502,9 +510,9 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, if (fb->pitches[0] != drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { drm_dbg_kms(display->drm, - "Invalid cursor stride (%u) (cursor width %d)\n", - fb->pitches[0], - drm_rect_width(&plane_state->uapi.dst)); + "[PLANE:%d:%s] invalid cursor stride (%u) (cursor width %d)\n", + plane->base.base.id, plane->base.name, + fb->pitches[0], drm_rect_width(&plane_state->uapi.dst)); return -EINVAL; } @@ -521,7 +529,8 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, if (display->platform.cherryview && pipe == PIPE_C && plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { drm_dbg_kms(display->drm, - "CHV cursor C not allowed to straddle the left screen edge\n"); + "[PLANE:%d:%s] cursor not allowed to straddle the left screen edge\n", + plane->base.base.id, plane->base.name); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a451c46d3795..310899e554d5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4495,9 +4495,9 @@ static int icl_check_nv12_planes(struct intel_atomic_state *state, if (!linked_state) { drm_dbg_kms(&dev_priv->drm, - "Need %d free Y planes for planar YUV\n", + "[CRTC:%d:%s] need %d free Y planes for planar YUV\n", + crtc->base.base.id, crtc->base.name, hweight8(crtc_state->nv12_planes)); - return -EINVAL; } @@ -4512,8 +4512,9 @@ static int icl_check_nv12_planes(struct intel_atomic_state *state, crtc_state->data_rate_y[plane->id]; crtc_state->rel_data_rate[linked->id] = crtc_state->rel_data_rate_y[plane->id]; - drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", - linked->base.name, plane->base.name); + drm_dbg_kms(&dev_priv->drm, "UV plane [PLANE:%d:%s] using [PLANE:%d:%s] as Y plane\n", + plane->base.base.id, plane->base.name, + linked->base.base.id, linked->base.name); /* Copy parameters to slave plane */ linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index f8d3a79a96ff..eb85d3d6cdc3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1706,6 +1706,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; @@ -1715,15 +1716,16 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && intel_fb_is_ccs_modifier(fb->modifier)) { drm_dbg_kms(display->drm, - "RC support only with 0/180 degree rotation (%x)\n", - rotation); + "[PLANE:%d:%s] RC support only with 0/180 degree rotation (%x)\n", + plane->base.base.id, plane->base.name, rotation); return -EINVAL; } if (rotation & DRM_MODE_REFLECT_X && fb->modifier == DRM_FORMAT_MOD_LINEAR) { drm_dbg_kms(display->drm, - "horizontal flip is not supported with linear surface formats\n"); + "[PLANE:%d:%s] horizontal flip is not supported with linear surface formats\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1734,14 +1736,16 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, intel_fb_is_tile4_modifier(fb->modifier) && DISPLAY_VER(display) >= 20) { drm_dbg_kms(display->drm, - "horizontal flip is not supported with tile4 surface formats\n"); + "[PLANE:%d:%s] horizontal flip is not supported with tile4 surface formats\n", + plane->base.base.id, plane->base.name); return -EINVAL; } if (drm_rotation_90_or_270(rotation)) { if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { drm_dbg_kms(display->drm, - "Y/Yf tiling required for 90/270!\n"); + "[PLANE:%d:%s] Y/Yf tiling required for 90/270!\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1765,8 +1769,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: drm_dbg_kms(display->drm, - "Unsupported pixel format %p4cc for 90/270!\n", - &fb->format->format); + "[PLANE:%d:%s] unsupported pixel format %p4cc for 90/270!\n", + plane->base.base.id, plane->base.name, &fb->format->format); return -EINVAL; default: break; @@ -1779,7 +1783,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, fb->modifier != DRM_FORMAT_MOD_LINEAR && fb->modifier != I915_FORMAT_MOD_X_TILED) { drm_dbg_kms(display->drm, - "Y/Yf tiling not supported in IF-ID mode\n"); + "[PLANE:%d:%s] Y/Yf tiling not supported in IF-ID mode\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1788,7 +1793,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && intel_format_is_p01x(fb->format->format)) { drm_dbg_kms(display->drm, - "Source color keying not supported with P01x formats\n"); + "[PLANE:%d:%s] source color keying not supported with P01x formats\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1799,6 +1805,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); int crtc_x = plane_state->uapi.dst.x1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); @@ -1815,7 +1822,8 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s if (DISPLAY_VER(display) == 10 && (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { drm_dbg_kms(display->drm, - "requested plane X %s position %d invalid (valid range %d-%d)\n", + "[PLANE:%d:%s] requested plane X %s position %d invalid (valid range %d-%d)\n", + plane->base.base.id, plane->base.name, crtc_x + crtc_w < 4 ? "end" : "start", crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 4, pipe_src_w - 4); @@ -1828,6 +1836,7 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; @@ -1837,7 +1846,9 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s src_w & 3 && (rotation == DRM_MODE_ROTATE_270 || rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { - drm_dbg_kms(display->drm, "src width must be multiple of 4 for rotated planar YUV\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] src width must be multiple of 4 for rotated planar YUV\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1977,7 +1988,8 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { if (*offset == 0) { drm_dbg_kms(display->drm, - "Unable to find suitable display surface offset due to X-tiling\n"); + "[PLANE:%d:%s] unable to find suitable display surface offset due to X-tiling\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -2010,7 +2022,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) if (w > max_width || w < min_width || h > max_height || h < 1) { drm_dbg_kms(display->drm, - "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", + "[PLANE:%d:%s] requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", + plane->base.base.id, plane->base.name, w, h, min_width, max_width, max_height); return -EINVAL; } @@ -2037,7 +2050,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) if (x != plane_state->view.color_plane[aux_plane].x || y != plane_state->view.color_plane[aux_plane].y) { drm_dbg_kms(display->drm, - "Unable to find suitable display surface offset due to CCS\n"); + "[PLANE:%d:%s] unable to find suitable display surface offset due to CCS\n", + plane->base.base.id, plane->base.name); return -EINVAL; } } @@ -2081,7 +2095,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) /* FIXME not quite sure how/if these apply to the chroma plane */ if (w > max_width || h > max_height) { drm_dbg_kms(display->drm, - "CbCr source size %dx%d too big (limit %dx%d)\n", + "[PLANE:%d:%s] CbCr source size %dx%d too big (limit %dx%d)\n", + plane->base.base.id, plane->base.name, w, h, max_width, max_height); return -EINVAL; } @@ -2115,7 +2130,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (x != plane_state->view.color_plane[ccs_plane].x || y != plane_state->view.color_plane[ccs_plane].y) { drm_dbg_kms(display->drm, - "Unable to find suitable display surface offset due to CCS\n"); + "[PLANE:%d:%s] unable to find suitable display surface offset due to CCS\n", + plane->base.base.id, plane->base.name); return -EINVAL; } } @@ -2899,7 +2915,8 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, if (crtc_state->joiner_pipes) { drm_dbg_kms(display->drm, - "Unsupported joiner configuration for initial FB\n"); + "[CRTC:%d:%s] Unsupported joiner configuration for initial FB\n", + crtc->base.base.id, crtc->base.name); return; } @@ -3036,10 +3053,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, plane_config->size = fb->pitches[0] * aligned_height; drm_dbg_kms(display->drm, - "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); + "[CRTC:%d:%s][PLANE:%d:%s] with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + fb->width, fb->height, fb->format->cpp[0] * 8, + base, fb->pitches[0], plane_config->size); plane_config->fb = intel_fb; return;