From patchwork Thu Feb 6 23:28:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13964083 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC72E23909B for ; Thu, 6 Feb 2025 23:29:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884556; cv=none; b=Vsxv01eLEe41APgHTxTV5bOWH960vXGyR9pscGnU3dhFizvxoyFDei5DZh8wbAThqX2TI3gnwftBnzuFFoY7dY7L7FYqyp+Z8XHuxSbx9ivfb++cAvLb5E29G24KrAQj7LyZB0KfeWNo6cKuKgzMstpSIlu0QmeIGXhxtDyV36I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884556; c=relaxed/simple; bh=s3bIi9NJPl7GvWtItHLAYMBhKKwwbJNGn6/L6WX4Qbc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BmGoaDurryk/37gi0VC3Tpk5SiOaNgMcNhVEqQHNrJznuiZzsMlhZPtAkgwNAVjyzmTc8vQgyHgavYe5tr+FeB1IupBAcLmhrMHW2JTZPY+PB+Izmu1YI+mRHIwKCMRVbbRLQOJiioywQpVRMteG7HGfF6ewaSf2TeoBOOc3HP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=d0eVWQD3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="d0eVWQD3" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 516E4fNY014301 for ; Thu, 6 Feb 2025 23:29:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XzVhPReZf2sVqu2mJY4+qLpMOX5OmiFM5s04YydtgQI=; b=d0eVWQD3ua6HtQp8 9IDZYbBqVXmbreERzwSspr2JPcgwfVaJQNXenZ2/XOYn9h9IAqPB6Mf1OxnOFYDY W7P4iYaQZFyUcBZToaqWhZthTvUbMG8wrZy5xqijINdsZeC8WeygGdmkVulgtEMQ a9TXxcGFqQ+/kNGe5/puZgcoT2B6RdEZZch2MQ4Rlaq1Fl1UGqcrg9jwapco5R0n XcvCd7HiYC4UWquB5UB29P2m71OusRXitKCS9g4cQGx70iQF3LFmAzFEV7DVHauj ivAP7vjZ9/EP6WNnzVqiuOO6DZvSfuZmH07plhoAXPFj6C8G3egjoR5UqRGqKFKI E56KJQ== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44mxhbs9yc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 06 Feb 2025 23:29:13 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-2f83e54432dso4649315a91.2 for ; Thu, 06 Feb 2025 15:29:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738884552; x=1739489352; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XzVhPReZf2sVqu2mJY4+qLpMOX5OmiFM5s04YydtgQI=; b=utB4xNZnfoONV1NitLT/kYT+t3sb+7L0hovzZ3YGVC8ZtouXSs2k+pa4LjR6znOnXW RVhv5FhUv4UajnT+BdhQ1AqCma3f6CUi5I0yPASvVYTYleMkHkdOv7UmFbdSG3fTPs3G JFCiBU7aKBsaeSaGxfGtzixjMgYjSb1XCIeOTlooRsmFeaDwOriuYnAeT33bI+RlxUT7 rLFbgAcUKUxlu/jI8Nznl1spYbnBoDNaKb86K71XGP0nPFjfsraeXyrC2JwX/oZKmV4L cmiA4vGIxEjBnrE0BHv7N2iqjBVFzOTxYILF9TEH6krfVk2QvDRYBiUMzCJz6Zl4i8do hZxg== X-Forwarded-Encrypted: i=1; AJvYcCX2jHzqLh7vLJfv7tO2JFuNxTQGZCADuBmvMZa3YtQV3RQougqGVLuyMLGzotppypSQV/2WKSj2xHQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz0+9O5n+1HFns9b9SdoHw3OXc/yP1rNA4Q9indAjP7eeGa4mHJ /S9R0RFcGYXaIUnB6nJUv7XRyTLs+JJEHXPNpyhKEhkhVhLD9hWKCE9sw9fJWFSxKbmXWfedojq NaGYXOiRTKINO/nW1ItC9NeBLyfU2bPp7e+mjAXh7uc5gHRbUFZziMYeZ8aNfJBwfzb0= X-Gm-Gg: ASbGncvBu+7lu+YJNXZZV0dnFMb9sdtpJXi0fWeRwbuMQ4NNDb648dQ4k3lm/Dz3OPJ fpzy+Hgm0kZucY3H1A8JpRdEWhnx0NNTCW5nPbI03K3w9LlJF7XV6BLX57ffmU3KJm0pNCFaQkB d7SvUuvh5REU+vDd6MZlC+ZYbPXKUjeGQpDuF6kfg2jw3hG9BUx6figpB2EpSzwltSyr6KLxoXV k0aMc945CsF+R3abzy/IETzn3hovYQDk/Xa++3JtGmE3a3wbWqFbWkd5Pq61VWCCZwuW/uts0Vx p33sHc3QbCJtAw9Z89SIc1AoYkY6tUczcFlO+Nat X-Received: by 2002:aa7:88cb:0:b0:725:eacf:cfda with SMTP id d2e1a72fcca58-7305d51bfafmr1883463b3a.17.1738884552140; Thu, 06 Feb 2025 15:29:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IHKUgf9YEV08t4p+ocW2IVUib9sdQwfg4g7HFAwuaqDpN3Hq9K+Kipy5UkLkFmKusvAFsXZzQ== X-Received: by 2002:aa7:88cb:0:b0:725:eacf:cfda with SMTP id d2e1a72fcca58-7305d51bfafmr1883423b3a.17.1738884551746; Thu, 06 Feb 2025 15:29:11 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048ae7f6esm1845905b3a.74.2025.02.06.15.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 15:29:11 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 07 Feb 2025 04:58:56 +0530 Subject: [PATCH v4 1/4] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250207-ecam_v4-v4-1-94b5d5ec5017@oss.qualcomm.com> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> In-Reply-To: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738884540; l=2049; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=s3bIi9NJPl7GvWtItHLAYMBhKKwwbJNGn6/L6WX4Qbc=; b=A6+UFleePIXXF4FhpC6Jr2fEHw1pX8UFKKV22d5aVWXk4TucvDFU0J2PaXvViYDf6Upqnguoo xebRSc2gt1FBu+mKnspdruViK0xkR46WpMKzqX8d6pK0kjbkCuchmmG X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: XA2q4b41mv_IA9NwOqfjAaEkoM5uLW_1 X-Proofpoint-GUID: XA2q4b41mv_IA9NwOqfjAaEkoM5uLW_1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_07,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 mlxlogscore=713 priorityscore=1501 mlxscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060182 PCIe ECAM(Enhanced Configuration Access Mechanism) feature requires maximum of 256MB configuration space. To enable this feature increase configuration space size to 256MB. If the config space is increased, the BAR space needs to be truncated as it resides in the same location. To avoid the bar space truncation move config space, DBI, ELBI, iATU to upper PCIe region and use lower PCIe iregion entirely for BAR region. This depends on the commit: '10ba0854c5e6 ("PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region")' Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0f2caf36910b..64c46221d8bf 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2201,10 +2201,10 @@ wifi: wifi@17a10040 { pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + <4 0x00000000 0 0xf1d>, + <4 0x00000f20 0 0xa8>, + <4 0x10000000 0 0x1000>, + <4 0x00000000 0 0x10000000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; @@ -2215,8 +2215,8 @@ pcie1: pcie@1c08000 { #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40000000 0x0 0x100000>, + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>; interrupts = , , From patchwork Thu Feb 6 23:28:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13964084 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5263023AE71 for ; Thu, 6 Feb 2025 23:29:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884564; cv=none; b=j/pCgdPAdwYzR4Iof0SBUxEPXdTB/t0fsfP49IMykssyrqOqm64ugzthtCe5JkEb07MZhohONLH/kRxkBk4MTjwsy4riviu3gFxNVzR6zCH8jS+abZqFfhZeSM00EJYa+zmBn/oXJjjHv7Gxv+KCJqRX9+qdarGdHlNos/30LeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884564; c=relaxed/simple; bh=uY93T0yUB36H70prew0kSW+OhiMEx+NY8OCEPWlQkBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Eqbmb6iKstRKX4ZFx20nwjlaCrcGcjVzT2weT6vXzmOs2j47LVOPz/hWeWFPZKjrKadDLP/+457l6XaAXeJw5wPUDcUKeFbGEfoHEAJf3cpXKVVbJ4mWsDbEqk1M0ylCevtx9WW5v+zYgWNaWaET6FXikU/vNE9BvfLADGPvT74= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=TAIHOo7T; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="TAIHOo7T" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 516C14iT012878 for ; Thu, 6 Feb 2025 23:29:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 6pWXiIdrgRFwUyrRZilnZJMRSt5DtiWHnfUqWM5BgNo=; b=TAIHOo7TGZfFO2cC HwPsTdUzwmGm3WsBOMp5fEelQzItkoKd/+nwC9HrrEKPn07BWhvp7WA21jTSa1yP gfxzOu8Afbd8yuV7FxEXYC2iXKzWrRAwWx+8QCxJcKb/lfP9jphwVEEz8/Vs4mDm Z/+cluCuueQ+a5OQEfEgu4TlT9q1kwhPuM4TKw49+WDrSjkS4cDOd8SUqfVxUCt6 zFSUEz6e0iVOaHAoZdbaUfp6HTVOdcolLV0Yfi/asN9cKqzI1bYlYzqXjjQ+5aT7 L53I7A/s/85AKbNS8BTjJC0dmf9qpWjmwBZinwcViJETZtbuuKRFZZtPuCrjlyZ6 bJQPDw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44mu6f1ta8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 06 Feb 2025 23:29:20 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-2fa05b7f858so2435647a91.0 for ; Thu, 06 Feb 2025 15:29:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738884558; x=1739489358; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6pWXiIdrgRFwUyrRZilnZJMRSt5DtiWHnfUqWM5BgNo=; b=qR0ci/O2IvNWG7E+dCZI6/E/CcWG6ipGcQm2+fllgWVxy5sbJkOJU9NH2wU2jdWyEl whyqWpVuE8OE2YaTg1zCv2xOGpxG6TdbYzl4got1kF2zX2FECb65TmaI1A+KW45mk1fN kjUStkFU/here01zwBT6k2SVK0B4akTyFCfX2DnAMAFsouE1mz3UyNCXcarRHVoPP7LT y6hUahD2Z6OdJM2q1k2GRA5emyBrHZhoScnDw4c7rEukWRekxL1J4k6AEdJ/8/78btIy +MiZuME0+HV5Z88bY3M4G77DiBHCuXDRcjZlp7HNFSMz5fF32vZWImn+X2wz1RbaJGxK vehQ== X-Forwarded-Encrypted: i=1; AJvYcCVwRa4JQIFA8bcu0KP6wwCte7bIFIDxCIxuj9fqRhbsS59x9dfI0nUKc/fQbOVl5yMkV+l4rXrEWr8=@vger.kernel.org X-Gm-Message-State: AOJu0YzMqJUphzxJ8j1N+MpTgH+/oIC8PY1n8s1EPQvAU/yaCb2NE0am ws25GT+mwGoMpQ2oGZgXZfnxtQ3lmhj0ojO7fRLOJaK2WThK2jQA/STL4/767NSV5mB9dmfS1Lk tCSYRXuoMF1yrN74gkfTIVICc8bnajbDIX22NEyw5XL6OIxFq90CnT5msRbmfCBVhvW4= X-Gm-Gg: ASbGncv0FY/WtSvRK5BguwYmRZ2gN6q4lnIU+hSUv+i4fsZQUH6ypxRq8it0N6mS8oV AxvITPqpqBlDFYnU8rvmA8gBBRPdoaQTEVgBuBGm90vWcHw7umryImHKRoowD/EfMYYqc36Irx3 3Ldbdyz/4LgRTNAIU5RKeBXFn6X7h73jtIFWDPjSqci9qJI8oGzZwNozxgNrxNfYPEuJ9Tw86Up 3r81ovBVfggnnGINrKd0SU4cLAf+Gqh8ZsgxKNGpFKimSfu3K8ByFM+8+EDq0E9sEl3iSMq3DIV H6aK5UJJvDm4R/vpF5roV6DOneVB0fAKctkpVeHg X-Received: by 2002:a05:6a00:909c:b0:725:4915:c0f with SMTP id d2e1a72fcca58-7305e504eaemr1346619b3a.11.1738884557756; Thu, 06 Feb 2025 15:29:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMlmubEM1tEV5w3QDKomU/ar27dKIKjLKn2kUcyPtPqM/HtBAHBYpz6Ib8q/iljUxg+UQO9g== X-Received: by 2002:a05:6a00:909c:b0:725:4915:c0f with SMTP id d2e1a72fcca58-7305e504eaemr1346564b3a.11.1738884557236; Thu, 06 Feb 2025 15:29:17 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048ae7f6esm1845905b3a.74.2025.02.06.15.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 15:29:16 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 07 Feb 2025 04:58:57 +0530 Subject: [PATCH v4 2/4] PCI: dwc: Add ECAM support with iATU configuration Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250207-ecam_v4-v4-2-94b5d5ec5017@oss.qualcomm.com> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> In-Reply-To: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738884540; l=10051; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=uY93T0yUB36H70prew0kSW+OhiMEx+NY8OCEPWlQkBg=; b=x8v0r/PRJSutajaFkl4I4fDV+YJ/r+2X/QfChZezxn1QueqE+L59BVSRoHVGCckak7ikUT6EB RK6pnuh4nuRCiLvQ48+sKJjpFyEXCjyvJyCgMMHGrJjKv/2o/ijEvY0 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: VMe7vCS3vOGBSMA1htVHja9ZVp25s8LU X-Proofpoint-ORIG-GUID: VMe7vCS3vOGBSMA1htVHja9ZVp25s8LU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_07,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060182 The current implementation requires iATU for every configuration space access which increases latency & cpu utilization. Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, which shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12]of the translated address. Configuring iATU in config shift feature enables ECAM feature to access the config space, which avoids iATU configuration for every config access. Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. As DBI comes under config space, this avoids remapping of DBI space separately. Instead, it uses the mapped config space address returned from ECAM initialization. Change the order of dw_pcie_get_resources() execution to achieve this. Enable the ECAM feature if the config space size is equal to size required to represent number of buses in the bus range property, add a function which checks this. The DWC glue drivers uses this function and decide to enable ECAM mode or not. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 133 +++++++++++++++++++--- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 11 ++ 4 files changed, 132 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..73c3aed6b60a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -9,6 +9,7 @@ config PCIE_DW config PCIE_DW_HOST bool select PCIE_DW + select PCI_HOST_COMMON config PCIE_DW_EP bool diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index ffaded8f2df7..826ff9338646 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,66 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) } } +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = {0}; + resource_size_t bus_range_max; + struct resource_entry *bus; + int ret; + + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + + /* + * Root bus under the host bridge doesn't require any iATU configuration + * as DBI space will represent Root bus configuration space. + * Immediate bus under Root Bus, needs type 0 iATU configuration and + * remaining buses need type 1 iATU configuration. + */ + atu.index = 0; + atu.type = PCIE_ATU_TYPE_CFG0; + atu.cpu_addr = pp->cfg0_base + SZ_1M; + atu.size = SZ_1M; + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + ret = dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + bus_range_max = resource_size(bus->res); + + if (bus_range_max < 2) + return 0; + + /* Configure remaining buses in type 1 iATU configuration */ + atu.index = 1; + atu.type = PCIE_ATU_TYPE_CFG1; + atu.cpu_addr = pp->cfg0_base + SZ_2M; + atu.size = (SZ_1M * (bus_range_max - 2)); + atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + + return dw_pcie_prog_outbound_atu(pci, &atu); +} + +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resource *res) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + struct resource_entry *bus; + + bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pp->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pp->cfg)) + return PTR_ERR(pp->cfg); + + pci->dbi_base = pp->cfg->win; + pci->dbi_phys_addr = res->start; + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -431,10 +491,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) raw_spin_lock_init(&pp->lock); - ret = dw_pcie_get_resources(pci); - if (ret) - return ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (!res) { dev_err(dev, "Missing \"config\" reg space\n"); @@ -444,9 +500,28 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->cfg0_size = resource_size(res); pp->cfg0_base = res->start; - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); + if (pp->ecam_mode) { + ret = dw_pcie_create_ecam_window(pp, res); + if (ret) + return ret; + + bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->sysdata = pp->cfg; + pp->cfg->priv = pp; + } else { + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; + bridge->sysdata = pp; + } + + ret = dw_pcie_get_resources(pci); + if (ret) + return ret; bridge = devm_pci_alloc_host_bridge(dev, 0); if (!bridge) @@ -462,14 +537,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base = pci_pio_to_address(win->res->start); } - /* Set default bus ops */ - bridge->ops = &dw_pcie_ops; - bridge->child_ops = &dw_child_pcie_ops; - if (pp->ops->init) { ret = pp->ops->init(pp); if (ret) - return ret; + goto err_free_ecam; } if (pci_msi_enabled()) { @@ -504,6 +575,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pp->ecam_mode) { + ret = dw_pcie_config_ecam_iatu(pp); + if (ret) { + dev_err(dev, "Failed to confuure iATU\n"); + goto err_free_msi; + } + } + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -539,8 +618,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); - bridge->sysdata = pp; - ret = pci_host_probe(bridge); if (ret) goto err_stop_link; @@ -564,6 +641,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); +err_free_ecam: + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_host_init); @@ -584,6 +665,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); + + if (pp->cfg) + pci_ecam_free(pp->cfg); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); @@ -999,3 +1083,24 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci) return ret; } EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); + +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct platform_device *pdev = to_platform_device(pci->dev); + struct resource *config_res, *bus_range; + u64 bus_config_space_count; + + bus_range = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; + if (!bus_range) + return false; + + config_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + if (!config_res) + return false; + + bus_config_space_count = resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; + + return !!(bus_config_space_count >= resource_size(bus_range)); +} +EXPORT_SYMBOL_GPL(dw_pcie_ecam_supported); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..523ca7f267fb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -509,7 +509,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - val = PCIE_ATU_ENABLE; + val = PCIE_ATU_ENABLE | atu->ctrl2; if (atu->type == PCIE_ATU_TYPE_MSG) { /* The data-less messages only for now */ val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 501d9ddfea16..d0ba8855ba2a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -171,6 +172,7 @@ #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 @@ -343,6 +345,7 @@ struct dw_pcie_ob_atu_cfg { u8 func_no; u8 code; u8 routing; + u32 ctrl2; u64 cpu_addr; u64 pci_addr; u64 size; @@ -381,6 +384,8 @@ struct dw_pcie_rp { int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; + bool ecam_mode; + struct pci_config_window *cfg; }; struct dw_pcie_ep_ops { @@ -686,6 +691,7 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp); int dw_pcie_allocate_domains(struct dw_pcie_rp *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp); #else static inline int dw_pcie_suspend_noirq(struct dw_pcie *pci) { @@ -726,6 +732,11 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static inline bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp) +{ + return 0; +} #endif #ifdef CONFIG_PCIE_DW_EP From patchwork Thu Feb 6 23:28:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13964085 X-Patchwork-Delegate: kw@linux.com Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CA7323AE90 for ; Thu, 6 Feb 2025 23:29:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884567; cv=none; b=d30WX19xsyYyn4N1E76cmbFzBtZ4izYg+FdafBmosmiuHKilOKeW/6YWLsdl50P6OjAQTZANJOgEz915KdrGEeFUMDIz4pjaBhMzdPKMxkMm17fdcb45hNUc6tY/PgEMtpIYYk6yhRRTDbDx/RxbkqwHhWRiw6BpX44ELvkZHPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884567; c=relaxed/simple; bh=SWWzA0HUJcFMbO1HqY5NCoLambaGtXZLJb30DVpO5fc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T5XbB1ddfTro41ugHjHktoU/Fs+SJxtFOO3DqZoKf7M4pnq/LqhVSdOZeGx1gFtrOYTvQBWooqSsYZqljiCVS2bVDOoUQ/x74fw7rYPW8+dzlGBbXCo9XOKSD5midIE28azqLxZrUyRd89sVfwmu9bV5mBLIQrZusn8x8g3T6mo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=SNEWzWhx; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="SNEWzWhx" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 516GrTUv019088 for ; Thu, 6 Feb 2025 23:29:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Z9b6+uWWlNVG1bR8nFXu1gMB9eppc8z9TSDppb/TGM4=; b=SNEWzWhxO+rHsHyP Duo7tdcMQ/jk1YS6ihmrXhXDoqm8VHhX4qQt4OtegyOSEwmI1+pM2Ut8JkCKlTTb 557+iRiiDU0ZTW3izl1fUM+0z6NypsCpjo+ikQJWbNtLG0THcqv1N5XIdxnXyxCZ +2pDUu+o9u/j5m4cbFiiiIFCqyo+N2+CXBDThkdDCC4CARolROtAPiqfqPE5y9SC K3GreRs0rsdyEkFb/owO0+lHtm4JvzMXI7odsGI/GkmJ6eaJugVfnKV8fmbQkAQ0 6TpikZaeQCqOoJI3jEZR8nhcAl7hMfY+nbIuLwnZ8iqalLMznyccHTHxswtNYZgc yDAPhQ== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44n10h0vfu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 06 Feb 2025 23:29:25 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2163dc0f689so47240435ad.1 for ; Thu, 06 Feb 2025 15:29:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738884564; x=1739489364; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z9b6+uWWlNVG1bR8nFXu1gMB9eppc8z9TSDppb/TGM4=; b=HsXa9kLoiAKy7EPI3tomFIpUzxeT+fCM8FTLR9hDth3EStWLyvSzzzieIGCE2bLYRj piUd+kMqy93e3BG1816R+4JD0/ZU2MMdocKgiCUO2LPHhhgxKuNpu1wkA7pwCwaQoJK1 nWZAyTU2iXxp9ffJc1pCa2BOeX+IvSH2cOx5X6Emec8ldzn7szudl/NoUhd06ko6mIfs yLnq6AO4RJrGzKzTSpv4Gfo9MqAxmF3DgRxkbm6ntJr1Lvr/pGxtt9wW85+kpww3f+nu Xt6Ga/ws3JqnlqVWcEnXwFd+c5c2uwdLuIz4+Gj10SEYDPNdH+Q1/KhwKCf9bCSVg6lU sgBA== X-Forwarded-Encrypted: i=1; AJvYcCWtnHb3rWMclPixpxNRq9tLx1JoNK9qrLGg802TVS/L99jG76dB7pGzokFBzInjfmvDZQB5XvzSOjY=@vger.kernel.org X-Gm-Message-State: AOJu0YwQuHLgeMwa7QPOw4Ck7hn2tvwXGrtspFjppGpxEkpyXrharkF3 uVT4ws30GzF1r7/kIJosMQxmMAbuy2j0vGPLvqr+HhpM2NAVMSuBLjL9NcaeIQUrqRePrTV/al+ Tb1OWTa1JY3+kf7r3tegZcbjRUjQ/jFJjqsvL8dCUl0I6OSfSwLWnDaTEXnZStUKx4Gc= X-Gm-Gg: ASbGncs00HfRYgKZBnF1hyJOV6DvEh1UbN4lfiwTVLLfn4c1IDyaoTQw8cPXpNbD9+d JXBcRqOEr31n+ioAHQks70wJLkf8h9zlEkf2ahezpjmqFkgAd3NTBg23qmtXbpkYxKAUSaGnK25 EgEWEG6FjWxyyU2EVI2mpGD4EUO394zlw4YnjzShXaa6Rvyt1pO208trbOjq65VXeHRaJZ8S/Yc nbTiw2yKtu7+JRjJDOMVzQVJvGiBptcbN5CuKUC1lfdc4GdbZaw22iTkfGmKh6p0qPqsZpxb3iv ULWWAqXTX/8E9qYgT03aiykdOba9JEm447Qu/Zhj X-Received: by 2002:a05:6a21:7101:b0:1ed:e2bc:5c9 with SMTP id adf61e73a8af0-1ee03b71f2emr2037056637.38.1738884564535; Thu, 06 Feb 2025 15:29:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVvvYMobydfHRdWhzMPIv8JZmHyxD+Mh3A0E5Fwkz+JeyDtuYL5YSOAi+LGBdODS/8LGwWcw== X-Received: by 2002:a05:6a21:7101:b0:1ed:e2bc:5c9 with SMTP id adf61e73a8af0-1ee03b71f2emr2036920637.38.1738884562752; Thu, 06 Feb 2025 15:29:22 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048ae7f6esm1845905b3a.74.2025.02.06.15.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 15:29:22 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 07 Feb 2025 04:58:58 +0530 Subject: [PATCH v4 3/4] PCI: dwc: Reduce DT reads by allocating host bridge via DWC glue driver Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250207-ecam_v4-v4-3-94b5d5ec5017@oss.qualcomm.com> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> In-Reply-To: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738884540; l=1728; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=SWWzA0HUJcFMbO1HqY5NCoLambaGtXZLJb30DVpO5fc=; b=fZyiGh+iMPqdX/K4h9jdTW+5zikUfOPuZjl5KcMx85+JOe7+rbVN381UpyvurlnEV16UJ7VQd jDdcMRo+q70DPlgYt791jj0Frlgw0Nhyo/Av/N0hwH9New5yG8qcNw9 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: lAFsEkM9N9TpRqyyha61nUUwRRassB-X X-Proofpoint-ORIG-GUID: lAFsEkM9N9TpRqyyha61nUUwRRassB-X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_07,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 mlxlogscore=930 lowpriorityscore=0 adultscore=0 bulkscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060182 dw_pcie_ecam_supported() needs to read bus-range to find the maximum bus range value. The devm_pci_alloc_host_bridge() is already reading bus range and storing it in host bridge.If devm_pci_alloc_host_bridge() moved to start of the controller probe, the dt reading can be avoided and use values stored in the host bridge. Allow DWC glue drivers to allocate the host bridge, avoiding redundant device tree reads primarily in dw_pcie_ecam_supported(). Suggested-by: Bjorn Helgaas Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 826ff9338646..a18cb1e411e4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -484,8 +484,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct device *dev = pci->dev; struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); + struct pci_host_bridge *bridge = pp->bridge; struct resource_entry *win; - struct pci_host_bridge *bridge; struct resource *res; int ret; @@ -527,7 +527,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (!bridge) return -ENOMEM; - pp->bridge = bridge; + if (!pp->bridge) { + bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return -ENOMEM; + pp->bridge = bridge; + } /* Get the I/O range from DT */ win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); From patchwork Thu Feb 6 23:28:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13964086 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D47F23909E for ; Thu, 6 Feb 2025 23:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884572; cv=none; b=c29blf1y1AcnXabHrV1IXG5KuYZPuK89+5KuOHcDbhaYdG9v40M0UCO3YEp0SelyUrIGVrVCoAzw/GSirOvsfo5yZ2Fl0H8/BcwMAk+4pfGFmCIPu6AieT4z2hmtCPmkk/QLaghfuDYyMECM6JJzcX5JO7dgV0MHBe0POnLvbJU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738884572; c=relaxed/simple; bh=BgNsZ2EhBxd/BSWpqXyZykgbwBhLSUsbRTbb1BSQdUc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m8ZtewGtYBhhbxMZZigkv3EfbOR3eBsBVIudmMFVyWVB8UXFzxv6TpQYEjWcGqQdeIG8OwT0FKPj7r04++y0dGA4z1q0F5VDzOdHn2yyzNaEgfGdoF4j/tiMeA02yonpRrl3ioyZO6/rfwxc1BGy/64YxD5xtHy7Zdea8rHYUMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NfNNVWdA; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NfNNVWdA" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 516ELgTi017417 for ; Thu, 6 Feb 2025 23:29:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= U+bqz9EHeHzQ2Pjn9rG9487ONwiuzpgqIzdaaOh917I=; b=NfNNVWdAWoboHRnz +N4Zg7BpQUG/peh4iVo+XwQBbLfrD09C+v0ZykMi8vDnNRVjss7p2gl+XKRcMKQ7 CuVuRYIXCYcxZcvhsJOTqDceuWVfI4GuXFWg+ddPnZtiCQxR7LQ4mrT5sRV306gO kbrBrvXpiHP6T3LBuec+ikVUmIiH2fHQTKPvHkYlJ7PDZJUNVTw+mM/eW+bXLobQ r6JYDxbCVPXhzeU8Xq5j8BM07UOt04ljxdtcPgml3WGQXHqoXStRaFGEkzl2OARQ Xy4u7aNv6E92mTlv+3HniBmlLNxbb02SjIXznACPURSLjRaXujwqeP+R9bKFdWmk Gr0yLQ== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44mxsc17wj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 06 Feb 2025 23:29:30 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-2fa11d8e448so3256115a91.0 for ; Thu, 06 Feb 2025 15:29:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738884569; x=1739489369; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U+bqz9EHeHzQ2Pjn9rG9487ONwiuzpgqIzdaaOh917I=; b=u8d7XGFIhmlBlDtJzGL4Qkbgwmby66kO+vSDTRmIAVL1G/i5p0+ppYbyQbGW8tteDb UF/PHNXmcm9eTOqBJHrJZbGzFeKqytKr0J2HMm0Pl3pzDp5scW7K6E5e1/+0KfXPsXeo rZezuCZ3LXX8PXlevwuhU9HUMhBzQvccqo6Io10lDPcm+zE3KLJGzshDicbNbINnHGD9 L+XQOA+ftDvLGAHOEw/Idg5W+Smv9fQXr7Uabb84tgf1R9EalqjkmqZmfjLXezs8R96d kqBs/rVvyi8/cYwPBmddicQbw8aTpCuDYSUnHuK0w9MAmiK6lhTwO51mCMpsEWtQwAc8 V6sg== X-Forwarded-Encrypted: i=1; AJvYcCX4dpidvsP3yOhxr2cIEICf8PR4OC4k+PoINFaK0ZTzdpXZPxAi0R1T84ZOuXtrUr1RMiHRALiAD0Q=@vger.kernel.org X-Gm-Message-State: AOJu0YxXLBlHYM0LZGKE+nAGuo+jyYHd3iDyAcu5Nq6jPDPmRKIaqzpZ 8R/JZPnCiQUgSqbLPPBUFYrDPu6MeKAD+EWKTcope+/z6Gv7HvHfnIEt51QVsEwBSxHey94UFTD Rfxd48pH1KuEJpqn5DggGeRTzkm9ZB+etA9Zl1osAd6Mx/VQ+NjRN3PNmfF7o0azT1wY= X-Gm-Gg: ASbGncvRfLd3XQbRNQMfW6s/OqmBO8C5O1BREMRLf839mSwoUJxKBkPA94Fl8GdjDKk opxt8+NTX9jzEUBpjpQ9bzRrior4vkLhSsrXvJXvSOe4IH/3gocN5J1YTQ8scPYEJ4iH/O5vlf5 NnDWPRgVuelpZt8J1/ILdy0yxaPtKHn8nW1YnIsIl90I3FTqvz/1v8EH2x5YpzF3+U4i8Js3UCw wWqKgmBpDRPiYn5NdzAKt4xKmr25mJ12s/U5kUkBBkqzm2TShnMG+tsflSq0e0uGq+PkV403FRY j4S/hbGZ9r2c3HmFnEbsUoDRRdtESFUHUp29NKaT X-Received: by 2002:a05:6a00:4303:b0:72a:83ec:b16e with SMTP id d2e1a72fcca58-7305d53a58fmr1438936b3a.21.1738884568601; Thu, 06 Feb 2025 15:29:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IE1nJAHgxkAN6yu/cuiRuyEu57hBwAYKzGaS3dQQShr42srddHjkm9PXWcqaHXZhbVEMDlPig== X-Received: by 2002:a05:6a00:4303:b0:72a:83ec:b16e with SMTP id d2e1a72fcca58-7305d53a58fmr1438906b3a.21.1738884568240; Thu, 06 Feb 2025 15:29:28 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048ae7f6esm1845905b3a.74.2025.02.06.15.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 15:29:27 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 07 Feb 2025 04:58:59 +0530 Subject: [PATCH v4 4/4] PCI: qcom: Enable ECAM feature Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250207-ecam_v4-v4-4-94b5d5ec5017@oss.qualcomm.com> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> In-Reply-To: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738884540; l=6070; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=BgNsZ2EhBxd/BSWpqXyZykgbwBhLSUsbRTbb1BSQdUc=; b=LUuYaHAwc2zakqylAGfB988VMwU6n8H9p/Go6NO2jnuQGQwnPr1ZV2j/g3cwoTXFzmrXapBWG 5rIWwjQ4XseBpCb7AXnc0WZ9i67sgP/RrbMPxDYSABKTH+VjaJLT5im X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: q5eb0K-RUiz95MZXCZFoJrVUufoEa4u2 X-Proofpoint-GUID: q5eb0K-RUiz95MZXCZFoJrVUufoEa4u2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_07,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 phishscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060182 The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register gives us the offset from which ELBI starts. so use this offset and cfg win to map these regions instead of doing the ioremap again. On root bus, we have only the root port. Any access other than that should not go out of the link and should return all F's. Since the iATU is configured for the buses which starts after root bus, block the transactions starting from function 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going outside the link through ECAM blocker through PARF registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e4d3366ead1f..84297b308e7e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -52,6 +52,7 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_SLV_DBI_ELBI 0x1b4 #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c @@ -61,6 +62,17 @@ #define PARF_DBI_BASE_ADDR_V2_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c +#define PARF_ECAM_BASE 0x380 +#define PARF_ECAM_BASE_HI 0x384 + #define PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 @@ -84,6 +96,7 @@ /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define PCIE_ECAM_BLOCKER_EN BIT(26) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -294,6 +307,44 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u64 addr, addr_end; + u32 val; + + /* Set the ECAM base */ + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); + + /* + * The only device on root bus is the Root Port. Any access other than that + * should not go out of the link and should return all F's. Since the iATU + * is configured for the buses which starts after root bus, block the transactions + * starting from function 1 of the root bus to the end of the root bus (i.e from + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. + */ + addr = pci->dbi_phys_addr + SZ_4K; + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); + + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); + + addr_end = pci->dbi_phys_addr + SZ_1M - 1; + + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); + + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); + + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL); + val |= PCIE_ECAM_BLOCKER_EN; + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); +} + static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); @@ -303,6 +354,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) qcom_pcie_common_set_16gt_lane_margining(pci); } + if (pci->pp.ecam_mode) + qcom_pci_config_ecam(&pci->pp); + /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) pcie->cfg->ops->ltssm_enable(pcie); @@ -1233,6 +1287,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie = to_qcom_pcie(pci); + u16 offset; int ret; qcom_ep_reset_assert(pcie); @@ -1241,6 +1296,11 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; + if (pp->ecam_mode) { + offset = readl(pcie->parf + PARF_SLV_DBI_ELBI); + pcie->elbi = pci->dbi_base + offset; + } + ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); if (ret) goto err_deinit; @@ -1615,6 +1675,13 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->ops = &dw_pcie_ops; pp = &pci->pp; + pp->bridge = devm_pci_alloc_host_bridge(dev, 0); + if (!pp->bridge) { + ret = -ENOMEM; + goto err_pm_runtime_put; + } + + pci->pp.ecam_mode = dw_pcie_ecam_supported(pp); pcie->pci = pci; pcie->cfg = pcie_cfg; @@ -1631,10 +1698,12 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); - if (IS_ERR(pcie->elbi)) { - ret = PTR_ERR(pcie->elbi); - goto err_pm_runtime_put; + if (!pp->ecam_mode) { + pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(pcie->elbi)) { + ret = PTR_ERR(pcie->elbi); + goto err_pm_runtime_put; + } } /* MHI region is optional */