From patchwork Fri Feb 7 22:31:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0CB6C0219D for ; Fri, 7 Feb 2025 22:34:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8652010E07F; Fri, 7 Feb 2025 22:34:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="egFDbnRz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 351D510EBB5; Fri, 7 Feb 2025 22:32:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738967525; x=1770503525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G3N2aomj3u4LY8OYi5XSbWS2TnTroo52D5J5TjF/Gt4=; b=egFDbnRzQNTOzks5/lkuqueJ3sYY7BB+4udZblejek98u4gTvIUUYy2r n9R8MQw2lJtOKnTpjpjLtH3PEiZiuqYooJEbOlfqa8Mp67YziZru/8IIT bFmqtZPmDhPGLfkJLSdvMWdXV0gBASAUMriRefp2iXFxVZ23xINxrH6iU OWFZYFFMyEqO8VIXksV/y4EC3Ld6Xg4cXktDJOQ4E3JZ2skimHl7e8esa VhEo8ZVCRUgCaitGJ7UigrNDWcvXr9STHYHvHPMSp3NGOXF3KYOFxN9r/ 02v/Intm6GiPjZCD88D+Q3NBHufloRLxIiLKriain1j3YNAsu3iuGZH1W A==; X-CSE-ConnectionGUID: qLmvRRfjQgWWpnrMmVakMw== X-CSE-MsgGUID: PpXOeQ6bRJmY407enM4fjw== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313389" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313389" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:05 -0800 X-CSE-ConnectionGUID: BOZwU7SjSsKgoImBJAjcIg== X-CSE-MsgGUID: lGTaA89sTfO+Azy7HjbrIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857412" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:03 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:02 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 1/8] drm/i915/dsb: Move the +1 usec adjustment into dsb_wait_usec() Date: Sat, 8 Feb 2025 00:31:52 +0200 Message-ID: <20250207223159.14132-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The "wait usec" DSB command doesn't quite seem to able to guarantee that it always waits at least the specified amount of usecs. Some of that could be just because it supposedly just does some kind of dumb timestamp comparison internally. But I also see cases where two hardware timestamps sampled on each side of the "wait usec" command come out one less than expected. So it looks like we always need at least a +1 to guarantee that we never wait less than specified. Always apply that adjustment in dsb_wait_usec(). Signed-off-by: Ville Syrjälä Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dsb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2f2812c23972..f8bd6fad0c87 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -369,7 +369,8 @@ void intel_dsb_interrupt(struct intel_dsb *dsb) void intel_dsb_wait_usec(struct intel_dsb *dsb, int count) { - intel_dsb_emit(dsb, count, + /* +1 to make sure we never wait less time than asked for */ + intel_dsb_emit(dsb, count + 1, DSB_OPCODE_WAIT_USEC << DSB_OPCODE_SHIFT); } @@ -622,7 +623,7 @@ void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state = intel_pre_commit_crtc_state(state, crtc); int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode, - dsb_vblank_delay(state, crtc)) + 1; + dsb_vblank_delay(state, crtc)); intel_dsb_wait_usec(dsb, usecs); } From patchwork Fri Feb 7 22:31:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B985CC021A0 for ; Fri, 7 Feb 2025 22:43:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F13610E329; Fri, 7 Feb 2025 22:43:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YG+ERrVs"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4077210EBB5; Fri, 7 Feb 2025 22:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738967528; x=1770503528; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CiYDqRbDpZj0WVl/5dvtRuCDXypfjRvSK/E/TE+p6vo=; b=YG+ERrVsstT3g2SEzI+hnJH/GSyDuspafwoXx/O74t0fuaD4oMHt2Zkq IiQBIwOphEao55ZSKGj5SXp9Z8SUCf7ZNUhaLm+iXgTka+crqzVnw/xUV jIdsBaMimcbI4lHkr3SeubYJl3x1Z67Kb/7qLRtjfDOBm9ae1+12I0Mrx veTT9HDbScdFTR6CyVtL6e2WYAuEvbILFuvtWdiQtvoHzvnOFqykHZFBp 9AEYDmc5+QJnoFOSkjkiGw3epHmwNy7aSr5fxA4QWzFzpa3IMC5MAIrbp Gv4koYysb+qmcEboMt+Y51eilmdPxcGPwV5obUN3K7qeXTbB1Jq/3JAY5 A==; X-CSE-ConnectionGUID: h8kIQTHJRPO17Q9sysiklA== X-CSE-MsgGUID: /37M87x2Reihf/tfzKDMmw== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313391" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313391" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:08 -0800 X-CSE-ConnectionGUID: cyVI0OpZQ9y7fOmtnvaoZQ== X-CSE-MsgGUID: wrhzstmfQpqDjyLLAs6gXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857421" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:06 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:05 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 2/8] drm/i915/vrr: Don't send push for legacy cursor updates Date: Sat, 8 Feb 2025 00:31:53 +0200 Message-ID: <20250207223159.14132-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We don't really want legacy cursor updates to trigger VRR pushes because these can happen willy nilly and we generally want more precise control over the pushes. The fastpath in intel_legacy_cursor_update() doesn't send pushes, but if we punt to the full commit path (with the flip completion short circuited) we are currently sending pushes. Skip those as well so that they don't interfere with the push handling from normal commits. Signed-off-by: Ville Syrjälä Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index e69b28779ac5..8fa3e64d4d52 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -714,7 +714,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, * which would cause the next frame to terminate already at vmin * vblank start instead of vmax vblank start. */ - intel_vrr_send_push(NULL, new_crtc_state); + if (!state->base.legacy_cursor_update) + intel_vrr_send_push(NULL, new_crtc_state); local_irq_enable(); From patchwork Fri Feb 7 22:31:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA40CC021A0 for ; Fri, 7 Feb 2025 22:41:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EC0D10EBBD; Fri, 7 Feb 2025 22:41:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mysZSI/l"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E6A010EBB7; Fri, 7 Feb 2025 22:32:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738967531; x=1770503531; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rCR70x35t9u4TUJihRyUiWzkX1087HffuOo97SMskkQ=; b=mysZSI/lCx0ZMrvZpLY3t4p+1o9pleEMCfatyfGQJL5UT1CdTz+VJlqw HZDGqm3xEVVMBw3/FOl9j+6bCTgieSOlF5U6XPGhyUdM7nshtQEdztrr4 Ctui66UzFEBzP4u+omnaFfyzwzux95VYUKIoqUNhteG1JoL8LkWhvo6Gu 1cPwA4Pd6Uvmoc+FAkJFUiBuvTbHzOkDyKEjPR1RlMtGOnrh/hGYJZq5s G57hoD4H3cvUIpetHCrhVCkpV5lSEfMxJupDGyxDFN+ASWn2zNWs7vzB4 4MbSA+pjhbyRKEBJze/D/hLKKdsfm74LSrr4xfza92PoudERzYLwwJnP3 w==; X-CSE-ConnectionGUID: RMrRvZUtTomlIqPLoFzZxQ== X-CSE-MsgGUID: fQXee6ixRf+M9ZMluw4AGg== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313394" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313394" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:11 -0800 X-CSE-ConnectionGUID: BwTXa+WJQxu4HeyAA081Sw== X-CSE-MsgGUID: BhqBGan0SVaZk4m+6i6VqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857428" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:09 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:08 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 3/8] drm/i915/vrr: Account for TRANS_PUSH delay Date: Sat, 8 Feb 2025 00:31:54 +0200 Message-ID: <20250207223159.14132-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä When we send a push during vblank the TRANS_PUSH write happens at some point during a scanline, and the hardware picks it up on the next scanline. Thus there is up to one extra scanline of delay between the TRANS_PUSH write and the delayed vblank triggering. Account for that during intel_dsb_wait_vblank_delay() so that we are guaranteed to be past the delayed vblank before we trigger the completion interrupt for the commit. Signed-off-by: Ville Syrjälä Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dsb.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index f8bd6fad0c87..01e3bd385cac 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -116,7 +116,13 @@ static int dsb_vblank_delay(struct intel_atomic_state *state, intel_pre_commit_crtc_state(state, crtc); if (pre_commit_is_vrr_active(state, crtc)) - return intel_vrr_vblank_delay(crtc_state); + /* + * When the push is sent during vblank it will trigger + * on the next scanline, hence we have up to one extra + * scanline until the delayed vblank occurs after + * TRANS_PUSH has been written. + */ + return intel_vrr_vblank_delay(crtc_state) + 1; else return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode); } From patchwork Fri Feb 7 22:31:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5FB8C021A1 for ; Fri, 7 Feb 2025 22:34:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8704B10E294; Fri, 7 Feb 2025 22:34:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jVaMA5oq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4B6BE10EBB7; Fri, 7 Feb 2025 22:32:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738967534; x=1770503534; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MIQrRcxB+ew8QmvEwYpgTGEPwI8zzZUnTHX6l+LOz08=; b=jVaMA5oqPuQOuygMp94n0dI61D/A7IGGNlCOwxF4WCYGAvJy1CjQShe+ Bk2NAMpim0wTZn0B9VqtS21rFS+bd7iyBejphX36Zb90N6xP0CTLdx7B+ HR+9oRStGjmUY8nfH4u8nBaYuQsiqP19UcwEHmZRTmVXQsf+2o3kcrKgT 4V7P2zTJtGcte03xI4ihGO7yAQccSFfB/98A7Hs42hvVJK+3Sw53AxbaO PUjS+FIhec9SjmHukuyZluDARIMDJpX0HLHamRzjV4Oej9DQ7z3pOgGfA MUVJ5Bx4wqS7s+tXP6O7BewB89fkaxJhvRYOkfZ+5gKE/9fOnAeJumViy Q==; X-CSE-ConnectionGUID: 2HaV+xfJSoGcBdT1jbEgYA== X-CSE-MsgGUID: 7kUP14UwQt6ex4GL+vKDIw== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313395" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313395" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:14 -0800 X-CSE-ConnectionGUID: tADcrjRyT06vE457A9vM8g== X-CSE-MsgGUID: 614qshm7Qf+E3hxtCXEdKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857435" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:12 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:11 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 4/8] drm/i915/dsb: Compute use_dsb earlier Date: Sat, 8 Feb 2025 00:31:55 +0200 Message-ID: <20250207223159.14132-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Skip all the commit completion interrupt stuff on the chained DSB when we don't take the full DSB path (ie. when the plane/pipe programming is done via MMIO). The commit completion will be done via the CPU side vblank interrupt. Currently this is just a redundant interrupt, so not a big deal. But in the future we'll be moving the TRANS_PUSH write into the chained DSB as well, and that we definitely don't want to do when it's also being done by the CPU from intel_pipe_update_end(). Signed-off-by: Ville Syrjälä Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_color.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------ 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 8400a97f7e43..792cf7cef58a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1987,8 +1987,10 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, display->funcs.color->load_luts(crtc_state); - intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); - intel_dsb_interrupt(crtc_state->dsb_color_vblank); + if (crtc_state->use_dsb) { + intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); + intel_dsb_interrupt(crtc_state->dsb_color_vblank); + } intel_dsb_finish(crtc_state->dsb_color_vblank); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a50b0a008231..452b70ffe97c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7676,12 +7676,6 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc) -{ - intel_color_prepare_commit(state, crtc); -} - -static void intel_atomic_dsb_finish(struct intel_atomic_state *state, - struct intel_crtc *crtc) { const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -7704,6 +7698,15 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state) && !intel_crtc_needs_fastset(new_crtc_state); + intel_color_prepare_commit(state, crtc); +} + +static void intel_atomic_dsb_finish(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) return; From patchwork Fri Feb 7 22:31:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DE7DC021A0 for ; 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X-CSE-ConnectionGUID: koJlxPVjR9yxK4CVqYDLdQ== X-CSE-MsgGUID: HAadJvsKSayKnPyhLzCdyA== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313400" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313400" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:17 -0800 X-CSE-ConnectionGUID: 2RMxBjxcTfq9iJH+nQYYCA== X-CSE-MsgGUID: 4Xjm4fXDTZKVrA981C1CIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857454" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:15 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:14 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Ankit Nautiyal Subject: [PATCH v2 5/8] drm/i915/dsb: Introduce intel_dsb_poll() Date: Sat, 8 Feb 2025 00:31:56 +0200 Message-ID: <20250207223159.14132-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add a function for emitting a DSB poll instruction. We'll allow the caller to specify the poll parameters. v2: s/wait/wait_us/ (Ankit) Reviewed-by: Ankit Nautiyal Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dsb.h | 3 +++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 01e3bd385cac..aba57ddfbb92 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -459,6 +459,25 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, start, end); } +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait_us, int count) +{ + struct intel_crtc *crtc = dsb->crtc; + enum pipe pipe = crtc->pipe; + + intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask); + intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id), + DSB_POLL_ENABLE | + DSB_POLL_WAIT(wait_us) | DSB_POLL_COUNT(count)); + + intel_dsb_noop(dsb, 5); + + intel_dsb_emit(dsb, val, + (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | + i915_mmio_reg_offset(reg)); +} + static void intel_dsb_align_tail(struct intel_dsb *dsb) { u32 aligned_tail, tail; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index da6df07a3c83..e843c52bf97c 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -54,6 +54,9 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, int lower, int upper); void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb); +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait_us, int count); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, From patchwork Fri Feb 7 22:31:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF747C0219E for ; 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X-CSE-ConnectionGUID: rCU9hH7vQpak8+DapqcjsA== X-CSE-MsgGUID: dZPiCTOZRoiESuW5MKKdgw== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313402" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313402" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:20 -0800 X-CSE-ConnectionGUID: GQJrjvdIRQyif/uhrqGaQg== X-CSE-MsgGUID: CktiEosCSQyCaHJ38oF5DA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857468" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:18 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:17 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Ankit Nautiyal Subject: [PATCH v2 6/8] drm/i915/vrr: Reorder the DSB "wait for safe window" vs. TRANS_PUSH Date: Sat, 8 Feb 2025 00:31:57 +0200 Message-ID: <20250207223159.14132-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we trigger the push send first, then follow it with a "wait for safe window". That approach no longer works on PTL+ because triggering the push send immediately ends the safe window. On prior hardware the safe window extended past the push being sent (presumably all the way to the pipe's delayed vblank). In order to deal with the new hardware behaviour we must reverse the order of these two operations: first wait for safe window, then trigger the push. The only slight danger with this approach is that if we mess up the vblank evasion around the vmax decision boundary the push might get postponed until after the next frame's vactive. But assuming we don't mess up the vblank evasion this approach is completely safe. As a slight bonus we can perform the push after we've done the LUT writes as well, meaning we no longer have to worry about extending the vblank delay to provide enough time for LUT programming. Instead we will now depend on the vblank evasion at vmax decision boundary to guarantee this. However vblank delay (or framestart delay) is still the only way to provide extra time for the LUT programming in the non-VRR use cases. Let's assume we don't need anything extra for now, but eventually we should come up with some proper estimates on how long the LUT programming can take and configure the vblank delay accordingly for the non-VRR use cases. Reviewed-by: Ankit Nautiyal Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 2 ++ drivers/gpu/drm/i915/display/intel_display.c | 12 ++---------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 792cf7cef58a..4d8f6509cac4 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -29,6 +29,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" +#include "intel_vrr.h" struct intel_color_funcs { int (*color_check)(struct intel_atomic_state *state, @@ -1988,6 +1989,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, display->funcs.color->load_luts(crtc_state); if (crtc_state->use_dsb) { + intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); intel_dsb_interrupt(crtc_state->dsb_color_vblank); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 452b70ffe97c..0790b2a4583e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2630,14 +2630,6 @@ static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state) if (intel_crtc_needs_wa_14015401596(crtc_state)) vblank_delay = max(vblank_delay, 1); - /* - * Add a minimal vblank delay to make sure the push - * doesn't race with the "wait for safe window" used - * for frame completion with DSB. - */ - if (intel_vrr_possible(crtc_state)) - vblank_delay = max(vblank_delay, 1); - return vblank_delay; } @@ -7740,10 +7732,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); - intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); - if (!new_crtc_state->dsb_color_vblank) { intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + + intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); intel_dsb_interrupt(new_crtc_state->dsb_commit); } From patchwork Fri Feb 7 22:31:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64D12C0219D for ; Fri, 7 Feb 2025 22:38:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 091FE10E2B0; Fri, 7 Feb 2025 22:38:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="39313403" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313403" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:24 -0800 X-CSE-ConnectionGUID: FFt+vg4NQImeyWWymVpU7Q== X-CSE-MsgGUID: 1ZqRjX74TyWrQl/7kQaJ5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857481" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:21 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:20 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Ankit Nautiyal Subject: [PATCH v2 7/8] drm/i915/vrr: Check that the push send bit is clear after delayed vblank Date: Sat, 8 Feb 2025 00:31:58 +0200 Message-ID: <20250207223159.14132-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Since we don't do mailbox updates the push send bit should alwyas clear by the time the delay vblank fires and the flip completes. Check for that to make sure we haven't screwed up the sequencing/vblank evasion/etc. On the DSB path we should be able to guarantee this since we don't have to deal with any scheduler latencies and whatnot. I suppose unexpected DMA/memory latencies might be the only thing that might trip us up here. For the MMIO path we do always have a non-zero chance that vblank evasion fails (since we can't really guarantee anything about the scheduling behaviour). That could trip up this check, but that seems fine since we already print errors for other types of vblank evasion failures. Should the CPU vblank evasion actually fail, then the push send bit can still be set when the next commit happens. But both the DSB and MMIO paths should handle that situation gracefully. v2: Only check once instead of polling for two scanlines since we should now be guaranteed to be past the delayed vblank. Also check in the MMIO path for good measure Reviewed-by: Ankit Nautiyal #v1 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 4 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 31 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4d8f6509cac4..cfe14162231d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1991,6 +1991,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (crtc_state->use_dsb) { intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); + intel_vrr_check_push_sent(crtc_state->dsb_color_vblank, crtc_state); intel_dsb_interrupt(crtc_state->dsb_color_vblank); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0790b2a4583e..34434071a415 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7737,6 +7737,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); + intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_interrupt(new_crtc_state->dsb_commit); } } @@ -7886,6 +7887,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_crtc_disable_flip_done(state, crtc); intel_atomic_dsb_wait_commit(new_crtc_state); + + if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb) + intel_vrr_check_push_sent(NULL, new_crtc_state); } /* diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index adb51609d0a3..e939b13bf0e1 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -416,6 +416,37 @@ void intel_vrr_send_push(struct intel_dsb *dsb, intel_dsb_nonpost_end(dsb); } +void intel_vrr_check_push_sent(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + /* + * Make sure the push send bit has cleared. This should + * already be the case as long as the caller makes sure + * this is called after the delayed vblank has occurred. + */ + if (dsb) { + int wait_us, count; + + wait_us = 2; + count = 1; + + /* + * If the bit hasn't cleared the DSB will + * raise the poll error interrupt. + */ + intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_SEND, 0, wait_us, count); + } else { + if (intel_vrr_is_push_sent(crtc_state)) + drm_err(display->drm, "[CRTC:%d:%s] VRR push send still pending\n", + crtc->base.base.id, crtc->base.name); + } +} + bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 899cbf40f880..514822577e8a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -25,6 +25,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) void intel_vrr_enable(const struct intel_crtc_state *crtc_state); void intel_vrr_send_push(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); +void intel_vrr_check_push_sent(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state); void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); void intel_vrr_get_config(struct intel_crtc_state *crtc_state); From patchwork Fri Feb 7 22:31:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13966036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A6AFC0219E for ; Fri, 7 Feb 2025 22:34:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1070610E105; Fri, 7 Feb 2025 22:34:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CuLFlWco"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC24310E105; Fri, 7 Feb 2025 22:32:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738967547; x=1770503547; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cn88Ursnt1X4vFovqVVy8lyyCBvXlsb83eOKKQb5JVc=; b=CuLFlWco6hz8fww4hkAkcpnV1UbirDHW9/gigAy/27aQ6OeHfAKTkBfy YteJ0G3yX8/DEnzrMrZIuAp9R0+j+hSOPmQ4rVXV8M46ErgFtAHprf+sN T/zRKpfJMqDnzOhWloBwpMnVLgb7OjT4jOOd1kkdjW4VuB4YWdydoDF2u D23FWQD5ciikjlJGzjZoh4OMMFfXG5NWtY953rBmmbaMhc/NWUCL8pkyL 0Lo2JF7l19M8y3IeQDeeOdsrlukLb7Z/RwHn4mBM2g2g8y0vdOSrylxi7 40iPCzbOKZ6DhgmzavoiI3djxwSG29ejev/7n/R+Lkb68HZ/vCQXZm+nd g==; X-CSE-ConnectionGUID: 2qLucytWQ+6HTf0hlImE+g== X-CSE-MsgGUID: +TheTSNHRLCAyqTPxxfEJg== X-IronPort-AV: E=McAfee;i="6700,10204,11338"; a="39313432" X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="39313432" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2025 14:32:26 -0800 X-CSE-ConnectionGUID: HPqyhIQFRo+UGnl8ufamtw== X-CSE-MsgGUID: u618OrXoR1SZYr3UV44RyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,268,1732608000"; d="scan'208";a="111857490" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 07 Feb 2025 14:32:25 -0800 Received: by stinkbox (sSMTP sendmail emulation); Sat, 08 Feb 2025 00:32:24 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 8/8] drm/i915/dsb: Decode DSB error interrupts Date: Sat, 8 Feb 2025 00:31:59 +0200 Message-ID: <20250207223159.14132-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250207223159.14132-1-ville.syrjala@linux.intel.com> References: <20250207223159.14132-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Decode the DSB error interrupts into human readable form for easier debugging. Signed-off-by: Ville Syrjälä Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dsb.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index aba57ddfbb92..db69b1c676f7 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -860,7 +860,16 @@ void intel_dsb_irq_handler(struct intel_display *display, } errors = tmp & dsb_error_int_status(display); - if (errors) - drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", - crtc->base.base.id, crtc->base.name, dsb_id, errors); + if (errors & DSB_ATS_FAULT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_GTT_FAULT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_RSPTIMEOUT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_POLL_ERR_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", + crtc->base.base.id, crtc->base.name, dsb_id); }